diff options
| author | Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> | 2021-01-11 18:26:36 +0900 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-18 07:25:48 +0000 |
| commit | 4c4f9161728f42f959b4394ba42aefb64e35afe2 (patch) | |
| tree | b58d0de55d085533945ef088187a6fc69d5fdc25 /src | |
| parent | 88418a74cf3c6f6cc4dc5c81cb2820a760f0c3ff (diff) | |
mb/google/dedede/var/sasuke: Disable PCIE RP8 and CLKSRC3
This change disables unused PCIE RP8 and CLKSRC3.
Without this change sasuke cannot enter into s0ix properly.
BUG=b:176862270
TEST=Built and verified entering s0ix
Change-Id: I0828813ed7924669cb0ff97be2565579762c810f
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49300
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jamie Chen <jamie.chen@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/dedede/variants/sasuke/overridetree.cb | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb index f4d385e614..57cfbc7c4f 100644 --- a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb @@ -1,4 +1,8 @@ chip soc/intel/jasperlake + # Disable PCIe Root Port 8 (index 7) + register "PcieRpEnable[7]" = "0" + # Disable PCIe Clock Source 4 (index 3) + register "PcieClkSrcUsage[3]" = "0xff" # USB Port Configuration register "usb2_ports[0]" = "{ @@ -107,7 +111,7 @@ chip soc/intel/jasperlake end end # I2C 0 device pci 15.2 on end - device pci 1c.7 on end + device pci 1c.7 off end # PCI Express Root Port 8 device pci 19.0 on chip drivers/i2c/da7219 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" |