diff options
| author | Keith Hui <buurin@gmail.com> | 2023-07-22 12:49:05 -0400 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-11-13 20:31:23 +0000 |
| commit | 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da (patch) | |
| tree | 8b0fb3b07ecb3cfa84aa77b51c0e1053a1415c73 /src | |
| parent | 940fe080bf1ed2dac827b569c70fb0ea11496041 (diff) | |
mb/*: Update SPD mapping for sandybridge boards
Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree.
Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping.
Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src')
112 files changed, 104 insertions, 672 deletions
diff --git a/src/mainboard/asrock/b75m-itx/devicetree.cb b/src/mainboard/asrock/b75m-itx/devicetree.cb index 5f45ffe621..6d4ca2d168 100644 --- a/src/mainboard/asrock/b75m-itx/devicetree.cb +++ b/src/mainboard/asrock/b75m-itx/devicetree.cb @@ -4,6 +4,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" device domain 0 on device pci 00.0 on diff --git a/src/mainboard/asrock/b75m-itx/early_init.c b/src/mainboard/asrock/b75m-itx/early_init.c index 189e24474a..b70794aeba 100644 --- a/src/mainboard/asrock/b75m-itx/early_init.c +++ b/src/mainboard/asrock/b75m-itx/early_init.c @@ -1,16 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <bootblock_common.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> const struct southbridge_usb_port mainboard_usb_ports[] = { {1, 0, 0}, {1, 0, 0}, {1, 1, 1}, {1, 1, 1}, {1, 1, 2}, {1, 1, 2}, {1, 0, 3}, {1, 0, 3}, {1, 0, 4}, {1, 0, 4}, {1, 0, 6}, {1, 1, 5}, {1, 1, 5}, {1, 0, 6}, }; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index dc6080d735..e2c898d0b8 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -13,6 +13,7 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "0" register "gpu_panel_power_up_delay" = "0" register "gpu_pch_backlight" = "0x00000000" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" device domain 0 on device ref host_bridge on diff --git a/src/mainboard/asrock/b75pro3-m/early_init.c b/src/mainboard/asrock/b75pro3-m/early_init.c index ed856b6b58..4052b6f22d 100644 --- a/src/mainboard/asrock/b75pro3-m/early_init.c +++ b/src/mainboard/asrock/b75pro3-m/early_init.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/nct6776/nct6776.h> #include <superio/nuvoton/common/nuvoton.h> @@ -40,11 +39,3 @@ void bootblock_mainboard_early_init(void) nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} diff --git a/src/mainboard/asrock/h77pro4-m/devicetree.cb b/src/mainboard/asrock/h77pro4-m/devicetree.cb index 42b8700783..2624c38ebe 100644 --- a/src/mainboard/asrock/h77pro4-m/devicetree.cb +++ b/src/mainboard/asrock/h77pro4-m/devicetree.cb @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" device domain 0 on device ref host_bridge on # Host bridge subsystemid 0x1849 0x0100 diff --git a/src/mainboard/asrock/h77pro4-m/early_init.c b/src/mainboard/asrock/h77pro4-m/early_init.c index 48024cba5c..4637378456 100644 --- a/src/mainboard/asrock/h77pro4-m/early_init.c +++ b/src/mainboard/asrock/h77pro4-m/early_init.c @@ -1,11 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <stdint.h> - #include <bootblock_common.h> #include <device/pci_ops.h> #include <device/pnp_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <option.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> @@ -87,11 +85,3 @@ void bootblock_mainboard_early_init(void) /* Enable UART */ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} diff --git a/src/mainboard/asus/h61-series/devicetree.cb b/src/mainboard/asus/h61-series/devicetree.cb index e1fe7c240f..cde04317f0 100644 --- a/src/mainboard/asus/h61-series/devicetree.cb +++ b/src/mainboard/asus/h61-series/devicetree.cb @@ -1,6 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0, 0x52, 0}" device domain 0 on device ref host_bridge on end # Host bridge device ref peg10 on end # PEG diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c b/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c index cb8daaf014..50e225a0d4 100644 --- a/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c +++ b/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6779d/nct6779d.h> @@ -35,9 +34,3 @@ void bootblock_mainboard_early_init(void) pnp_write_config(ACPI_DEV, 0xe4, 0x10); nuvoton_pnp_exit_conf_state(SIO_DEV); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c index 5e54d08e85..5f5c684aa2 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <bootblock_common.h> -#include <device/dram/ddr3.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> @@ -30,9 +28,3 @@ void bootblock_mainboard_early_init(void) { nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c index 33efaf6e04..404a8503bf 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6779d/nct6779d.h> @@ -47,9 +46,3 @@ void bootblock_mainboard_early_init(void) /* Do not enable UART, the header is not populated by default */ } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c index 05e87c1c68..1c8d84442b 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> @@ -49,9 +48,3 @@ void bootblock_mainboard_early_init(void) nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c index af90702cfe..e76e1094cb 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> @@ -49,9 +48,3 @@ void bootblock_mainboard_early_init(void) /* Enable UART */ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x51, id_only); - read_spd(&spd[2], 0x53, id_only); -} diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb index 7882bf0748..1b78b9b9bd 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb @@ -1,6 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x51, 0, 0x53, 0}" device domain 0 on chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" # HWM diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index 9174e82621..146ee6c7dc 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -1,6 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" device domain 0 on subsystemid 0x1043 0x844d inherit diff --git a/src/mainboard/asus/maximus_iv_gene-z/early_init.c b/src/mainboard/asus/maximus_iv_gene-z/early_init.c index df0a99beb0..ed593f65f5 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/early_init.c +++ b/src/mainboard/asus/maximus_iv_gene-z/early_init.c @@ -2,8 +2,6 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> -#include <device/dram/ddr3.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> @@ -42,11 +40,3 @@ void bootblock_mainboard_early_init(void) nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb index 2913519ca9..cd4336f19e 100644 --- a/src/mainboard/asus/p8x7x-series/devicetree.cb +++ b/src/mainboard/asus/p8x7x-series/devicetree.cb @@ -6,6 +6,7 @@ chip northbridge/intel/sandybridge register "ddr3lv_support" = "1" # FIXME: Nothing can run native at 800MHz on p8z77-m, others may have same problem register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" register "usb_port_config" = "{ {1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080}, diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c index 9f84b49e6b..79b67f07f1 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> @@ -52,11 +51,3 @@ void bootblock_mainboard_early_init(void) /* Enable UART */ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c index 3a297f9e38..89f9eee106 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6779d/nct6779d.h> @@ -50,11 +49,3 @@ void bootblock_mainboard_early_init(void) /* Enable UART */ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c index fdb0a455a5..47c5cb302d 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <bootblock_common.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/pei_data.h> #include <southbridge/intel/bd82x6x/pch.h> @@ -42,20 +41,8 @@ void bootblock_mainboard_early_init(void) */ } -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} - void mainboard_fill_pei_data(struct pei_data *pei) { - const uint8_t spdaddr[] = {0xa0, 0xa2, 0xa4, 0xa6}; /* SMBus mul 2 */ - - memcpy(pei->spd_addresses, &spdaddr, sizeof(spdaddr)); - /* * USB 3 mode settings. * These are obtained from option table then bit masked to keep within range. diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c index ac3eb42039..c8d5e33cbc 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c @@ -1,9 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/hpet.h> #include <bootblock_common.h> #include <device/pnp_ops.h> -#include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> @@ -11,7 +9,6 @@ #include <option.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/pei_data.h> @@ -48,20 +45,8 @@ void bootblock_mainboard_early_init(void) nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} - void mainboard_fill_pei_data(struct pei_data *pei_data) { - const uint8_t spdaddr[] = {0xa0, 0xa2, 0xa4, 0xa6}; /* SMBus mul 2 */ - - memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses)); - /* * USB3 mode: * 0 = Disable: work always as USB 2.0(ehci) diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c index 42b4ebc6dc..c16b055aa4 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> @@ -47,11 +46,3 @@ void bootblock_mainboard_early_init(void) /* Enable UART */ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c index 3a297f9e38..89f9eee106 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6779d/nct6779d.h> @@ -50,11 +49,3 @@ void bootblock_mainboard_early_init(void) /* Enable UART */ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} diff --git a/src/mainboard/biostar/th61-itx/devicetree.cb b/src/mainboard/biostar/th61-itx/devicetree.cb index 611671aad1..af9f9b5937 100644 --- a/src/mainboard/biostar/th61-itx/devicetree.cb +++ b/src/mainboard/biostar/th61-itx/devicetree.cb @@ -1,6 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0, 0x52, 0}" device domain 0 on subsystemid 0x1565 0x3108 inherit diff --git a/src/mainboard/biostar/th61-itx/early_init.c b/src/mainboard/biostar/th61-itx/early_init.c index 9d537e6428..c8d6471779 100644 --- a/src/mainboard/biostar/th61-itx/early_init.c +++ b/src/mainboard/biostar/th61-itx/early_init.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <stdbool.h> const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, @@ -20,9 +18,3 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 5 }, { 1, 0, 6 }, }; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index c108d4de91..d09c9e0b1f 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -6,6 +6,8 @@ chip northbridge/intel/sandybridge # FIXME: check gfx register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" + device domain 0 on device ref host_bridge on # Host bridge subsystemid 0x8086 0x2010 diff --git a/src/mainboard/compulab/intense_pc/early_init.c b/src/mainboard/compulab/intense_pc/early_init.c index d3842f83f5..f5859e99d6 100644 --- a/src/mainboard/compulab/intense_pc/early_init.c +++ b/src/mainboard/compulab/intense_pc/early_init.c @@ -3,7 +3,6 @@ #include <bootblock_common.h> #include <stdint.h> #include <arch/io.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <superio/smsc/sio1007/sio1007.h> #include <southbridge/intel/bd82x6x/pch.h> @@ -62,9 +61,3 @@ void bootblock_mainboard_early_init(void) /* Turn off configuration mode. */ outb(0xaa, port); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/dell/snb_ivb_workstations/romstage.c b/src/mainboard/dell/snb_ivb_workstations/romstage.c index 83c00c7260..d2a6b11848 100644 --- a/src/mainboard/dell/snb_ivb_workstations/romstage.c +++ b/src/mainboard/dell/snb_ivb_workstations/romstage.c @@ -4,7 +4,6 @@ #include <arch/io.h> #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/smsc/sch5545/sch5545.h> @@ -56,11 +55,3 @@ void mainboard_early_init(int s3resume) outb(0, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_SMI_EN); outb(SCH5545_SMI_GLOBAL_STS, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_SMI_STS); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb index 5e52764550..bf04692c91 100644 --- a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb +++ b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb @@ -1,4 +1,5 @@ chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" chip cpu/intel/model_206ax device cpu_cluster 0 on end diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index b0ef1ee4ea..3b9584360b 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -1,4 +1,6 @@ chip northbridge/intel/sandybridge + # FIXME: The GA-B75M-D3V only has two DIMM slots! + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" device domain 0 on subsystemid 0x1458 0x5000 inherit device ref host_bridge on # Host bridge diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c index a88abf89c9..8fd6f989ec 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8728f/it8728f.h> @@ -57,12 +56,3 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 5, 5 }, { 1, 5, 6 }, }; - -/* FIXME: The GA-B75M-D3V only has two DIMM slots! */ -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} diff --git a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb index 8b602a3b7b..8a29171fda 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb @@ -1,6 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0, 0x52, 0}" device domain 0 on subsystemid 0x1458 0x5000 inherit diff --git a/src/mainboard/gigabyte/ga-h61m-series/early_init.c b/src/mainboard/gigabyte/ga-h61m-series/early_init.c index 975e88a261..6f9109af0f 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/early_init.c +++ b/src/mainboard/gigabyte/ga-h61m-series/early_init.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <northbridge/intel/sandybridge/raminit_native.h> +#include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8728f/it8728f.h> @@ -36,9 +36,3 @@ void bootblock_mainboard_early_init(void) /* Disable SIO WDT which kicks in DualBIOS */ ite_reg_write(SUPERIO_GPIO, 0xEF, 0x7E); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index a72d984369..f3960ca654 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -18,6 +18,7 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x000001e8" register "gpu_pch_backlight" = "0x03d00000" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" register "ec_present" = "1" # FIXME: Native raminit requires reduced max clock register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800" diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index e658d37465..f63d3c3d75 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -1,12 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/hpet.h> #include <stdint.h> -#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/gpio.h> void mainboard_late_rcba_config(void) { @@ -66,17 +62,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 0, -1 }, /* P13: Empty */ }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} - void mainboard_fill_pei_data(struct pei_data *pei_data) { - const uint8_t spdaddr[] = {0xA0, 0x00, 0xA4, 0x00}; - - memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses)); - /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ } diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index a4127f14d8..e40531dac1 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -1,17 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/hpet.h> -#include <stdint.h> -#include <string.h> #include <device/pci_ops.h> -#include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include "ec/google/chromeec/ec.h" -#include <cbfs.h> #include <southbridge/intel/bd82x6x/chip.h> @@ -58,39 +52,15 @@ void mainboard_late_rcba_config(void) DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); } -static uint8_t *locate_spd(void) +static unsigned int get_spd_index(void) { const int gpio_vector[] = {41, 42, 43, 10, -1}; - uint8_t *spd_file; - size_t spd_file_len; - int spd_index = get_gpios(gpio_vector); - - printk(BIOS_DEBUG, "spd index %d\n", spd_index); - spd_file = cbfs_map("spd.bin", &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < ((spd_index + 1) * 256)) { - printk(BIOS_ERR, "spd index override to 0 - old hardware?\n"); - spd_index = 0; - } - - if (spd_file_len < 256) - die("Missing SPD data."); - - return spd_file + spd_index * 256; + return get_gpios(gpio_vector); } void mainboard_fill_pei_data(struct pei_data *pei_data) { /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ - - /* LINK has 2 channels of memory down, so spd_data[0] and [2] - both need to be populated */ - memcpy(pei_data->spd_data[0], locate_spd(), - sizeof(pei_data->spd_data[0])); - memcpy(pei_data->spd_data[2], pei_data->spd_data[0], - sizeof(pei_data->spd_data[0])); } const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -111,12 +81,12 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 0, -1 }, /* P13: Empty */ }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) +void mb_get_spd_map(struct spd_info *spdi) { - /* LINK has 2 channels of memory down, so spd_data[0] and [2] - both need to be populated */ - memcpy(&spd[0], locate_spd(), 128); - memcpy(&spd[2], &spd[0], 128); + /* LINK has 2 channels of memory down */ + spdi->addresses[0] = SPD_MEMORY_DOWN; + spdi->addresses[2] = SPD_MEMORY_DOWN; + spdi->spd_index = get_spd_index(); } void mainboard_early_init(int s3resume) diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index bf1bff36f2..49b40b95b6 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -17,6 +17,7 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x000001d4" register "gpu_pch_backlight" = "0x03aa0000" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" register "ec_present" = "1" # FIXME: Native raminit requires reduced max clock register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800" diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index efdb9a2fea..f91b7d9f45 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -1,12 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/hpet.h> -#include <stdint.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/gpio.h> #include "ec/compal/ene932/ec.h" void mainboard_late_rcba_config(void) @@ -52,10 +48,6 @@ void mainboard_late_rcba_config(void) void mainboard_fill_pei_data(struct pei_data *pei_data) { - const uint8_t spdaddr[] = {0xA0, 0x00, 0xA4, 0x00}; - - memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses)); - /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ } @@ -77,9 +69,3 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 0, -1 }, /* P12: Empty */ { 0, 0, -1 }, /* P13: Empty */ }; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index a2b8452d99..8fd19fce58 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -17,6 +17,7 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" register "ec_present" = "1" # FIXME: Native raminit requires reduced max clock register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800" diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index 85c4e154dd..0739f6e720 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -1,11 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/hpet.h> #include <stdint.h> #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <bootmode.h> @@ -81,18 +79,8 @@ static void early_ec_init(void) } } -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} - void mainboard_fill_pei_data(struct pei_data *pei_data) { - const uint8_t spdaddr[] = {0xA0, 0x00, 0xA4, 0x00}; - - memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses)); - /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ } diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index a18ec3c779..993721b473 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -5,6 +5,8 @@ chip northbridge/intel/sandybridge register "gpu_dp_b_hotplug" = "0" register "gpu_dp_c_hotplug" = "0" register "gpu_dp_d_hotplug" = "0" + # BTX mainboard: Reversed mapping + register "spd_addresses" = "{0x53, 0x52, 0x51, 0x50}" device domain 0 on subsystemid 0x103c 0x1495 inherit diff --git a/src/mainboard/hp/compaq_8200_elite_sff/early_init.c b/src/mainboard/hp/compaq_8200_elite_sff/early_init.c index ffff01af3e..31fa913a21 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/early_init.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/early_init.c @@ -3,7 +3,6 @@ #include <bootblock_common.h> #include <superio/nuvoton/npcd378/npcd378.h> #include <superio/nuvoton/common/nuvoton.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2) @@ -30,12 +29,3 @@ void bootblock_mainboard_early_init(void) if (CONFIG(CONSOLE_SERIAL)) nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - /* BTX mainboard: Reversed mapping */ - read_spd(&spd[3], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); - read_spd(&spd[1], 0x52, id_only); - read_spd(&spd[0], 0x53, id_only); -} diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb index f7f321fc83..7a62df1001 100644 --- a/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb +++ b/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb @@ -1,6 +1,8 @@ chip northbridge/intel/sandybridge register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" + # BTX mainboard: Reversed mapping + register "spd_addresses" = "{0, 0x52, 0, 0x50}" device domain 0x0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "docking_supported" = "0" diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/early_init.c b/src/mainboard/hp/compaq_elite_8300_usdt/early_init.c index 857c25dd19..ae75d7c32a 100644 --- a/src/mainboard/hp/compaq_elite_8300_usdt/early_init.c +++ b/src/mainboard/hp/compaq_elite_8300_usdt/early_init.c @@ -1,14 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include <bootblock_common.h> #include <superio/nuvoton/npcd378/npcd378.h> #include <superio/nuvoton/common/nuvoton.h> #include <device/pci_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, @@ -31,9 +28,3 @@ void bootblock_mainboard_early_init(void) pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1408); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[3], 0x50, id_only); - read_spd(&spd[1], 0x52, id_only); -} diff --git a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb index 54d522c93d..42dc4bd2c9 100644 --- a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb @@ -15,6 +15,7 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "230" register "gpu_panel_power_up_delay" = "300" register "gpu_pch_backlight" = "0x02880288" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" device domain 0 on diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2170p/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/2170p/early_init.c index f17680a389..e5a9da72ca 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2170p/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2170p/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/smsc/lpc47n217/lpc47n217.h> #include <ec/hp/kbc1126/ec.h> @@ -35,9 +34,3 @@ void bootblock_mainboard_early_init(void) kbc1126_pm1_init(); kbc1126_exit_conf(); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/early_init.c index 29e9e0f827..9be20365fe 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <bootblock_common.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/hp/kbc1126/ec.h> @@ -32,9 +31,3 @@ void bootblock_mainboard_early_init(void) kbc1126_exit_conf(); kbc1126_disable4e(); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/early_init.c index 686601e874..aa4e9da2ff 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/hp/kbc1126/ec.h> @@ -32,9 +31,3 @@ void bootblock_mainboard_early_init(void) kbc1126_exit_conf(); kbc1126_disable4e(); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/early_init.c index 563371d7ae..ed40b31862 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/hp/kbc1126/ec.h> @@ -33,9 +32,3 @@ void bootblock_mainboard_early_init(void) kbc1126_exit_conf(); kbc1126_disable4e(); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/early_init.c index b31f515a11..e930e6bf17 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/smsc/lpc47n217/lpc47n217.h> #include <ec/hp/kbc1126/ec.h> @@ -35,9 +34,3 @@ void bootblock_mainboard_early_init(void) kbc1126_pm1_init(); kbc1126_exit_conf(); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/early_init.c index df3b9e1686..87e46ff612 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/smsc/lpc47n217/lpc47n217.h> #include <ec/hp/kbc1126/ec.h> @@ -35,9 +34,3 @@ void bootblock_mainboard_early_init(void) kbc1126_pm1_init(); kbc1126_exit_conf(); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/early_init.c index 3f813403cc..32b03da185 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/smsc/lpc47n217/lpc47n217.h> #include <ec/hp/kbc1126/ec.h> @@ -35,11 +34,3 @@ void bootblock_mainboard_early_init(void) kbc1126_pm1_init(); kbc1126_exit_conf(); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb index 7244acd731..02ee795054 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" device domain 0 on subsystemid 0x103c 0x176c inherit diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/early_init.c index bf59f264ed..24100be19e 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/hp/kbc1126/ec.h> @@ -31,9 +30,3 @@ void bootblock_mainboard_early_init(void) kbc1126_pm1_init(); kbc1126_exit_conf(); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/early_init.c index 95243016e6..623aaf1842 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/early_init.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <bootblock_common.h> -#include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/smsc/lpc47n217/lpc47n217.h> #include <ec/hp/kbc1126/ec.h> @@ -36,9 +34,3 @@ void bootblock_mainboard_early_init(void) kbc1126_pm1_init(); kbc1126_exit_conf(); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c index 65a18199e7..2799a8538b 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c @@ -1,10 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <string.h> -#include <cbfs.h> -#include <console/console.h> -#include <northbridge/intel/sandybridge/raminit_native.h> +#include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/hp/kbc1126/ec.h> @@ -35,15 +32,10 @@ void bootblock_mainboard_early_init(void) kbc1126_exit_conf(); } -void mainboard_get_spd(spd_raw_data *spd, bool id_only) +void mb_get_spd_map(struct spd_info *spdi) { + spdi->addresses[0] = 0x50; /* C1S0 is a soldered RAM with no real SPD. Use stored SPD. */ - size_t spd_file_len = 0; - void *spd_file = cbfs_map("spd.bin", &spd_file_len); - - if (!spd_file || spd_file_len < sizeof(spd_raw_data)) - die("SPD data for C1S0 not found."); - - read_spd(&spd[0], 0x50, id_only); - memcpy(&spd[2], spd_file, spd_file_len); + spdi->addresses[2] = SPD_MEMORY_DOWN; + spdi->spd_index = 0; } diff --git a/src/mainboard/hp/z220_series/devicetree.cb b/src/mainboard/hp/z220_series/devicetree.cb index 71b1865254..f02ff76123 100644 --- a/src/mainboard/hp/z220_series/devicetree.cb +++ b/src/mainboard/hp/z220_series/devicetree.cb @@ -5,6 +5,8 @@ chip northbridge/intel/sandybridge register "gpu_dp_b_hotplug" = "0" register "gpu_dp_c_hotplug" = "0" register "gpu_dp_d_hotplug" = "0" + # BTX mainboard: Reversed mapping + register "spd_addresses" = "{0x53, 0x52, 0x51, 0x50}" device domain 0 on subsystemid 0x103c 0x1791 inherit diff --git a/src/mainboard/hp/z220_series/early_init.c b/src/mainboard/hp/z220_series/early_init.c index c0d84f5127..74a646238c 100644 --- a/src/mainboard/hp/z220_series/early_init.c +++ b/src/mainboard/hp/z220_series/early_init.c @@ -3,7 +3,6 @@ #include <bootblock_common.h> #include <superio/nuvoton/npcd378/npcd378.h> #include <superio/nuvoton/common/nuvoton.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2) @@ -30,12 +29,3 @@ void bootblock_mainboard_early_init(void) if (CONFIG(CONSOLE_SERIAL)) nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - /* BTX mainboard: Reversed mapping */ - read_spd(&spd[3], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); - read_spd(&spd[1], 0x52, id_only); - read_spd(&spd[0], 0x53, id_only); -} diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index 37304f2167..f4e948f76c 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -13,6 +13,7 @@ chip northbridge/intel/sandybridge # 1333MHz RAM frequency register "max_mem_clock_mhz" = "666" + register "spd_addresses" = "{0x50, 0, 0x51, 0}" register "usb_port_config" = "{ {1, 0, 0x0040}, diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index e2fd2aae9c..e0f27bab51 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <stdint.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include "superio.h" @@ -126,12 +125,6 @@ void bootblock_mainboard_early_init(void) hwm_init(); } -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); -} - const struct southbridge_usb_port mainboard_usb_ports[] = { #define USB_CONFIG(enabled, current, ocpin) { enabled, current, ocpin } #include "usb.h" diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index d0decb4602..d9a6a9ebbb 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -2,13 +2,8 @@ #include <stdint.h> #include <northbridge/intel/sandybridge/raminit.h> -#include <southbridge/intel/bd82x6x/pch.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { - const uint8_t spdaddr[] = {0xa0, 0x00, 0xa2, 0x00}; - - memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses)); - /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ } diff --git a/src/mainboard/intel/dq67sw/devicetree.cb b/src/mainboard/intel/dq67sw/devicetree.cb index 544a525b97..f29b772e8a 100644 --- a/src/mainboard/intel/dq67sw/devicetree.cb +++ b/src/mainboard/intel/dq67sw/devicetree.cb @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" device domain 0 on subsystemid 0x8086 0x2008 inherit device ref host_bridge on end # Host bridge diff --git a/src/mainboard/intel/dq67sw/early_init.c b/src/mainboard/intel/dq67sw/early_init.c index 683dbf8f66..14317a69e0 100644 --- a/src/mainboard/intel/dq67sw/early_init.c +++ b/src/mainboard/intel/dq67sw/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/winbond/w83667hg-a/w83667hg-a.h> #include <superio/winbond/common/winbond.h> @@ -29,11 +28,3 @@ void bootblock_mainboard_early_init(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index a7f5d3bd3e..e75505e270 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -12,6 +12,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_b_hotplug" = "0x06" register "max_mem_clock_mhz" = "800" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" register "usb_port_config" = "{ { 1, 0, 0x0040 }, diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index 853add4dd6..1974713520 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -1,15 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/hpet.h> #include <bootblock_common.h> #include <stdint.h> #include <arch/io.h> #include <superio/smsc/sio1007/sio1007.h> -#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/gpio.h> #define SIO_PORT 0x164e @@ -50,9 +46,6 @@ void bootblock_mainboard_early_init(void) void mainboard_fill_pei_data(struct pei_data *pei_data) { - const uint8_t spdaddr[] = { 0xa0, 0x00, 0xa4, 0x00 }; - - memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses)); } const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -72,9 +65,3 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, /* P12: Back port (OC6) */ { 1, 0, 5 }, /* P13: Back port (OC5) */ }; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index 853a410247..a03562842c 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/intel/sandybridge # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" register "max_mem_clock_mhz" = "800" register "ec_present" = "1" diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index e8fa6b1d69..e514f102b5 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -1,13 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/hpet.h> #include <bootblock_common.h> -#include <stdint.h> #include <device/pnp_def.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> @@ -55,9 +52,6 @@ void bootblock_mainboard_early_init(void) void mainboard_fill_pei_data(struct pei_data *pei_data) { - const uint8_t spdaddr[] = {0xA0, 0x00, 0xA4, 0x00}; - - memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses)); } const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -78,12 +72,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 4 }, /* P13: internal USB 2.0 (OC4) */ }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} - void mainboard_early_init(int s3resume) { /* Enable PEG10 (1x16) */ diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index dd431dfda4..ead7e0bb87 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -11,6 +11,7 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "0" register "gpu_panel_power_up_delay" = "0" register "gpu_pch_backlight" = "0x00000000" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" device domain 0 on subsystemid 0x17aa 0x21dd inherit diff --git a/src/mainboard/lenovo/l520/early_init.c b/src/mainboard/lenovo/l520/early_init.c index b6202c735a..ebcd639e6a 100644 --- a/src/mainboard/lenovo/l520/early_init.c +++ b/src/mainboard/lenovo/l520/early_init.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> @@ -20,9 +19,3 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, -1 }, { 1, 0, -1 }, }; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/lenovo/s230u/early_init.c b/src/mainboard/lenovo/s230u/early_init.c index 434b58c6a3..58e95932b8 100644 --- a/src/mainboard/lenovo/s230u/early_init.c +++ b/src/mainboard/lenovo/s230u/early_init.c @@ -1,17 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> -#include <string.h> -#include <cbfs.h> #include <device/pci_ops.h> #include <console/console.h> -#include <northbridge/intel/sandybridge/raminit_native.h> +#include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include "ec.h" -#define SPD_LEN 256 - void mainboard_pch_lpc_setup(void) { /* Memory map KB9012 EC registers */ @@ -54,26 +49,27 @@ static const char *mainboard_spd_names[9] = { "HYNIX 2GB", }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) +static unsigned int get_spd_index(void) { - void *spd_file; - size_t spd_file_len = 0; const int spd_gpios[] = {71, 70, 16, 48, -1}; - u32 spd_index = get_gpios(spd_gpios); + unsigned int spd_index = get_gpios(spd_gpios); if (spd_index >= ARRAY_SIZE(mainboard_spd_names)) { /* Fallback to pessimistic 2GB image (ELPIDA 2GB) */ spd_index = 6; } + return spd_index; +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + unsigned int spd_index = get_spd_index(); + printk(BIOS_INFO, "SPD index %d (%s)\n", spd_index, mainboard_spd_names[spd_index]); /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */ - spd_file = cbfs_map("spd.bin", &spd_file_len); - - if (!spd_file || spd_file_len < SPD_LEN * spd_index + SPD_LEN) - die("SPD data not found."); - - memcpy(spd, spd_file + SPD_LEN * spd_index, SPD_LEN); + spdi->addresses[0] = SPD_MEMORY_DOWN; + spdi->spd_index = spd_index; } diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 953044a5d2..d4b31afe88 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -15,6 +15,8 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" + register "spd_addresses" = "{0x50, 0, 0x51, 0}" + device domain 0 on subsystemid 0x17aa 0x21ce inherit diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c index 1be50fd6ed..c90221ed67 100644 --- a/src/mainboard/lenovo/t420/early_init.c +++ b/src/mainboard/lenovo/t420/early_init.c @@ -1,11 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/pci_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <device/device.h> static void hybrid_graphics_init(void) { @@ -51,12 +49,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, -1 }, /* P13: camera (LCD), no OC */ }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); -} - void mainboard_early_init(int s3resume) { hybrid_graphics_init(); diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index fc3b12c1dd..fb309170fe 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -15,6 +15,8 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" + register "spd_addresses" = "{0x50, 0, 0x51, 0}" + device domain 0 on subsystemid 0x17aa 0x21d2 inherit diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c index 990a0b3e52..e5e95b218a 100644 --- a/src/mainboard/lenovo/t420s/early_init.c +++ b/src/mainboard/lenovo/t420s/early_init.c @@ -1,11 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/pci_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <device/device.h> static void hybrid_graphics_init(void) { @@ -50,12 +48,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, -1 }, /* P13: camera (LCD), no OC */ }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); -} - void mainboard_early_init(int s3resume) { hybrid_graphics_init(); diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 73fd5b20cc..6492542906 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -14,6 +14,8 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" + register "spd_addresses" = "{0x50, 0, 0x51, 0}" + device domain 0 on subsystemid 0x17aa 0x21f3 inherit diff --git a/src/mainboard/lenovo/t430/early_init.c b/src/mainboard/lenovo/t430/early_init.c index baafb5032a..5e397ab7c4 100644 --- a/src/mainboard/lenovo/t430/early_init.c +++ b/src/mainboard/lenovo/t430/early_init.c @@ -2,12 +2,10 @@ #include <device/pci_ops.h> #include <device/pci_def.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/lenovo/pmh7/pmh7.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <device/device.h> static void hybrid_graphics_init(void) { @@ -57,9 +55,3 @@ void mainboard_early_init(int s3resume) { hybrid_graphics_init(); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); -} diff --git a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb index 4250665e2c..698460b1dc 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb @@ -1,4 +1,5 @@ chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0, 0x51, 0}" device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH # Enable hotplug on Port 5 for Thunderbolt controller diff --git a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c index c6414863ce..8980572174 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c @@ -3,7 +3,7 @@ #include <option.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <northbridge/intel/sandybridge/raminit_native.h> +#include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/lenovo/pmh7/pmh7.h> #include <types.h> @@ -25,12 +25,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, -1 }, /* P13: camera, no OC */ }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); -} - void mainboard_early_init(int s3resume) { u8 enable_peg = get_uint_option("enable_dual_graphics", 0); diff --git a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c index 54236a1ffc..6fbbaadbf4 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c @@ -1,11 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> -#include <cbfs.h> -#include <northbridge/intel/sandybridge/raminit_native.h> -#include <string.h> +#include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <ec/lenovo/pmh7/pmh7.h> const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, /* SSP1: right */ @@ -24,15 +20,10 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, -1 }, /* B1P6: Camera */ }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) +void mb_get_spd_map(struct spd_info *spdi) { /* C1S0 is a soldered RAM with no real SPD. Use stored SPD. */ - size_t spd_file_len = 0; - void *spd_file = cbfs_map("spd.bin", &spd_file_len); - - if (!spd_file || spd_file_len < sizeof(spd_raw_data)) - die("SPD data for C1S0 not found."); - - memcpy(&spd[0], spd_file, spd_file_len); - read_spd(&spd[2], 0x51, id_only); + spdi->addresses[0] = SPD_MEMORY_DOWN; + spdi->addresses[2] = 0x51; + spdi->spd_index = 0; } diff --git a/src/mainboard/lenovo/t520/Makefile.inc b/src/mainboard/lenovo/t520/Makefile.inc index a3b838ba10..69ef08873b 100644 --- a/src/mainboard/lenovo/t520/Makefile.inc +++ b/src/mainboard/lenovo/t520/Makefile.inc @@ -2,7 +2,6 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c -romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t520/early_init.c b/src/mainboard/lenovo/t520/early_init.c index 54d42ea3dc..219ffc1751 100644 --- a/src/mainboard/lenovo/t520/early_init.c +++ b/src/mainboard/lenovo/t520/early_init.c @@ -4,7 +4,6 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <device/device.h> diff --git a/src/mainboard/lenovo/t520/variants/t520/overridetree.cb b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb index b976d6d904..d1634f81d6 100644 --- a/src/mainboard/lenovo/t520/variants/t520/overridetree.cb +++ b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb @@ -1,4 +1,5 @@ chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0, 0x51, 0}" device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH device pci 1f.0 on # LPC bridge diff --git a/src/mainboard/lenovo/t520/variants/t520/romstage.c b/src/mainboard/lenovo/t520/variants/t520/romstage.c deleted file mode 100644 index cf5b18d4f2..0000000000 --- a/src/mainboard/lenovo/t520/variants/t520/romstage.c +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <northbridge/intel/sandybridge/raminit_native.h> - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); -} diff --git a/src/mainboard/lenovo/t520/variants/w520/overridetree.cb b/src/mainboard/lenovo/t520/variants/w520/overridetree.cb index 3e1c90ee63..4e03e753f4 100644 --- a/src/mainboard/lenovo/t520/variants/w520/overridetree.cb +++ b/src/mainboard/lenovo/t520/variants/w520/overridetree.cb @@ -1,4 +1,5 @@ chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0x52, 0x51, 0x53}" device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH device pci 1c.6 on end # PCIe Port #7 USB 3.0 diff --git a/src/mainboard/lenovo/t520/variants/w520/romstage.c b/src/mainboard/lenovo/t520/variants/w520/romstage.c deleted file mode 100644 index 493a0a05ff..0000000000 --- a/src/mainboard/lenovo/t520/variants/w520/romstage.c +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <northbridge/intel/sandybridge/raminit_native.h> - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x52, id_only); - read_spd(&spd[2], 0x51, id_only); - read_spd(&spd[3], 0x53, id_only); -} diff --git a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb index 78f7b9b34c..98551ac968 100644 --- a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb @@ -1,4 +1,5 @@ chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0, 0x51, 0}" device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH device pci 1f.0 on # PCI-LPC bridge diff --git a/src/mainboard/lenovo/t530/variants/t530/romstage.c b/src/mainboard/lenovo/t530/variants/t530/romstage.c index 22bf0764aa..2290bcea13 100644 --- a/src/mainboard/lenovo/t530/variants/t530/romstage.c +++ b/src/mainboard/lenovo/t530/variants/t530/romstage.c @@ -1,14 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* P0: USB double port upper, USB3, OC 0 */ { 1, 1, 1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */ diff --git a/src/mainboard/lenovo/t530/variants/w530/overridetree.cb b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb index 115bc1f12a..77b75fd237 100644 --- a/src/mainboard/lenovo/t530/variants/w530/overridetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb @@ -1,4 +1,5 @@ chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0x52, 0x51, 0x53}" device domain 0 on device pci 02.0 on # Internal graphics VGA controller subsystemid 0x17aa 0x21f5 diff --git a/src/mainboard/lenovo/t530/variants/w530/romstage.c b/src/mainboard/lenovo/t530/variants/w530/romstage.c index f3ccc14266..7458d1ad4d 100644 --- a/src/mainboard/lenovo/t530/variants/w530/romstage.c +++ b/src/mainboard/lenovo/t530/variants/w530/romstage.c @@ -1,16 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x52, id_only); - read_spd(&spd[2], 0x51, id_only); - read_spd(&spd[3], 0x53, id_only); -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* P0: USB double port upper, USB3, OC 0 */ { 1, 1, 1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */ diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index beb26095d4..96385ed2cd 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -14,6 +14,8 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" + device domain 0 on subsystemid 0x17aa 0x21fe inherit diff --git a/src/mainboard/lenovo/x131e/early_init.c b/src/mainboard/lenovo/x131e/early_init.c index 9ace77820b..410dea6aff 100644 --- a/src/mainboard/lenovo/x131e/early_init.c +++ b/src/mainboard/lenovo/x131e/early_init.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -19,9 +18,3 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { {0, 0, 0}, {1, 0, -1}, /* P13: Bluetooth (no OC) */ }; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c index 6f18feee91..00d94e69ab 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c @@ -1,12 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> #include <string.h> #include <console/console.h> -#include <northbridge/intel/sandybridge/raminit_native.h> +#include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include <cbfs.h> const struct southbridge_usb_port mainboard_usb_ports[] = { /* enabled, current, OC pin */ @@ -26,27 +24,10 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, -1 },/* P13 Camera */ }; -static uint8_t *get_spd_data(int spd_index) +static unsigned int get_spd_index(void) { - uint8_t *spd_file; - size_t spd_file_len; - - printk(BIOS_DEBUG, "spd index %d\n", spd_index); - spd_file = cbfs_map("spd.bin", &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < spd_index * 256) - die("Missing SPD data."); - - return spd_file + spd_index * 256; -} - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - uint8_t *memory; const int spd_gpio_vector[] = {25, 45, -1}; - int spd_index = get_gpios(spd_gpio_vector); + unsigned int spd_index = get_gpios(spd_gpio_vector); /* 4gb model = 0, 8gb model = 1 */ /* int extended_memory_version = get_gpio(44); */ @@ -69,7 +50,12 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) if (spd_index == 3) die("Unsupported Memory. (detected 'reserved' memory configuration)."); - memory = get_spd_data(spd_index); - memcpy(&spd[0], memory, 256); - memcpy(&spd[2], memory, 256); + return spd_index; +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + spdi->addresses[0] = SPD_MEMORY_DOWN; + spdi->addresses[2] = SPD_MEMORY_DOWN; + spdi->spd_index = get_spd_index(); } diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 049eea6d84..b6736d2412 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -15,6 +15,7 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" + register "spd_addresses" = "{0x50, 0, 0x51, 0}" register "ec_present" = "1" # I have an embedded controller register "max_mem_clock_mhz" = "666" # So DDR3 freq = 1333 diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c index 8edb0dd735..f969b4feb3 100644 --- a/src/mainboard/lenovo/x220/early_init.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -1,21 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/hpet.h> #include <stdint.h> #include <northbridge/intel/sandybridge/raminit.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/gpio.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { - const uint8_t spdaddr[] = {0xa0, 0x00, 0xa2, 0x00}; - - memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses)); -} - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); } diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index fdd5059e6a..52a2e70a22 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -15,6 +15,7 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" + register "spd_addresses" = "{0x50, 0, 0x51, 0}" device domain 0 on subsystemid 0x17aa 0x21fa inherit diff --git a/src/mainboard/lenovo/x230/variants/x230/early_init.c b/src/mainboard/lenovo/x230/variants/x230/early_init.c index 5fe81791de..7084e9a0b0 100644 --- a/src/mainboard/lenovo/x230/variants/x230/early_init.c +++ b/src/mainboard/lenovo/x230/variants/x230/early_init.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> @@ -20,9 +19,3 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, -1 }, /* P12: wlan, no OC */ { 1, 1, -1 }, /* P13: webcam, no OC */ }; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); -} diff --git a/src/mainboard/lenovo/x230/variants/x230s/early_init.c b/src/mainboard/lenovo/x230/variants/x230s/early_init.c index 362e7fa64a..16d11a37ce 100644 --- a/src/mainboard/lenovo/x230/variants/x230s/early_init.c +++ b/src/mainboard/lenovo/x230/variants/x230s/early_init.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -19,8 +18,3 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { {1, 3, -1}, /* B1P5: WLAN USB */ {1, 1, -1}, /* B1P6: Camera */ }; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); -} diff --git a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb index 1c0efd346b..9d020e31ce 100644 --- a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb +++ b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb @@ -11,6 +11,7 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "500" # 50ms register "gpu_panel_power_up_delay" = "2000" # 200ms + register "spd_addresses" = "{0x50, 0, 0, 0}" device domain 0 on subsystemid 0x17aa 0x2209 inherit chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index a2c0237209..90eea95cb7 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -1,4 +1,5 @@ chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0, 0x52, 0}" device domain 0 on subsystemid 0x1462 0x7707 inherit diff --git a/src/mainboard/msi/ms7707/early_init.c b/src/mainboard/msi/ms7707/early_init.c index a859cd19af..24ba8ebfa5 100644 --- a/src/mainboard/msi/ms7707/early_init.c +++ b/src/mainboard/msi/ms7707/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/pci_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/bd82x6x/pch.h> @@ -29,9 +28,3 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { {1, 0, 5}, {1, 0, 6}, }; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 0e952b7a28..9da9cb88e1 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -22,6 +22,7 @@ chip northbridge/intel/sandybridge register "usb3.preboot_support" = "1" register "usb3.xhci_streams" = "1" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" register "ec_present" = "1" register "max_mem_clock_mhz" = "800" diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c index 328de9d022..5de8f563d6 100644 --- a/src/mainboard/roda/rv11/variants/rv11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c @@ -1,18 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/hpet.h> -#include <stdint.h> #include <northbridge/intel/sandybridge/raminit.h> -#include <northbridge/intel/sandybridge/raminit_native.h> -#include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> -void mainboard_fill_pei_data(struct pei_data *const pei_data) +void mainboard_fill_pei_data(struct pei_data *pei_data) { - const uint8_t spdaddr[] = {0xA0, 0x00, 0xA4, 0x00}; - - memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses)); - /* TODO: Confirm if need to enable peg10 in devicetree */ pei_data->pcie_init = 1; } @@ -34,9 +26,3 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 8 }, /* P12: Touch Screen USB2 (no OC) */ { 1, 0, 5 }, /* P13: reserved? USB2 (OC #5) */ }; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index d2c38f3c10..9dae3fffa6 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -17,6 +17,7 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x00000ac8" register "gpu_pch_backlight" = "0x13120000" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" register "ec_present" = "1" register "max_mem_clock_mhz" = "800" diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c index ffe095d23c..451c4b795b 100644 --- a/src/mainboard/roda/rv11/variants/rw11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c @@ -6,8 +6,6 @@ #include <device/pnp_ops.h> #include <device/pnp.h> #include <northbridge/intel/sandybridge/raminit.h> -#include <northbridge/intel/sandybridge/raminit_native.h> -#include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/ite/it8783ef/it8783ef.h> #include <superio/ite/common/ite.h> @@ -37,12 +35,8 @@ void bootblock_mainboard_early_init(void) pnp_exit_conf_state(dev); } -void mainboard_fill_pei_data(struct pei_data *const pei_data) +void mainboard_fill_pei_data(struct pei_data *pei_data) { - const uint8_t spdaddr[] = {0xA0, 0xA2, 0xA4, 0xA6}; - - memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses)); - /* TODO: Confirm if need to enable peg10 in devicetree */ pei_data->pcie_init = 1; } @@ -64,11 +58,3 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 8 }, /* P12: misc internal USB2 (no OC) */ { 1, 1, 6 }, /* P13: misc internal USB2 (OC #6) */ }; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index 495d04eae8..5b355a206b 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -1,20 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/hpet.h> #include <stdint.h> #include <string.h> #include <arch/io.h> #include <bootblock_common.h> -#include <cbfs.h> #include <console/console.h> #include <bootmode.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <superio/smsc/lpc47n207/lpc47n207.h> -#include "option_table.h" void bootblock_mainboard_early_init(void) { @@ -61,12 +57,8 @@ void mainboard_late_rcba_config(void) DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); } -static const uint8_t *locate_spd(void) +static unsigned int get_spd_index(void) { - typedef const uint8_t spd_blob[256]; - spd_blob *spd_data; - size_t spd_file_len; - u32 gp_lvl2 = inl(DEFAULT_GPIOBASE + 0x38); u8 gpio33, gpio41, gpio49; gpio33 = (gp_lvl2 >> (33-32)) & 1; @@ -80,7 +72,7 @@ static const uint8_t *locate_spd(void) printk(BIOS_DEBUG, " - vendor %s\n", gpio49 ? "Samsung" : "Other"); - int spd_index = 0; + unsigned int spd_index = 0; switch ((gpio49 << 2) | (gpio41 << 1) | gpio33) { case 0: // Other 1G Rev 1 @@ -104,25 +96,16 @@ static const uint8_t *locate_spd(void) spd_index = 5; break; } - - spd_data = cbfs_map("spd.bin", &spd_file_len); - if (!spd_data) - die("SPD data not found."); - if (spd_file_len < (spd_index + 1) * 256) - die("Missing SPD data."); - return spd_data[spd_index]; + return spd_index; } void mainboard_fill_pei_data(struct pei_data *pei_data) { - const uint8_t spdaddr[] = {0xa0, 0x00, 0x00, 0x00}; const uint8_t tsaddr[] = {0x30, 0x00, 0x00, 0x00}; /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ - memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses)); /* Only this board uses .ts_addresses. Fill here to allow removal from devicetree. */ memcpy(pei_data->ts_addresses, &tsaddr, sizeof(pei_data->ts_addresses)); - memcpy(pei_data->spd_data[2], locate_spd(), 256); } const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -143,10 +126,9 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 0, -1 }, /* P13: Empty */ }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) +void mb_get_spd_map(struct spd_info *spdi) { - /* get onboard dimm spd */ - memcpy(&spd[2], locate_spd(), 256); - /* read removable dimm spd */ - read_spd(&spd[0], 0x50, id_only); + spdi->addresses[0] = 0x50; + spdi->addresses[2] = SPD_MEMORY_DOWN; + spdi->spd_index = get_spd_index(); } diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index 6847726308..ae3aab5078 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -9,6 +9,7 @@ chip northbridge/intel/sandybridge # Enable DVI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" register "max_mem_clock_mhz" = "666" register "usb_port_config" = "{ diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index d4c1cc5166..681373c7d8 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -1,16 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/hpet.h> #include <bootblock_common.h> #include <stdint.h> #include <pc80/mc146818rtc.h> -#include <console/console.h> #include <bootmode.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8772f/it8772f.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <superio/smsc/lpc47n207/lpc47n207.h> @@ -91,19 +88,9 @@ static void setup_sio_gpios(void) void mainboard_fill_pei_data(struct pei_data *pei_data) { - const uint8_t spdaddr[] = {0xa0, 0x00, 0xa4, 0x00}; - - memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses)); - /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ } -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} - const struct southbridge_usb_port mainboard_usb_ports[] = { /* enabled power USB oc pin */ { 1, 1, 0 }, /* P0: Front port (OC0) */ diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index 9e6789df3a..87d1532df9 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0, 0x51, 0}" device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "gen1_dec" = "0x000c0291" diff --git a/src/mainboard/sapphire/pureplatinumh61/early_init.c b/src/mainboard/sapphire/pureplatinumh61/early_init.c index f2ab137c0f..8749e49925 100644 --- a/src/mainboard/sapphire/pureplatinumh61/early_init.c +++ b/src/mainboard/sapphire/pureplatinumh61/early_init.c @@ -2,7 +2,6 @@ #include <device/pci_ops.h> #include <device/pci_def.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> void mainboard_pch_lpc_setup(void) @@ -26,9 +25,3 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 5 }, { 1, 0, 6 }, }; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); -} diff --git a/src/mainboard/supermicro/x9sae/devicetree.cb b/src/mainboard/supermicro/x9sae/devicetree.cb index 12cbbaff3b..f5183819d1 100644 --- a/src/mainboard/supermicro/x9sae/devicetree.cb +++ b/src/mainboard/supermicro/x9sae/devicetree.cb @@ -6,6 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" register "gpu_panel_power_cycle_delay" = "4" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" device domain 0 on subsystemid 0x15d9 0x0644 inherit diff --git a/src/mainboard/supermicro/x9sae/early_init.c b/src/mainboard/supermicro/x9sae/early_init.c index 7e032120bc..5966b6607d 100644 --- a/src/mainboard/supermicro/x9sae/early_init.c +++ b/src/mainboard/supermicro/x9sae/early_init.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <device/pnp_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> @@ -52,11 +51,3 @@ void bootblock_mainboard_early_init(void) /* Enable UART */ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb index e20aac28c2..203a7a64ee 100644 --- a/src/mainboard/supermicro/x9scl/devicetree.cb +++ b/src/mainboard/supermicro/x9scl/devicetree.cb @@ -1,4 +1,5 @@ chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" device domain 0 on subsystemid 0x15d9 0x0624 inherit device ref host_bridge on end # Host bridge diff --git a/src/mainboard/supermicro/x9scl/early_init.c b/src/mainboard/supermicro/x9scl/early_init.c index 9438a51420..288666654d 100644 --- a/src/mainboard/supermicro/x9scl/early_init.c +++ b/src/mainboard/supermicro/x9scl/early_init.c @@ -1,12 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> #include <device/pci_ops.h> #include <device/pnp_def.h> #include <device/pnp_ops.h> #include <bootblock_common.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> @@ -103,14 +101,6 @@ void bootblock_mainboard_early_init(void) bmc_init(); } -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} - void mainboard_early_init(int s3resume) { /* Disable IGD VGA decode, no GTT or GFX stolen */ |