diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2022-10-07 18:24:58 +0200 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-10-22 16:39:05 +0000 |
| commit | 436f1c471a576d36101d7ef42e29d2c4e28950e6 (patch) | |
| tree | 3354b40e1b314d5a8aeeeef06efd3e2309c4e12b /src | |
| parent | 036b16b884725c044c82724c005b823a8663c970 (diff) | |
mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M
Apollo Lake seems to start with PCIe root ports unusable/uninitialized
before FspMemoryInit() is called and FSP-M properly initializes these
root ports.
However, we need the root ports accessible before FspMemoryInit() in
certain cases, such as emitting POST codes through a PCIe device.
For the initialization to happen properly, certain register writes
specified in Apollo Lake IAFW BIOS spec, vol. 2 (#559811), chapter
3.3.1 have to be done.
BUG=none
TEST=Boot on siemens/mc_apl2 with NC_FPGA_POST_CODE enabled and check
that the POST codes are emitted before FspMemoryInit().
Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68223
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/bootblock.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_apl1/bootblock.c b/src/mainboard/siemens/mc_apl1/bootblock.c index a858f1b048..7aab2a0f07 100644 --- a/src/mainboard/siemens/mc_apl1/bootblock.c +++ b/src/mainboard/siemens/mc_apl1/bootblock.c @@ -2,7 +2,26 @@ #include <baseboard/variants.h> #include <bootblock_common.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> #include <intelblocks/gpio.h> +#include <types.h> + +static void pcie_rp_early_enable(void) +{ + const pci_devfn_t rp_dev = PCI_DEV(0, CONFIG_EARLY_PCI_BRIDGE_DEVICE, + CONFIG_EARLY_PCI_BRIDGE_FUNCTION); + + if (pci_read_config16(rp_dev, PCI_VENDOR_ID) == 0xffff) + return; + + /* + * Needs to be done "immediately after PERST# de-assertion" + * as per IAFW BIOS spec volume 2 (doc 559811) + */ + pci_and_config32(rp_dev, 0x338, ~(1 << 26)); /* BLKDQDA */ + pci_and_config32(rp_dev, 0xf4, ~(1 << 2)); /* BLKPLLEN */ +} void bootblock_mainboard_early_init(void) { @@ -11,4 +30,8 @@ void bootblock_mainboard_early_init(void) pads = variant_early_gpio_table(&num); gpio_configure_pads(pads, num); + + /* Enable the PCIe root port when used before FSP-M MemoryInit() */ + if (CONFIG(EARLY_PCI_BRIDGE)) + pcie_rp_early_enable(); } |