diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-09-08 07:45:23 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-09-23 06:37:38 +0000 |
| commit | cbc609957fb8feedc7eb7795a3324cf364c178f1 (patch) | |
| tree | eef08338f05bb1304899f488ea5ffd4100cc016f /src/vendorcode/intel/fsp/fsp2_0 | |
| parent | bf46ba5adbd7cec13986d8b6584a2a14bfc9109e (diff) | |
soc/intel/xeon_sp/cpx: Rename FSP UPDs using CPP
coreboot expects different names for FSP UPDs so use some CPP to make
it happy.
Change-Id: I4b2c2dd6ba40cb58bc2089eb9204fd4f70b037aa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index 8abff098ae..8533c364c7 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -35,14 +35,6 @@ are permitted provided that the following conditions are met: #include <FspUpd.h> -/* - * Intel CPX-SP FSP has been using FSPM_CONFIG intead of FSP_M_CONFIG. - * Other Intel FSPs have been using FSP_M_CONFIG. The feedback from Intel - * is that they will converge to use FSPM_CONFIG over time. So both will - * co-exist for some time. Today coreboot common code expects FSP_M_CONFIG. - */ -#define FSP_M_CONFIG FSPM_CONFIG - #define SPEED_REC_96GT 0 #define SPEED_REC_104GT 1 #define ADAPTIVE_CTLE 0x3f |