diff options
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h | 11 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h | 8 |
3 files changed, 13 insertions, 8 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index ac8d837322..67d7584ac5 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -17,6 +17,8 @@ ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx +CPPFLAGS_common += -include $(src)/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h + cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-0b endif ## CONFIG_SOC_INTEL_COOPERLAKE_SP diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h b/src/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h new file mode 100644 index 0000000000..55b2e990db --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _FSP_UPD_H_ +#define _FSP_UPD_H_ + +/* Rename the FSP UPD structs to what they were historically called on other platforms. */ +#define FSP_T_CONFIG FSPT_CONFIG +#define FSP_M_CONFIG FSPM_CONFIG +#define FSP_S_CONFIG FSPS_CONFIG + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index 8abff098ae..8533c364c7 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -35,14 +35,6 @@ are permitted provided that the following conditions are met: #include <FspUpd.h> -/* - * Intel CPX-SP FSP has been using FSPM_CONFIG intead of FSP_M_CONFIG. - * Other Intel FSPs have been using FSP_M_CONFIG. The feedback from Intel - * is that they will converge to use FSPM_CONFIG over time. So both will - * co-exist for some time. Today coreboot common code expects FSP_M_CONFIG. - */ -#define FSP_M_CONFIG FSPM_CONFIG - #define SPEED_REC_96GT 0 #define SPEED_REC_104GT 1 #define ADAPTIVE_CTLE 0x3f |