diff options
| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-11-12 20:19:04 -0800 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2020-11-15 05:14:55 +0000 |
| commit | 34c59056143f3611083fe8f6a88e9920f6a8531e (patch) | |
| tree | f0ca7cff126f2443694b375277131dcb68866915 /src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h | |
| parent | c66e1c2a319a682a4616589901df301a816076ae (diff) | |
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3444
Update FSP headers for Tiger Lake platform generated based on FSP
version 3444. Previous version was 3425.
BUG=b:173160613
BRANCH=none
TEST=build and boot delbin
Cq-Depend:chrome-internal:3403586, chrome-internal:3403392
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I9e5de1617d00cd7543d4de1660f448e2fe220b0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47555
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 6038b13eff..35cc43bcbb 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -2498,7 +2498,7 @@ typedef struct { /** Offset 0x091C - Reserved **/ - UINT8 Reserved45[36]; + UINT8 Reserved45[44]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -2517,11 +2517,11 @@ typedef struct { **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0940 +/** Offset 0x0948 **/ UINT8 UnusedUpdSpace27[6]; -/** Offset 0x0946 +/** Offset 0x094E **/ UINT16 UpdTerminator; } FSPM_UPD; |