vendorcode/intel: Add UDK2017 support

This patch includes (edk2/UDK2017) all required headers for UDK2017
from EDK2 github project using below command

>> git clone https://github.com/tianocore/edk2.git vUDK2017

commit hash: 66833b2a87d98be8d81d1337c193bcbf0de47d47

Change-Id: If0d5a3fef016c67e9eed6aed9b698b3b13b930c4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

78 files changed, 41647 insertions, 0 deletions

diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi.h
new file mode 100644
index 0000000000..1710ad596f
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi.h
@@ -0,0 +1,21 @@
+/** @file
+  This file contains the latest ACPI definitions that are
+  consumed by drivers that do not care about ACPI versions.
+
+  Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _ACPI_H_
+#define _ACPI_H_
+
+#include <IndustryStandard/Acpi62.h>
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi10.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi10.h
new file mode 100644
index 0000000000..5a17db6ac5
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi10.h
@@ -0,0 +1,661 @@
+/** @file   
+  ACPI 1.0b definitions from the ACPI Specification, revision 1.0b
+
+Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under 
+the terms and conditions of the BSD License that accompanies this distribution.  
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.                                          
+    
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+**/
+
+#ifndef _ACPI_1_0_H_
+#define _ACPI_1_0_H_
+
+#include <IndustryStandard/AcpiAml.h>
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure.
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+} EFI_ACPI_COMMON_HEADER;
+
+#pragma pack(1)
+///
+/// The common ACPI description table header.  This structure prefaces most ACPI tables.
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+  UINT8   Revision;
+  UINT8   Checksum;
+  UINT8   OemId[6];
+  UINT64  OemTableId;
+  UINT32  OemRevision;
+  UINT32  CreatorId;
+  UINT32  CreatorRevision;
+} EFI_ACPI_DESCRIPTION_HEADER;
+#pragma pack()
+
+//
+// Define for Desriptor
+//
+#define ACPI_SMALL_ITEM_FLAG                   0x00
+#define ACPI_LARGE_ITEM_FLAG                   0x01
+
+//
+// Small Item Descriptor Name
+//
+#define ACPI_SMALL_IRQ_DESCRIPTOR_NAME                       0x04
+#define ACPI_SMALL_DMA_DESCRIPTOR_NAME                       0x05
+#define ACPI_SMALL_START_DEPENDENT_DESCRIPTOR_NAME           0x06
+#define ACPI_SMALL_END_DEPENDENT_DESCRIPTOR_NAME             0x07
+#define ACPI_SMALL_IO_PORT_DESCRIPTOR_NAME                   0x08
+#define ACPI_SMALL_FIXED_IO_PORT_DESCRIPTOR_NAME             0x09
+#define ACPI_SMALL_VENDOR_DEFINED_DESCRIPTOR_NAME            0x0E
+#define ACPI_SMALL_END_TAG_DESCRIPTOR_NAME                   0x0F
+
+//
+// Large Item Descriptor Name
+//
+#define ACPI_LARGE_24_BIT_MEMORY_RANGE_DESCRIPTOR_NAME       0x01
+#define ACPI_LARGE_VENDOR_DEFINED_DESCRIPTOR_NAME            0x04
+#define ACPI_LARGE_32_BIT_MEMORY_RANGE_DESCRIPTOR_NAME       0x05
+#define ACPI_LARGE_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR_NAME 0x06
+#define ACPI_LARGE_DWORD_ADDRESS_SPACE_DESCRIPTOR_NAME       0x07
+#define ACPI_LARGE_WORD_ADDRESS_SPACE_DESCRIPTOR_NAME        0x08
+#define ACPI_LARGE_EXTENDED_IRQ_DESCRIPTOR_NAME              0x09
+#define ACPI_LARGE_QWORD_ADDRESS_SPACE_DESCRIPTOR_NAME       0x0A
+
+//
+// Small Item Descriptor Value
+//
+#define ACPI_IRQ_NOFLAG_DESCRIPTOR                0x22
+#define ACPI_IRQ_DESCRIPTOR                       0x23
+#define ACPI_DMA_DESCRIPTOR                       0x2A
+#define ACPI_START_DEPENDENT_DESCRIPTOR           0x30
+#define ACPI_START_DEPENDENT_EX_DESCRIPTOR        0x31
+#define ACPI_END_DEPENDENT_DESCRIPTOR             0x38
+#define ACPI_IO_PORT_DESCRIPTOR                   0x47
+#define ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR    0x4B
+#define ACPI_END_TAG_DESCRIPTOR                   0x79
+
+//
+// Large Item Descriptor Value
+//
+#define ACPI_24_BIT_MEMORY_RANGE_DESCRIPTOR       0x81
+#define ACPI_32_BIT_MEMORY_RANGE_DESCRIPTOR       0x85
+#define ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR 0x86
+#define ACPI_DWORD_ADDRESS_SPACE_DESCRIPTOR       0x87
+#define ACPI_WORD_ADDRESS_SPACE_DESCRIPTOR        0x88
+#define ACPI_EXTENDED_INTERRUPT_DESCRIPTOR        0x89
+#define ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR       0x8A
+#define ACPI_ADDRESS_SPACE_DESCRIPTOR             0x8A
+
+//
+// Resource Type
+//
+#define ACPI_ADDRESS_SPACE_TYPE_MEM   0x00
+#define ACPI_ADDRESS_SPACE_TYPE_IO    0x01
+#define ACPI_ADDRESS_SPACE_TYPE_BUS   0x02
+
+///
+/// Power Management Timer frequency is fixed at 3.579545MHz.
+///
+#define ACPI_TIMER_FREQUENCY       3579545
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// The commond definition of QWORD, DWORD, and WORD
+/// Address Space Descriptors.
+///
+typedef PACKED struct {
+  UINT8   Desc;
+  UINT16  Len;
+  UINT8   ResType;
+  UINT8   GenFlag;
+  UINT8   SpecificFlag;
+  UINT64  AddrSpaceGranularity;
+  UINT64  AddrRangeMin;
+  UINT64  AddrRangeMax;
+  UINT64  AddrTranslationOffset;
+  UINT64  AddrLen;
+} EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR;
+
+typedef PACKED union {
+  UINT8     Byte;
+  PACKED struct {
+    UINT8 Length : 3;
+    UINT8 Name : 4;
+    UINT8 Type : 1;
+  } Bits;
+} ACPI_SMALL_RESOURCE_HEADER;
+
+typedef PACKED struct {
+  PACKED union {
+    UINT8 Byte;
+    PACKED struct {
+      UINT8 Name : 7;
+      UINT8 Type : 1;
+    }Bits;
+  } Header;
+  UINT16 Length;
+} ACPI_LARGE_RESOURCE_HEADER;
+
+///
+/// IRQ Descriptor.
+///
+typedef PACKED struct {
+  ACPI_SMALL_RESOURCE_HEADER   Header;
+  UINT16                       Mask;
+} EFI_ACPI_IRQ_NOFLAG_DESCRIPTOR;
+
+///
+/// IRQ Descriptor.
+///
+typedef PACKED struct {
+  ACPI_SMALL_RESOURCE_HEADER   Header;
+  UINT16                       Mask;
+  UINT8                        Information;
+} EFI_ACPI_IRQ_DESCRIPTOR;
+
+///
+/// DMA Descriptor.
+///
+typedef PACKED struct {
+  ACPI_SMALL_RESOURCE_HEADER   Header;
+  UINT8                        ChannelMask;
+  UINT8                        Information;
+} EFI_ACPI_DMA_DESCRIPTOR;
+
+///
+/// I/O Port Descriptor
+///
+typedef PACKED struct {
+  ACPI_SMALL_RESOURCE_HEADER   Header;
+  UINT8                        Information;
+  UINT16                       BaseAddressMin;
+  UINT16                       BaseAddressMax;
+  UINT8                        Alignment;
+  UINT8                        Length;
+} EFI_ACPI_IO_PORT_DESCRIPTOR;
+
+///
+/// Fixed Location I/O Port Descriptor.
+///
+typedef PACKED struct {
+  ACPI_SMALL_RESOURCE_HEADER   Header;
+  UINT16                       BaseAddress;
+  UINT8                        Length;
+} EFI_ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR;
+
+///
+/// 24-Bit Memory Range Descriptor
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         Information;
+  UINT16                        BaseAddressMin;
+  UINT16                        BaseAddressMax;
+  UINT16                        Alignment;
+  UINT16                        Length;
+} EFI_ACPI_24_BIT_MEMORY_RANGE_DESCRIPTOR;
+
+///
+/// 32-Bit Memory Range Descriptor
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         Information;
+  UINT32                        BaseAddressMin;
+  UINT32                        BaseAddressMax;
+  UINT32                        Alignment;
+  UINT32                        Length;
+} EFI_ACPI_32_BIT_MEMORY_RANGE_DESCRIPTOR;
+
+///
+/// Fixed 32-Bit Fixed Memory Range Descriptor
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         Information;
+  UINT32                        BaseAddress;
+  UINT32                        Length;
+} EFI_ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR;
+
+///
+/// QWORD Address Space Descriptor
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         ResType;
+  UINT8                         GenFlag;
+  UINT8                         SpecificFlag;
+  UINT64                        AddrSpaceGranularity;
+  UINT64                        AddrRangeMin;
+  UINT64                        AddrRangeMax;
+  UINT64                        AddrTranslationOffset;
+  UINT64                        AddrLen;
+} EFI_ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR;
+
+///
+/// DWORD Address Space Descriptor
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         ResType;
+  UINT8                         GenFlag;
+  UINT8                         SpecificFlag;
+  UINT32                        AddrSpaceGranularity;
+  UINT32                        AddrRangeMin;
+  UINT32                        AddrRangeMax;
+  UINT32                        AddrTranslationOffset;
+  UINT32                        AddrLen;
+} EFI_ACPI_DWORD_ADDRESS_SPACE_DESCRIPTOR;
+
+///
+/// WORD Address Space Descriptor
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         ResType;
+  UINT8                         GenFlag;
+  UINT8                         SpecificFlag;
+  UINT16                        AddrSpaceGranularity;
+  UINT16                        AddrRangeMin;
+  UINT16                        AddrRangeMax;
+  UINT16                        AddrTranslationOffset;
+  UINT16                        AddrLen;
+} EFI_ACPI_WORD_ADDRESS_SPACE_DESCRIPTOR;
+
+///
+/// Extended Interrupt Descriptor
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         InterruptVectorFlags;
+  UINT8                         InterruptTableLength;
+  UINT32                        InterruptNumber[1];
+} EFI_ACPI_EXTENDED_INTERRUPT_DESCRIPTOR;
+
+#pragma pack()
+
+///
+/// The End tag identifies an end of resource data.
+///
+typedef struct {
+  UINT8 Desc;
+  UINT8 Checksum;
+} EFI_ACPI_END_TAG_DESCRIPTOR;
+
+//
+// General use definitions
+//
+#define EFI_ACPI_RESERVED_BYTE  0x00
+#define EFI_ACPI_RESERVED_WORD  0x0000
+#define EFI_ACPI_RESERVED_DWORD 0x00000000
+#define EFI_ACPI_RESERVED_QWORD 0x0000000000000000
+
+//
+// Resource Type Specific Flags
+// Ref ACPI specification 6.4.3.5.5
+//
+// Bit [0]    : Write Status, _RW
+//
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_WRITE                (1 << 0)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_ONLY                 (0 << 0)
+//
+// Bit [2:1]  : Memory Attributes, _MEM
+//
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_NON_CACHEABLE             (0 << 1)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE                 (1 << 1)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_WRITE_COMBINING (2 << 1)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE    (3 << 1)
+//
+// Bit [4:3]  : Memory Attributes, _MTP
+//
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_MEMORY      (0 << 3)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_RESERVED    (1 << 3)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_ACPI        (2 << 3)
+#define EFI_APCI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_NVS         (3 << 3)
+//
+// Bit [5]    : Memory to I/O Translation, _TTP
+//
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_TRANSLATION          (1 << 5)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_STATIC               (0 << 5)
+
+//
+// IRQ Information
+// Ref ACPI specification 6.4.2.1
+//
+#define EFI_ACPI_IRQ_SHARABLE_MASK                      0x10
+#define   EFI_ACPI_IRQ_SHARABLE                         0x10
+
+#define EFI_ACPI_IRQ_POLARITY_MASK                      0x08
+#define   EFI_ACPI_IRQ_HIGH_TRUE                        0x00
+#define   EFI_ACPI_IRQ_LOW_FALSE                        0x08
+
+#define EFI_ACPI_IRQ_MODE                               0x01
+#define   EFI_ACPI_IRQ_LEVEL_TRIGGERED                  0x00
+#define   EFI_ACPI_IRQ_EDGE_TRIGGERED                   0x01
+
+//
+// DMA Information
+// Ref ACPI specification 6.4.2.2
+//
+#define EFI_ACPI_DMA_SPEED_TYPE_MASK                    0x60
+#define   EFI_ACPI_DMA_SPEED_TYPE_COMPATIBILITY         0x00
+#define   EFI_ACPI_DMA_SPEED_TYPE_A                     0x20
+#define   EFI_ACPI_DMA_SPEED_TYPE_B                     0x40
+#define   EFI_ACPI_DMA_SPEED_TYPE_F                     0x60
+                                               
+#define EFI_ACPI_DMA_BUS_MASTER_MASK                    0x04
+#define   EFI_ACPI_DMA_BUS_MASTER                       0x04
+
+#define EFI_ACPI_DMA_TRANSFER_TYPE_MASK                 0x03
+#define   EFI_ACPI_DMA_TRANSFER_TYPE_8_BIT              0x00
+#define   EFI_ACPI_DMA_TRANSFER_TYPE_8_BIT_AND_16_BIT   0x01
+#define   EFI_ACPI_DMA_TRANSFER_TYPE_16_BIT             0x10
+
+//
+// IO Information
+// Ref ACPI specification 6.4.2.5
+//
+#define EFI_ACPI_IO_DECODE_MASK                         0x01
+#define   EFI_ACPI_IO_DECODE_16_BIT                     0x01
+#define   EFI_ACPI_IO_DECODE_10_BIT                     0x00
+
+//
+// Memory Information
+// Ref ACPI specification 6.4.3.4
+//
+#define EFI_ACPI_MEMORY_WRITE_STATUS_MASK               0x01
+#define   EFI_ACPI_MEMORY_WRITABLE                      0x01
+#define   EFI_ACPI_MEMORY_NON_WRITABLE                  0x00
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+//
+// ACPI 1.0b table structures
+//
+
+///
+/// Root System Description Pointer Structure.
+///
+typedef struct {
+  UINT64  Signature;
+  UINT8   Checksum;
+  UINT8   OemId[6];
+  UINT8   Reserved;
+  UINT32  RsdtAddress;
+} EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with 
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 1.0b specification).
+///
+#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT).
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      FirmwareCtrl;
+  UINT32                      Dsdt;
+  UINT8                       IntModel;
+  UINT8                       Reserved1;
+  UINT16                      SciInt;
+  UINT32                      SmiCmd;
+  UINT8                       AcpiEnable;
+  UINT8                       AcpiDisable;
+  UINT8                       S4BiosReq;
+  UINT8                       Reserved2;
+  UINT32                      Pm1aEvtBlk;
+  UINT32                      Pm1bEvtBlk;
+  UINT32                      Pm1aCntBlk;
+  UINT32                      Pm1bCntBlk;
+  UINT32                      Pm2CntBlk;
+  UINT32                      PmTmrBlk;
+  UINT32                      Gpe0Blk;
+  UINT32                      Gpe1Blk;
+  UINT8                       Pm1EvtLen;
+  UINT8                       Pm1CntLen;
+  UINT8                       Pm2CntLen;
+  UINT8                       PmTmLen;
+  UINT8                       Gpe0BlkLen;
+  UINT8                       Gpe1BlkLen;
+  UINT8                       Gpe1Base;
+  UINT8                       Reserved3;
+  UINT16                      PLvl2Lat;
+  UINT16                      PLvl3Lat;
+  UINT16                      FlushSize;
+  UINT16                      FlushStride;
+  UINT8                       DutyOffset;
+  UINT8                       DutyWidth;
+  UINT8                       DayAlrm;
+  UINT8                       MonAlrm;
+  UINT8                       Century;
+  UINT8                       Reserved4;
+  UINT8                       Reserved5;
+  UINT8                       Reserved6;
+  UINT32                      Flags;
+} EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 1.0b specification).
+///
+#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION  0x01
+
+#define EFI_ACPI_1_0_INT_MODE_DUAL_PIC         0
+#define EFI_ACPI_1_0_INT_MODE_MULTIPLE_APIC    1
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_1_0_WBINVD               BIT0
+#define EFI_ACPI_1_0_WBINVD_FLUSH         BIT1
+#define EFI_ACPI_1_0_PROC_C1              BIT2
+#define EFI_ACPI_1_0_P_LVL2_UP            BIT3
+#define EFI_ACPI_1_0_PWR_BUTTON           BIT4
+#define EFI_ACPI_1_0_SLP_BUTTON           BIT5
+#define EFI_ACPI_1_0_FIX_RTC              BIT6
+#define EFI_ACPI_1_0_RTC_S4               BIT7
+#define EFI_ACPI_1_0_TMR_VAL_EXT          BIT8
+#define EFI_ACPI_1_0_DCK_CAP              BIT9
+
+///
+/// Firmware ACPI Control Structure.
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+  UINT32  HardwareSignature;
+  UINT32  FirmwareWakingVector;
+  UINT32  GlobalLock;
+  UINT32  Flags;
+  UINT8   Reserved[40];
+} EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// Firmware Control Structure Feature Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_1_0_S4BIOS_F             BIT0
+
+///
+/// Multiple APIC Description Table header definition.  The rest of the table
+/// must be defined in a platform-specific manner.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      LocalApicAddress;
+  UINT32                      Flags;
+} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 1.0b specification).
+///
+#define EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_1_0_PCAT_COMPAT           BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x05 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC           0x00
+#define EFI_ACPI_1_0_IO_APIC                        0x01
+#define EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE      0x02
+#define EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE  0x03
+#define EFI_ACPI_1_0_LOCAL_APIC_NMI                 0x04
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition.
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT8   ApicId;
+  UINT32  Flags;
+} EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_1_0_LOCAL_APIC_ENABLED      BIT0
+
+///
+/// IO APIC Structure.
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  IoApicAddress;
+  UINT32  SystemVectorBase;
+} EFI_ACPI_1_0_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure.
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Bus;
+  UINT8   Source;
+  UINT32  GlobalSystemInterruptVector;
+  UINT16  Flags;
+} EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Non-Maskable Interrupt Source Structure.
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT32  GlobalSystemInterruptVector;
+} EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure.
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT16  Flags;
+  UINT8   LocalApicInti;
+} EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      WarningEnergyLevel;
+  UINT32                      LowEnergyLevel;
+  UINT32                      CriticalEnergyLevel;
+} EFI_ACPI_1_0_SMART_BATTERY_DESCRIPTION_TABLE;
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer.
+///
+#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+
+///
+/// "APIC" Multiple APIC Description Table.
+///
+#define EFI_ACPI_1_0_APIC_SIGNATURE  SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "DSDT" Differentiated System Description Table.
+///
+#define EFI_ACPI_1_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "FACS" Firmware ACPI Control Structure.
+///
+#define EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "FACP" Fixed ACPI Description Table.
+///
+#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "PSDT" Persistent System Description Table.
+///
+#define EFI_ACPI_1_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RSDT" Root System Description Table.
+///
+#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table.
+///
+#define EFI_ACPI_1_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SSDT" Secondary System Description Table.
+///
+#define EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'S', 'D', 'T')
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi20.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi20.h
new file mode 100644
index 0000000000..d84b7db7b7
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi20.h
@@ -0,0 +1,545 @@
+/** @file   
+  ACPI 2.0 definitions from the ACPI Specification, revision 2.0
+
+  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+**/
+
+#ifndef _ACPI_2_0_H_
+#define _ACPI_2_0_H_
+
+#include <IndustryStandard/Acpi10.h>
+
+//
+// Define for Desriptor
+//
+#define ACPI_LARGE_GENERIC_REGISTER_DESCRIPTOR_NAME          0x02
+
+#define ACPI_GENERIC_REGISTER_DESCRIPTOR          0x82
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// Generic Register Descriptor
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         AddressSpaceId;
+  UINT8                         RegisterBitWidth;
+  UINT8                         RegisterBitOffset;
+  UINT8                         AddressSize;
+  UINT64                        RegisterAddress;
+} EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR;
+
+#pragma pack()
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 2.0 Generic Address Space definition
+///
+typedef struct {
+  UINT8   AddressSpaceId;
+  UINT8   RegisterBitWidth;
+  UINT8   RegisterBitOffset;
+  UINT8   Reserved;
+  UINT64  Address;
+} EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_2_0_SYSTEM_MEMORY              0
+#define EFI_ACPI_2_0_SYSTEM_IO                  1
+#define EFI_ACPI_2_0_PCI_CONFIGURATION_SPACE    2
+#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER        3
+#define EFI_ACPI_2_0_SMBUS                      4
+#define EFI_ACPI_2_0_FUNCTIONAL_FIXED_HARDWARE  0x7F
+
+//
+// ACPI 2.0 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+  UINT64  Signature;
+  UINT8   Checksum;
+  UINT8   OemId[6];
+  UINT8   Revision;
+  UINT32  RsdtAddress;
+  UINT32  Length;
+  UINT64  XsdtAddress;
+  UINT8   ExtendedChecksum;
+  UINT8   Reserved[3];
+} EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 2.0 spec.)
+///
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+} EFI_ACPI_2_0_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with 
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 2.0 spec.)
+///
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with 
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 2.0 spec.)
+///
+#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  UINT32                                  FirmwareCtrl;
+  UINT32                                  Dsdt;
+  UINT8                                   Reserved0;
+  UINT8                                   PreferredPmProfile;
+  UINT16                                  SciInt;
+  UINT32                                  SmiCmd;
+  UINT8                                   AcpiEnable;
+  UINT8                                   AcpiDisable;
+  UINT8                                   S4BiosReq;
+  UINT8                                   PstateCnt;
+  UINT32                                  Pm1aEvtBlk;
+  UINT32                                  Pm1bEvtBlk;
+  UINT32                                  Pm1aCntBlk;
+  UINT32                                  Pm1bCntBlk;
+  UINT32                                  Pm2CntBlk;
+  UINT32                                  PmTmrBlk;
+  UINT32                                  Gpe0Blk;
+  UINT32                                  Gpe1Blk;
+  UINT8                                   Pm1EvtLen;
+  UINT8                                   Pm1CntLen;
+  UINT8                                   Pm2CntLen;
+  UINT8                                   PmTmrLen;
+  UINT8                                   Gpe0BlkLen;
+  UINT8                                   Gpe1BlkLen;
+  UINT8                                   Gpe1Base;
+  UINT8                                   CstCnt;
+  UINT16                                  PLvl2Lat;
+  UINT16                                  PLvl3Lat;
+  UINT16                                  FlushSize;
+  UINT16                                  FlushStride;
+  UINT8                                   DutyOffset;
+  UINT8                                   DutyWidth;
+  UINT8                                   DayAlrm;
+  UINT8                                   MonAlrm;
+  UINT8                                   Century;
+  UINT16                                  IaPcBootArch;
+  UINT8                                   Reserved1;
+  UINT32                                  Flags;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  ResetReg;
+  UINT8                                   ResetValue;
+  UINT8                                   Reserved2[3];
+  UINT64                                  XFirmwareCtrl;
+  UINT64                                  XDsdt;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk;
+} EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 2.0 spec.)
+///
+#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION  0x03
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_2_0_PM_PROFILE_UNSPECIFIED         0
+#define EFI_ACPI_2_0_PM_PROFILE_DESKTOP             1
+#define EFI_ACPI_2_0_PM_PROFILE_MOBILE              2
+#define EFI_ACPI_2_0_PM_PROFILE_WORKSTATION         3
+#define EFI_ACPI_2_0_PM_PROFILE_ENTERPRISE_SERVER   4
+#define EFI_ACPI_2_0_PM_PROFILE_SOHO_SERVER         5
+#define EFI_ACPI_2_0_PM_PROFILE_APPLIANCE_PC        6
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_2_0_LEGACY_DEVICES          BIT0
+#define EFI_ACPI_2_0_8042                    BIT1
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_2_0_WBINVD                  BIT0
+#define EFI_ACPI_2_0_WBINVD_FLUSH            BIT1
+#define EFI_ACPI_2_0_PROC_C1                 BIT2
+#define EFI_ACPI_2_0_P_LVL2_UP               BIT3
+#define EFI_ACPI_2_0_PWR_BUTTON              BIT4
+#define EFI_ACPI_2_0_SLP_BUTTON              BIT5
+#define EFI_ACPI_2_0_FIX_RTC                 BIT6
+#define EFI_ACPI_2_0_RTC_S4                  BIT7
+#define EFI_ACPI_2_0_TMR_VAL_EXT             BIT8
+#define EFI_ACPI_2_0_DCK_CAP                 BIT9
+#define EFI_ACPI_2_0_RESET_REG_SUP           BIT10
+#define EFI_ACPI_2_0_SEALED_CASE             BIT11
+#define EFI_ACPI_2_0_HEADLESS                BIT12
+#define EFI_ACPI_2_0_CPU_SW_SLP              BIT13
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+  UINT32  HardwareSignature;
+  UINT32  FirmwareWakingVector;
+  UINT32  GlobalLock;
+  UINT32  Flags;
+  UINT64  XFirmwareWakingVector;
+  UINT8   Version;
+  UINT8   Reserved[31];
+} EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 2.0 spec.)
+///
+#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION  0x01
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_2_0_S4BIOS_F        BIT0
+
+///
+/// Multiple APIC Description Table header definition.  The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      LocalApicAddress;
+  UINT32                      Flags;
+} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 2.0 spec.)
+///
+#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_2_0_PCAT_COMPAT          BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x09 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC           0x00
+#define EFI_ACPI_2_0_IO_APIC                        0x01
+#define EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE      0x02
+#define EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE  0x03
+#define EFI_ACPI_2_0_LOCAL_APIC_NMI                 0x04
+#define EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE    0x05
+#define EFI_ACPI_2_0_IO_SAPIC                       0x06
+#define EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC          0x07
+#define EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES     0x08
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT8   ApicId;
+  UINT32  Flags;
+} EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED         BIT0
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  IoApicAddress;
+  UINT32  GlobalSystemInterruptBase;
+} EFI_ACPI_2_0_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Bus;
+  UINT8   Source;
+  UINT32  GlobalSystemInterrupt;
+  UINT16  Flags;
+} EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT32  GlobalSystemInterrupt;
+} EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT16  Flags;
+  UINT8   LocalApicLint;
+} EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT64  LocalApicAddress;
+} EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  GlobalSystemInterruptBase;
+  UINT64  IoSapicAddress;
+} EFI_ACPI_2_0_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT8   LocalSapicId;
+  UINT8   LocalSapicEid;
+  UINT8   Reserved[3];
+  UINT32  Flags;
+} EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT8   InterruptType;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT8   IoSapicVector;
+  UINT32  GlobalSystemInterrupt;
+  UINT32  Reserved;
+} EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      WarningEnergyLevel;
+  UINT32                      LowEnergyLevel;
+  UINT32                      CriticalEnergyLevel;
+} EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 2.0 spec.)
+///
+#define EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  EcControl;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  EcData;
+  UINT32                                  Uid;
+  UINT8                                   GpeBit;
+} EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 2.0 spec.)
+///
+#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION  0x01
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+
+///
+/// "SPIC" Multiple SAPIC Description Table
+///
+/// BUGBUG: Don't know where this came from except SR870BN4 uses it.
+/// #define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE 0x43495053
+///
+#define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_2_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE  SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "DBGP" MS Bebug Port Spec
+///
+#define EFI_ACPI_2_0_DEBUG_PORT_TABLE_SIGNATURE  SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE  SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_2_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_2_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_2_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_2_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SPCR" Serial Port Concole Redirection Table
+///
+#define EFI_ACPI_2_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SRAT" Static Resource Affinity Table
+///
+#define EFI_ACPI_2_0_STATIC_RESOURCE_AFFINITY_TABLE_SIGNATURE  SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_2_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_2_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_SIGNATURE  SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_2_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE  SIGNATURE_32('M', 'C', 'F', 'G')
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi30.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi30.h
new file mode 100644
index 0000000000..d510d8b934
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi30.h
@@ -0,0 +1,729 @@
+/** @file   
+  ACPI 3.0 definitions from the ACPI Specification Revision 3.0b October 10, 2006
+
+  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+**/
+
+#ifndef _ACPI_3_0_H_
+#define _ACPI_3_0_H_
+
+#include <IndustryStandard/Acpi20.h>
+
+//
+// Define for Desriptor
+//
+#define ACPI_LARGE_EXTENDED_ADDRESS_SPACE_DESCRIPTOR_NAME    0x0B
+
+#define ACPI_EXTENDED_ADDRESS_SPACE_DESCRIPTOR    0x8B
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// Extended Address Space Descriptor
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         ResType;
+  UINT8                         GenFlag;
+  UINT8                         SpecificFlag;
+  UINT8                         RevisionId;
+  UINT8                         Reserved;
+  UINT64                        AddrSpaceGranularity;
+  UINT64                        AddrRangeMin;
+  UINT64                        AddrRangeMax;
+  UINT64                        AddrTranslationOffset;
+  UINT64                        AddrLen;
+  UINT64                        TypeSpecificAttribute;
+} EFI_ACPI_EXTENDED_ADDRESS_SPACE_DESCRIPTOR;
+
+#pragma pack()
+
+//
+// Memory Type Specific Flags
+//
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_UC  0x0000000000000001
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WC  0x0000000000000002
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WT  0x0000000000000004
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WB  0x0000000000000008
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_UCE 0x0000000000000010
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_NV  0x0000000000008000
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 3.0 Generic Address Space definition
+///
+typedef struct {
+  UINT8   AddressSpaceId;
+  UINT8   RegisterBitWidth;
+  UINT8   RegisterBitOffset;
+  UINT8   AccessSize;
+  UINT64  Address;
+} EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_3_0_SYSTEM_MEMORY              0
+#define EFI_ACPI_3_0_SYSTEM_IO                  1
+#define EFI_ACPI_3_0_PCI_CONFIGURATION_SPACE    2
+#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER        3
+#define EFI_ACPI_3_0_SMBUS                      4
+#define EFI_ACPI_3_0_FUNCTIONAL_FIXED_HARDWARE  0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_3_0_UNDEFINED  0
+#define EFI_ACPI_3_0_BYTE       1
+#define EFI_ACPI_3_0_WORD       2
+#define EFI_ACPI_3_0_DWORD      3
+#define EFI_ACPI_3_0_QWORD      4
+
+//
+// ACPI 3.0 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+  UINT64  Signature;
+  UINT8   Checksum;
+  UINT8   OemId[6];
+  UINT8   Revision;
+  UINT32  RsdtAddress;
+  UINT32  Length;
+  UINT64  XsdtAddress;
+  UINT8   ExtendedChecksum;
+  UINT8   Reserved[3];
+} EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 3.0b spec.)
+///
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02  ///< ACPISpec (Revision 3.0b) says current value is 2
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+} EFI_ACPI_3_0_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with 
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 3.0 spec.)
+///
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with 
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 3.0 spec.)
+///
+#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  UINT32                                  FirmwareCtrl;
+  UINT32                                  Dsdt;
+  UINT8                                   Reserved0;
+  UINT8                                   PreferredPmProfile;
+  UINT16                                  SciInt;
+  UINT32                                  SmiCmd;
+  UINT8                                   AcpiEnable;
+  UINT8                                   AcpiDisable;
+  UINT8                                   S4BiosReq;
+  UINT8                                   PstateCnt;
+  UINT32                                  Pm1aEvtBlk;
+  UINT32                                  Pm1bEvtBlk;
+  UINT32                                  Pm1aCntBlk;
+  UINT32                                  Pm1bCntBlk;
+  UINT32                                  Pm2CntBlk;
+  UINT32                                  PmTmrBlk;
+  UINT32                                  Gpe0Blk;
+  UINT32                                  Gpe1Blk;
+  UINT8                                   Pm1EvtLen;
+  UINT8                                   Pm1CntLen;
+  UINT8                                   Pm2CntLen;
+  UINT8                                   PmTmrLen;
+  UINT8                                   Gpe0BlkLen;
+  UINT8                                   Gpe1BlkLen;
+  UINT8                                   Gpe1Base;
+  UINT8                                   CstCnt;
+  UINT16                                  PLvl2Lat;
+  UINT16                                  PLvl3Lat;
+  UINT16                                  FlushSize;
+  UINT16                                  FlushStride;
+  UINT8                                   DutyOffset;
+  UINT8                                   DutyWidth;
+  UINT8                                   DayAlrm;
+  UINT8                                   MonAlrm;
+  UINT8                                   Century;
+  UINT16                                  IaPcBootArch;
+  UINT8                                   Reserved1;
+  UINT32                                  Flags;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  ResetReg;
+  UINT8                                   ResetValue;
+  UINT8                                   Reserved2[3];
+  UINT64                                  XFirmwareCtrl;
+  UINT64                                  XDsdt;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk;
+} EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 3.0 spec.)
+///
+#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION  0x04
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_3_0_PM_PROFILE_UNSPECIFIED         0
+#define EFI_ACPI_3_0_PM_PROFILE_DESKTOP             1
+#define EFI_ACPI_3_0_PM_PROFILE_MOBILE              2
+#define EFI_ACPI_3_0_PM_PROFILE_WORKSTATION         3
+#define EFI_ACPI_3_0_PM_PROFILE_ENTERPRISE_SERVER   4
+#define EFI_ACPI_3_0_PM_PROFILE_SOHO_SERVER         5
+#define EFI_ACPI_3_0_PM_PROFILE_APPLIANCE_PC        6
+#define EFI_ACPI_3_0_PM_PROFILE_PERFORMANCE_SERVER  7
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_LEGACY_DEVICES              BIT0
+#define EFI_ACPI_3_0_8042                        BIT1
+#define EFI_ACPI_3_0_VGA_NOT_PRESENT             BIT2
+#define EFI_ACPI_3_0_MSI_NOT_SUPPORTED           BIT3
+#define EFI_ACPI_3_0_PCIE_ASPM_CONTROLS          BIT4
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_WBINVD                                 BIT0
+#define EFI_ACPI_3_0_WBINVD_FLUSH                           BIT1
+#define EFI_ACPI_3_0_PROC_C1                                BIT2
+#define EFI_ACPI_3_0_P_LVL2_UP                              BIT3
+#define EFI_ACPI_3_0_PWR_BUTTON                             BIT4
+#define EFI_ACPI_3_0_SLP_BUTTON                             BIT5
+#define EFI_ACPI_3_0_FIX_RTC                                BIT6
+#define EFI_ACPI_3_0_RTC_S4                                 BIT7
+#define EFI_ACPI_3_0_TMR_VAL_EXT                            BIT8
+#define EFI_ACPI_3_0_DCK_CAP                                BIT9
+#define EFI_ACPI_3_0_RESET_REG_SUP                          BIT10
+#define EFI_ACPI_3_0_SEALED_CASE                            BIT11
+#define EFI_ACPI_3_0_HEADLESS                               BIT12
+#define EFI_ACPI_3_0_CPU_SW_SLP                             BIT13
+#define EFI_ACPI_3_0_PCI_EXP_WAK                            BIT14
+#define EFI_ACPI_3_0_USE_PLATFORM_CLOCK                     BIT15
+#define EFI_ACPI_3_0_S4_RTC_STS_VALID                       BIT16
+#define EFI_ACPI_3_0_REMOTE_POWER_ON_CAPABLE                BIT17
+#define EFI_ACPI_3_0_FORCE_APIC_CLUSTER_MODEL               BIT18
+#define EFI_ACPI_3_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE   BIT19
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+  UINT32  HardwareSignature;
+  UINT32  FirmwareWakingVector;
+  UINT32  GlobalLock;
+  UINT32  Flags;
+  UINT64  XFirmwareWakingVector;
+  UINT8   Version;
+  UINT8   Reserved[31];
+} EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 3.0 spec.)
+///
+#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION  0x01
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_3_0_S4BIOS_F       BIT0
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
+//
+#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION   0x02
+#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION        0x02
+
+///
+/// Multiple APIC Description Table header definition.  The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      LocalApicAddress;
+  UINT32                      Flags;
+} EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 3.0 spec.)
+///
+#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_3_0_PCAT_COMPAT         BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x09 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC           0x00
+#define EFI_ACPI_3_0_IO_APIC                        0x01
+#define EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE      0x02
+#define EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE  0x03
+#define EFI_ACPI_3_0_LOCAL_APIC_NMI                 0x04
+#define EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE    0x05
+#define EFI_ACPI_3_0_IO_SAPIC                       0x06
+#define EFI_ACPI_3_0_LOCAL_SAPIC                    0x07
+#define EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES     0x08
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT8   ApicId;
+  UINT32  Flags;
+} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_3_0_LOCAL_APIC_ENABLED        BIT0
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  IoApicAddress;
+  UINT32  GlobalSystemInterruptBase;
+} EFI_ACPI_3_0_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Bus;
+  UINT8   Source;
+  UINT32  GlobalSystemInterrupt;
+  UINT16  Flags;
+} EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT8   InterruptType;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT8   IoSapicVector;
+  UINT32  GlobalSystemInterrupt;
+  UINT32  PlatformInterruptSourceFlags;
+  UINT8   CpeiProcessorOverride;
+  UINT8   Reserved[31];
+} EFI_ACPI_3_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_POLARITY      (3 << 0)
+#define EFI_ACPI_3_0_TRIGGER_MODE  (3 << 2)
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT32  GlobalSystemInterrupt;
+} EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT16  Flags;
+  UINT8   LocalApicLint;
+} EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT64  LocalApicAddress;
+} EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  GlobalSystemInterruptBase;
+  UINT64  IoSapicAddress;
+} EFI_ACPI_3_0_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT8   LocalSapicId;
+  UINT8   LocalSapicEid;
+  UINT8   Reserved[3];
+  UINT32  Flags;
+  UINT32  ACPIProcessorUIDValue;
+} EFI_ACPI_3_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT8   InterruptType;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT8   IoSapicVector;
+  UINT32  GlobalSystemInterrupt;
+  UINT32  PlatformInterruptSourceFlags;
+} EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Platform Interrupt Source Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_3_0_CPEI_PROCESSOR_OVERRIDE          BIT0
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      WarningEnergyLevel;
+  UINT32                      LowEnergyLevel;
+  UINT32                      CriticalEnergyLevel;
+} EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 3.0 spec.)
+///
+#define EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  EcControl;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  EcData;
+  UINT32                                  Uid;
+  UINT8                                   GpeBit;
+} EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 3.0 spec.)
+///
+#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION  0x01
+
+///
+/// System Resource Affinity Table (SRAT.  The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Reserved1;  ///< Must be set to 1
+  UINT64                      Reserved2;
+} EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+///
+/// SRAT Version (as defined in ACPI 3.0 spec.)
+///
+#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION  0x02
+
+//
+// SRAT structure types.
+// All other values between 0x02 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY  0x00
+#define EFI_ACPI_3_0_MEMORY_AFFINITY                      0x01
+
+///
+/// Processor Local APIC/SAPIC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   ProximityDomain7To0;
+  UINT8   ApicId;
+  UINT32  Flags;
+  UINT8   LocalSapicEid;
+  UINT8   ProximityDomain31To8[3];
+  UINT8   Reserved[4];
+} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+///
+/// Local APIC/SAPIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+///
+/// Memory Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT32  ProximityDomain;
+  UINT16  Reserved1;
+  UINT32  AddressBaseLow;
+  UINT32  AddressBaseHigh;
+  UINT32  LengthLow;
+  UINT32  LengthHigh;
+  UINT32  Reserved2;
+  UINT32  Flags;
+  UINT64  Reserved3;
+} EFI_ACPI_3_0_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags.  All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_3_0_MEMORY_ENABLED       (1 << 0)
+#define EFI_ACPI_3_0_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_3_0_MEMORY_NONVOLATILE   (1 << 2)
+
+///
+/// System Locality Distance Information Table (SLIT).
+/// The rest of the table is a matrix.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT64                      NumberOfSystemLocalities;
+} EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+///
+/// SLIT Version (as defined in ACPI 3.0 spec.)
+///
+#define EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION  0x01
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') 
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE  SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_3_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_3_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_3_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SRAT" System Resource Affinity Table
+///
+#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE  SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_3_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE  SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "CPEP" Corrected Platform Error Polling Table
+///
+#define EFI_ACPI_3_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE  SIGNATURE_32('C', 'P', 'E', 'P')
+
+///
+/// "DBGP" MS Debug Port Spec
+///
+#define EFI_ACPI_3_0_DEBUG_PORT_TABLE_SIGNATURE  SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_3_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "HPET" IA-PC High Precision Event Timer Table
+///
+#define EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE  SIGNATURE_32('H', 'P', 'E', 'T')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('M', 'C', 'F', 'G')
+
+///
+/// "SPCR" Serial Port Concole Redirection Table
+///
+#define EFI_ACPI_3_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_3_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+///
+#define EFI_ACPI_3_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE  SIGNATURE_32('T', 'C', 'P', 'A')
+
+///
+/// "WDRT" Watchdog Resource Table
+///
+#define EFI_ACPI_3_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('W', 'D', 'R', 'T')
+
+///
+/// "WDAT" Watchdog Action Table
+///
+#define EFI_ACPI_3_0_WATCHDOG_ACTION_TABLE_SIGNATURE  SIGNATURE_32('W', 'D', 'A', 'T')
+
+///
+/// "WSPT" Windows Specific Properties Table
+///
+#define EFI_ACPI_3_0_WINDOWS_SPECIFIC_PROPERTIES_TABLE_SIGNATURE  SIGNATURE_32('W', 'S', 'P', 'T')
+
+///
+/// "iBFT" iSCSI Boot Firmware Table
+///
+#define EFI_ACPI_3_0_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE  SIGNATURE_32('i', 'B', 'F', 'T')
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi40.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi40.h
new file mode 100644
index 0000000000..94ae5fc567
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi40.h
@@ -0,0 +1,1309 @@
+/** @file   
+  ACPI 4.0 definitions from the ACPI Specification Revision 4.0a April 5, 2010
+
+  Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+**/
+
+#ifndef _ACPI_4_0_H_
+#define _ACPI_4_0_H_
+
+#include <IndustryStandard/Acpi30.h>
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 4.0 Generic Address Space definition
+///
+typedef struct {
+  UINT8   AddressSpaceId;
+  UINT8   RegisterBitWidth;
+  UINT8   RegisterBitOffset;
+  UINT8   AccessSize;
+  UINT64  Address;
+} EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_4_0_SYSTEM_MEMORY              0
+#define EFI_ACPI_4_0_SYSTEM_IO                  1
+#define EFI_ACPI_4_0_PCI_CONFIGURATION_SPACE    2
+#define EFI_ACPI_4_0_EMBEDDED_CONTROLLER        3
+#define EFI_ACPI_4_0_SMBUS                      4
+#define EFI_ACPI_4_0_FUNCTIONAL_FIXED_HARDWARE  0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_4_0_UNDEFINED  0
+#define EFI_ACPI_4_0_BYTE       1
+#define EFI_ACPI_4_0_WORD       2
+#define EFI_ACPI_4_0_DWORD      3
+#define EFI_ACPI_4_0_QWORD      4
+
+//
+// ACPI 4.0 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+  UINT64  Signature;
+  UINT8   Checksum;
+  UINT8   OemId[6];
+  UINT8   Revision;
+  UINT32  RsdtAddress;
+  UINT32  Length;
+  UINT64  XsdtAddress;
+  UINT8   ExtendedChecksum;
+  UINT8   Reserved[3];
+} EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 4.0b spec.)
+///
+#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02  ///< ACPISpec (Revision 4.0a) says current value is 2
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+} EFI_ACPI_4_0_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with 
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with 
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  UINT32                                  FirmwareCtrl;
+  UINT32                                  Dsdt;
+  UINT8                                   Reserved0;
+  UINT8                                   PreferredPmProfile;
+  UINT16                                  SciInt;
+  UINT32                                  SmiCmd;
+  UINT8                                   AcpiEnable;
+  UINT8                                   AcpiDisable;
+  UINT8                                   S4BiosReq;
+  UINT8                                   PstateCnt;
+  UINT32                                  Pm1aEvtBlk;
+  UINT32                                  Pm1bEvtBlk;
+  UINT32                                  Pm1aCntBlk;
+  UINT32                                  Pm1bCntBlk;
+  UINT32                                  Pm2CntBlk;
+  UINT32                                  PmTmrBlk;
+  UINT32                                  Gpe0Blk;
+  UINT32                                  Gpe1Blk;
+  UINT8                                   Pm1EvtLen;
+  UINT8                                   Pm1CntLen;
+  UINT8                                   Pm2CntLen;
+  UINT8                                   PmTmrLen;
+  UINT8                                   Gpe0BlkLen;
+  UINT8                                   Gpe1BlkLen;
+  UINT8                                   Gpe1Base;
+  UINT8                                   CstCnt;
+  UINT16                                  PLvl2Lat;
+  UINT16                                  PLvl3Lat;
+  UINT16                                  FlushSize;
+  UINT16                                  FlushStride;
+  UINT8                                   DutyOffset;
+  UINT8                                   DutyWidth;
+  UINT8                                   DayAlrm;
+  UINT8                                   MonAlrm;
+  UINT8                                   Century;
+  UINT16                                  IaPcBootArch;
+  UINT8                                   Reserved1;
+  UINT32                                  Flags;
+  EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE  ResetReg;
+  UINT8                                   ResetValue;
+  UINT8                                   Reserved2[3];
+  UINT64                                  XFirmwareCtrl;
+  UINT64                                  XDsdt;
+  EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk;
+  EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk;
+  EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk;
+  EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk;
+  EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk;
+  EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk;
+  EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk;
+  EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk;
+} EFI_ACPI_4_0_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION  0x04
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_4_0_PM_PROFILE_UNSPECIFIED         0
+#define EFI_ACPI_4_0_PM_PROFILE_DESKTOP             1
+#define EFI_ACPI_4_0_PM_PROFILE_MOBILE              2
+#define EFI_ACPI_4_0_PM_PROFILE_WORKSTATION         3
+#define EFI_ACPI_4_0_PM_PROFILE_ENTERPRISE_SERVER   4
+#define EFI_ACPI_4_0_PM_PROFILE_SOHO_SERVER         5
+#define EFI_ACPI_4_0_PM_PROFILE_APPLIANCE_PC        6
+#define EFI_ACPI_4_0_PM_PROFILE_PERFORMANCE_SERVER  7
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_4_0_LEGACY_DEVICES              BIT0
+#define EFI_ACPI_4_0_8042                        BIT1
+#define EFI_ACPI_4_0_VGA_NOT_PRESENT             BIT2
+#define EFI_ACPI_4_0_MSI_NOT_SUPPORTED           BIT3
+#define EFI_ACPI_4_0_PCIE_ASPM_CONTROLS          BIT4
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_4_0_WBINVD                                 BIT0
+#define EFI_ACPI_4_0_WBINVD_FLUSH                           BIT1
+#define EFI_ACPI_4_0_PROC_C1                                BIT2
+#define EFI_ACPI_4_0_P_LVL2_UP                              BIT3
+#define EFI_ACPI_4_0_PWR_BUTTON                             BIT4
+#define EFI_ACPI_4_0_SLP_BUTTON                             BIT5
+#define EFI_ACPI_4_0_FIX_RTC                                BIT6
+#define EFI_ACPI_4_0_RTC_S4                                 BIT7
+#define EFI_ACPI_4_0_TMR_VAL_EXT                            BIT8
+#define EFI_ACPI_4_0_DCK_CAP                                BIT9
+#define EFI_ACPI_4_0_RESET_REG_SUP                          BIT10
+#define EFI_ACPI_4_0_SEALED_CASE                            BIT11
+#define EFI_ACPI_4_0_HEADLESS                               BIT12
+#define EFI_ACPI_4_0_CPU_SW_SLP                             BIT13
+#define EFI_ACPI_4_0_PCI_EXP_WAK                            BIT14
+#define EFI_ACPI_4_0_USE_PLATFORM_CLOCK                     BIT15
+#define EFI_ACPI_4_0_S4_RTC_STS_VALID                       BIT16
+#define EFI_ACPI_4_0_REMOTE_POWER_ON_CAPABLE                BIT17
+#define EFI_ACPI_4_0_FORCE_APIC_CLUSTER_MODEL               BIT18
+#define EFI_ACPI_4_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE   BIT19
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+  UINT32  HardwareSignature;
+  UINT32  FirmwareWakingVector;
+  UINT32  GlobalLock;
+  UINT32  Flags;
+  UINT64  XFirmwareWakingVector;
+  UINT8   Version;
+  UINT8   Reserved0[3];
+  UINT32  OspmFlags;
+  UINT8   Reserved1[24];
+} EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION  0x02
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_4_0_S4BIOS_F                     BIT0
+#define EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F       BIT1
+
+///
+/// OSPM Enabled Firmware Control Structure Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_4_0_OSPM_64BIT_WAKE__F           BIT0
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
+//
+#define EFI_ACPI_4_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION   0x02
+#define EFI_ACPI_4_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION        0x02
+
+///
+/// Multiple APIC Description Table header definition.  The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      LocalApicAddress;
+  UINT32                      Flags;
+} EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_4_0_PCAT_COMPAT         BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x0B an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC           0x00
+#define EFI_ACPI_4_0_IO_APIC                        0x01
+#define EFI_ACPI_4_0_INTERRUPT_SOURCE_OVERRIDE      0x02
+#define EFI_ACPI_4_0_NON_MASKABLE_INTERRUPT_SOURCE  0x03
+#define EFI_ACPI_4_0_LOCAL_APIC_NMI                 0x04
+#define EFI_ACPI_4_0_LOCAL_APIC_ADDRESS_OVERRIDE    0x05
+#define EFI_ACPI_4_0_IO_SAPIC                       0x06
+#define EFI_ACPI_4_0_LOCAL_SAPIC                    0x07
+#define EFI_ACPI_4_0_PLATFORM_INTERRUPT_SOURCES     0x08
+#define EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC         0x09
+#define EFI_ACPI_4_0_LOCAL_X2APIC_NMI               0x0A
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT8   ApicId;
+  UINT32  Flags;
+} EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_4_0_LOCAL_APIC_ENABLED        BIT0
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  IoApicAddress;
+  UINT32  GlobalSystemInterruptBase;
+} EFI_ACPI_4_0_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Bus;
+  UINT8   Source;
+  UINT32  GlobalSystemInterrupt;
+  UINT16  Flags;
+} EFI_ACPI_4_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT8   InterruptType;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT8   IoSapicVector;
+  UINT32  GlobalSystemInterrupt;
+  UINT32  PlatformInterruptSourceFlags;
+  UINT8   CpeiProcessorOverride;
+  UINT8   Reserved[31];
+} EFI_ACPI_4_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_4_0_POLARITY      (3 << 0)
+#define EFI_ACPI_4_0_TRIGGER_MODE  (3 << 2)
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT32  GlobalSystemInterrupt;
+} EFI_ACPI_4_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT16  Flags;
+  UINT8   LocalApicLint;
+} EFI_ACPI_4_0_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT64  LocalApicAddress;
+} EFI_ACPI_4_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  GlobalSystemInterruptBase;
+  UINT64  IoSapicAddress;
+} EFI_ACPI_4_0_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT8   LocalSapicId;
+  UINT8   LocalSapicEid;
+  UINT8   Reserved[3];
+  UINT32  Flags;
+  UINT32  ACPIProcessorUIDValue;
+} EFI_ACPI_4_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT8   InterruptType;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT8   IoSapicVector;
+  UINT32  GlobalSystemInterrupt;
+  UINT32  PlatformInterruptSourceFlags;
+} EFI_ACPI_4_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Platform Interrupt Source Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_4_0_CPEI_PROCESSOR_OVERRIDE          BIT0
+
+///
+/// Processor Local x2APIC Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Reserved[2];
+  UINT32  X2ApicId;
+  UINT32  Flags;
+  UINT32  AcpiProcessorUid;
+} EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
+
+///
+/// Local x2APIC NMI Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT32  AcpiProcessorUid;
+  UINT8   LocalX2ApicLint;
+  UINT8   Reserved[3];
+} EFI_ACPI_4_0_LOCAL_X2APIC_NMI_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      WarningEnergyLevel;
+  UINT32                      LowEnergyLevel;
+  UINT32                      CriticalEnergyLevel;
+} EFI_ACPI_4_0_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE  EcControl;
+  EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE  EcData;
+  UINT32                                  Uid;
+  UINT8                                   GpeBit;
+} EFI_ACPI_4_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION  0x01
+
+///
+/// System Resource Affinity Table (SRAT.  The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Reserved1;  ///< Must be set to 1
+  UINT64                      Reserved2;
+} EFI_ACPI_4_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+///
+/// SRAT Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION  0x03
+
+//
+// SRAT structure types.
+// All other values between 0x03 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY  0x00
+#define EFI_ACPI_4_0_MEMORY_AFFINITY                      0x01
+#define EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_AFFINITY      0x02
+
+///
+/// Processor Local APIC/SAPIC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   ProximityDomain7To0;
+  UINT8   ApicId;
+  UINT32  Flags;
+  UINT8   LocalSapicEid;
+  UINT8   ProximityDomain31To8[3];
+  UINT32  ClockDomain;
+} EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+///
+/// Local APIC/SAPIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+///
+/// Memory Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT32  ProximityDomain;
+  UINT16  Reserved1;
+  UINT32  AddressBaseLow;
+  UINT32  AddressBaseHigh;
+  UINT32  LengthLow;
+  UINT32  LengthHigh;
+  UINT32  Reserved2;
+  UINT32  Flags;
+  UINT64  Reserved3;
+} EFI_ACPI_4_0_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags.  All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_4_0_MEMORY_ENABLED       (1 << 0)
+#define EFI_ACPI_4_0_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_4_0_MEMORY_NONVOLATILE   (1 << 2)
+
+///
+/// Processor Local x2APIC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Reserved1[2];
+  UINT32  ProximityDomain;
+  UINT32  X2ApicId;
+  UINT32  Flags;
+  UINT32  ClockDomain;
+  UINT8   Reserved2[4];
+} EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
+
+///
+/// System Locality Distance Information Table (SLIT).
+/// The rest of the table is a matrix.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT64                      NumberOfSystemLocalities;
+} EFI_ACPI_4_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+///
+/// SLIT Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION  0x01
+
+///
+/// Corrected Platform Error Polling Table (CPEP)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       Reserved[8];
+} EFI_ACPI_4_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
+
+///
+/// CPEP Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+
+//
+// CPEP processor structure types.
+//
+#define EFI_ACPI_4_0_CPEP_PROCESSOR_APIC_SAPIC  0x00
+
+///
+/// Corrected Platform Error Polling Processor Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT32  PollingInterval;
+} EFI_ACPI_4_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
+
+///
+/// Maximum System Characteristics Table (MSCT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      OffsetProxDomInfo;
+  UINT32                      MaximumNumberOfProximityDomains;
+  UINT32                      MaximumNumberOfClockDomains;
+  UINT64                      MaximumPhysicalAddress;
+} EFI_ACPI_4_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
+
+///
+/// MSCT Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+
+///
+/// Maximum Proximity Domain Information Structure Definition
+///
+typedef struct {
+  UINT8   Revision;
+  UINT8   Length;
+  UINT32  ProximityDomainRangeLow;
+  UINT32  ProximityDomainRangeHigh;
+  UINT32  MaximumProcessorCapacity;
+  UINT64  MaximumMemoryCapacity;
+} EFI_ACPI_4_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
+
+///
+/// Boot Error Record Table (BERT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      BootErrorRegionLength;
+  UINT64                      BootErrorRegion;
+} EFI_ACPI_4_0_BOOT_ERROR_RECORD_TABLE_HEADER;
+
+///
+/// BERT Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+
+///
+/// Boot Error Region Block Status Definition
+///
+typedef struct {
+  UINT32       UncorrectableErrorValid:1;
+  UINT32       CorrectableErrorValid:1;
+  UINT32       MultipleUncorrectableErrors:1;
+  UINT32       MultipleCorrectableErrors:1;
+  UINT32       ErrorDataEntryCount:10;
+  UINT32       Reserved:18;
+} EFI_ACPI_4_0_ERROR_BLOCK_STATUS;
+
+///
+/// Boot Error Region Definition
+///
+typedef struct {
+  EFI_ACPI_4_0_ERROR_BLOCK_STATUS              BlockStatus;
+  UINT32                                       RawDataOffset;
+  UINT32                                       RawDataLength;
+  UINT32                                       DataLength;
+  UINT32                                       ErrorSeverity;
+} EFI_ACPI_4_0_BOOT_ERROR_REGION_STRUCTURE;
+
+//
+// Boot Error Severity types
+//
+#define EFI_ACPI_4_0_ERROR_SEVERITY_CORRECTABLE  0x00
+#define EFI_ACPI_4_0_ERROR_SEVERITY_FATAL        0x01
+#define EFI_ACPI_4_0_ERROR_SEVERITY_CORRECTED    0x02
+#define EFI_ACPI_4_0_ERROR_SEVERITY_NONE         0x03
+
+///
+/// Generic Error Data Entry Definition
+///
+typedef struct {
+  UINT8    SectionType[16];
+  UINT32   ErrorSeverity;
+  UINT16   Revision;
+  UINT8    ValidationBits;
+  UINT8    Flags;
+  UINT32   ErrorDataLength;
+  UINT8    FruId[16];
+  UINT8    FruText[20];
+} EFI_ACPI_4_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
+
+///
+/// Generic Error Data Entry Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_GENERIC_ERROR_DATA_ENTRY_REVISION  0x0201
+
+///
+/// HEST - Hardware Error Source Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      ErrorSourceCount;
+} EFI_ACPI_4_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
+
+///
+/// HEST Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+
+//
+// Error Source structure types.
+//
+#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION  0x00
+#define EFI_ACPI_4_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK  0x01
+#define EFI_ACPI_4_0_IA32_ARCHITECTURE_NMI_ERROR                0x02
+#define EFI_ACPI_4_0_PCI_EXPRESS_ROOT_PORT_AER                  0x06
+#define EFI_ACPI_4_0_PCI_EXPRESS_DEVICE_AER                     0x07
+#define EFI_ACPI_4_0_PCI_EXPRESS_BRIDGE_AER                     0x08
+#define EFI_ACPI_4_0_GENERIC_HARDWARE_ERROR                     0x09
+
+//
+// Error Source structure flags.
+//
+#define EFI_ACPI_4_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST       (1 << 0)
+#define EFI_ACPI_4_0_ERROR_SOURCE_FLAG_GLOBAL               (1 << 1)
+
+///
+/// IA-32 Architecture Machine Check Exception Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT64  GlobalCapabilityInitData;
+  UINT64  GlobalControlInitData;
+  UINT8   NumberOfHardwareBanks;
+  UINT8   Reserved1[7];
+} EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure Definition
+///
+typedef struct {
+  UINT8   BankNumber;
+  UINT8   ClearStatusOnInitialization;
+  UINT8   StatusDataFormat;
+  UINT8   Reserved0;
+  UINT32  ControlRegisterMsrAddress;
+  UINT64  ControlInitData;
+  UINT32  StatusRegisterMsrAddress;
+  UINT32  AddressRegisterMsrAddress;
+  UINT32  MiscRegisterMsrAddress;
+} EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure MCA data format
+///
+#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32      0x00
+#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64   0x01
+#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64     0x02
+
+//
+// Hardware Error Notification types. All other values are reserved
+//
+#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_POLLED                0x00
+#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT    0x01
+#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT       0x02
+#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_SCI                   0x03
+#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_NMI                   0x04
+
+///
+/// Hardware Error Notification Configuration Write Enable Structure Definition
+///
+typedef struct {
+  UINT16    Type:1;
+  UINT16    PollInterval:1;
+  UINT16    SwitchToPollingThresholdValue:1;
+  UINT16    SwitchToPollingThresholdWindow:1;
+  UINT16    ErrorThresholdValue:1;
+  UINT16    ErrorThresholdWindow:1;
+  UINT16    Reserved:10;
+} EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
+
+///
+/// Hardware Error Notification Structure Definition
+///
+typedef struct {
+  UINT8                                                                          Type;
+  UINT8                                                                          Length;
+  EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE  ConfigurationWriteEnable;
+  UINT32                                                                         PollInterval;
+  UINT32                                                                         Vector;
+  UINT32                                                                         SwitchToPollingThresholdValue;
+  UINT32                                                                         SwitchToPollingThresholdWindow;
+  UINT32                                                                         ErrorThresholdValue;
+  UINT32                                                                         ErrorThresholdWindow;
+} EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
+
+///
+/// IA-32 Architecture Corrected Machine Check Structure Definition
+///
+typedef struct {
+  UINT16                                                 Type;
+  UINT16                                                 SourceId;
+  UINT8                                                  Reserved0[2];
+  UINT8                                                  Flags;
+  UINT8                                                  Enabled;
+  UINT32                                                 NumberOfRecordsToPreAllocate;
+  UINT32                                                 MaxSectionsPerRecord;
+  EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE     NotificationStructure;
+  UINT8                                                  NumberOfHardwareBanks;
+  UINT8                                                  Reserved1[3];
+} EFI_ACPI_4_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// IA-32 Architecture NMI Error Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  MaxRawDataLength;
+} EFI_ACPI_4_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
+
+///
+/// PCI Express Root Port AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+  UINT32  RootErrorCommand;
+} EFI_ACPI_4_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
+
+///
+/// PCI Express Device AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_4_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
+
+///
+/// PCI Express Bridge AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+  UINT32  SecondaryUncorrectableErrorMask;
+  UINT32  SecondaryUncorrectableErrorSeverity;
+  UINT32  SecondaryAdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_4_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Structure Definition
+///
+typedef struct {
+  UINT16                                                 Type;
+  UINT16                                                 SourceId;
+  UINT16                                                 RelatedSourceId;
+  UINT8                                                  Flags;
+  UINT8                                                  Enabled;
+  UINT32                                                 NumberOfRecordsToPreAllocate;
+  UINT32                                                 MaxSectionsPerRecord;
+  UINT32                                                 MaxRawDataLength;
+  EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE                 ErrorStatusAddress;
+  EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE     NotificationStructure;
+  UINT32                                                 ErrorStatusBlockLength;
+} EFI_ACPI_4_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
+
+///
+/// Generic Error Status Definition
+///
+typedef struct {
+  EFI_ACPI_4_0_ERROR_BLOCK_STATUS              BlockStatus;
+  UINT32                                       RawDataOffset;
+  UINT32                                       RawDataLength;
+  UINT32                                       DataLength;
+  UINT32                                       ErrorSeverity;
+} EFI_ACPI_4_0_GENERIC_ERROR_STATUS_STRUCTURE;
+
+///
+/// ERST - Error Record Serialization Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      SerializationHeaderSize;
+  UINT8                       Reserved0[4];
+  UINT32                      InstructionEntryCount;
+} EFI_ACPI_4_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
+
+///
+/// ERST Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+
+///
+/// ERST Serialization Actions
+///
+#define EFI_ACPI_4_0_ERST_BEGIN_WRITE_OPERATION                    0x00
+#define EFI_ACPI_4_0_ERST_BEGIN_READ_OPERATION                     0x01
+#define EFI_ACPI_4_0_ERST_BEGIN_CLEAR_OPERATION                    0x02
+#define EFI_ACPI_4_0_ERST_END_OPERATION                            0x03
+#define EFI_ACPI_4_0_ERST_SET_RECORD_OFFSET                        0x04
+#define EFI_ACPI_4_0_ERST_EXECUTE_OPERATION                        0x05
+#define EFI_ACPI_4_0_ERST_CHECK_BUSY_STATUS                        0x06
+#define EFI_ACPI_4_0_ERST_GET_COMMAND_STATUS                       0x07
+#define EFI_ACPI_4_0_ERST_GET_RECORD_IDENTIFIER                    0x08
+#define EFI_ACPI_4_0_ERST_SET_RECORD_IDENTIFIER                    0x09
+#define EFI_ACPI_4_0_ERST_GET_RECORD_COUNT                         0x0A
+#define EFI_ACPI_4_0_ERST_BEGIN_DUMMY_WRITE_OPERATION              0x0B
+#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE              0x0D
+#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH       0x0E
+#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES   0x0F
+
+///
+/// ERST Action Command Status
+///
+#define EFI_ACPI_4_0_EINJ_STATUS_SUCCESS                           0x00
+#define EFI_ACPI_4_0_EINJ_STATUS_NOT_ENOUGH_SPACE                  0x01
+#define EFI_ACPI_4_0_EINJ_STATUS_HARDWARE_NOT_AVAILABLE            0x02
+#define EFI_ACPI_4_0_EINJ_STATUS_FAILED                            0x03
+#define EFI_ACPI_4_0_EINJ_STATUS_RECORD_STORE_EMPTY                0x04
+#define EFI_ACPI_4_0_EINJ_STATUS_RECORD_NOT_FOUND                  0x05
+
+///
+/// ERST Serialization Instructions
+///
+#define EFI_ACPI_4_0_ERST_READ_REGISTER                            0x00
+#define EFI_ACPI_4_0_ERST_READ_REGISTER_VALUE                      0x01
+#define EFI_ACPI_4_0_ERST_WRITE_REGISTER                           0x02
+#define EFI_ACPI_4_0_ERST_WRITE_REGISTER_VALUE                     0x03
+#define EFI_ACPI_4_0_ERST_NOOP                                     0x04
+#define EFI_ACPI_4_0_ERST_LOAD_VAR1                                0x05
+#define EFI_ACPI_4_0_ERST_LOAD_VAR2                                0x06
+#define EFI_ACPI_4_0_ERST_STORE_VAR1                               0x07
+#define EFI_ACPI_4_0_ERST_ADD                                      0x08
+#define EFI_ACPI_4_0_ERST_SUBTRACT                                 0x09
+#define EFI_ACPI_4_0_ERST_ADD_VALUE                                0x0A
+#define EFI_ACPI_4_0_ERST_SUBTRACT_VALUE                           0x0B
+#define EFI_ACPI_4_0_ERST_STALL                                    0x0C
+#define EFI_ACPI_4_0_ERST_STALL_WHILE_TRUE                         0x0D
+#define EFI_ACPI_4_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE            0x0E
+#define EFI_ACPI_4_0_ERST_GOTO                                     0x0F
+#define EFI_ACPI_4_0_ERST_SET_SRC_ADDRESS_BASE                     0x10
+#define EFI_ACPI_4_0_ERST_SET_DST_ADDRESS_BASE                     0x11
+#define EFI_ACPI_4_0_ERST_MOVE_DATA                                0x12
+
+///
+/// ERST Instruction Flags
+///
+#define EFI_ACPI_4_0_ERST_PRESERVE_REGISTER                        0x01
+
+///
+/// ERST Serialization Instruction Entry
+///
+typedef struct {
+  UINT8                                    SerializationAction;
+  UINT8                                    Instruction;
+  UINT8                                    Flags;
+  UINT8                                    Reserved0;
+  EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE   RegisterRegion;
+  UINT64                                   Value;
+  UINT64                                   Mask;
+} EFI_ACPI_4_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ - Error Injection Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      InjectionHeaderSize;
+  UINT8                       InjectionFlags;
+  UINT8                       Reserved0[3];
+  UINT32                      InjectionEntryCount;
+} EFI_ACPI_4_0_ERROR_INJECTION_TABLE_HEADER;
+
+///
+/// EINJ Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_ERROR_INJECTION_TABLE_REVISION 0x01
+
+///
+/// EINJ Error Injection Actions
+///
+#define EFI_ACPI_4_0_EINJ_BEGIN_INJECTION_OPERATION                0x00
+#define EFI_ACPI_4_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE           0x01
+#define EFI_ACPI_4_0_EINJ_SET_ERROR_TYPE                           0x02
+#define EFI_ACPI_4_0_EINJ_GET_ERROR_TYPE                           0x03
+#define EFI_ACPI_4_0_EINJ_END_OPERATION                            0x04
+#define EFI_ACPI_4_0_EINJ_EXECUTE_OPERATION                        0x05
+#define EFI_ACPI_4_0_EINJ_CHECK_BUSY_STATUS                        0x06
+#define EFI_ACPI_4_0_EINJ_GET_COMMAND_STATUS                       0x07
+#define EFI_ACPI_4_0_EINJ_TRIGGER_ERROR                            0xFF
+
+///
+/// EINJ Action Command Status
+///
+#define EFI_ACPI_4_0_EINJ_STATUS_SUCCESS                           0x00
+#define EFI_ACPI_4_0_EINJ_STATUS_UNKNOWN_FAILURE                   0x01
+#define EFI_ACPI_4_0_EINJ_STATUS_INVALID_ACCESS                    0x02
+
+///
+/// EINJ Error Type Definition
+///
+#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_CORRECTABLE                 (1 << 0)
+#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL      (1 << 1)
+#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL         (1 << 2)
+#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_CORRECTABLE                    (1 << 3)
+#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL         (1 << 4)
+#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL            (1 << 5)
+#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE               (1 << 6)
+#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL    (1 << 7)
+#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL       (1 << 8)
+#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_CORRECTABLE                  (1 << 9)
+#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL       (1 << 10)
+#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL          (1 << 11)
+
+///
+/// EINJ Injection Instructions
+///
+#define EFI_ACPI_4_0_EINJ_READ_REGISTER                            0x00
+#define EFI_ACPI_4_0_EINJ_READ_REGISTER_VALUE                      0x01
+#define EFI_ACPI_4_0_EINJ_WRITE_REGISTER                           0x02
+#define EFI_ACPI_4_0_EINJ_WRITE_REGISTER_VALUE                     0x03
+#define EFI_ACPI_4_0_EINJ_NOOP                                     0x04
+
+///
+/// EINJ Instruction Flags
+///
+#define EFI_ACPI_4_0_EINJ_PRESERVE_REGISTER                        0x01
+
+///
+/// EINJ Injection Instruction Entry
+///
+typedef struct {
+  UINT8                                    InjectionAction;
+  UINT8                                    Instruction;
+  UINT8                                    Flags;
+  UINT8                                    Reserved0;
+  EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE   RegisterRegion;
+  UINT64                                   Value;
+  UINT64                                   Mask;
+} EFI_ACPI_4_0_EINJ_INJECTION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ Trigger Action Table
+///
+typedef struct {
+  UINT32  HeaderSize;
+  UINT32  Revision;
+  UINT32  TableSize;
+  UINT32  EntryCount;
+} EFI_ACPI_4_0_EINJ_TRIGGER_ACTION_TABLE;
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') 
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "BERT" Boot Error Record Table
+///
+#define EFI_ACPI_4_0_BOOT_ERROR_RECORD_TABLE_SIGNATURE  SIGNATURE_32('B', 'E', 'R', 'T')
+
+///
+/// "CPEP" Corrected Platform Error Polling Table
+///
+#define EFI_ACPI_4_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE  SIGNATURE_32('C', 'P', 'E', 'P')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_4_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_4_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE  SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "EINJ" Error Injection Table
+///
+#define EFI_ACPI_4_0_ERROR_INJECTION_TABLE_SIGNATURE  SIGNATURE_32('E', 'I', 'N', 'J')
+
+///
+/// "ERST" Error Record Serialization Table
+///
+#define EFI_ACPI_4_0_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE  SIGNATURE_32('E', 'R', 'S', 'T')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_4_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "HEST" Hardware Error Source Table
+///
+#define EFI_ACPI_4_0_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE  SIGNATURE_32('H', 'E', 'S', 'T')
+
+///
+/// "MSCT" Maximum System Characteristics Table
+///
+#define EFI_ACPI_4_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE  SIGNATURE_32('M', 'S', 'C', 'T')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_4_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_4_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_4_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SRAT" System Resource Affinity Table
+///
+#define EFI_ACPI_4_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE  SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_4_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_4_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_4_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE  SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "DBGP" MS Debug Port Spec
+///
+#define EFI_ACPI_4_0_DEBUG_PORT_TABLE_SIGNATURE  SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "DMAR" DMA Remapping Table
+///
+#define EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE  SIGNATURE_32('D', 'M', 'A', 'R')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_4_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "HPET" IA-PC High Precision Event Timer Table
+///
+#define EFI_ACPI_4_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE  SIGNATURE_32('H', 'P', 'E', 'T')
+
+///
+/// "iBFT" iSCSI Boot Firmware Table
+///
+#define EFI_ACPI_4_0_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE  SIGNATURE_32('i', 'B', 'F', 'T')
+
+///
+/// "IVRS" I/O Virtualization Reporting Structure
+///
+#define EFI_ACPI_4_0_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE  SIGNATURE_32('I', 'V', 'R', 'S')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_4_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('M', 'C', 'F', 'G')
+
+///
+/// "MCHI" Management Controller Host Interface Table
+///
+#define EFI_ACPI_4_0_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('M', 'C', 'H', 'I')
+
+///
+/// "SPCR" Serial Port Concole Redirection Table
+///
+#define EFI_ACPI_4_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_4_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+///
+#define EFI_ACPI_4_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE  SIGNATURE_32('T', 'C', 'P', 'A')
+
+///
+/// "UEFI" UEFI ACPI Data Table
+///
+#define EFI_ACPI_4_0_UEFI_ACPI_DATA_TABLE_SIGNATURE  SIGNATURE_32('U', 'E', 'F', 'I')
+
+///
+/// "WAET" Windows ACPI Enlightenment Table
+///
+#define EFI_ACPI_4_0_WINDOWS_ACPI_ENLIGHTENMENT_TABLE_SIGNATURE  SIGNATURE_32('W', 'A', 'E', 'T')
+
+///
+/// "WDAT" Watchdog Action Table
+///
+#define EFI_ACPI_4_0_WATCHDOG_ACTION_TABLE_SIGNATURE  SIGNATURE_32('W', 'D', 'A', 'T')
+
+///
+/// "WDRT" Watchdog Resource Table
+///
+#define EFI_ACPI_4_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('W', 'D', 'R', 'T')
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi50.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi50.h
new file mode 100644
index 0000000000..a371c9ade1
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi50.h
@@ -0,0 +1,2119 @@
+/** @file   
+  ACPI 5.0 definitions from the ACPI Specification Revision 5.0a November 13, 2013.
+
+  Copyright (c) 2014 Hewlett-Packard Development Company, L.P.<BR>
+  Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+**/
+
+#ifndef _ACPI_5_0_H_
+#define _ACPI_5_0_H_
+
+#include <IndustryStandard/Acpi40.h>
+
+//
+// Define for Desriptor
+//
+#define ACPI_SMALL_FIXED_DMA_DESCRIPTOR_NAME                         0x0A
+#define ACPI_LARGE_GPIO_CONNECTION_DESCRIPTOR_NAME                   0x0C
+#define ACPI_LARGE_GENERIC_SERIAL_BUS_CONNECTION_DESCRIPTOR_NAME     0x0E
+
+#define ACPI_FIXED_DMA_DESCRIPTOR                         0x55
+#define ACPI_GPIO_CONNECTION_DESCRIPTOR                   0x8C
+#define ACPI_GENERIC_SERIAL_BUS_CONNECTION_DESCRIPTOR     0x8E
+
+#pragma pack(1)
+
+///
+/// Generic DMA Descriptor.
+///
+typedef PACKED struct {
+  ACPI_SMALL_RESOURCE_HEADER   Header;
+  UINT16                       DmaRequestLine;
+  UINT16                       DmaChannel;
+  UINT8                        DmaTransferWidth;
+} EFI_ACPI_FIXED_DMA_DESCRIPTOR;
+
+///
+/// GPIO Connection Descriptor
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         RevisionId;
+  UINT8                         ConnectionType;
+  UINT16                        GeneralFlags;
+  UINT16                        InterruptFlags;
+  UINT8                         PinConfiguration;
+  UINT16                        OutputDriveStrength;
+  UINT16                        DebounceTimeout;
+  UINT16                        PinTableOffset;
+  UINT8                         ResourceSourceIndex;
+  UINT16                        ResourceSourceNameOffset;
+  UINT16                        VendorDataOffset;
+  UINT16                        VendorDataLength;
+} EFI_ACPI_GPIO_CONNECTION_DESCRIPTOR;
+
+#define EFI_ACPI_GPIO_CONNECTION_TYPE_INTERRUPT   0x0
+#define EFI_ACPI_GPIO_CONNECTION_TYPE_IO          0x1
+
+///
+/// Serial Bus Resource Descriptor (Generic)
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         RevisionId;
+  UINT8                         ResourceSourceIndex;
+  UINT8                         SerialBusType;
+  UINT8                         GeneralFlags;
+  UINT16                        TypeSpecificFlags;
+  UINT8                         TypeSpecificRevisionId;
+  UINT16                        TypeDataLength;
+// Type specific data
+} EFI_ACPI_SERIAL_BUS_RESOURCE_DESCRIPTOR;
+
+#define EFI_ACPI_SERIAL_BUS_RESOURCE_TYPE_I2C   0x1
+#define EFI_ACPI_SERIAL_BUS_RESOURCE_TYPE_SPI   0x2
+#define EFI_ACPI_SERIAL_BUS_RESOURCE_TYPE_UART  0x3
+
+///
+/// Serial Bus Resource Descriptor (I2C)
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         RevisionId;
+  UINT8                         ResourceSourceIndex;
+  UINT8                         SerialBusType;
+  UINT8                         GeneralFlags;
+  UINT16                        TypeSpecificFlags;
+  UINT8                         TypeSpecificRevisionId;
+  UINT16                        TypeDataLength;
+  UINT32                        ConnectionSpeed;
+  UINT16                        SlaveAddress;
+} EFI_ACPI_SERIAL_BUS_RESOURCE_I2C_DESCRIPTOR;
+
+///
+/// Serial Bus Resource Descriptor (SPI)
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         RevisionId;
+  UINT8                         ResourceSourceIndex;
+  UINT8                         SerialBusType;
+  UINT8                         GeneralFlags;
+  UINT16                        TypeSpecificFlags;
+  UINT8                         TypeSpecificRevisionId;
+  UINT16                        TypeDataLength;
+  UINT32                        ConnectionSpeed;
+  UINT8                         DataBitLength;
+  UINT8                         Phase;
+  UINT8                         Polarity;
+  UINT16                        DeviceSelection;
+} EFI_ACPI_SERIAL_BUS_RESOURCE_SPI_DESCRIPTOR;
+
+///
+/// Serial Bus Resource Descriptor (UART)
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         RevisionId;
+  UINT8                         ResourceSourceIndex;
+  UINT8                         SerialBusType;
+  UINT8                         GeneralFlags;
+  UINT16                        TypeSpecificFlags;
+  UINT8                         TypeSpecificRevisionId;
+  UINT16                        TypeDataLength;
+  UINT32                        DefaultBaudRate;
+  UINT16                        RxFIFO;
+  UINT16                        TxFIFO;
+  UINT8                         Parity;
+  UINT8                         SerialLinesEnabled;
+} EFI_ACPI_SERIAL_BUS_RESOURCE_UART_DESCRIPTOR;
+
+#pragma pack()
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 5.0 Generic Address Space definition
+///
+typedef struct {
+  UINT8   AddressSpaceId;
+  UINT8   RegisterBitWidth;
+  UINT8   RegisterBitOffset;
+  UINT8   AccessSize;
+  UINT64  Address;
+} EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_5_0_SYSTEM_MEMORY              0
+#define EFI_ACPI_5_0_SYSTEM_IO                  1
+#define EFI_ACPI_5_0_PCI_CONFIGURATION_SPACE    2
+#define EFI_ACPI_5_0_EMBEDDED_CONTROLLER        3
+#define EFI_ACPI_5_0_SMBUS                      4
+#define EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL  0x0A
+#define EFI_ACPI_5_0_FUNCTIONAL_FIXED_HARDWARE       0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_5_0_UNDEFINED  0
+#define EFI_ACPI_5_0_BYTE       1
+#define EFI_ACPI_5_0_WORD       2
+#define EFI_ACPI_5_0_DWORD      3
+#define EFI_ACPI_5_0_QWORD      4
+
+//
+// ACPI 5.0 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+  UINT64  Signature;
+  UINT8   Checksum;
+  UINT8   OemId[6];
+  UINT8   Revision;
+  UINT32  RsdtAddress;
+  UINT32  Length;
+  UINT64  XsdtAddress;
+  UINT8   ExtendedChecksum;
+  UINT8   Reserved[3];
+} EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02  ///< ACPISpec (Revision 5.0) says current value is 2
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+} EFI_ACPI_5_0_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with 
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with 
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  UINT32                                  FirmwareCtrl;
+  UINT32                                  Dsdt;
+  UINT8                                   Reserved0;
+  UINT8                                   PreferredPmProfile;
+  UINT16                                  SciInt;
+  UINT32                                  SmiCmd;
+  UINT8                                   AcpiEnable;
+  UINT8                                   AcpiDisable;
+  UINT8                                   S4BiosReq;
+  UINT8                                   PstateCnt;
+  UINT32                                  Pm1aEvtBlk;
+  UINT32                                  Pm1bEvtBlk;
+  UINT32                                  Pm1aCntBlk;
+  UINT32                                  Pm1bCntBlk;
+  UINT32                                  Pm2CntBlk;
+  UINT32                                  PmTmrBlk;
+  UINT32                                  Gpe0Blk;
+  UINT32                                  Gpe1Blk;
+  UINT8                                   Pm1EvtLen;
+  UINT8                                   Pm1CntLen;
+  UINT8                                   Pm2CntLen;
+  UINT8                                   PmTmrLen;
+  UINT8                                   Gpe0BlkLen;
+  UINT8                                   Gpe1BlkLen;
+  UINT8                                   Gpe1Base;
+  UINT8                                   CstCnt;
+  UINT16                                  PLvl2Lat;
+  UINT16                                  PLvl3Lat;
+  UINT16                                  FlushSize;
+  UINT16                                  FlushStride;
+  UINT8                                   DutyOffset;
+  UINT8                                   DutyWidth;
+  UINT8                                   DayAlrm;
+  UINT8                                   MonAlrm;
+  UINT8                                   Century;
+  UINT16                                  IaPcBootArch;
+  UINT8                                   Reserved1;
+  UINT32                                  Flags;
+  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  ResetReg;
+  UINT8                                   ResetValue;
+  UINT8                                   Reserved2[3];
+  UINT64                                  XFirmwareCtrl;
+  UINT64                                  XDsdt;
+  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk;
+  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk;
+  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk;
+  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk;
+  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk;
+  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk;
+  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk;
+  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk;
+  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  SleepControlReg;
+  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  SleepStatusReg;
+} EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION  0x05
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED         0
+#define EFI_ACPI_5_0_PM_PROFILE_DESKTOP             1
+#define EFI_ACPI_5_0_PM_PROFILE_MOBILE              2
+#define EFI_ACPI_5_0_PM_PROFILE_WORKSTATION         3
+#define EFI_ACPI_5_0_PM_PROFILE_ENTERPRISE_SERVER   4
+#define EFI_ACPI_5_0_PM_PROFILE_SOHO_SERVER         5
+#define EFI_ACPI_5_0_PM_PROFILE_APPLIANCE_PC        6
+#define EFI_ACPI_5_0_PM_PROFILE_PERFORMANCE_SERVER  7
+#define EFI_ACPI_5_0_PM_PROFILE_TABLET              8
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_5_0_LEGACY_DEVICES              BIT0
+#define EFI_ACPI_5_0_8042                        BIT1
+#define EFI_ACPI_5_0_VGA_NOT_PRESENT             BIT2
+#define EFI_ACPI_5_0_MSI_NOT_SUPPORTED           BIT3
+#define EFI_ACPI_5_0_PCIE_ASPM_CONTROLS          BIT4
+#define EFI_ACPI_5_0_CMOS_RTC_NOT_PRESENT        BIT5
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_5_0_WBINVD                                 BIT0
+#define EFI_ACPI_5_0_WBINVD_FLUSH                           BIT1
+#define EFI_ACPI_5_0_PROC_C1                                BIT2
+#define EFI_ACPI_5_0_P_LVL2_UP                              BIT3
+#define EFI_ACPI_5_0_PWR_BUTTON                             BIT4
+#define EFI_ACPI_5_0_SLP_BUTTON                             BIT5
+#define EFI_ACPI_5_0_FIX_RTC                                BIT6
+#define EFI_ACPI_5_0_RTC_S4                                 BIT7
+#define EFI_ACPI_5_0_TMR_VAL_EXT                            BIT8
+#define EFI_ACPI_5_0_DCK_CAP                                BIT9
+#define EFI_ACPI_5_0_RESET_REG_SUP                          BIT10
+#define EFI_ACPI_5_0_SEALED_CASE                            BIT11
+#define EFI_ACPI_5_0_HEADLESS                               BIT12
+#define EFI_ACPI_5_0_CPU_SW_SLP                             BIT13
+#define EFI_ACPI_5_0_PCI_EXP_WAK                            BIT14
+#define EFI_ACPI_5_0_USE_PLATFORM_CLOCK                     BIT15
+#define EFI_ACPI_5_0_S4_RTC_STS_VALID                       BIT16
+#define EFI_ACPI_5_0_REMOTE_POWER_ON_CAPABLE                BIT17
+#define EFI_ACPI_5_0_FORCE_APIC_CLUSTER_MODEL               BIT18
+#define EFI_ACPI_5_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE   BIT19
+#define EFI_ACPI_5_0_HW_REDUCED_ACPI                        BIT20
+#define EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE              BIT21
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+  UINT32  HardwareSignature;
+  UINT32  FirmwareWakingVector;
+  UINT32  GlobalLock;
+  UINT32  Flags;
+  UINT64  XFirmwareWakingVector;
+  UINT8   Version;
+  UINT8   Reserved0[3];
+  UINT32  OspmFlags;
+  UINT8   Reserved1[24];
+} EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION  0x02
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_5_0_S4BIOS_F                     BIT0
+#define EFI_ACPI_5_0_64BIT_WAKE_SUPPORTED_F       BIT1
+
+///
+/// OSPM Enabled Firmware Control Structure Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_5_0_OSPM_64BIT_WAKE_F            BIT0
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
+//
+#define EFI_ACPI_5_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION   0x02
+#define EFI_ACPI_5_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION        0x02
+
+///
+/// Multiple APIC Description Table header definition.  The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      LocalApicAddress;
+  UINT32                      Flags;
+} EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_5_0_PCAT_COMPAT         BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x0D and 0x7F are reserved and
+// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.
+//
+#define EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC           0x00
+#define EFI_ACPI_5_0_IO_APIC                        0x01
+#define EFI_ACPI_5_0_INTERRUPT_SOURCE_OVERRIDE      0x02
+#define EFI_ACPI_5_0_NON_MASKABLE_INTERRUPT_SOURCE  0x03
+#define EFI_ACPI_5_0_LOCAL_APIC_NMI                 0x04
+#define EFI_ACPI_5_0_LOCAL_APIC_ADDRESS_OVERRIDE    0x05
+#define EFI_ACPI_5_0_IO_SAPIC                       0x06
+#define EFI_ACPI_5_0_LOCAL_SAPIC                    0x07
+#define EFI_ACPI_5_0_PLATFORM_INTERRUPT_SOURCES     0x08
+#define EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC         0x09
+#define EFI_ACPI_5_0_LOCAL_X2APIC_NMI               0x0A
+#define EFI_ACPI_5_0_GIC                            0x0B
+#define EFI_ACPI_5_0_GICD                           0x0C
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT8   ApicId;
+  UINT32  Flags;
+} EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_0_LOCAL_APIC_ENABLED        BIT0
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  IoApicAddress;
+  UINT32  GlobalSystemInterruptBase;
+} EFI_ACPI_5_0_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Bus;
+  UINT8   Source;
+  UINT32  GlobalSystemInterrupt;
+  UINT16  Flags;
+} EFI_ACPI_5_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT8   InterruptType;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT8   IoSapicVector;
+  UINT32  GlobalSystemInterrupt;
+  UINT32  PlatformInterruptSourceFlags;
+  UINT8   CpeiProcessorOverride;
+  UINT8   Reserved[31];
+} EFI_ACPI_5_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_5_0_POLARITY      (3 << 0)
+#define EFI_ACPI_5_0_TRIGGER_MODE  (3 << 2)
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT32  GlobalSystemInterrupt;
+} EFI_ACPI_5_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT16  Flags;
+  UINT8   LocalApicLint;
+} EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT64  LocalApicAddress;
+} EFI_ACPI_5_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  GlobalSystemInterruptBase;
+  UINT64  IoSapicAddress;
+} EFI_ACPI_5_0_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT8   LocalSapicId;
+  UINT8   LocalSapicEid;
+  UINT8   Reserved[3];
+  UINT32  Flags;
+  UINT32  ACPIProcessorUIDValue;
+} EFI_ACPI_5_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT8   InterruptType;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT8   IoSapicVector;
+  UINT32  GlobalSystemInterrupt;
+  UINT32  PlatformInterruptSourceFlags;
+} EFI_ACPI_5_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Platform Interrupt Source Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_5_0_CPEI_PROCESSOR_OVERRIDE          BIT0
+
+///
+/// Processor Local x2APIC Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Reserved[2];
+  UINT32  X2ApicId;
+  UINT32  Flags;
+  UINT32  AcpiProcessorUid;
+} EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
+
+///
+/// Local x2APIC NMI Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT32  AcpiProcessorUid;
+  UINT8   LocalX2ApicLint;
+  UINT8   Reserved[3];
+} EFI_ACPI_5_0_LOCAL_X2APIC_NMI_STRUCTURE;
+
+///
+/// GIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT32  GicId;
+  UINT32  AcpiProcessorUid;
+  UINT32  Flags;
+  UINT32  ParkingProtocolVersion;
+  UINT32  PerformanceInterruptGsiv;
+  UINT64  ParkedAddress;
+  UINT64  PhysicalBaseAddress;
+} EFI_ACPI_5_0_GIC_STRUCTURE;
+
+///
+/// GIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_0_GIC_ENABLED                     BIT0
+#define EFI_ACPI_5_0_PERFORMANCE_INTERRUPT_MODEL     BIT1
+
+///
+/// GIC Distributor Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved1;
+  UINT32  GicId;
+  UINT64  PhysicalBaseAddress;
+  UINT32  SystemVectorBase;
+  UINT32  Reserved2;
+} EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      WarningEnergyLevel;
+  UINT32                      LowEnergyLevel;
+  UINT32                      CriticalEnergyLevel;
+} EFI_ACPI_5_0_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  EcControl;
+  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  EcData;
+  UINT32                                  Uid;
+  UINT8                                   GpeBit;
+} EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION  0x01
+
+///
+/// System Resource Affinity Table (SRAT).  The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Reserved1;  ///< Must be set to 1
+  UINT64                      Reserved2;
+} EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+///
+/// SRAT Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION  0x03
+
+//
+// SRAT structure types.
+// All other values between 0x03 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY  0x00
+#define EFI_ACPI_5_0_MEMORY_AFFINITY                      0x01
+#define EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_AFFINITY      0x02
+
+///
+/// Processor Local APIC/SAPIC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   ProximityDomain7To0;
+  UINT8   ApicId;
+  UINT32  Flags;
+  UINT8   LocalSapicEid;
+  UINT8   ProximityDomain31To8[3];
+  UINT32  ClockDomain;
+} EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+///
+/// Local APIC/SAPIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+///
+/// Memory Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT32  ProximityDomain;
+  UINT16  Reserved1;
+  UINT32  AddressBaseLow;
+  UINT32  AddressBaseHigh;
+  UINT32  LengthLow;
+  UINT32  LengthHigh;
+  UINT32  Reserved2;
+  UINT32  Flags;
+  UINT64  Reserved3;
+} EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags.  All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_5_0_MEMORY_ENABLED       (1 << 0)
+#define EFI_ACPI_5_0_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_5_0_MEMORY_NONVOLATILE   (1 << 2)
+
+///
+/// Processor Local x2APIC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Reserved1[2];
+  UINT32  ProximityDomain;
+  UINT32  X2ApicId;
+  UINT32  Flags;
+  UINT32  ClockDomain;
+  UINT8   Reserved2[4];
+} EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
+
+///
+/// System Locality Distance Information Table (SLIT).
+/// The rest of the table is a matrix.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT64                      NumberOfSystemLocalities;
+} EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+///
+/// SLIT Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION  0x01
+
+///
+/// Corrected Platform Error Polling Table (CPEP)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       Reserved[8];
+} EFI_ACPI_5_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
+
+///
+/// CPEP Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+
+//
+// CPEP processor structure types.
+//
+#define EFI_ACPI_5_0_CPEP_PROCESSOR_APIC_SAPIC  0x00
+
+///
+/// Corrected Platform Error Polling Processor Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT32  PollingInterval;
+} EFI_ACPI_5_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
+
+///
+/// Maximum System Characteristics Table (MSCT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      OffsetProxDomInfo;
+  UINT32                      MaximumNumberOfProximityDomains;
+  UINT32                      MaximumNumberOfClockDomains;
+  UINT64                      MaximumPhysicalAddress;
+} EFI_ACPI_5_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
+
+///
+/// MSCT Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+
+///
+/// Maximum Proximity Domain Information Structure Definition
+///
+typedef struct {
+  UINT8   Revision;
+  UINT8   Length;
+  UINT32  ProximityDomainRangeLow;
+  UINT32  ProximityDomainRangeHigh;
+  UINT32  MaximumProcessorCapacity;
+  UINT64  MaximumMemoryCapacity;
+} EFI_ACPI_5_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
+
+///
+/// ACPI RAS Feature Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       PlatformCommunicationChannelIdentifier[12];
+} EFI_ACPI_5_0_RAS_FEATURE_TABLE;
+
+///
+/// RASF Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_RAS_FEATURE_TABLE_REVISION 0x01
+
+///
+/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+  UINT32                      Signature;
+  UINT16                      Command;
+  UINT16                      Status;
+  UINT16                      Version;
+  UINT8                       RASCapabilities[16];
+  UINT8                       SetRASCapabilities[16];
+  UINT16                      NumberOfRASFParameterBlocks;
+  UINT32                      SetRASCapabilitiesStatus;
+} EFI_ACPI_5_0_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI RASF PCC command code
+///
+#define EFI_ACPI_5_0_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND  0x01
+
+///
+/// ACPI RASF Platform RAS Capabilities
+///
+#define EFI_ACPI_5_0_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED                          0x01
+#define EFI_ACPI_5_0_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED_AND_EXPOSED_TO_SOFTWARE  0x02
+
+///
+/// ACPI RASF Parameter Block structure for PATROL_SCRUB
+///
+typedef struct {
+  UINT16                      Type;
+  UINT16                      Version;
+  UINT16                      Length;
+  UINT16                      PatrolScrubCommand;
+  UINT64                      RequestedAddressRange[2];
+  UINT64                      ActualAddressRange[2];
+  UINT16                      Flags;
+  UINT8                       RequestedSpeed;
+} EFI_ACPI_5_0_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
+
+///
+/// ACPI RASF Patrol Scrub command
+///
+#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS   0x01
+#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER   0x02
+#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER    0x03
+
+///
+/// Memory Power State Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       PlatformCommunicationChannelIdentifier;
+  UINT8                       Reserved[3];
+// Memory Power Node Structure
+// Memory Power State Characteristics
+} EFI_ACPI_5_0_MEMORY_POWER_STATUS_TABLE;
+
+///
+/// MPST Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+
+///
+/// MPST Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+  UINT32                      Signature;
+  UINT16                      Command;
+  UINT16                      Status;
+  UINT32                      MemoryPowerCommandRegister;
+  UINT32                      MemoryPowerStatusRegister;
+  UINT32                      PowerStateId;
+  UINT32                      MemoryPowerNodeId;
+  UINT64                      MemoryEnergyConsumed;
+  UINT64                      ExpectedAveragePowerComsuned;
+} EFI_ACPI_5_0_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI MPST PCC command code
+///
+#define EFI_ACPI_5_0_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND  0x03
+
+///
+/// ACPI MPST Memory Power command
+///
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE       0x01
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE       0x02
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED   0x03
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED   0x04
+
+///
+/// MPST Memory Power Node Table
+///
+typedef struct {
+  UINT8                                             PowerStateValue;
+  UINT8                                             PowerStateInformationIndex;
+} EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE;
+
+typedef struct {
+  UINT8                                             Flag;
+  UINT8                                             Reserved;
+  UINT16                                            MemoryPowerNodeId;
+  UINT32                                            Length;
+  UINT64                                            AddressBase;
+  UINT64                                            AddressLength;
+  UINT32                                            NumberOfPowerStates;
+  UINT32                                            NumberOfPhysicalComponents;
+//EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE              MemoryPowerState[NumberOfPowerStates];
+//UINT16                                            PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+} EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE;
+
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE          0x01
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED   0x02
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE   0x04
+
+typedef struct {
+  UINT16                      MemoryPowerNodeCount;
+  UINT8                       Reserved[2];
+} EFI_ACPI_5_0_MPST_MEMORY_POWER_NODE_TABLE;
+
+///
+/// MPST Memory Power State Characteristics Table
+///
+typedef struct {
+  UINT8                                             PowerStateStructureID;
+  UINT8                                             Flag;
+  UINT16                                            Reserved;
+  UINT32                                            AveragePowerConsumedInMPS0;
+  UINT32                                            RelativePowerSavingToMPS0;
+  UINT64                                            ExitLatencyToMPS0;
+} EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
+
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED              0x01
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY   0x02
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT    0x04
+
+typedef struct {
+  UINT16                      MemoryPowerStateCharacteristicsCount;
+  UINT8                       Reserved[2];
+} EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
+
+///
+/// Memory Topology Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Reserved;
+} EFI_ACPI_5_0_MEMORY_TOPOLOGY_TABLE;
+
+///
+/// PMTT Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
+
+///
+/// Common Memory Aggregator Device Structure.
+///
+typedef struct {
+  UINT8                       Type;
+  UINT8                       Reserved;
+  UINT16                      Length;
+  UINT16                      Flags;
+  UINT16                      Reserved1;
+} EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Memory Aggregator Device Type
+///
+#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET            0x1
+#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x2
+#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM              0x3
+
+///
+/// Socket Memory Aggregator Device Structure.
+///
+typedef struct {
+  EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  Header;
+  UINT16                                                       SocketIdentifier;
+  UINT16                                                       Reserved;
+//EFI_ACPI_5_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  MemoryController[];
+} EFI_ACPI_5_0_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// MemoryController Memory Aggregator Device Structure.
+///
+typedef struct {
+  EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  Header;
+  UINT32                                                       ReadLatency;
+  UINT32                                                       WriteLatency;
+  UINT32                                                       ReadBandwidth;
+  UINT32                                                       WriteBandwidth;
+  UINT16                                                       OptimalAccessUnit;
+  UINT16                                                       OptimalAccessAlignment;
+  UINT16                                                       Reserved;
+  UINT16                                                       NumberOfProximityDomains;
+//UINT32                                                       ProximityDomain[NumberOfProximityDomains];
+//EFI_ACPI_5_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE    PhysicalComponent[];
+} EFI_ACPI_5_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// DIMM Memory Aggregator Device Structure.
+///
+typedef struct {
+  EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  Header;
+  UINT16                                                       PhysicalComponentIdentifier;
+  UINT16                                                       Reserved;
+  UINT32                                                       SizeOfDimm;
+  UINT32                                                       SmbiosHandle;
+} EFI_ACPI_5_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Boot Graphics Resource Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  ///
+  /// 2-bytes (16 bit) version ID. This value must be 1.
+  ///
+  UINT16                      Version;
+  ///
+  /// 1-byte status field indicating current status about the table.
+  ///     Bits[7:1] = Reserved (must be zero)
+  ///     Bit [0] = Valid. A one indicates the boot image graphic is valid.
+  ///
+  UINT8                       Status;
+  ///
+  /// 1-byte enumerated type field indicating format of the image.
+  ///     0 = Bitmap
+  ///     1 - 255  Reserved (for future use)
+  ///
+  UINT8                       ImageType;
+  ///
+  /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
+  /// of the image bitmap.
+  ///
+  UINT64                      ImageAddress;
+  ///
+  /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
+  /// (X, Y) display offset of the top left corner of the boot image.
+  /// The top left corner of the display is at offset (0, 0).
+  ///
+  UINT32                      ImageOffsetX;
+  ///
+  /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
+  /// (X, Y) display offset of the top left corner of the boot image.
+  /// The top left corner of the display is at offset (0, 0).
+  ///
+  UINT32                      ImageOffsetY;
+} EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE;
+
+///
+/// BGRT Revision
+///
+#define EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+
+///
+/// BGRT Version
+///
+#define EFI_ACPI_5_0_BGRT_VERSION         0x01
+
+///
+/// BGRT Status
+///
+#define EFI_ACPI_5_0_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_5_0_BGRT_STATUS_DISPLAYED     0x01
+#define EFI_ACPI_5_0_BGRT_STATUS_INVALID       EFI_ACPI_5_0_BGRT_STATUS_NOT_DISPLAYED
+#define EFI_ACPI_5_0_BGRT_STATUS_VALID         EFI_ACPI_5_0_BGRT_STATUS_DISPLAYED
+
+///
+/// BGRT Image Type
+///
+#define EFI_ACPI_5_0_BGRT_IMAGE_TYPE_BMP  0x00
+
+///
+/// FPDT Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+
+///
+/// FPDT Performance Record Types
+///
+#define EFI_ACPI_5_0_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER      0x0000
+#define EFI_ACPI_5_0_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER     0x0001
+
+///
+/// FPDT Performance Record Revision
+///
+#define EFI_ACPI_5_0_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER  0x01
+#define EFI_ACPI_5_0_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+
+///
+/// FPDT Runtime Performance Record Types
+///
+#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME                0x0000
+#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND               0x0001
+#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT      0x0002
+
+///
+/// FPDT Runtime Performance Record Revision
+///
+#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME            0x01
+#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND           0x01
+#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT  0x02
+
+///
+/// FPDT Performance Record header
+///
+typedef struct {
+  UINT16           Type;
+  UINT8            Length;
+  UINT8            Revision;
+} EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER;
+
+///
+/// FPDT Performance Table header
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+} EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER;
+
+///
+/// FPDT Firmware Basic Boot Performance Pointer Record Structure
+///
+typedef struct {
+  EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  UINT32                                          Reserved;
+  ///
+  /// 64-bit processor-relative physical address of the Basic Boot Performance Table.
+  ///
+  UINT64                                          BootPerformanceTablePointer;
+} EFI_ACPI_5_0_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT S3 Performance Table Pointer Record Structure
+///
+typedef struct {
+  EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  UINT32                                          Reserved;
+  ///
+  /// 64-bit processor-relative physical address of the S3 Performance Table.
+  ///
+  UINT64                                          S3PerformanceTablePointer;
+} EFI_ACPI_5_0_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Record Structure
+///
+typedef struct {
+  EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  UINT32                                          Reserved;
+  ///
+  /// Timer value logged at the beginning of firmware image execution.
+  /// This may not always be zero or near zero.
+  ///
+  UINT64                                          ResetEnd;
+  ///
+  /// Timer value logged just prior to loading the OS boot loader into memory.
+  /// For non-UEFI compatible boots, this field must be zero.
+  ///
+  UINT64                                          OsLoaderLoadImageStart;
+  ///
+  /// Timer value logged just prior to launching the previously loaded OS boot loader image.
+  /// For non-UEFI compatible boots, the timer value logged will be just prior
+  /// to the INT 19h handler invocation.
+  ///
+  UINT64                                          OsLoaderStartImageStart;
+  ///
+  /// Timer value logged at the point when the OS loader calls the
+  /// ExitBootServices function for UEFI compatible firmware.
+  /// For non-UEFI compatible boots, this field must be zero.
+  ///
+  UINT64                                          ExitBootServicesEntry;
+  ///
+  /// Timer value logged at the point just prior towhen the OS loader gaining
+  /// control back from calls the ExitBootServices function for UEFI compatible firmware.
+  /// For non-UEFI compatible boots, this field must be zero.
+  ///
+  UINT64                                          ExitBootServicesExit;
+} EFI_ACPI_5_0_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Table signature
+///
+#define EFI_ACPI_5_0_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE  SIGNATURE_32('F', 'B', 'P', 'T')
+
+//
+// FPDT Firmware Basic Boot Performance Table
+//
+typedef struct {
+  EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER      Header;
+  //
+  // one or more Performance Records.
+  //
+} EFI_ACPI_5_0_FPDT_FIRMWARE_BASIC_BOOT_TABLE;
+
+///
+/// FPDT "S3PT" S3 Performance Table
+///
+#define EFI_ACPI_5_0_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE  SIGNATURE_32('S', '3', 'P', 'T')
+
+//
+// FPDT Firmware S3 Boot Performance Table
+//
+typedef struct {
+  EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER      Header;
+  //
+  // one or more Performance Records.
+  //
+} EFI_ACPI_5_0_FPDT_FIRMWARE_S3_BOOT_TABLE;
+
+///
+/// FPDT Basic S3 Resume Performance Record
+///
+typedef struct {
+  EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  ///
+  /// A count of the number of S3 resume cycles since the last full boot sequence.
+  ///
+  UINT32                                          ResumeCount;
+  ///
+  /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
+  /// OS waking vector. Only the most recent resume cycle's time is retained.
+  ///
+  UINT64                                          FullResume;
+  ///
+  /// Average timer value of all resume cycles logged since the last full boot
+  /// sequence, including the most recent resume.  Note that the entire log of
+  /// timer values does not need to be retained in order to calculate this average.
+  ///
+  UINT64                                          AverageResume;
+} EFI_ACPI_5_0_FPDT_S3_RESUME_RECORD;
+
+///
+/// FPDT Basic S3 Suspend Performance Record
+///
+typedef struct {
+  EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  ///
+  /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
+  /// Only the most recent suspend cycle's timer value is retained.
+  ///
+  UINT64                                          SuspendStart;
+  ///
+  /// Timer value recorded at the final firmware write to SLP_TYP (or other
+  /// mechanism) used to trigger hardware entry to S3.
+  /// Only the most recent suspend cycle's timer value is retained.
+  ///
+  UINT64                                          SuspendEnd;
+} EFI_ACPI_5_0_FPDT_S3_SUSPEND_RECORD;
+
+///
+/// Firmware Performance Record Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_RECORD_TABLE;
+
+///
+/// Generic Timer Description Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT64                      PhysicalAddress;
+  UINT32                      GlobalFlags;
+  UINT32                      SecurePL1TimerGSIV;
+  UINT32                      SecurePL1TimerFlags;
+  UINT32                      NonSecurePL1TimerGSIV;
+  UINT32                      NonSecurePL1TimerFlags;
+  UINT32                      VirtualTimerGSIV;
+  UINT32                      VirtualTimerFlags;
+  UINT32                      NonSecurePL2TimerGSIV;
+  UINT32                      NonSecurePL2TimerFlags;
+} EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE;
+
+///
+/// GTDT Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Global Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT   BIT0
+#define EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE                BIT1
+
+///
+/// Timer Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE          BIT0
+#define EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY      BIT1
+
+///
+/// Boot Error Record Table (BERT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      BootErrorRegionLength;
+  UINT64                      BootErrorRegion;
+} EFI_ACPI_5_0_BOOT_ERROR_RECORD_TABLE_HEADER;
+
+///
+/// BERT Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+
+///
+/// Boot Error Region Block Status Definition
+///
+typedef struct {
+  UINT32       UncorrectableErrorValid:1;
+  UINT32       CorrectableErrorValid:1;
+  UINT32       MultipleUncorrectableErrors:1;
+  UINT32       MultipleCorrectableErrors:1;
+  UINT32       ErrorDataEntryCount:10;
+  UINT32       Reserved:18;
+} EFI_ACPI_5_0_ERROR_BLOCK_STATUS;
+
+///
+/// Boot Error Region Definition
+///
+typedef struct {
+  EFI_ACPI_5_0_ERROR_BLOCK_STATUS              BlockStatus;
+  UINT32                                       RawDataOffset;
+  UINT32                                       RawDataLength;
+  UINT32                                       DataLength;
+  UINT32                                       ErrorSeverity;
+} EFI_ACPI_5_0_BOOT_ERROR_REGION_STRUCTURE;
+
+//
+// Boot Error Severity types
+//
+#define EFI_ACPI_5_0_ERROR_SEVERITY_CORRECTABLE  0x00
+#define EFI_ACPI_5_0_ERROR_SEVERITY_FATAL        0x01
+#define EFI_ACPI_5_0_ERROR_SEVERITY_CORRECTED    0x02
+#define EFI_ACPI_5_0_ERROR_SEVERITY_NONE         0x03
+
+///
+/// Generic Error Data Entry Definition
+///
+typedef struct {
+  UINT8    SectionType[16];
+  UINT32   ErrorSeverity;
+  UINT16   Revision;
+  UINT8    ValidationBits;
+  UINT8    Flags;
+  UINT32   ErrorDataLength;
+  UINT8    FruId[16];
+  UINT8    FruText[20];
+} EFI_ACPI_5_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
+
+///
+/// Generic Error Data Entry Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_GENERIC_ERROR_DATA_ENTRY_REVISION  0x0201
+
+///
+/// HEST - Hardware Error Source Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      ErrorSourceCount;
+} EFI_ACPI_5_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
+
+///
+/// HEST Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+
+//
+// Error Source structure types.
+//
+#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION  0x00
+#define EFI_ACPI_5_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK  0x01
+#define EFI_ACPI_5_0_IA32_ARCHITECTURE_NMI_ERROR                0x02
+#define EFI_ACPI_5_0_PCI_EXPRESS_ROOT_PORT_AER                  0x06
+#define EFI_ACPI_5_0_PCI_EXPRESS_DEVICE_AER                     0x07
+#define EFI_ACPI_5_0_PCI_EXPRESS_BRIDGE_AER                     0x08
+#define EFI_ACPI_5_0_GENERIC_HARDWARE_ERROR                     0x09
+
+//
+// Error Source structure flags.
+//
+#define EFI_ACPI_5_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST       (1 << 0)
+#define EFI_ACPI_5_0_ERROR_SOURCE_FLAG_GLOBAL               (1 << 1)
+
+///
+/// IA-32 Architecture Machine Check Exception Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT64  GlobalCapabilityInitData;
+  UINT64  GlobalControlInitData;
+  UINT8   NumberOfHardwareBanks;
+  UINT8   Reserved1[7];
+} EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure Definition
+///
+typedef struct {
+  UINT8   BankNumber;
+  UINT8   ClearStatusOnInitialization;
+  UINT8   StatusDataFormat;
+  UINT8   Reserved0;
+  UINT32  ControlRegisterMsrAddress;
+  UINT64  ControlInitData;
+  UINT32  StatusRegisterMsrAddress;
+  UINT32  AddressRegisterMsrAddress;
+  UINT32  MiscRegisterMsrAddress;
+} EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure MCA data format
+///
+#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32      0x00
+#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64   0x01
+#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64     0x02
+
+//
+// Hardware Error Notification types. All other values are reserved
+//
+#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_POLLED                0x00
+#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT    0x01
+#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT       0x02
+#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_SCI                   0x03
+#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_NMI                   0x04
+
+///
+/// Hardware Error Notification Configuration Write Enable Structure Definition
+///
+typedef struct {
+  UINT16    Type:1;
+  UINT16    PollInterval:1;
+  UINT16    SwitchToPollingThresholdValue:1;
+  UINT16    SwitchToPollingThresholdWindow:1;
+  UINT16    ErrorThresholdValue:1;
+  UINT16    ErrorThresholdWindow:1;
+  UINT16    Reserved:10;
+} EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
+
+///
+/// Hardware Error Notification Structure Definition
+///
+typedef struct {
+  UINT8                                                                          Type;
+  UINT8                                                                          Length;
+  EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE  ConfigurationWriteEnable;
+  UINT32                                                                         PollInterval;
+  UINT32                                                                         Vector;
+  UINT32                                                                         SwitchToPollingThresholdValue;
+  UINT32                                                                         SwitchToPollingThresholdWindow;
+  UINT32                                                                         ErrorThresholdValue;
+  UINT32                                                                         ErrorThresholdWindow;
+} EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
+
+///
+/// IA-32 Architecture Corrected Machine Check Structure Definition
+///
+typedef struct {
+  UINT16                                                 Type;
+  UINT16                                                 SourceId;
+  UINT8                                                  Reserved0[2];
+  UINT8                                                  Flags;
+  UINT8                                                  Enabled;
+  UINT32                                                 NumberOfRecordsToPreAllocate;
+  UINT32                                                 MaxSectionsPerRecord;
+  EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE     NotificationStructure;
+  UINT8                                                  NumberOfHardwareBanks;
+  UINT8                                                  Reserved1[3];
+} EFI_ACPI_5_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// IA-32 Architecture NMI Error Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  MaxRawDataLength;
+} EFI_ACPI_5_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
+
+///
+/// PCI Express Root Port AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+  UINT32  RootErrorCommand;
+} EFI_ACPI_5_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
+
+///
+/// PCI Express Device AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_5_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
+
+///
+/// PCI Express Bridge AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+  UINT32  SecondaryUncorrectableErrorMask;
+  UINT32  SecondaryUncorrectableErrorSeverity;
+  UINT32  SecondaryAdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_5_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Structure Definition
+///
+typedef struct {
+  UINT16                                                 Type;
+  UINT16                                                 SourceId;
+  UINT16                                                 RelatedSourceId;
+  UINT8                                                  Flags;
+  UINT8                                                  Enabled;
+  UINT32                                                 NumberOfRecordsToPreAllocate;
+  UINT32                                                 MaxSectionsPerRecord;
+  UINT32                                                 MaxRawDataLength;
+  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE                 ErrorStatusAddress;
+  EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE     NotificationStructure;
+  UINT32                                                 ErrorStatusBlockLength;
+} EFI_ACPI_5_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
+
+///
+/// Generic Error Status Definition
+///
+typedef struct {
+  EFI_ACPI_5_0_ERROR_BLOCK_STATUS              BlockStatus;
+  UINT32                                       RawDataOffset;
+  UINT32                                       RawDataLength;
+  UINT32                                       DataLength;
+  UINT32                                       ErrorSeverity;
+} EFI_ACPI_5_0_GENERIC_ERROR_STATUS_STRUCTURE;
+
+///
+/// ERST - Error Record Serialization Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      SerializationHeaderSize;
+  UINT8                       Reserved0[4];
+  UINT32                      InstructionEntryCount;
+} EFI_ACPI_5_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
+
+///
+/// ERST Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+
+///
+/// ERST Serialization Actions
+///
+#define EFI_ACPI_5_0_ERST_BEGIN_WRITE_OPERATION                    0x00
+#define EFI_ACPI_5_0_ERST_BEGIN_READ_OPERATION                     0x01
+#define EFI_ACPI_5_0_ERST_BEGIN_CLEAR_OPERATION                    0x02
+#define EFI_ACPI_5_0_ERST_END_OPERATION                            0x03
+#define EFI_ACPI_5_0_ERST_SET_RECORD_OFFSET                        0x04
+#define EFI_ACPI_5_0_ERST_EXECUTE_OPERATION                        0x05
+#define EFI_ACPI_5_0_ERST_CHECK_BUSY_STATUS                        0x06
+#define EFI_ACPI_5_0_ERST_GET_COMMAND_STATUS                       0x07
+#define EFI_ACPI_5_0_ERST_GET_RECORD_IDENTIFIER                    0x08
+#define EFI_ACPI_5_0_ERST_SET_RECORD_IDENTIFIER                    0x09
+#define EFI_ACPI_5_0_ERST_GET_RECORD_COUNT                         0x0A
+#define EFI_ACPI_5_0_ERST_BEGIN_DUMMY_WRITE_OPERATION              0x0B
+#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE              0x0D
+#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH       0x0E
+#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES   0x0F
+
+///
+/// ERST Action Command Status
+///
+#define EFI_ACPI_5_0_ERST_STATUS_SUCCESS                           0x00
+#define EFI_ACPI_5_0_ERST_STATUS_NOT_ENOUGH_SPACE                  0x01
+#define EFI_ACPI_5_0_ERST_STATUS_HARDWARE_NOT_AVAILABLE            0x02
+#define EFI_ACPI_5_0_ERST_STATUS_FAILED                            0x03
+#define EFI_ACPI_5_0_ERST_STATUS_RECORD_STORE_EMPTY                0x04
+#define EFI_ACPI_5_0_ERST_STATUS_RECORD_NOT_FOUND                  0x05
+
+///
+/// ERST Serialization Instructions
+///
+#define EFI_ACPI_5_0_ERST_READ_REGISTER                            0x00
+#define EFI_ACPI_5_0_ERST_READ_REGISTER_VALUE                      0x01
+#define EFI_ACPI_5_0_ERST_WRITE_REGISTER                           0x02
+#define EFI_ACPI_5_0_ERST_WRITE_REGISTER_VALUE                     0x03
+#define EFI_ACPI_5_0_ERST_NOOP                                     0x04
+#define EFI_ACPI_5_0_ERST_LOAD_VAR1                                0x05
+#define EFI_ACPI_5_0_ERST_LOAD_VAR2                                0x06
+#define EFI_ACPI_5_0_ERST_STORE_VAR1                               0x07
+#define EFI_ACPI_5_0_ERST_ADD                                      0x08
+#define EFI_ACPI_5_0_ERST_SUBTRACT                                 0x09
+#define EFI_ACPI_5_0_ERST_ADD_VALUE                                0x0A
+#define EFI_ACPI_5_0_ERST_SUBTRACT_VALUE                           0x0B
+#define EFI_ACPI_5_0_ERST_STALL                                    0x0C
+#define EFI_ACPI_5_0_ERST_STALL_WHILE_TRUE                         0x0D
+#define EFI_ACPI_5_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE            0x0E
+#define EFI_ACPI_5_0_ERST_GOTO                                     0x0F
+#define EFI_ACPI_5_0_ERST_SET_SRC_ADDRESS_BASE                     0x10
+#define EFI_ACPI_5_0_ERST_SET_DST_ADDRESS_BASE                     0x11
+#define EFI_ACPI_5_0_ERST_MOVE_DATA                                0x12
+
+///
+/// ERST Instruction Flags
+///
+#define EFI_ACPI_5_0_ERST_PRESERVE_REGISTER                        0x01
+
+///
+/// ERST Serialization Instruction Entry
+///
+typedef struct {
+  UINT8                                    SerializationAction;
+  UINT8                                    Instruction;
+  UINT8                                    Flags;
+  UINT8                                    Reserved0;
+  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE   RegisterRegion;
+  UINT64                                   Value;
+  UINT64                                   Mask;
+} EFI_ACPI_5_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ - Error Injection Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      InjectionHeaderSize;
+  UINT8                       InjectionFlags;
+  UINT8                       Reserved0[3];
+  UINT32                      InjectionEntryCount;
+} EFI_ACPI_5_0_ERROR_INJECTION_TABLE_HEADER;
+
+///
+/// EINJ Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_ERROR_INJECTION_TABLE_REVISION 0x01
+
+///
+/// EINJ Error Injection Actions
+///
+#define EFI_ACPI_5_0_EINJ_BEGIN_INJECTION_OPERATION                0x00
+#define EFI_ACPI_5_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE           0x01
+#define EFI_ACPI_5_0_EINJ_SET_ERROR_TYPE                           0x02
+#define EFI_ACPI_5_0_EINJ_GET_ERROR_TYPE                           0x03
+#define EFI_ACPI_5_0_EINJ_END_OPERATION                            0x04
+#define EFI_ACPI_5_0_EINJ_EXECUTE_OPERATION                        0x05
+#define EFI_ACPI_5_0_EINJ_CHECK_BUSY_STATUS                        0x06
+#define EFI_ACPI_5_0_EINJ_GET_COMMAND_STATUS                       0x07
+#define EFI_ACPI_5_0_EINJ_TRIGGER_ERROR                            0xFF
+
+///
+/// EINJ Action Command Status
+///
+#define EFI_ACPI_5_0_EINJ_STATUS_SUCCESS                           0x00
+#define EFI_ACPI_5_0_EINJ_STATUS_UNKNOWN_FAILURE                   0x01
+#define EFI_ACPI_5_0_EINJ_STATUS_INVALID_ACCESS                    0x02
+
+///
+/// EINJ Error Type Definition
+///
+#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_CORRECTABLE                 (1 << 0)
+#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL      (1 << 1)
+#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL         (1 << 2)
+#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_CORRECTABLE                    (1 << 3)
+#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL         (1 << 4)
+#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL            (1 << 5)
+#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE               (1 << 6)
+#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL    (1 << 7)
+#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL       (1 << 8)
+#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_CORRECTABLE                  (1 << 9)
+#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL       (1 << 10)
+#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL          (1 << 11)
+
+///
+/// EINJ Injection Instructions
+///
+#define EFI_ACPI_5_0_EINJ_READ_REGISTER                            0x00
+#define EFI_ACPI_5_0_EINJ_READ_REGISTER_VALUE                      0x01
+#define EFI_ACPI_5_0_EINJ_WRITE_REGISTER                           0x02
+#define EFI_ACPI_5_0_EINJ_WRITE_REGISTER_VALUE                     0x03
+#define EFI_ACPI_5_0_EINJ_NOOP                                     0x04
+
+///
+/// EINJ Instruction Flags
+///
+#define EFI_ACPI_5_0_EINJ_PRESERVE_REGISTER                        0x01
+
+///
+/// EINJ Injection Instruction Entry
+///
+typedef struct {
+  UINT8                                    InjectionAction;
+  UINT8                                    Instruction;
+  UINT8                                    Flags;
+  UINT8                                    Reserved0;
+  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE   RegisterRegion;
+  UINT64                                   Value;
+  UINT64                                   Mask;
+} EFI_ACPI_5_0_EINJ_INJECTION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ Trigger Action Table
+///
+typedef struct {
+  UINT32  HeaderSize;
+  UINT32  Revision;
+  UINT32  TableSize;
+  UINT32  EntryCount;
+} EFI_ACPI_5_0_EINJ_TRIGGER_ACTION_TABLE;
+
+///
+/// Platform Communications Channel Table (PCCT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Flags;
+  UINT64                      Reserved;
+} EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
+
+///
+/// PCCT Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01
+
+///
+/// PCCT Global Flags
+///
+#define EFI_ACPI_5_0_PCCT_FLAGS_SCI_DOORBELL                      BIT0
+
+//
+// PCCT Subspace type
+//
+#define EFI_ACPI_5_0_PCCT_SUBSPACE_TYPE_GENERIC  0x00
+
+///
+/// PCC Subspace Structure Header
+///
+typedef struct {
+  UINT8        Type;
+  UINT8        Length;
+} EFI_ACPI_5_0_PCCT_SUBSPACE_HEADER;
+
+///
+/// Generic Communications Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT8                                    Reserved[6];
+  UINT64                                   BaseAddress;
+  UINT64                                   AddressLength;
+  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT16                                   MinimumRequestTurnaroundTime;
+} EFI_ACPI_5_0_PCCT_SUBSPACE_GENERIC;
+
+///
+/// Generic Communications Channel Shared Memory Region
+///
+
+typedef struct {
+  UINT8                                    Command;
+  UINT8                                    Reserved:7;
+  UINT8                                    GenerateSci:1;
+} EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
+
+typedef struct {
+  UINT8                                    CommandComplete:1;
+  UINT8                                    SciDoorbell:1;
+  UINT8                                    Error:1;
+  UINT8                                    PlatformNotification:1;
+  UINT8                                    Reserved:4;
+  UINT8                                    Reserved1;
+} EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
+
+typedef struct {
+  UINT32                                                    Signature;
+  EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND    Command;
+  EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS     Status;
+} EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') 
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "BERT" Boot Error Record Table
+///
+#define EFI_ACPI_5_0_BOOT_ERROR_RECORD_TABLE_SIGNATURE  SIGNATURE_32('B', 'E', 'R', 'T')
+
+///
+/// "BGRT" Boot Graphics Resource Table
+///
+#define EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('B', 'G', 'R', 'T')
+
+///
+/// "CPEP" Corrected Platform Error Polling Table
+///
+#define EFI_ACPI_5_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE  SIGNATURE_32('C', 'P', 'E', 'P')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_5_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE  SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "EINJ" Error Injection Table
+///
+#define EFI_ACPI_5_0_ERROR_INJECTION_TABLE_SIGNATURE  SIGNATURE_32('E', 'I', 'N', 'J')
+
+///
+/// "ERST" Error Record Serialization Table
+///
+#define EFI_ACPI_5_0_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE  SIGNATURE_32('E', 'R', 'S', 'T')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "FPDT" Firmware Performance Data Table
+///
+#define EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE  SIGNATURE_32('F', 'P', 'D', 'T')
+
+///
+/// "GTDT" Generic Timer Description Table
+///
+#define EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('G', 'T', 'D', 'T')
+
+///
+/// "HEST" Hardware Error Source Table
+///
+#define EFI_ACPI_5_0_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE  SIGNATURE_32('H', 'E', 'S', 'T')
+
+///
+/// "MPST" Memory Power State Table
+///
+#define EFI_ACPI_5_0_MEMORY_POWER_STATE_TABLE_SIGNATURE  SIGNATURE_32('M', 'P', 'S', 'T')
+
+///
+/// "MSCT" Maximum System Characteristics Table
+///
+#define EFI_ACPI_5_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE  SIGNATURE_32('M', 'S', 'C', 'T')
+
+///
+/// "PMTT" Platform Memory Topology Table
+///
+#define EFI_ACPI_5_0_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE  SIGNATURE_32('P', 'M', 'T', 'T')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_5_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RASF" ACPI RAS Feature Table
+///
+#define EFI_ACPI_5_0_ACPI_RAS_FEATURE_TABLE_SIGNATURE  SIGNATURE_32('R', 'A', 'S', 'F')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_5_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SRAT" System Resource Affinity Table
+///
+#define EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE  SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_5_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_5_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_5_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE  SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "CSRT" MS Core System Resource Table
+///
+#define EFI_ACPI_5_0_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('C', 'S', 'R', 'T')
+
+///
+/// "DBG2" MS Debug Port 2 Spec
+///
+#define EFI_ACPI_5_0_DEBUG_PORT_2_TABLE_SIGNATURE  SIGNATURE_32('D', 'B', 'G', '2')
+
+///
+/// "DBGP" MS Debug Port Spec
+///
+#define EFI_ACPI_5_0_DEBUG_PORT_TABLE_SIGNATURE  SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "DMAR" DMA Remapping Table
+///
+#define EFI_ACPI_5_0_DMA_REMAPPING_TABLE_SIGNATURE  SIGNATURE_32('D', 'M', 'A', 'R')
+
+///
+/// "DRTM" Dynamic Root of Trust for Measurement Table
+///
+#define EFI_ACPI_5_0_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE  SIGNATURE_32('D', 'R', 'T', 'M')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_5_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "HPET" IA-PC High Precision Event Timer Table
+///
+#define EFI_ACPI_5_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE  SIGNATURE_32('H', 'P', 'E', 'T')
+
+///
+/// "iBFT" iSCSI Boot Firmware Table
+///
+#define EFI_ACPI_5_0_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE  SIGNATURE_32('i', 'B', 'F', 'T')
+
+///
+/// "IVRS" I/O Virtualization Reporting Structure
+///
+#define EFI_ACPI_5_0_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE  SIGNATURE_32('I', 'V', 'R', 'S')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('M', 'C', 'F', 'G')
+
+///
+/// "MCHI" Management Controller Host Interface Table
+///
+#define EFI_ACPI_5_0_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('M', 'C', 'H', 'I')
+
+///
+/// "MSDM" MS Data Management Table
+///
+#define EFI_ACPI_5_0_DATA_MANAGEMENT_TABLE_SIGNATURE  SIGNATURE_32('M', 'S', 'D', 'M')
+
+///
+/// "SLIC" MS Software Licensing Table Specification
+///
+#define EFI_ACPI_5_0_SOFTWARE_LICENSING_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'C')
+
+///
+/// "SPCR" Serial Port Concole Redirection Table
+///
+#define EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_5_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+///
+#define EFI_ACPI_5_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE  SIGNATURE_32('T', 'C', 'P', 'A')
+
+///
+/// "TPM2" Trusted Computing Platform 1 Table
+///
+#define EFI_ACPI_5_0_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE  SIGNATURE_32('T', 'P', 'M', '2')
+
+///
+/// "UEFI" UEFI ACPI Data Table
+///
+#define EFI_ACPI_5_0_UEFI_ACPI_DATA_TABLE_SIGNATURE  SIGNATURE_32('U', 'E', 'F', 'I')
+
+///
+/// "WAET" Windows ACPI Emulated Devices Table
+///
+#define EFI_ACPI_5_0_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE  SIGNATURE_32('W', 'A', 'E', 'T')
+#define EFI_ACPI_5_0_WINDOWS_ACPI_ENLIGHTENMENT_TABLE_SIGNATURE  EFI_ACPI_5_0_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE
+
+///
+/// "WDAT" Watchdog Action Table
+///
+#define EFI_ACPI_5_0_WATCHDOG_ACTION_TABLE_SIGNATURE  SIGNATURE_32('W', 'D', 'A', 'T')
+
+///
+/// "WDRT" Watchdog Resource Table
+///
+#define EFI_ACPI_5_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('W', 'D', 'R', 'T')
+
+///
+/// "WPBT" MS Platform Binary Table
+///
+#define EFI_ACPI_5_0_PLATFORM_BINARY_TABLE_SIGNATURE  SIGNATURE_32('W', 'P', 'B', 'T')
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi51.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi51.h
new file mode 100644
index 0000000000..457706befd
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi51.h
@@ -0,0 +1,2139 @@
+/** @file   
+  ACPI 5.1 definitions from the ACPI Specification Revision 5.1 Errata B January, 2016.
+
+  Copyright (c) 2014 Hewlett-Packard Development Company, L.P.<BR>
+  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+  (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+**/
+
+#ifndef _ACPI_5_1_H_
+#define _ACPI_5_1_H_
+
+#include <IndustryStandard/Acpi50.h>
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 5.1 Generic Address Space definition
+///
+typedef struct {
+  UINT8   AddressSpaceId;
+  UINT8   RegisterBitWidth;
+  UINT8   RegisterBitOffset;
+  UINT8   AccessSize;
+  UINT64  Address;
+} EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_5_1_SYSTEM_MEMORY              0
+#define EFI_ACPI_5_1_SYSTEM_IO                  1
+#define EFI_ACPI_5_1_PCI_CONFIGURATION_SPACE    2
+#define EFI_ACPI_5_1_EMBEDDED_CONTROLLER        3
+#define EFI_ACPI_5_1_SMBUS                      4
+#define EFI_ACPI_5_1_PLATFORM_COMMUNICATION_CHANNEL  0x0A
+#define EFI_ACPI_5_1_FUNCTIONAL_FIXED_HARDWARE       0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_5_1_UNDEFINED  0
+#define EFI_ACPI_5_1_BYTE       1
+#define EFI_ACPI_5_1_WORD       2
+#define EFI_ACPI_5_1_DWORD      3
+#define EFI_ACPI_5_1_QWORD      4
+
+//
+// ACPI 5.1 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+  UINT64  Signature;
+  UINT8   Checksum;
+  UINT8   OemId[6];
+  UINT8   Revision;
+  UINT32  RsdtAddress;
+  UINT32  Length;
+  UINT64  XsdtAddress;
+  UINT8   ExtendedChecksum;
+  UINT8   Reserved[3];
+} EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02  ///< ACPISpec (Revision 5.1) says current value is 2
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+} EFI_ACPI_5_1_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with 
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with 
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  UINT32                                  FirmwareCtrl;
+  UINT32                                  Dsdt;
+  UINT8                                   Reserved0;
+  UINT8                                   PreferredPmProfile;
+  UINT16                                  SciInt;
+  UINT32                                  SmiCmd;
+  UINT8                                   AcpiEnable;
+  UINT8                                   AcpiDisable;
+  UINT8                                   S4BiosReq;
+  UINT8                                   PstateCnt;
+  UINT32                                  Pm1aEvtBlk;
+  UINT32                                  Pm1bEvtBlk;
+  UINT32                                  Pm1aCntBlk;
+  UINT32                                  Pm1bCntBlk;
+  UINT32                                  Pm2CntBlk;
+  UINT32                                  PmTmrBlk;
+  UINT32                                  Gpe0Blk;
+  UINT32                                  Gpe1Blk;
+  UINT8                                   Pm1EvtLen;
+  UINT8                                   Pm1CntLen;
+  UINT8                                   Pm2CntLen;
+  UINT8                                   PmTmrLen;
+  UINT8                                   Gpe0BlkLen;
+  UINT8                                   Gpe1BlkLen;
+  UINT8                                   Gpe1Base;
+  UINT8                                   CstCnt;
+  UINT16                                  PLvl2Lat;
+  UINT16                                  PLvl3Lat;
+  UINT16                                  FlushSize;
+  UINT16                                  FlushStride;
+  UINT8                                   DutyOffset;
+  UINT8                                   DutyWidth;
+  UINT8                                   DayAlrm;
+  UINT8                                   MonAlrm;
+  UINT8                                   Century;
+  UINT16                                  IaPcBootArch;
+  UINT8                                   Reserved1;
+  UINT32                                  Flags;
+  EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  ResetReg;
+  UINT8                                   ResetValue;
+  UINT16                                  ArmBootArch;
+  UINT8                                   MinorVersion;
+  UINT64                                  XFirmwareCtrl;
+  UINT64                                  XDsdt;
+  EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk;
+  EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk;
+  EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk;
+  EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk;
+  EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk;
+  EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk;
+  EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk;
+  EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk;
+  EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  SleepControlReg;
+  EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  SleepStatusReg;
+} EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION  0x05
+#define EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION  0x01
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_5_1_PM_PROFILE_UNSPECIFIED         0
+#define EFI_ACPI_5_1_PM_PROFILE_DESKTOP             1
+#define EFI_ACPI_5_1_PM_PROFILE_MOBILE              2
+#define EFI_ACPI_5_1_PM_PROFILE_WORKSTATION         3
+#define EFI_ACPI_5_1_PM_PROFILE_ENTERPRISE_SERVER   4
+#define EFI_ACPI_5_1_PM_PROFILE_SOHO_SERVER         5
+#define EFI_ACPI_5_1_PM_PROFILE_APPLIANCE_PC        6
+#define EFI_ACPI_5_1_PM_PROFILE_PERFORMANCE_SERVER  7
+#define EFI_ACPI_5_1_PM_PROFILE_TABLET              8
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_5_1_LEGACY_DEVICES              BIT0
+#define EFI_ACPI_5_1_8042                        BIT1
+#define EFI_ACPI_5_1_VGA_NOT_PRESENT             BIT2
+#define EFI_ACPI_5_1_MSI_NOT_SUPPORTED           BIT3
+#define EFI_ACPI_5_1_PCIE_ASPM_CONTROLS          BIT4
+#define EFI_ACPI_5_1_CMOS_RTC_NOT_PRESENT        BIT5
+
+//
+// Fixed ACPI Description Table Arm Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_5_1_ARM_PSCI_COMPLIANT              BIT0
+#define EFI_ACPI_5_1_ARM_PSCI_USE_HVC                BIT1
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_5_1_WBINVD                                 BIT0
+#define EFI_ACPI_5_1_WBINVD_FLUSH                           BIT1
+#define EFI_ACPI_5_1_PROC_C1                                BIT2
+#define EFI_ACPI_5_1_P_LVL2_UP                              BIT3
+#define EFI_ACPI_5_1_PWR_BUTTON                             BIT4
+#define EFI_ACPI_5_1_SLP_BUTTON                             BIT5
+#define EFI_ACPI_5_1_FIX_RTC                                BIT6
+#define EFI_ACPI_5_1_RTC_S4                                 BIT7
+#define EFI_ACPI_5_1_TMR_VAL_EXT                            BIT8
+#define EFI_ACPI_5_1_DCK_CAP                                BIT9
+#define EFI_ACPI_5_1_RESET_REG_SUP                          BIT10
+#define EFI_ACPI_5_1_SEALED_CASE                            BIT11
+#define EFI_ACPI_5_1_HEADLESS                               BIT12
+#define EFI_ACPI_5_1_CPU_SW_SLP                             BIT13
+#define EFI_ACPI_5_1_PCI_EXP_WAK                            BIT14
+#define EFI_ACPI_5_1_USE_PLATFORM_CLOCK                     BIT15
+#define EFI_ACPI_5_1_S4_RTC_STS_VALID                       BIT16
+#define EFI_ACPI_5_1_REMOTE_POWER_ON_CAPABLE                BIT17
+#define EFI_ACPI_5_1_FORCE_APIC_CLUSTER_MODEL               BIT18
+#define EFI_ACPI_5_1_FORCE_APIC_PHYSICAL_DESTINATION_MODE   BIT19
+#define EFI_ACPI_5_1_HW_REDUCED_ACPI                        BIT20
+#define EFI_ACPI_5_1_LOW_POWER_S0_IDLE_CAPABLE              BIT21
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+  UINT32  HardwareSignature;
+  UINT32  FirmwareWakingVector;
+  UINT32  GlobalLock;
+  UINT32  Flags;
+  UINT64  XFirmwareWakingVector;
+  UINT8   Version;
+  UINT8   Reserved0[3];
+  UINT32  OspmFlags;
+  UINT8   Reserved1[24];
+} EFI_ACPI_5_1_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION  0x02
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_5_1_S4BIOS_F                     BIT0
+#define EFI_ACPI_5_1_64BIT_WAKE_SUPPORTED_F       BIT1
+
+///
+/// OSPM Enabled Firmware Control Structure Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_5_1_OSPM_64BIT_WAKE_F            BIT0
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
+//
+#define EFI_ACPI_5_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION   0x02
+#define EFI_ACPI_5_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION        0x02
+
+///
+/// Multiple APIC Description Table header definition.  The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      LocalApicAddress;
+  UINT32                      Flags;
+} EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_5_1_PCAT_COMPAT         BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x0D and 0x7F are reserved and
+// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.
+//
+#define EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC           0x00
+#define EFI_ACPI_5_1_IO_APIC                        0x01
+#define EFI_ACPI_5_1_INTERRUPT_SOURCE_OVERRIDE      0x02
+#define EFI_ACPI_5_1_NON_MASKABLE_INTERRUPT_SOURCE  0x03
+#define EFI_ACPI_5_1_LOCAL_APIC_NMI                 0x04
+#define EFI_ACPI_5_1_LOCAL_APIC_ADDRESS_OVERRIDE    0x05
+#define EFI_ACPI_5_1_IO_SAPIC                       0x06
+#define EFI_ACPI_5_1_LOCAL_SAPIC                    0x07
+#define EFI_ACPI_5_1_PLATFORM_INTERRUPT_SOURCES     0x08
+#define EFI_ACPI_5_1_PROCESSOR_LOCAL_X2APIC         0x09
+#define EFI_ACPI_5_1_LOCAL_X2APIC_NMI               0x0A
+#define EFI_ACPI_5_1_GIC                            0x0B
+#define EFI_ACPI_5_1_GICD                           0x0C
+#define EFI_ACPI_5_1_GIC_MSI_FRAME                  0x0D
+#define EFI_ACPI_5_1_GICR                           0x0E
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT8   ApicId;
+  UINT32  Flags;
+} EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_1_LOCAL_APIC_ENABLED        BIT0
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  IoApicAddress;
+  UINT32  GlobalSystemInterruptBase;
+} EFI_ACPI_5_1_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Bus;
+  UINT8   Source;
+  UINT32  GlobalSystemInterrupt;
+  UINT16  Flags;
+} EFI_ACPI_5_1_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT8   InterruptType;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT8   IoSapicVector;
+  UINT32  GlobalSystemInterrupt;
+  UINT32  PlatformInterruptSourceFlags;
+  UINT8   CpeiProcessorOverride;
+  UINT8   Reserved[31];
+} EFI_ACPI_5_1_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_5_1_POLARITY      (3 << 0)
+#define EFI_ACPI_5_1_TRIGGER_MODE  (3 << 2)
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT32  GlobalSystemInterrupt;
+} EFI_ACPI_5_1_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT16  Flags;
+  UINT8   LocalApicLint;
+} EFI_ACPI_5_1_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT64  LocalApicAddress;
+} EFI_ACPI_5_1_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  GlobalSystemInterruptBase;
+  UINT64  IoSapicAddress;
+} EFI_ACPI_5_1_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT8   LocalSapicId;
+  UINT8   LocalSapicEid;
+  UINT8   Reserved[3];
+  UINT32  Flags;
+  UINT32  ACPIProcessorUIDValue;
+} EFI_ACPI_5_1_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT8   InterruptType;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT8   IoSapicVector;
+  UINT32  GlobalSystemInterrupt;
+  UINT32  PlatformInterruptSourceFlags;
+} EFI_ACPI_5_1_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Platform Interrupt Source Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_5_1_CPEI_PROCESSOR_OVERRIDE          BIT0
+
+///
+/// Processor Local x2APIC Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Reserved[2];
+  UINT32  X2ApicId;
+  UINT32  Flags;
+  UINT32  AcpiProcessorUid;
+} EFI_ACPI_5_1_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
+
+///
+/// Local x2APIC NMI Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT32  AcpiProcessorUid;
+  UINT8   LocalX2ApicLint;
+  UINT8   Reserved[3];
+} EFI_ACPI_5_1_LOCAL_X2APIC_NMI_STRUCTURE;
+
+///
+/// GIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT32  CPUInterfaceNumber;
+  UINT32  AcpiProcessorUid;
+  UINT32  Flags;
+  UINT32  ParkingProtocolVersion;
+  UINT32  PerformanceInterruptGsiv;
+  UINT64  ParkedAddress;
+  UINT64  PhysicalBaseAddress;
+  UINT64  GICV;
+  UINT64  GICH;
+  UINT32  VGICMaintenanceInterrupt;
+  UINT64  GICRBaseAddress;
+  UINT64  MPIDR;
+} EFI_ACPI_5_1_GIC_STRUCTURE;
+
+///
+/// GIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_1_GIC_ENABLED                              BIT0
+#define EFI_ACPI_5_1_PERFORMANCE_INTERRUPT_MODEL              BIT1
+#define EFI_ACPI_5_1_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS    BIT2
+
+///
+/// GIC Distributor Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved1;
+  UINT32  GicId;
+  UINT64  PhysicalBaseAddress;
+  UINT32  SystemVectorBase;
+  UINT8   GicVersion;
+  UINT8   Reserved2[3];
+} EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE;
+
+///
+/// GIC Version
+///
+#define EFI_ACPI_5_1_GIC_V1                                   0x01
+#define EFI_ACPI_5_1_GIC_V2                                   0x02
+#define EFI_ACPI_5_1_GIC_V3                                   0x03
+#define EFI_ACPI_5_1_GIC_V4                                   0x04
+
+///
+/// GIC MSI Frame Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved1;
+  UINT32  GicMsiFrameId;
+  UINT64  PhysicalBaseAddress;
+  UINT32  Flags;
+  UINT16  SPICount;
+  UINT16  SPIBase;
+} EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE;
+
+///
+/// GIC MSI Frame Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_1_SPI_COUNT_BASE_SELECT                    BIT0
+
+///
+/// GICR Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT64  DiscoveryRangeBaseAddress;
+  UINT32  DiscoveryRangeLength;
+} EFI_ACPI_5_1_GICR_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      WarningEnergyLevel;
+  UINT32                      LowEnergyLevel;
+  UINT32                      CriticalEnergyLevel;
+} EFI_ACPI_5_1_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  EcControl;
+  EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  EcData;
+  UINT32                                  Uid;
+  UINT8                                   GpeBit;
+} EFI_ACPI_5_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION  0x01
+
+///
+/// System Resource Affinity Table (SRAT).  The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Reserved1;  ///< Must be set to 1
+  UINT64                      Reserved2;
+} EFI_ACPI_5_1_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+///
+/// SRAT Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION  0x03
+
+//
+// SRAT structure types.
+// All other values between 0x04 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY  0x00
+#define EFI_ACPI_5_1_MEMORY_AFFINITY                      0x01
+#define EFI_ACPI_5_1_PROCESSOR_LOCAL_X2APIC_AFFINITY      0x02
+#define EFI_ACPI_5_1_GICC_AFFINITY                        0x03
+
+///
+/// Processor Local APIC/SAPIC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   ProximityDomain7To0;
+  UINT8   ApicId;
+  UINT32  Flags;
+  UINT8   LocalSapicEid;
+  UINT8   ProximityDomain31To8[3];
+  UINT32  ClockDomain;
+} EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+///
+/// Local APIC/SAPIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+///
+/// Memory Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT32  ProximityDomain;
+  UINT16  Reserved1;
+  UINT32  AddressBaseLow;
+  UINT32  AddressBaseHigh;
+  UINT32  LengthLow;
+  UINT32  LengthHigh;
+  UINT32  Reserved2;
+  UINT32  Flags;
+  UINT64  Reserved3;
+} EFI_ACPI_5_1_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags.  All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_5_1_MEMORY_ENABLED       (1 << 0)
+#define EFI_ACPI_5_1_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_5_1_MEMORY_NONVOLATILE   (1 << 2)
+
+///
+/// Processor Local x2APIC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Reserved1[2];
+  UINT32  ProximityDomain;
+  UINT32  X2ApicId;
+  UINT32  Flags;
+  UINT32  ClockDomain;
+  UINT8   Reserved2[4];
+} EFI_ACPI_5_1_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT32  ProximityDomain;
+  UINT32  AcpiProcessorUid;
+  UINT32  Flags;
+  UINT32  ClockDomain;
+} EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_1_GICC_ENABLED (1 << 0)
+
+///
+/// System Locality Distance Information Table (SLIT).
+/// The rest of the table is a matrix.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT64                      NumberOfSystemLocalities;
+} EFI_ACPI_5_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+///
+/// SLIT Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION  0x01
+
+///
+/// Corrected Platform Error Polling Table (CPEP)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       Reserved[8];
+} EFI_ACPI_5_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
+
+///
+/// CPEP Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+
+//
+// CPEP processor structure types.
+//
+#define EFI_ACPI_5_1_CPEP_PROCESSOR_APIC_SAPIC  0x00
+
+///
+/// Corrected Platform Error Polling Processor Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT32  PollingInterval;
+} EFI_ACPI_5_1_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
+
+///
+/// Maximum System Characteristics Table (MSCT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      OffsetProxDomInfo;
+  UINT32                      MaximumNumberOfProximityDomains;
+  UINT32                      MaximumNumberOfClockDomains;
+  UINT64                      MaximumPhysicalAddress;
+} EFI_ACPI_5_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
+
+///
+/// MSCT Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+
+///
+/// Maximum Proximity Domain Information Structure Definition
+///
+typedef struct {
+  UINT8   Revision;
+  UINT8   Length;
+  UINT32  ProximityDomainRangeLow;
+  UINT32  ProximityDomainRangeHigh;
+  UINT32  MaximumProcessorCapacity;
+  UINT64  MaximumMemoryCapacity;
+} EFI_ACPI_5_1_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
+
+///
+/// ACPI RAS Feature Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       PlatformCommunicationChannelIdentifier[12];
+} EFI_ACPI_5_1_RAS_FEATURE_TABLE;
+
+///
+/// RASF Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_RAS_FEATURE_TABLE_REVISION 0x01
+
+///
+/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+  UINT32                      Signature;
+  UINT16                      Command;
+  UINT16                      Status;
+  UINT16                      Version;
+  UINT8                       RASCapabilities[16];
+  UINT8                       SetRASCapabilities[16];
+  UINT16                      NumberOfRASFParameterBlocks;
+  UINT32                      SetRASCapabilitiesStatus;
+} EFI_ACPI_5_1_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI RASF PCC command code
+///
+#define EFI_ACPI_5_1_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND  0x01
+
+///
+/// ACPI RASF Platform RAS Capabilities
+///
+#define EFI_ACPI_5_1_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED                          0x01
+#define EFI_ACPI_5_1_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED_AND_EXPOSED_TO_SOFTWARE  0x02
+
+///
+/// ACPI RASF Parameter Block structure for PATROL_SCRUB
+///
+typedef struct {
+  UINT16                      Type;
+  UINT16                      Version;
+  UINT16                      Length;
+  UINT16                      PatrolScrubCommand;
+  UINT64                      RequestedAddressRange[2];
+  UINT64                      ActualAddressRange[2];
+  UINT16                      Flags;
+  UINT8                       RequestedSpeed;
+} EFI_ACPI_5_1_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
+
+///
+/// ACPI RASF Patrol Scrub command
+///
+#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS   0x01
+#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER   0x02
+#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER    0x03
+
+///
+/// Memory Power State Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       PlatformCommunicationChannelIdentifier;
+  UINT8                       Reserved[3];
+// Memory Power Node Structure
+// Memory Power State Characteristics
+} EFI_ACPI_5_1_MEMORY_POWER_STATUS_TABLE;
+
+///
+/// MPST Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+
+///
+/// MPST Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+  UINT32                      Signature;
+  UINT16                      Command;
+  UINT16                      Status;
+  UINT32                      MemoryPowerCommandRegister;
+  UINT32                      MemoryPowerStatusRegister;
+  UINT32                      PowerStateId;
+  UINT32                      MemoryPowerNodeId;
+  UINT64                      MemoryEnergyConsumed;
+  UINT64                      ExpectedAveragePowerComsuned;
+} EFI_ACPI_5_1_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI MPST PCC command code
+///
+#define EFI_ACPI_5_1_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND  0x03
+
+///
+/// ACPI MPST Memory Power command
+///
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE       0x01
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE       0x02
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED   0x03
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED   0x04
+
+///
+/// MPST Memory Power Node Table
+///
+typedef struct {
+  UINT8                                             PowerStateValue;
+  UINT8                                             PowerStateInformationIndex;
+} EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE;
+
+typedef struct {
+  UINT8                                             Flag;
+  UINT8                                             Reserved;
+  UINT16                                            MemoryPowerNodeId;
+  UINT32                                            Length;
+  UINT64                                            AddressBase;
+  UINT64                                            AddressLength;
+  UINT32                                            NumberOfPowerStates;
+  UINT32                                            NumberOfPhysicalComponents;
+//EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE              MemoryPowerState[NumberOfPowerStates];
+//UINT16                                            PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+} EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE;
+
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE          0x01
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED   0x02
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE   0x04
+
+typedef struct {
+  UINT16                      MemoryPowerNodeCount;
+  UINT8                       Reserved[2];
+} EFI_ACPI_5_1_MPST_MEMORY_POWER_NODE_TABLE;
+
+///
+/// MPST Memory Power State Characteristics Table
+///
+typedef struct {
+  UINT8                                             PowerStateStructureID;
+  UINT8                                             Flag;
+  UINT16                                            Reserved;
+  UINT32                                            AveragePowerConsumedInMPS0;
+  UINT32                                            RelativePowerSavingToMPS0;
+  UINT64                                            ExitLatencyToMPS0;
+} EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
+
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED              0x01
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY   0x02
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT    0x04
+
+typedef struct {
+  UINT16                      MemoryPowerStateCharacteristicsCount;
+  UINT8                       Reserved[2];
+} EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
+
+///
+/// Memory Topology Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Reserved;
+} EFI_ACPI_5_1_MEMORY_TOPOLOGY_TABLE;
+
+///
+/// PMTT Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
+
+///
+/// Common Memory Aggregator Device Structure.
+///
+typedef struct {
+  UINT8                       Type;
+  UINT8                       Reserved;
+  UINT16                      Length;
+  UINT16                      Flags;
+  UINT16                      Reserved1;
+} EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Memory Aggregator Device Type
+///
+#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET            0x1
+#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x2
+#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM              0x3
+
+///
+/// Socket Memory Aggregator Device Structure.
+///
+typedef struct {
+  EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  Header;
+  UINT16                                                       SocketIdentifier;
+  UINT16                                                       Reserved;
+//EFI_ACPI_5_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  MemoryController[];
+} EFI_ACPI_5_1_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// MemoryController Memory Aggregator Device Structure.
+///
+typedef struct {
+  EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  Header;
+  UINT32                                                       ReadLatency;
+  UINT32                                                       WriteLatency;
+  UINT32                                                       ReadBandwidth;
+  UINT32                                                       WriteBandwidth;
+  UINT16                                                       OptimalAccessUnit;
+  UINT16                                                       OptimalAccessAlignment;
+  UINT16                                                       Reserved;
+  UINT16                                                       NumberOfProximityDomains;
+//UINT32                                                       ProximityDomain[NumberOfProximityDomains];
+//EFI_ACPI_5_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE    PhysicalComponent[];
+} EFI_ACPI_5_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// DIMM Memory Aggregator Device Structure.
+///
+typedef struct {
+  EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  Header;
+  UINT16                                                       PhysicalComponentIdentifier;
+  UINT16                                                       Reserved;
+  UINT32                                                       SizeOfDimm;
+  UINT32                                                       SmbiosHandle;
+} EFI_ACPI_5_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Boot Graphics Resource Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  ///
+  /// 2-bytes (16 bit) version ID. This value must be 1.
+  ///
+  UINT16                      Version;
+  ///
+  /// 1-byte status field indicating current status about the table.
+  ///     Bits[7:1] = Reserved (must be zero)
+  ///     Bit [0] = Valid. A one indicates the boot image graphic is valid.
+  ///
+  UINT8                       Status;
+  ///
+  /// 1-byte enumerated type field indicating format of the image.
+  ///     0 = Bitmap
+  ///     1 - 255  Reserved (for future use)
+  ///
+  UINT8                       ImageType;
+  ///
+  /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
+  /// of the image bitmap.
+  ///
+  UINT64                      ImageAddress;
+  ///
+  /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
+  /// (X, Y) display offset of the top left corner of the boot image.
+  /// The top left corner of the display is at offset (0, 0).
+  ///
+  UINT32                      ImageOffsetX;
+  ///
+  /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
+  /// (X, Y) display offset of the top left corner of the boot image.
+  /// The top left corner of the display is at offset (0, 0).
+  ///
+  UINT32                      ImageOffsetY;
+} EFI_ACPI_5_1_BOOT_GRAPHICS_RESOURCE_TABLE;
+
+///
+/// BGRT Revision
+///
+#define EFI_ACPI_5_1_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+
+///
+/// BGRT Version
+///
+#define EFI_ACPI_5_1_BGRT_VERSION         0x01
+
+///
+/// BGRT Status
+///
+#define EFI_ACPI_5_1_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_5_1_BGRT_STATUS_DISPLAYED     0x01
+
+///
+/// BGRT Image Type
+///
+#define EFI_ACPI_5_1_BGRT_IMAGE_TYPE_BMP  0x00
+
+///
+/// FPDT Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+
+///
+/// FPDT Performance Record Types
+///
+#define EFI_ACPI_5_1_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER      0x0000
+#define EFI_ACPI_5_1_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER     0x0001
+
+///
+/// FPDT Performance Record Revision
+///
+#define EFI_ACPI_5_1_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER  0x01
+#define EFI_ACPI_5_1_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+
+///
+/// FPDT Runtime Performance Record Types
+///
+#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME                0x0000
+#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND               0x0001
+#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT      0x0002
+
+///
+/// FPDT Runtime Performance Record Revision
+///
+#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME            0x01
+#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND           0x01
+#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT  0x02
+
+///
+/// FPDT Performance Record header
+///
+typedef struct {
+  UINT16           Type;
+  UINT8            Length;
+  UINT8            Revision;
+} EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER;
+
+///
+/// FPDT Performance Table header
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+} EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER;
+
+///
+/// FPDT Firmware Basic Boot Performance Pointer Record Structure
+///
+typedef struct {
+  EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  UINT32                                          Reserved;
+  ///
+  /// 64-bit processor-relative physical address of the Basic Boot Performance Table.
+  ///
+  UINT64                                          BootPerformanceTablePointer;
+} EFI_ACPI_5_1_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT S3 Performance Table Pointer Record Structure
+///
+typedef struct {
+  EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  UINT32                                          Reserved;
+  ///
+  /// 64-bit processor-relative physical address of the S3 Performance Table.
+  ///
+  UINT64                                          S3PerformanceTablePointer;
+} EFI_ACPI_5_1_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Record Structure
+///
+typedef struct {
+  EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  UINT32                                          Reserved;
+  ///
+  /// Timer value logged at the beginning of firmware image execution.
+  /// This may not always be zero or near zero.
+  ///
+  UINT64                                          ResetEnd;
+  ///
+  /// Timer value logged just prior to loading the OS boot loader into memory.
+  /// For non-UEFI compatible boots, this field must be zero.
+  ///
+  UINT64                                          OsLoaderLoadImageStart;
+  ///
+  /// Timer value logged just prior to launching the previously loaded OS boot loader image.
+  /// For non-UEFI compatible boots, the timer value logged will be just prior
+  /// to the INT 19h handler invocation.
+  ///
+  UINT64                                          OsLoaderStartImageStart;
+  ///
+  /// Timer value logged at the point when the OS loader calls the
+  /// ExitBootServices function for UEFI compatible firmware.
+  /// For non-UEFI compatible boots, this field must be zero.
+  ///
+  UINT64                                          ExitBootServicesEntry;
+  ///
+  /// Timer value logged at the point just prior towhen the OS loader gaining
+  /// control back from calls the ExitBootServices function for UEFI compatible firmware.
+  /// For non-UEFI compatible boots, this field must be zero.
+  ///
+  UINT64                                          ExitBootServicesExit;
+} EFI_ACPI_5_1_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Table signature
+///
+#define EFI_ACPI_5_1_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE  SIGNATURE_32('F', 'B', 'P', 'T')
+
+//
+// FPDT Firmware Basic Boot Performance Table
+//
+typedef struct {
+  EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER      Header;
+  //
+  // one or more Performance Records.
+  //
+} EFI_ACPI_5_1_FPDT_FIRMWARE_BASIC_BOOT_TABLE;
+
+///
+/// FPDT "S3PT" S3 Performance Table
+///
+#define EFI_ACPI_5_1_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE  SIGNATURE_32('S', '3', 'P', 'T')
+
+//
+// FPDT Firmware S3 Boot Performance Table
+//
+typedef struct {
+  EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER      Header;
+  //
+  // one or more Performance Records.
+  //
+} EFI_ACPI_5_1_FPDT_FIRMWARE_S3_BOOT_TABLE;
+
+///
+/// FPDT Basic S3 Resume Performance Record
+///
+typedef struct {
+  EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  ///
+  /// A count of the number of S3 resume cycles since the last full boot sequence.
+  ///
+  UINT32                                          ResumeCount;
+  ///
+  /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
+  /// OS waking vector. Only the most recent resume cycle's time is retained.
+  ///
+  UINT64                                          FullResume;
+  ///
+  /// Average timer value of all resume cycles logged since the last full boot
+  /// sequence, including the most recent resume.  Note that the entire log of
+  /// timer values does not need to be retained in order to calculate this average.
+  ///
+  UINT64                                          AverageResume;
+} EFI_ACPI_5_1_FPDT_S3_RESUME_RECORD;
+
+///
+/// FPDT Basic S3 Suspend Performance Record
+///
+typedef struct {
+  EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  ///
+  /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
+  /// Only the most recent suspend cycle's timer value is retained.
+  ///
+  UINT64                                          SuspendStart;
+  ///
+  /// Timer value recorded at the final firmware write to SLP_TYP (or other
+  /// mechanism) used to trigger hardware entry to S3.
+  /// Only the most recent suspend cycle's timer value is retained.
+  ///
+  UINT64                                          SuspendEnd;
+} EFI_ACPI_5_1_FPDT_S3_SUSPEND_RECORD;
+
+///
+/// Firmware Performance Record Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_5_1_FIRMWARE_PERFORMANCE_RECORD_TABLE;
+
+///
+/// Generic Timer Description Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT64                      CntControlBasePhysicalAddress;
+  UINT32                      Reserved;
+  UINT32                      SecurePL1TimerGSIV;
+  UINT32                      SecurePL1TimerFlags;
+  UINT32                      NonSecurePL1TimerGSIV;
+  UINT32                      NonSecurePL1TimerFlags;
+  UINT32                      VirtualTimerGSIV;
+  UINT32                      VirtualTimerFlags;
+  UINT32                      NonSecurePL2TimerGSIV;
+  UINT32                      NonSecurePL2TimerFlags;
+  UINT64                      CntReadBasePhysicalAddress;
+  UINT32                      PlatformTimerCount;
+  UINT32                      PlatformTimerOffset;
+} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE;
+
+///
+/// GTDT Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Timer Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE          BIT0
+#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY      BIT1
+#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY          BIT2
+
+///
+/// Platform Timer Type
+///
+#define EFI_ACPI_5_1_GTDT_GT_BLOCK                       0
+#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG          1
+
+///
+/// GT Block Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT16  Length;
+  UINT8   Reserved;
+  UINT64  CntCtlBase;
+  UINT32  GTBlockTimerCount;
+  UINT32  GTBlockTimerOffset;
+} EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE;
+
+///
+/// GT Block Timer Structure
+///
+typedef struct {
+  UINT8   GTFrameNumber;
+  UINT8   Reserved[3];
+  UINT64  CntBaseX;
+  UINT64  CntEL0BaseX;
+  UINT32  GTxPhysicalTimerGSIV;
+  UINT32  GTxPhysicalTimerFlags;
+  UINT32  GTxVirtualTimerGSIV;
+  UINT32  GTxVirtualTimerFlags;
+  UINT32  GTxCommonFlags;
+} EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_STRUCTURE;
+
+///
+/// GT Block Physical Timers and Virtual Timers Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE          BIT0
+#define EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY      BIT1
+
+///
+/// Common Flags Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER              BIT0
+#define EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY      BIT1
+
+///
+/// SBSA Generic Watchdog Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT16  Length;
+  UINT8   Reserved;
+  UINT64  RefreshFramePhysicalAddress;
+  UINT64  WatchdogControlFramePhysicalAddress;
+  UINT32  WatchdogTimerGSIV;
+  UINT32  WatchdogTimerFlags;
+} EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;
+
+///
+/// SBSA Generic Watchdog Timer Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE          BIT0
+#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY      BIT1
+#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER                  BIT2
+
+///
+/// Boot Error Record Table (BERT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      BootErrorRegionLength;
+  UINT64                      BootErrorRegion;
+} EFI_ACPI_5_1_BOOT_ERROR_RECORD_TABLE_HEADER;
+
+///
+/// BERT Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+
+///
+/// Boot Error Region Block Status Definition
+///
+typedef struct {
+  UINT32       UncorrectableErrorValid:1;
+  UINT32       CorrectableErrorValid:1;
+  UINT32       MultipleUncorrectableErrors:1;
+  UINT32       MultipleCorrectableErrors:1;
+  UINT32       ErrorDataEntryCount:10;
+  UINT32       Reserved:18;
+} EFI_ACPI_5_1_ERROR_BLOCK_STATUS;
+
+///
+/// Boot Error Region Definition
+///
+typedef struct {
+  EFI_ACPI_5_1_ERROR_BLOCK_STATUS              BlockStatus;
+  UINT32                                       RawDataOffset;
+  UINT32                                       RawDataLength;
+  UINT32                                       DataLength;
+  UINT32                                       ErrorSeverity;
+} EFI_ACPI_5_1_BOOT_ERROR_REGION_STRUCTURE;
+
+//
+// Boot Error Severity types
+//
+#define EFI_ACPI_5_1_ERROR_SEVERITY_CORRECTABLE  0x00
+#define EFI_ACPI_5_1_ERROR_SEVERITY_FATAL        0x01
+#define EFI_ACPI_5_1_ERROR_SEVERITY_CORRECTED    0x02
+#define EFI_ACPI_5_1_ERROR_SEVERITY_NONE         0x03
+
+///
+/// Generic Error Data Entry Definition
+///
+typedef struct {
+  UINT8    SectionType[16];
+  UINT32   ErrorSeverity;
+  UINT16   Revision;
+  UINT8    ValidationBits;
+  UINT8    Flags;
+  UINT32   ErrorDataLength;
+  UINT8    FruId[16];
+  UINT8    FruText[20];
+} EFI_ACPI_5_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
+
+///
+/// Generic Error Data Entry Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_GENERIC_ERROR_DATA_ENTRY_REVISION  0x0201
+
+///
+/// HEST - Hardware Error Source Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      ErrorSourceCount;
+} EFI_ACPI_5_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
+
+///
+/// HEST Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+
+//
+// Error Source structure types.
+//
+#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION  0x00
+#define EFI_ACPI_5_1_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK  0x01
+#define EFI_ACPI_5_1_IA32_ARCHITECTURE_NMI_ERROR                0x02
+#define EFI_ACPI_5_1_PCI_EXPRESS_ROOT_PORT_AER                  0x06
+#define EFI_ACPI_5_1_PCI_EXPRESS_DEVICE_AER                     0x07
+#define EFI_ACPI_5_1_PCI_EXPRESS_BRIDGE_AER                     0x08
+#define EFI_ACPI_5_1_GENERIC_HARDWARE_ERROR                     0x09
+
+//
+// Error Source structure flags.
+//
+#define EFI_ACPI_5_1_ERROR_SOURCE_FLAG_FIRMWARE_FIRST       (1 << 0)
+#define EFI_ACPI_5_1_ERROR_SOURCE_FLAG_GLOBAL               (1 << 1)
+
+///
+/// IA-32 Architecture Machine Check Exception Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT64  GlobalCapabilityInitData;
+  UINT64  GlobalControlInitData;
+  UINT8   NumberOfHardwareBanks;
+  UINT8   Reserved1[7];
+} EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure Definition
+///
+typedef struct {
+  UINT8   BankNumber;
+  UINT8   ClearStatusOnInitialization;
+  UINT8   StatusDataFormat;
+  UINT8   Reserved0;
+  UINT32  ControlRegisterMsrAddress;
+  UINT64  ControlInitData;
+  UINT32  StatusRegisterMsrAddress;
+  UINT32  AddressRegisterMsrAddress;
+  UINT32  MiscRegisterMsrAddress;
+} EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure MCA data format
+///
+#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32      0x00
+#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64   0x01
+#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64     0x02
+
+//
+// Hardware Error Notification types. All other values are reserved
+//
+#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_POLLED                0x00
+#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT    0x01
+#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT       0x02
+#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_SCI                   0x03
+#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_NMI                   0x04
+
+///
+/// Hardware Error Notification Configuration Write Enable Structure Definition
+///
+typedef struct {
+  UINT16    Type:1;
+  UINT16    PollInterval:1;
+  UINT16    SwitchToPollingThresholdValue:1;
+  UINT16    SwitchToPollingThresholdWindow:1;
+  UINT16    ErrorThresholdValue:1;
+  UINT16    ErrorThresholdWindow:1;
+  UINT16    Reserved:10;
+} EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
+
+///
+/// Hardware Error Notification Structure Definition
+///
+typedef struct {
+  UINT8                                                                          Type;
+  UINT8                                                                          Length;
+  EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE  ConfigurationWriteEnable;
+  UINT32                                                                         PollInterval;
+  UINT32                                                                         Vector;
+  UINT32                                                                         SwitchToPollingThresholdValue;
+  UINT32                                                                         SwitchToPollingThresholdWindow;
+  UINT32                                                                         ErrorThresholdValue;
+  UINT32                                                                         ErrorThresholdWindow;
+} EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
+
+///
+/// IA-32 Architecture Corrected Machine Check Structure Definition
+///
+typedef struct {
+  UINT16                                                 Type;
+  UINT16                                                 SourceId;
+  UINT8                                                  Reserved0[2];
+  UINT8                                                  Flags;
+  UINT8                                                  Enabled;
+  UINT32                                                 NumberOfRecordsToPreAllocate;
+  UINT32                                                 MaxSectionsPerRecord;
+  EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE     NotificationStructure;
+  UINT8                                                  NumberOfHardwareBanks;
+  UINT8                                                  Reserved1[3];
+} EFI_ACPI_5_1_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// IA-32 Architecture NMI Error Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  MaxRawDataLength;
+} EFI_ACPI_5_1_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
+
+///
+/// PCI Express Root Port AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+  UINT32  RootErrorCommand;
+} EFI_ACPI_5_1_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
+
+///
+/// PCI Express Device AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_5_1_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
+
+///
+/// PCI Express Bridge AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+  UINT32  SecondaryUncorrectableErrorMask;
+  UINT32  SecondaryUncorrectableErrorSeverity;
+  UINT32  SecondaryAdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_5_1_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Structure Definition
+///
+typedef struct {
+  UINT16                                                 Type;
+  UINT16                                                 SourceId;
+  UINT16                                                 RelatedSourceId;
+  UINT8                                                  Flags;
+  UINT8                                                  Enabled;
+  UINT32                                                 NumberOfRecordsToPreAllocate;
+  UINT32                                                 MaxSectionsPerRecord;
+  UINT32                                                 MaxRawDataLength;
+  EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE                 ErrorStatusAddress;
+  EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE     NotificationStructure;
+  UINT32                                                 ErrorStatusBlockLength;
+} EFI_ACPI_5_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
+
+///
+/// Generic Error Status Definition
+///
+typedef struct {
+  EFI_ACPI_5_1_ERROR_BLOCK_STATUS              BlockStatus;
+  UINT32                                       RawDataOffset;
+  UINT32                                       RawDataLength;
+  UINT32                                       DataLength;
+  UINT32                                       ErrorSeverity;
+} EFI_ACPI_5_1_GENERIC_ERROR_STATUS_STRUCTURE;
+
+///
+/// ERST - Error Record Serialization Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      SerializationHeaderSize;
+  UINT8                       Reserved0[4];
+  UINT32                      InstructionEntryCount;
+} EFI_ACPI_5_1_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
+
+///
+/// ERST Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+
+///
+/// ERST Serialization Actions
+///
+#define EFI_ACPI_5_1_ERST_BEGIN_WRITE_OPERATION                    0x00
+#define EFI_ACPI_5_1_ERST_BEGIN_READ_OPERATION                     0x01
+#define EFI_ACPI_5_1_ERST_BEGIN_CLEAR_OPERATION                    0x02
+#define EFI_ACPI_5_1_ERST_END_OPERATION                            0x03
+#define EFI_ACPI_5_1_ERST_SET_RECORD_OFFSET                        0x04
+#define EFI_ACPI_5_1_ERST_EXECUTE_OPERATION                        0x05
+#define EFI_ACPI_5_1_ERST_CHECK_BUSY_STATUS                        0x06
+#define EFI_ACPI_5_1_ERST_GET_COMMAND_STATUS                       0x07
+#define EFI_ACPI_5_1_ERST_GET_RECORD_IDENTIFIER                    0x08
+#define EFI_ACPI_5_1_ERST_SET_RECORD_IDENTIFIER                    0x09
+#define EFI_ACPI_5_1_ERST_GET_RECORD_COUNT                         0x0A
+#define EFI_ACPI_5_1_ERST_BEGIN_DUMMY_WRITE_OPERATION              0x0B
+#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE              0x0D
+#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH       0x0E
+#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES   0x0F
+
+///
+/// ERST Action Command Status
+///
+#define EFI_ACPI_5_1_ERST_STATUS_SUCCESS                           0x00
+#define EFI_ACPI_5_1_ERST_STATUS_NOT_ENOUGH_SPACE                  0x01
+#define EFI_ACPI_5_1_ERST_STATUS_HARDWARE_NOT_AVAILABLE            0x02
+#define EFI_ACPI_5_1_ERST_STATUS_FAILED                            0x03
+#define EFI_ACPI_5_1_ERST_STATUS_RECORD_STORE_EMPTY                0x04
+#define EFI_ACPI_5_1_ERST_STATUS_RECORD_NOT_FOUND                  0x05
+
+///
+/// ERST Serialization Instructions
+///
+#define EFI_ACPI_5_1_ERST_READ_REGISTER                            0x00
+#define EFI_ACPI_5_1_ERST_READ_REGISTER_VALUE                      0x01
+#define EFI_ACPI_5_1_ERST_WRITE_REGISTER                           0x02
+#define EFI_ACPI_5_1_ERST_WRITE_REGISTER_VALUE                     0x03
+#define EFI_ACPI_5_1_ERST_NOOP                                     0x04
+#define EFI_ACPI_5_1_ERST_LOAD_VAR1                                0x05
+#define EFI_ACPI_5_1_ERST_LOAD_VAR2                                0x06
+#define EFI_ACPI_5_1_ERST_STORE_VAR1                               0x07
+#define EFI_ACPI_5_1_ERST_ADD                                      0x08
+#define EFI_ACPI_5_1_ERST_SUBTRACT                                 0x09
+#define EFI_ACPI_5_1_ERST_ADD_VALUE                                0x0A
+#define EFI_ACPI_5_1_ERST_SUBTRACT_VALUE                           0x0B
+#define EFI_ACPI_5_1_ERST_STALL                                    0x0C
+#define EFI_ACPI_5_1_ERST_STALL_WHILE_TRUE                         0x0D
+#define EFI_ACPI_5_1_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE            0x0E
+#define EFI_ACPI_5_1_ERST_GOTO                                     0x0F
+#define EFI_ACPI_5_1_ERST_SET_SRC_ADDRESS_BASE                     0x10
+#define EFI_ACPI_5_1_ERST_SET_DST_ADDRESS_BASE                     0x11
+#define EFI_ACPI_5_1_ERST_MOVE_DATA                                0x12
+
+///
+/// ERST Instruction Flags
+///
+#define EFI_ACPI_5_1_ERST_PRESERVE_REGISTER                        0x01
+
+///
+/// ERST Serialization Instruction Entry
+///
+typedef struct {
+  UINT8                                    SerializationAction;
+  UINT8                                    Instruction;
+  UINT8                                    Flags;
+  UINT8                                    Reserved0;
+  EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE   RegisterRegion;
+  UINT64                                   Value;
+  UINT64                                   Mask;
+} EFI_ACPI_5_1_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ - Error Injection Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      InjectionHeaderSize;
+  UINT8                       InjectionFlags;
+  UINT8                       Reserved0[3];
+  UINT32                      InjectionEntryCount;
+} EFI_ACPI_5_1_ERROR_INJECTION_TABLE_HEADER;
+
+///
+/// EINJ Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_ERROR_INJECTION_TABLE_REVISION 0x01
+
+///
+/// EINJ Error Injection Actions
+///
+#define EFI_ACPI_5_1_EINJ_BEGIN_INJECTION_OPERATION                0x00
+#define EFI_ACPI_5_1_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE           0x01
+#define EFI_ACPI_5_1_EINJ_SET_ERROR_TYPE                           0x02
+#define EFI_ACPI_5_1_EINJ_GET_ERROR_TYPE                           0x03
+#define EFI_ACPI_5_1_EINJ_END_OPERATION                            0x04
+#define EFI_ACPI_5_1_EINJ_EXECUTE_OPERATION                        0x05
+#define EFI_ACPI_5_1_EINJ_CHECK_BUSY_STATUS                        0x06
+#define EFI_ACPI_5_1_EINJ_GET_COMMAND_STATUS                       0x07
+#define EFI_ACPI_5_1_EINJ_TRIGGER_ERROR                            0xFF
+
+///
+/// EINJ Action Command Status
+///
+#define EFI_ACPI_5_1_EINJ_STATUS_SUCCESS                           0x00
+#define EFI_ACPI_5_1_EINJ_STATUS_UNKNOWN_FAILURE                   0x01
+#define EFI_ACPI_5_1_EINJ_STATUS_INVALID_ACCESS                    0x02
+
+///
+/// EINJ Error Type Definition
+///
+#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_CORRECTABLE                 (1 << 0)
+#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL      (1 << 1)
+#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL         (1 << 2)
+#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_CORRECTABLE                    (1 << 3)
+#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL         (1 << 4)
+#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL            (1 << 5)
+#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE               (1 << 6)
+#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL    (1 << 7)
+#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL       (1 << 8)
+#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_CORRECTABLE                  (1 << 9)
+#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL       (1 << 10)
+#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL          (1 << 11)
+
+///
+/// EINJ Injection Instructions
+///
+#define EFI_ACPI_5_1_EINJ_READ_REGISTER                            0x00
+#define EFI_ACPI_5_1_EINJ_READ_REGISTER_VALUE                      0x01
+#define EFI_ACPI_5_1_EINJ_WRITE_REGISTER                           0x02
+#define EFI_ACPI_5_1_EINJ_WRITE_REGISTER_VALUE                     0x03
+#define EFI_ACPI_5_1_EINJ_NOOP                                     0x04
+
+///
+/// EINJ Instruction Flags
+///
+#define EFI_ACPI_5_1_EINJ_PRESERVE_REGISTER                        0x01
+
+///
+/// EINJ Injection Instruction Entry
+///
+typedef struct {
+  UINT8                                    InjectionAction;
+  UINT8                                    Instruction;
+  UINT8                                    Flags;
+  UINT8                                    Reserved0;
+  EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE   RegisterRegion;
+  UINT64                                   Value;
+  UINT64                                   Mask;
+} EFI_ACPI_5_1_EINJ_INJECTION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ Trigger Action Table
+///
+typedef struct {
+  UINT32  HeaderSize;
+  UINT32  Revision;
+  UINT32  TableSize;
+  UINT32  EntryCount;
+} EFI_ACPI_5_1_EINJ_TRIGGER_ACTION_TABLE;
+
+///
+/// Platform Communications Channel Table (PCCT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Flags;
+  UINT64                      Reserved;
+} EFI_ACPI_5_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
+
+///
+/// PCCT Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01
+
+///
+/// PCCT Global Flags
+///
+#define EFI_ACPI_5_1_PCCT_FLAGS_SCI_DOORBELL                      BIT0
+
+//
+// PCCT Subspace type
+//
+#define EFI_ACPI_5_1_PCCT_SUBSPACE_TYPE_GENERIC  0x00
+
+///
+/// PCC Subspace Structure Header
+///
+typedef struct {
+  UINT8        Type;
+  UINT8        Length;
+} EFI_ACPI_5_1_PCCT_SUBSPACE_HEADER;
+
+///
+/// Generic Communications Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT8                                    Reserved[6];
+  UINT64                                   BaseAddress;
+  UINT64                                   AddressLength;
+  EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT16                                   MinimumRequestTurnaroundTime;
+} EFI_ACPI_5_1_PCCT_SUBSPACE_GENERIC;
+
+///
+/// Generic Communications Channel Shared Memory Region
+///
+
+typedef struct {
+  UINT8                                    Command;
+  UINT8                                    Reserved:7;
+  UINT8                                    GenerateSci:1;
+} EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
+
+typedef struct {
+  UINT8                                    CommandComplete:1;
+  UINT8                                    SciDoorbell:1;
+  UINT8                                    Error:1;
+  UINT8                                    PlatformNotification:1;  
+  UINT8                                    Reserved:4;
+  UINT8                                    Reserved1;
+} EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
+
+typedef struct {
+  UINT32                                                    Signature;
+  EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND    Command;
+  EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS     Status;
+} EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') 
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "BERT" Boot Error Record Table
+///
+#define EFI_ACPI_5_1_BOOT_ERROR_RECORD_TABLE_SIGNATURE  SIGNATURE_32('B', 'E', 'R', 'T')
+
+///
+/// "BGRT" Boot Graphics Resource Table
+///
+#define EFI_ACPI_5_1_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('B', 'G', 'R', 'T')
+
+///
+/// "CPEP" Corrected Platform Error Polling Table
+///
+#define EFI_ACPI_5_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE  SIGNATURE_32('C', 'P', 'E', 'P')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_5_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_5_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE  SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "EINJ" Error Injection Table
+///
+#define EFI_ACPI_5_1_ERROR_INJECTION_TABLE_SIGNATURE  SIGNATURE_32('E', 'I', 'N', 'J')
+
+///
+/// "ERST" Error Record Serialization Table
+///
+#define EFI_ACPI_5_1_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE  SIGNATURE_32('E', 'R', 'S', 'T')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_5_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "FPDT" Firmware Performance Data Table
+///
+#define EFI_ACPI_5_1_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE  SIGNATURE_32('F', 'P', 'D', 'T')
+
+///
+/// "GTDT" Generic Timer Description Table
+///
+#define EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('G', 'T', 'D', 'T')
+
+///
+/// "HEST" Hardware Error Source Table
+///
+#define EFI_ACPI_5_1_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE  SIGNATURE_32('H', 'E', 'S', 'T')
+
+///
+/// "MPST" Memory Power State Table
+///
+#define EFI_ACPI_5_1_MEMORY_POWER_STATE_TABLE_SIGNATURE  SIGNATURE_32('M', 'P', 'S', 'T')
+
+///
+/// "MSCT" Maximum System Characteristics Table
+///
+#define EFI_ACPI_5_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE  SIGNATURE_32('M', 'S', 'C', 'T')
+
+///
+/// "PMTT" Platform Memory Topology Table
+///
+#define EFI_ACPI_5_1_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE  SIGNATURE_32('P', 'M', 'T', 'T')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_5_1_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RASF" ACPI RAS Feature Table
+///
+#define EFI_ACPI_5_1_ACPI_RAS_FEATURE_TABLE_SIGNATURE  SIGNATURE_32('R', 'A', 'S', 'F')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_5_1_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_5_1_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SRAT" System Resource Affinity Table
+///
+#define EFI_ACPI_5_1_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE  SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_5_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_5_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_5_1_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE  SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "CSRT" MS Core System Resource Table
+///
+#define EFI_ACPI_5_1_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('C', 'S', 'R', 'T')
+
+///
+/// "DBG2" MS Debug Port 2 Spec
+///
+#define EFI_ACPI_5_1_DEBUG_PORT_2_TABLE_SIGNATURE  SIGNATURE_32('D', 'B', 'G', '2')
+
+///
+/// "DBGP" MS Debug Port Spec
+///
+#define EFI_ACPI_5_1_DEBUG_PORT_TABLE_SIGNATURE  SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "DMAR" DMA Remapping Table
+///
+#define EFI_ACPI_5_1_DMA_REMAPPING_TABLE_SIGNATURE  SIGNATURE_32('D', 'M', 'A', 'R')
+
+///
+/// "DRTM" Dynamic Root of Trust for Measurement Table
+///
+#define EFI_ACPI_5_1_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE  SIGNATURE_32('D', 'R', 'T', 'M')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_5_1_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "HPET" IA-PC High Precision Event Timer Table
+///
+#define EFI_ACPI_5_1_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE  SIGNATURE_32('H', 'P', 'E', 'T')
+
+///
+/// "iBFT" iSCSI Boot Firmware Table
+///
+#define EFI_ACPI_5_1_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE  SIGNATURE_32('i', 'B', 'F', 'T')
+
+///
+/// "IVRS" I/O Virtualization Reporting Structure
+///
+#define EFI_ACPI_5_1_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE  SIGNATURE_32('I', 'V', 'R', 'S')
+
+///
+/// "LPIT" Low Power Idle Table
+///
+#define EFI_ACPI_5_1_IO_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE  SIGNATURE_32('L', 'P', 'I', 'T')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_5_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('M', 'C', 'F', 'G')
+
+///
+/// "MCHI" Management Controller Host Interface Table
+///
+#define EFI_ACPI_5_1_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('M', 'C', 'H', 'I')
+
+///
+/// "MSDM" MS Data Management Table
+///
+#define EFI_ACPI_5_1_DATA_MANAGEMENT_TABLE_SIGNATURE  SIGNATURE_32('M', 'S', 'D', 'M')
+
+///
+/// "SLIC" MS Software Licensing Table Specification
+///
+#define EFI_ACPI_5_1_SOFTWARE_LICENSING_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'C')
+
+///
+/// "SPCR" Serial Port Concole Redirection Table
+///
+#define EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_5_1_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+///
+#define EFI_ACPI_5_1_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE  SIGNATURE_32('T', 'C', 'P', 'A')
+
+///
+/// "TPM2" Trusted Computing Platform 1 Table
+///
+#define EFI_ACPI_5_1_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE  SIGNATURE_32('T', 'P', 'M', '2')
+
+///
+/// "UEFI" UEFI ACPI Data Table
+///
+#define EFI_ACPI_5_1_UEFI_ACPI_DATA_TABLE_SIGNATURE  SIGNATURE_32('U', 'E', 'F', 'I')
+
+///
+/// "WAET" Windows ACPI Emulated Devices Table
+///
+#define EFI_ACPI_5_1_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE  SIGNATURE_32('W', 'A', 'E', 'T')
+
+///
+/// "WDAT" Watchdog Action Table
+///
+#define EFI_ACPI_5_1_WATCHDOG_ACTION_TABLE_SIGNATURE  SIGNATURE_32('W', 'D', 'A', 'T')
+
+///
+/// "WDRT" Watchdog Resource Table
+///
+#define EFI_ACPI_5_1_WATCHDOG_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('W', 'D', 'R', 'T')
+
+///
+/// "WPBT" MS Platform Binary Table
+///
+#define EFI_ACPI_5_1_PLATFORM_BINARY_TABLE_SIGNATURE  SIGNATURE_32('W', 'P', 'B', 'T')
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi60.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi60.h
new file mode 100644
index 0000000000..6bc9b0e1f6
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi60.h
@@ -0,0 +1,2392 @@
+/** @file   
+  ACPI 6.0 definitions from the ACPI Specification Revision 6.0 Errata A January, 2016.
+
+  Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+  (C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+**/
+
+#ifndef _ACPI_6_0_H_
+#define _ACPI_6_0_H_
+
+#include <IndustryStandard/Acpi51.h>
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 6.0 Generic Address Space definition
+///
+typedef struct {
+  UINT8   AddressSpaceId;
+  UINT8   RegisterBitWidth;
+  UINT8   RegisterBitOffset;
+  UINT8   AccessSize;
+  UINT64  Address;
+} EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_6_0_SYSTEM_MEMORY              0
+#define EFI_ACPI_6_0_SYSTEM_IO                  1
+#define EFI_ACPI_6_0_PCI_CONFIGURATION_SPACE    2
+#define EFI_ACPI_6_0_EMBEDDED_CONTROLLER        3
+#define EFI_ACPI_6_0_SMBUS                      4
+#define EFI_ACPI_6_0_PLATFORM_COMMUNICATION_CHANNEL  0x0A
+#define EFI_ACPI_6_0_FUNCTIONAL_FIXED_HARDWARE       0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_6_0_UNDEFINED  0
+#define EFI_ACPI_6_0_BYTE       1
+#define EFI_ACPI_6_0_WORD       2
+#define EFI_ACPI_6_0_DWORD      3
+#define EFI_ACPI_6_0_QWORD      4
+
+//
+// ACPI 6.0 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+  UINT64  Signature;
+  UINT8   Checksum;
+  UINT8   OemId[6];
+  UINT8   Revision;
+  UINT32  RsdtAddress;
+  UINT32  Length;
+  UINT64  XsdtAddress;
+  UINT8   ExtendedChecksum;
+  UINT8   Reserved[3];
+} EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02  ///< ACPISpec (Revision 6.0) says current value is 2
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+} EFI_ACPI_6_0_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with 
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with 
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  UINT32                                  FirmwareCtrl;
+  UINT32                                  Dsdt;
+  UINT8                                   Reserved0;
+  UINT8                                   PreferredPmProfile;
+  UINT16                                  SciInt;
+  UINT32                                  SmiCmd;
+  UINT8                                   AcpiEnable;
+  UINT8                                   AcpiDisable;
+  UINT8                                   S4BiosReq;
+  UINT8                                   PstateCnt;
+  UINT32                                  Pm1aEvtBlk;
+  UINT32                                  Pm1bEvtBlk;
+  UINT32                                  Pm1aCntBlk;
+  UINT32                                  Pm1bCntBlk;
+  UINT32                                  Pm2CntBlk;
+  UINT32                                  PmTmrBlk;
+  UINT32                                  Gpe0Blk;
+  UINT32                                  Gpe1Blk;
+  UINT8                                   Pm1EvtLen;
+  UINT8                                   Pm1CntLen;
+  UINT8                                   Pm2CntLen;
+  UINT8                                   PmTmrLen;
+  UINT8                                   Gpe0BlkLen;
+  UINT8                                   Gpe1BlkLen;
+  UINT8                                   Gpe1Base;
+  UINT8                                   CstCnt;
+  UINT16                                  PLvl2Lat;
+  UINT16                                  PLvl3Lat;
+  UINT16                                  FlushSize;
+  UINT16                                  FlushStride;
+  UINT8                                   DutyOffset;
+  UINT8                                   DutyWidth;
+  UINT8                                   DayAlrm;
+  UINT8                                   MonAlrm;
+  UINT8                                   Century;
+  UINT16                                  IaPcBootArch;
+  UINT8                                   Reserved1;
+  UINT32                                  Flags;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  ResetReg;
+  UINT8                                   ResetValue;
+  UINT16                                  ArmBootArch;
+  UINT8                                   MinorVersion;
+  UINT64                                  XFirmwareCtrl;
+  UINT64                                  XDsdt;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  SleepControlReg;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  SleepStatusReg;
+  UINT64                                  HypervisorVendorIdentity;
+} EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION  0x06
+#define EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION  0x00
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_6_0_PM_PROFILE_UNSPECIFIED         0
+#define EFI_ACPI_6_0_PM_PROFILE_DESKTOP             1
+#define EFI_ACPI_6_0_PM_PROFILE_MOBILE              2
+#define EFI_ACPI_6_0_PM_PROFILE_WORKSTATION         3
+#define EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER   4
+#define EFI_ACPI_6_0_PM_PROFILE_SOHO_SERVER         5
+#define EFI_ACPI_6_0_PM_PROFILE_APPLIANCE_PC        6
+#define EFI_ACPI_6_0_PM_PROFILE_PERFORMANCE_SERVER  7
+#define EFI_ACPI_6_0_PM_PROFILE_TABLET              8
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_0_LEGACY_DEVICES              BIT0
+#define EFI_ACPI_6_0_8042                        BIT1
+#define EFI_ACPI_6_0_VGA_NOT_PRESENT             BIT2
+#define EFI_ACPI_6_0_MSI_NOT_SUPPORTED           BIT3
+#define EFI_ACPI_6_0_PCIE_ASPM_CONTROLS          BIT4
+#define EFI_ACPI_6_0_CMOS_RTC_NOT_PRESENT        BIT5
+
+//
+// Fixed ACPI Description Table Arm Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_0_ARM_PSCI_COMPLIANT              BIT0
+#define EFI_ACPI_6_0_ARM_PSCI_USE_HVC                BIT1
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_0_WBINVD                                 BIT0
+#define EFI_ACPI_6_0_WBINVD_FLUSH                           BIT1
+#define EFI_ACPI_6_0_PROC_C1                                BIT2
+#define EFI_ACPI_6_0_P_LVL2_UP                              BIT3
+#define EFI_ACPI_6_0_PWR_BUTTON                             BIT4
+#define EFI_ACPI_6_0_SLP_BUTTON                             BIT5
+#define EFI_ACPI_6_0_FIX_RTC                                BIT6
+#define EFI_ACPI_6_0_RTC_S4                                 BIT7
+#define EFI_ACPI_6_0_TMR_VAL_EXT                            BIT8
+#define EFI_ACPI_6_0_DCK_CAP                                BIT9
+#define EFI_ACPI_6_0_RESET_REG_SUP                          BIT10
+#define EFI_ACPI_6_0_SEALED_CASE                            BIT11
+#define EFI_ACPI_6_0_HEADLESS                               BIT12
+#define EFI_ACPI_6_0_CPU_SW_SLP                             BIT13
+#define EFI_ACPI_6_0_PCI_EXP_WAK                            BIT14
+#define EFI_ACPI_6_0_USE_PLATFORM_CLOCK                     BIT15
+#define EFI_ACPI_6_0_S4_RTC_STS_VALID                       BIT16
+#define EFI_ACPI_6_0_REMOTE_POWER_ON_CAPABLE                BIT17
+#define EFI_ACPI_6_0_FORCE_APIC_CLUSTER_MODEL               BIT18
+#define EFI_ACPI_6_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE   BIT19
+#define EFI_ACPI_6_0_HW_REDUCED_ACPI                        BIT20
+#define EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE              BIT21
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+  UINT32  HardwareSignature;
+  UINT32  FirmwareWakingVector;
+  UINT32  GlobalLock;
+  UINT32  Flags;
+  UINT64  XFirmwareWakingVector;
+  UINT8   Version;
+  UINT8   Reserved0[3];
+  UINT32  OspmFlags;
+  UINT8   Reserved1[24];
+} EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION  0x02
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_0_S4BIOS_F                     BIT0
+#define EFI_ACPI_6_0_64BIT_WAKE_SUPPORTED_F       BIT1
+
+///
+/// OSPM Enabled Firmware Control Structure Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_0_OSPM_64BIT_WAKE_F            BIT0
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
+//
+#define EFI_ACPI_6_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION   0x02
+#define EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION        0x02
+
+///
+/// Multiple APIC Description Table header definition.  The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      LocalApicAddress;
+  UINT32                      Flags;
+} EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 6.0 Errata A spec.)
+///
+#define EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_0_PCAT_COMPAT         BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x0D and 0x7F are reserved and
+// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.
+//
+#define EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC           0x00
+#define EFI_ACPI_6_0_IO_APIC                        0x01
+#define EFI_ACPI_6_0_INTERRUPT_SOURCE_OVERRIDE      0x02
+#define EFI_ACPI_6_0_NON_MASKABLE_INTERRUPT_SOURCE  0x03
+#define EFI_ACPI_6_0_LOCAL_APIC_NMI                 0x04
+#define EFI_ACPI_6_0_LOCAL_APIC_ADDRESS_OVERRIDE    0x05
+#define EFI_ACPI_6_0_IO_SAPIC                       0x06
+#define EFI_ACPI_6_0_LOCAL_SAPIC                    0x07
+#define EFI_ACPI_6_0_PLATFORM_INTERRUPT_SOURCES     0x08
+#define EFI_ACPI_6_0_PROCESSOR_LOCAL_X2APIC         0x09
+#define EFI_ACPI_6_0_LOCAL_X2APIC_NMI               0x0A
+#define EFI_ACPI_6_0_GIC                            0x0B
+#define EFI_ACPI_6_0_GICD                           0x0C
+#define EFI_ACPI_6_0_GIC_MSI_FRAME                  0x0D
+#define EFI_ACPI_6_0_GICR                           0x0E
+#define EFI_ACPI_6_0_GIC_ITS                        0x0F
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorUid;
+  UINT8   ApicId;
+  UINT32  Flags;
+} EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_0_LOCAL_APIC_ENABLED        BIT0
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  IoApicAddress;
+  UINT32  GlobalSystemInterruptBase;
+} EFI_ACPI_6_0_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Bus;
+  UINT8   Source;
+  UINT32  GlobalSystemInterrupt;
+  UINT16  Flags;
+} EFI_ACPI_6_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT8   InterruptType;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT8   IoSapicVector;
+  UINT32  GlobalSystemInterrupt;
+  UINT32  PlatformInterruptSourceFlags;
+  UINT8   CpeiProcessorOverride;
+  UINT8   Reserved[31];
+} EFI_ACPI_6_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_0_POLARITY      (3 << 0)
+#define EFI_ACPI_6_0_TRIGGER_MODE  (3 << 2)
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT32  GlobalSystemInterrupt;
+} EFI_ACPI_6_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorUid;
+  UINT16  Flags;
+  UINT8   LocalApicLint;
+} EFI_ACPI_6_0_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT64  LocalApicAddress;
+} EFI_ACPI_6_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  GlobalSystemInterruptBase;
+  UINT64  IoSapicAddress;
+} EFI_ACPI_6_0_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT8   LocalSapicId;
+  UINT8   LocalSapicEid;
+  UINT8   Reserved[3];
+  UINT32  Flags;
+  UINT32  ACPIProcessorUIDValue;
+} EFI_ACPI_6_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT8   InterruptType;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT8   IoSapicVector;
+  UINT32  GlobalSystemInterrupt;
+  UINT32  PlatformInterruptSourceFlags;
+} EFI_ACPI_6_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Platform Interrupt Source Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_0_CPEI_PROCESSOR_OVERRIDE          BIT0
+
+///
+/// Processor Local x2APIC Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Reserved[2];
+  UINT32  X2ApicId;
+  UINT32  Flags;
+  UINT32  AcpiProcessorUid;
+} EFI_ACPI_6_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
+
+///
+/// Local x2APIC NMI Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT32  AcpiProcessorUid;
+  UINT8   LocalX2ApicLint;
+  UINT8   Reserved[3];
+} EFI_ACPI_6_0_LOCAL_X2APIC_NMI_STRUCTURE;
+
+///
+/// GIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT32  CPUInterfaceNumber;
+  UINT32  AcpiProcessorUid;
+  UINT32  Flags;
+  UINT32  ParkingProtocolVersion;
+  UINT32  PerformanceInterruptGsiv;
+  UINT64  ParkedAddress;
+  UINT64  PhysicalBaseAddress;
+  UINT64  GICV;
+  UINT64  GICH;
+  UINT32  VGICMaintenanceInterrupt;
+  UINT64  GICRBaseAddress;
+  UINT64  MPIDR;
+  UINT8   ProcessorPowerEfficiencyClass;
+  UINT8   Reserved2[3];
+} EFI_ACPI_6_0_GIC_STRUCTURE;
+
+///
+/// GIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_0_GIC_ENABLED                              BIT0
+#define EFI_ACPI_6_0_PERFORMANCE_INTERRUPT_MODEL              BIT1
+#define EFI_ACPI_6_0_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS    BIT2
+
+///
+/// GIC Distributor Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved1;
+  UINT32  GicId;
+  UINT64  PhysicalBaseAddress;
+  UINT32  SystemVectorBase;
+  UINT8   GicVersion;
+  UINT8   Reserved2[3];
+} EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE;
+
+///
+/// GIC Version
+///
+#define EFI_ACPI_6_0_GIC_V1                                   0x01
+#define EFI_ACPI_6_0_GIC_V2                                   0x02
+#define EFI_ACPI_6_0_GIC_V3                                   0x03
+#define EFI_ACPI_6_0_GIC_V4                                   0x04
+
+///
+/// GIC MSI Frame Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved1;
+  UINT32  GicMsiFrameId;
+  UINT64  PhysicalBaseAddress;
+  UINT32  Flags;
+  UINT16  SPICount;
+  UINT16  SPIBase;
+} EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE;
+
+///
+/// GIC MSI Frame Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_0_SPI_COUNT_BASE_SELECT                    BIT0
+
+///
+/// GICR Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT64  DiscoveryRangeBaseAddress;
+  UINT32  DiscoveryRangeLength;
+} EFI_ACPI_6_0_GICR_STRUCTURE;
+
+///
+/// GIC Interrupt Translation Service Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT32  GicItsId;
+  UINT64  PhysicalBaseAddress;
+  UINT32  Reserved2;
+} EFI_ACPI_6_0_GIC_ITS_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      WarningEnergyLevel;
+  UINT32                      LowEnergyLevel;
+  UINT32                      CriticalEnergyLevel;
+} EFI_ACPI_6_0_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  EcControl;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  EcData;
+  UINT32                                  Uid;
+  UINT8                                   GpeBit;
+} EFI_ACPI_6_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION  0x01
+
+///
+/// System Resource Affinity Table (SRAT).  The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Reserved1;  ///< Must be set to 1
+  UINT64                      Reserved2;
+} EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+///
+/// SRAT Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION  0x03
+
+//
+// SRAT structure types.
+// All other values between 0x04 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY  0x00
+#define EFI_ACPI_6_0_MEMORY_AFFINITY                      0x01
+#define EFI_ACPI_6_0_PROCESSOR_LOCAL_X2APIC_AFFINITY      0x02
+#define EFI_ACPI_6_0_GICC_AFFINITY                        0x03
+
+///
+/// Processor Local APIC/SAPIC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   ProximityDomain7To0;
+  UINT8   ApicId;
+  UINT32  Flags;
+  UINT8   LocalSapicEid;
+  UINT8   ProximityDomain31To8[3];
+  UINT32  ClockDomain;
+} EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+///
+/// Local APIC/SAPIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+///
+/// Memory Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT32  ProximityDomain;
+  UINT16  Reserved1;
+  UINT32  AddressBaseLow;
+  UINT32  AddressBaseHigh;
+  UINT32  LengthLow;
+  UINT32  LengthHigh;
+  UINT32  Reserved2;
+  UINT32  Flags;
+  UINT64  Reserved3;
+} EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags.  All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_6_0_MEMORY_ENABLED       (1 << 0)
+#define EFI_ACPI_6_0_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_6_0_MEMORY_NONVOLATILE   (1 << 2)
+
+///
+/// Processor Local x2APIC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Reserved1[2];
+  UINT32  ProximityDomain;
+  UINT32  X2ApicId;
+  UINT32  Flags;
+  UINT32  ClockDomain;
+  UINT8   Reserved2[4];
+} EFI_ACPI_6_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT32  ProximityDomain;
+  UINT32  AcpiProcessorUid;
+  UINT32  Flags;
+  UINT32  ClockDomain;
+} EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_0_GICC_ENABLED (1 << 0)
+
+///
+/// System Locality Distance Information Table (SLIT).
+/// The rest of the table is a matrix.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT64                      NumberOfSystemLocalities;
+} EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+///
+/// SLIT Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION  0x01
+
+///
+/// Corrected Platform Error Polling Table (CPEP)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       Reserved[8];
+} EFI_ACPI_6_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
+
+///
+/// CPEP Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+
+//
+// CPEP processor structure types.
+//
+#define EFI_ACPI_6_0_CPEP_PROCESSOR_APIC_SAPIC  0x00
+
+///
+/// Corrected Platform Error Polling Processor Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT32  PollingInterval;
+} EFI_ACPI_6_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
+
+///
+/// Maximum System Characteristics Table (MSCT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      OffsetProxDomInfo;
+  UINT32                      MaximumNumberOfProximityDomains;
+  UINT32                      MaximumNumberOfClockDomains;
+  UINT64                      MaximumPhysicalAddress;
+} EFI_ACPI_6_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
+
+///
+/// MSCT Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+
+///
+/// Maximum Proximity Domain Information Structure Definition
+///
+typedef struct {
+  UINT8   Revision;
+  UINT8   Length;
+  UINT32  ProximityDomainRangeLow;
+  UINT32  ProximityDomainRangeHigh;
+  UINT32  MaximumProcessorCapacity;
+  UINT64  MaximumMemoryCapacity;
+} EFI_ACPI_6_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
+
+///
+/// ACPI RAS Feature Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       PlatformCommunicationChannelIdentifier[12];
+} EFI_ACPI_6_0_RAS_FEATURE_TABLE;
+
+///
+/// RASF Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_RAS_FEATURE_TABLE_REVISION 0x01
+
+///
+/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+  UINT32                      Signature;
+  UINT16                      Command;
+  UINT16                      Status;
+  UINT16                      Version;
+  UINT8                       RASCapabilities[16];
+  UINT8                       SetRASCapabilities[16];
+  UINT16                      NumberOfRASFParameterBlocks;
+  UINT32                      SetRASCapabilitiesStatus;
+} EFI_ACPI_6_0_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI RASF PCC command code
+///
+#define EFI_ACPI_6_0_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND  0x01
+
+///
+/// ACPI RASF Platform RAS Capabilities
+///
+#define EFI_ACPI_6_0_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED                          0x01
+#define EFI_ACPI_6_0_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED_AND_EXPOSED_TO_SOFTWARE  0x02
+
+///
+/// ACPI RASF Parameter Block structure for PATROL_SCRUB
+///
+typedef struct {
+  UINT16                      Type;
+  UINT16                      Version;
+  UINT16                      Length;
+  UINT16                      PatrolScrubCommand;
+  UINT64                      RequestedAddressRange[2];
+  UINT64                      ActualAddressRange[2];
+  UINT16                      Flags;
+  UINT8                       RequestedSpeed;
+} EFI_ACPI_6_0_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
+
+///
+/// ACPI RASF Patrol Scrub command
+///
+#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS   0x01
+#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER   0x02
+#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER    0x03
+
+///
+/// Memory Power State Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       PlatformCommunicationChannelIdentifier;
+  UINT8                       Reserved[3];
+// Memory Power Node Structure
+// Memory Power State Characteristics
+} EFI_ACPI_6_0_MEMORY_POWER_STATUS_TABLE;
+
+///
+/// MPST Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+
+///
+/// MPST Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+  UINT32                      Signature;
+  UINT16                      Command;
+  UINT16                      Status;
+  UINT32                      MemoryPowerCommandRegister;
+  UINT32                      MemoryPowerStatusRegister;
+  UINT32                      PowerStateId;
+  UINT32                      MemoryPowerNodeId;
+  UINT64                      MemoryEnergyConsumed;
+  UINT64                      ExpectedAveragePowerComsuned;
+} EFI_ACPI_6_0_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI MPST PCC command code
+///
+#define EFI_ACPI_6_0_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND  0x03
+
+///
+/// ACPI MPST Memory Power command
+///
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE       0x01
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE       0x02
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED   0x03
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED   0x04
+
+///
+/// MPST Memory Power Node Table
+///
+typedef struct {
+  UINT8                                             PowerStateValue;
+  UINT8                                             PowerStateInformationIndex;
+} EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE;
+
+typedef struct {
+  UINT8                                             Flag;
+  UINT8                                             Reserved;
+  UINT16                                            MemoryPowerNodeId;
+  UINT32                                            Length;
+  UINT64                                            AddressBase;
+  UINT64                                            AddressLength;
+  UINT32                                            NumberOfPowerStates;
+  UINT32                                            NumberOfPhysicalComponents;
+//EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE              MemoryPowerState[NumberOfPowerStates];
+//UINT16                                            PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+} EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE;
+
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE          0x01
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED   0x02
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE   0x04
+
+typedef struct {
+  UINT16                      MemoryPowerNodeCount;
+  UINT8                       Reserved[2];
+} EFI_ACPI_6_0_MPST_MEMORY_POWER_NODE_TABLE;
+
+///
+/// MPST Memory Power State Characteristics Table
+///
+typedef struct {
+  UINT8                                             PowerStateStructureID;
+  UINT8                                             Flag;
+  UINT16                                            Reserved;
+  UINT32                                            AveragePowerConsumedInMPS0;
+  UINT32                                            RelativePowerSavingToMPS0;
+  UINT64                                            ExitLatencyToMPS0;
+} EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
+
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED              0x01
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY   0x02
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT    0x04
+
+typedef struct {
+  UINT16                      MemoryPowerStateCharacteristicsCount;
+  UINT8                       Reserved[2];
+} EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
+
+///
+/// Memory Topology Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Reserved;
+} EFI_ACPI_6_0_MEMORY_TOPOLOGY_TABLE;
+
+///
+/// PMTT Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
+
+///
+/// Common Memory Aggregator Device Structure.
+///
+typedef struct {
+  UINT8                       Type;
+  UINT8                       Reserved;
+  UINT16                      Length;
+  UINT16                      Flags;
+  UINT16                      Reserved1;
+} EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Memory Aggregator Device Type
+///
+#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET            0x1
+#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x2
+#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM              0x3
+
+///
+/// Socket Memory Aggregator Device Structure.
+///
+typedef struct {
+  EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  Header;
+  UINT16                                                       SocketIdentifier;
+  UINT16                                                       Reserved;
+//EFI_ACPI_6_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  MemoryController[];
+} EFI_ACPI_6_0_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// MemoryController Memory Aggregator Device Structure.
+///
+typedef struct {
+  EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  Header;
+  UINT32                                                       ReadLatency;
+  UINT32                                                       WriteLatency;
+  UINT32                                                       ReadBandwidth;
+  UINT32                                                       WriteBandwidth;
+  UINT16                                                       OptimalAccessUnit;
+  UINT16                                                       OptimalAccessAlignment;
+  UINT16                                                       Reserved;
+  UINT16                                                       NumberOfProximityDomains;
+//UINT32                                                       ProximityDomain[NumberOfProximityDomains];
+//EFI_ACPI_6_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE    PhysicalComponent[];
+} EFI_ACPI_6_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// DIMM Memory Aggregator Device Structure.
+///
+typedef struct {
+  EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  Header;
+  UINT16                                                       PhysicalComponentIdentifier;
+  UINT16                                                       Reserved;
+  UINT32                                                       SizeOfDimm;
+  UINT32                                                       SmbiosHandle;
+} EFI_ACPI_6_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Boot Graphics Resource Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  ///
+  /// 2-bytes (16 bit) version ID. This value must be 1.
+  ///
+  UINT16                      Version;
+  ///
+  /// 1-byte status field indicating current status about the table.
+  ///     Bits[7:1] = Reserved (must be zero)
+  ///     Bit [0] = Valid. A one indicates the boot image graphic is valid.
+  ///
+  UINT8                       Status;
+  ///
+  /// 1-byte enumerated type field indicating format of the image.
+  ///     0 = Bitmap
+  ///     1 - 255  Reserved (for future use)
+  ///
+  UINT8                       ImageType;
+  ///
+  /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
+  /// of the image bitmap.
+  ///
+  UINT64                      ImageAddress;
+  ///
+  /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
+  /// (X, Y) display offset of the top left corner of the boot image.
+  /// The top left corner of the display is at offset (0, 0).
+  ///
+  UINT32                      ImageOffsetX;
+  ///
+  /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
+  /// (X, Y) display offset of the top left corner of the boot image.
+  /// The top left corner of the display is at offset (0, 0).
+  ///
+  UINT32                      ImageOffsetY;
+} EFI_ACPI_6_0_BOOT_GRAPHICS_RESOURCE_TABLE;
+
+///
+/// BGRT Revision
+///
+#define EFI_ACPI_6_0_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+
+///
+/// BGRT Version
+///
+#define EFI_ACPI_6_0_BGRT_VERSION         0x01
+
+///
+/// BGRT Status
+///
+#define EFI_ACPI_6_0_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_6_0_BGRT_STATUS_DISPLAYED     0x01
+
+///
+/// BGRT Image Type
+///
+#define EFI_ACPI_6_0_BGRT_IMAGE_TYPE_BMP  0x00
+
+///
+/// FPDT Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+
+///
+/// FPDT Performance Record Types
+///
+#define EFI_ACPI_6_0_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER      0x0000
+#define EFI_ACPI_6_0_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER     0x0001
+
+///
+/// FPDT Performance Record Revision
+///
+#define EFI_ACPI_6_0_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER  0x01
+#define EFI_ACPI_6_0_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+
+///
+/// FPDT Runtime Performance Record Types
+///
+#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME                0x0000
+#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND               0x0001
+#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT      0x0002
+
+///
+/// FPDT Runtime Performance Record Revision
+///
+#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME            0x01
+#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND           0x01
+#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT  0x02
+
+///
+/// FPDT Performance Record header
+///
+typedef struct {
+  UINT16           Type;
+  UINT8            Length;
+  UINT8            Revision;
+} EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER;
+
+///
+/// FPDT Performance Table header
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+} EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER;
+
+///
+/// FPDT Firmware Basic Boot Performance Pointer Record Structure
+///
+typedef struct {
+  EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  UINT32                                          Reserved;
+  ///
+  /// 64-bit processor-relative physical address of the Basic Boot Performance Table.
+  ///
+  UINT64                                          BootPerformanceTablePointer;
+} EFI_ACPI_6_0_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT S3 Performance Table Pointer Record Structure
+///
+typedef struct {
+  EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  UINT32                                          Reserved;
+  ///
+  /// 64-bit processor-relative physical address of the S3 Performance Table.
+  ///
+  UINT64                                          S3PerformanceTablePointer;
+} EFI_ACPI_6_0_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Record Structure
+///
+typedef struct {
+  EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  UINT32                                          Reserved;
+  ///
+  /// Timer value logged at the beginning of firmware image execution.
+  /// This may not always be zero or near zero.
+  ///
+  UINT64                                          ResetEnd;
+  ///
+  /// Timer value logged just prior to loading the OS boot loader into memory.
+  /// For non-UEFI compatible boots, this field must be zero.
+  ///
+  UINT64                                          OsLoaderLoadImageStart;
+  ///
+  /// Timer value logged just prior to launching the previously loaded OS boot loader image.
+  /// For non-UEFI compatible boots, the timer value logged will be just prior
+  /// to the INT 19h handler invocation.
+  ///
+  UINT64                                          OsLoaderStartImageStart;
+  ///
+  /// Timer value logged at the point when the OS loader calls the
+  /// ExitBootServices function for UEFI compatible firmware.
+  /// For non-UEFI compatible boots, this field must be zero.
+  ///
+  UINT64                                          ExitBootServicesEntry;
+  ///
+  /// Timer value logged at the point just prior towhen the OS loader gaining
+  /// control back from calls the ExitBootServices function for UEFI compatible firmware.
+  /// For non-UEFI compatible boots, this field must be zero.
+  ///
+  UINT64                                          ExitBootServicesExit;
+} EFI_ACPI_6_0_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Table signature
+///
+#define EFI_ACPI_6_0_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE  SIGNATURE_32('F', 'B', 'P', 'T')
+
+//
+// FPDT Firmware Basic Boot Performance Table
+//
+typedef struct {
+  EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER      Header;
+  //
+  // one or more Performance Records.
+  //
+} EFI_ACPI_6_0_FPDT_FIRMWARE_BASIC_BOOT_TABLE;
+
+///
+/// FPDT "S3PT" S3 Performance Table
+///
+#define EFI_ACPI_6_0_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE  SIGNATURE_32('S', '3', 'P', 'T')
+
+//
+// FPDT Firmware S3 Boot Performance Table
+//
+typedef struct {
+  EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER      Header;
+  //
+  // one or more Performance Records.
+  //
+} EFI_ACPI_6_0_FPDT_FIRMWARE_S3_BOOT_TABLE;
+
+///
+/// FPDT Basic S3 Resume Performance Record
+///
+typedef struct {
+  EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  ///
+  /// A count of the number of S3 resume cycles since the last full boot sequence.
+  ///
+  UINT32                                          ResumeCount;
+  ///
+  /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
+  /// OS waking vector. Only the most recent resume cycle's time is retained.
+  ///
+  UINT64                                          FullResume;
+  ///
+  /// Average timer value of all resume cycles logged since the last full boot
+  /// sequence, including the most recent resume.  Note that the entire log of
+  /// timer values does not need to be retained in order to calculate this average.
+  ///
+  UINT64                                          AverageResume;
+} EFI_ACPI_6_0_FPDT_S3_RESUME_RECORD;
+
+///
+/// FPDT Basic S3 Suspend Performance Record
+///
+typedef struct {
+  EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  ///
+  /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
+  /// Only the most recent suspend cycle's timer value is retained.
+  ///
+  UINT64                                          SuspendStart;
+  ///
+  /// Timer value recorded at the final firmware write to SLP_TYP (or other
+  /// mechanism) used to trigger hardware entry to S3.
+  /// Only the most recent suspend cycle's timer value is retained.
+  ///
+  UINT64                                          SuspendEnd;
+} EFI_ACPI_6_0_FPDT_S3_SUSPEND_RECORD;
+
+///
+/// Firmware Performance Record Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_0_FIRMWARE_PERFORMANCE_RECORD_TABLE;
+
+///
+/// Generic Timer Description Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT64                      CntControlBasePhysicalAddress;
+  UINT32                      Reserved;
+  UINT32                      SecurePL1TimerGSIV;
+  UINT32                      SecurePL1TimerFlags;
+  UINT32                      NonSecurePL1TimerGSIV;
+  UINT32                      NonSecurePL1TimerFlags;
+  UINT32                      VirtualTimerGSIV;
+  UINT32                      VirtualTimerFlags;
+  UINT32                      NonSecurePL2TimerGSIV;
+  UINT32                      NonSecurePL2TimerFlags;
+  UINT64                      CntReadBasePhysicalAddress;
+  UINT32                      PlatformTimerCount;
+  UINT32                      PlatformTimerOffset;
+} EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE;
+
+///
+/// GTDT Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Timer Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE          BIT0
+#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY      BIT1
+#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY          BIT2
+
+///
+/// Platform Timer Type
+///
+#define EFI_ACPI_6_0_GTDT_GT_BLOCK                       0
+#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG          1
+
+///
+/// GT Block Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT16  Length;
+  UINT8   Reserved;
+  UINT64  CntCtlBase;
+  UINT32  GTBlockTimerCount;
+  UINT32  GTBlockTimerOffset;
+} EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE;
+
+///
+/// GT Block Timer Structure
+///
+typedef struct {
+  UINT8   GTFrameNumber;
+  UINT8   Reserved[3];
+  UINT64  CntBaseX;
+  UINT64  CntEL0BaseX;
+  UINT32  GTxPhysicalTimerGSIV;
+  UINT32  GTxPhysicalTimerFlags;
+  UINT32  GTxVirtualTimerGSIV;
+  UINT32  GTxVirtualTimerFlags;
+  UINT32  GTxCommonFlags;
+} EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_STRUCTURE;
+
+///
+/// GT Block Physical Timers and Virtual Timers Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE          BIT0
+#define EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY      BIT1
+
+///
+/// Common Flags Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_0_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER              BIT0
+#define EFI_ACPI_6_0_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY      BIT1
+
+///
+/// SBSA Generic Watchdog Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT16  Length;
+  UINT8   Reserved;
+  UINT64  RefreshFramePhysicalAddress;
+  UINT64  WatchdogControlFramePhysicalAddress;
+  UINT32  WatchdogTimerGSIV;
+  UINT32  WatchdogTimerFlags;
+} EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;
+
+///
+/// SBSA Generic Watchdog Timer Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE          BIT0
+#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY      BIT1
+#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER                  BIT2
+
+//
+// NVDIMM Firmware Interface Table definition.
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER    Header;
+  UINT32                         Reserved;
+} EFI_ACPI_6_0_NVDIMM_FIRMWARE_INTERFACE_TABLE;
+
+//
+// NFIT Version (as defined in ACPI 6.0 spec.)
+//
+#define EFI_ACPI_6_0_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
+
+//
+// Definition for NFIT Table Structure Types
+//
+#define EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE              0
+#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_TO_SYSTEM_ADDRESS_RANGE_MAP_STRUCTURE_TYPE  1
+#define EFI_ACPI_6_0_NFIT_INTERLEAVE_STRUCTURE_TYPE                                 2
+#define EFI_ACPI_6_0_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE              3
+#define EFI_ACPI_6_0_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE                      4
+#define EFI_ACPI_6_0_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE            5
+#define EFI_ACPI_6_0_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE                         6
+
+//
+// Definition for NFIT Structure Header
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+} EFI_ACPI_6_0_NFIT_STRUCTURE_HEADER;
+
+//
+// Definition for System Physical Address Range Structure
+//
+#define EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT      BIT0
+#define EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID             BIT1
+#define EFI_ACPI_6_0_NFIT_GUID_VOLATILE_MEMORY_REGION                             { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
+#define EFI_ACPI_6_0_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION          { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
+#define EFI_ACPI_6_0_NFIT_GUID_NVDIMM_CONTROL_REGION                              { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
+#define EFI_ACPI_6_0_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION                    { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
+#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE   { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
+#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE     { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
+#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
+#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT   { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT16                                      SPARangeStructureIndex;
+  UINT16                                      Flags;
+  UINT32                                      Reserved_8;
+  UINT32                                      ProximityDomain;
+  GUID                                        AddressRangeTypeGUID;
+  UINT64                                      SystemPhysicalAddressRangeBase;
+  UINT64                                      SystemPhysicalAddressRangeLength;
+  UINT64                                      AddressRangeMemoryMappingAttribute;
+} EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;
+
+//
+// Definition for Memory Device to System Physical Address Range Mapping Structure
+//
+typedef struct {
+  UINT32                                      DIMMNumber:4;
+  UINT32                                      MemoryChannelNumber:4;
+  UINT32                                      MemoryControllerID:4;
+  UINT32                                      SocketID:4;
+  UINT32                                      NodeControllerID:12;
+  UINT32                                      Reserved_28:4;
+} EFI_ACPI_6_0_NFIT_DEVICE_HANDLE;
+
+#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL                                      BIT0
+#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL                                       BIT1
+#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL                                     BIT2
+#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF                        BIT3
+#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF                 BIT4
+#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS  BIT5
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  EFI_ACPI_6_0_NFIT_DEVICE_HANDLE             NFITDeviceHandle;
+  UINT16                                      MemoryDevicePhysicalID;
+  UINT16                                      MemoryDeviceRegionID;
+  UINT16                                      SPARangeStructureIndex ;
+  UINT16                                      NVDIMMControlRegionStructureIndex;
+  UINT64                                      MemoryDeviceRegionSize;
+  UINT64                                      RegionOffset;
+  UINT64                                      MemoryDevicePhysicalAddressRegionBase;
+  UINT16                                      InterleaveStructureIndex;
+  UINT16                                      InterleaveWays;
+  UINT16                                      MemoryDeviceStateFlags;
+  UINT16                                      Reserved_46;
+} EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_TO_SYSTEM_ADDRESS_RANGE_MAP_STRUCTURE;
+
+//
+// Definition for Interleave Structure
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT16                                      InterleaveStructureIndex;
+  UINT16                                      Reserved_6;
+  UINT32                                      NumberOfLines;
+  UINT32                                      LineSize;
+//UINT32                                      LineOffset[NumberOfLines];
+} EFI_ACPI_6_0_NFIT_INTERLEAVE_STRUCTURE;
+
+//
+// Definition for SMBIOS Management Information Structure
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT32                                      Reserved_4;
+//UINT8                                       Data[];
+} EFI_ACPI_6_0_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;
+
+//
+// Definition for NVDIMM Control Region Structure
+//
+#define EFI_ACPI_6_0_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED    BIT0
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT16                                      NVDIMMControlRegionStructureIndex;
+  UINT16                                      VendorID;
+  UINT16                                      DeviceID;
+  UINT16                                      RevisionID;
+  UINT16                                      SubsystemVendorID;
+  UINT16                                      SubsystemDeviceID;
+  UINT16                                      SubsystemRevisionID;
+  UINT8                                       Reserved_18[6];
+  UINT32                                      SerialNumber;
+  UINT16                                      RegionFormatInterfaceCode;
+  UINT16                                      NumberOfBlockControlWindows;
+  UINT64                                      SizeOfBlockControlWindow;
+  UINT64                                      CommandRegisterOffsetInBlockControlWindow;
+  UINT64                                      SizeOfCommandRegisterInBlockControlWindows;
+  UINT64                                      StatusRegisterOffsetInBlockControlWindow;
+  UINT64                                      SizeOfStatusRegisterInBlockControlWindows;
+  UINT16                                      NVDIMMControlRegionFlag;
+  UINT8                                       Reserved_74[6];
+} EFI_ACPI_6_0_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;
+
+//
+// Definition for NVDIMM Block Data Window Region Structure
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT16                                      NVDIMMControlRegionStructureIndex;
+  UINT16                                      NumberOfBlockDataWindows;
+  UINT64                                      BlockDataWindowStartOffset;
+  UINT64                                      SizeOfBlockDataWindow;
+  UINT64                                      BlockAccessibleMemoryCapacity;
+  UINT64                                      BeginningAddressOfFirstBlockInBlockAccessibleMemory;
+} EFI_ACPI_6_0_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;
+
+//
+// Definition for Flush Hint Address Structure
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  EFI_ACPI_6_0_NFIT_DEVICE_HANDLE             NFITDeviceHandle;
+  UINT16                                      NumberOfFlushHintAddresses;
+  UINT8                                       Reserved_10[6];
+//UINT64                                      FlushHintAddress[NumberOfFlushHintAddresses];
+} EFI_ACPI_6_0_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;
+
+///
+/// Boot Error Record Table (BERT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      BootErrorRegionLength;
+  UINT64                      BootErrorRegion;
+} EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_HEADER;
+
+///
+/// BERT Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+
+///
+/// Boot Error Region Block Status Definition
+///
+typedef struct {
+  UINT32       UncorrectableErrorValid:1;
+  UINT32       CorrectableErrorValid:1;
+  UINT32       MultipleUncorrectableErrors:1;
+  UINT32       MultipleCorrectableErrors:1;
+  UINT32       ErrorDataEntryCount:10;
+  UINT32       Reserved:18;
+} EFI_ACPI_6_0_ERROR_BLOCK_STATUS;
+
+///
+/// Boot Error Region Definition
+///
+typedef struct {
+  EFI_ACPI_6_0_ERROR_BLOCK_STATUS              BlockStatus;
+  UINT32                                       RawDataOffset;
+  UINT32                                       RawDataLength;
+  UINT32                                       DataLength;
+  UINT32                                       ErrorSeverity;
+} EFI_ACPI_6_0_BOOT_ERROR_REGION_STRUCTURE;
+
+//
+// Boot Error Severity types
+//
+#define EFI_ACPI_6_0_ERROR_SEVERITY_CORRECTABLE  0x00
+#define EFI_ACPI_6_0_ERROR_SEVERITY_FATAL        0x01
+#define EFI_ACPI_6_0_ERROR_SEVERITY_CORRECTED    0x02
+#define EFI_ACPI_6_0_ERROR_SEVERITY_NONE         0x03
+
+///
+/// Generic Error Data Entry Definition
+///
+typedef struct {
+  UINT8    SectionType[16];
+  UINT32   ErrorSeverity;
+  UINT16   Revision;
+  UINT8    ValidationBits;
+  UINT8    Flags;
+  UINT32   ErrorDataLength;
+  UINT8    FruId[16];
+  UINT8    FruText[20];
+} EFI_ACPI_6_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
+
+///
+/// Generic Error Data Entry Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_GENERIC_ERROR_DATA_ENTRY_REVISION  0x0201
+
+///
+/// HEST - Hardware Error Source Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      ErrorSourceCount;
+} EFI_ACPI_6_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
+
+///
+/// HEST Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+
+//
+// Error Source structure types.
+//
+#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION  0x00
+#define EFI_ACPI_6_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK  0x01
+#define EFI_ACPI_6_0_IA32_ARCHITECTURE_NMI_ERROR                0x02
+#define EFI_ACPI_6_0_PCI_EXPRESS_ROOT_PORT_AER                  0x06
+#define EFI_ACPI_6_0_PCI_EXPRESS_DEVICE_AER                     0x07
+#define EFI_ACPI_6_0_PCI_EXPRESS_BRIDGE_AER                     0x08
+#define EFI_ACPI_6_0_GENERIC_HARDWARE_ERROR                     0x09
+
+//
+// Error Source structure flags.
+//
+#define EFI_ACPI_6_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST       (1 << 0)
+#define EFI_ACPI_6_0_ERROR_SOURCE_FLAG_GLOBAL               (1 << 1)
+
+///
+/// IA-32 Architecture Machine Check Exception Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT64  GlobalCapabilityInitData;
+  UINT64  GlobalControlInitData;
+  UINT8   NumberOfHardwareBanks;
+  UINT8   Reserved1[7];
+} EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure Definition
+///
+typedef struct {
+  UINT8   BankNumber;
+  UINT8   ClearStatusOnInitialization;
+  UINT8   StatusDataFormat;
+  UINT8   Reserved0;
+  UINT32  ControlRegisterMsrAddress;
+  UINT64  ControlInitData;
+  UINT32  StatusRegisterMsrAddress;
+  UINT32  AddressRegisterMsrAddress;
+  UINT32  MiscRegisterMsrAddress;
+} EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure MCA data format
+///
+#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32      0x00
+#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64   0x01
+#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64     0x02
+
+//
+// Hardware Error Notification types. All other values are reserved
+//
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_POLLED                0x00
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT    0x01
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT       0x02
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_SCI                   0x03
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_NMI                   0x04
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CMCI                  0x05
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_MCE                   0x06
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL           0x07
+
+///
+/// Hardware Error Notification Configuration Write Enable Structure Definition
+///
+typedef struct {
+  UINT16    Type:1;
+  UINT16    PollInterval:1;
+  UINT16    SwitchToPollingThresholdValue:1;
+  UINT16    SwitchToPollingThresholdWindow:1;
+  UINT16    ErrorThresholdValue:1;
+  UINT16    ErrorThresholdWindow:1;
+  UINT16    Reserved:10;
+} EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
+
+///
+/// Hardware Error Notification Structure Definition
+///
+typedef struct {
+  UINT8                                                                          Type;
+  UINT8                                                                          Length;
+  EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE  ConfigurationWriteEnable;
+  UINT32                                                                         PollInterval;
+  UINT32                                                                         Vector;
+  UINT32                                                                         SwitchToPollingThresholdValue;
+  UINT32                                                                         SwitchToPollingThresholdWindow;
+  UINT32                                                                         ErrorThresholdValue;
+  UINT32                                                                         ErrorThresholdWindow;
+} EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
+
+///
+/// IA-32 Architecture Corrected Machine Check Structure Definition
+///
+typedef struct {
+  UINT16                                                 Type;
+  UINT16                                                 SourceId;
+  UINT8                                                  Reserved0[2];
+  UINT8                                                  Flags;
+  UINT8                                                  Enabled;
+  UINT32                                                 NumberOfRecordsToPreAllocate;
+  UINT32                                                 MaxSectionsPerRecord;
+  EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE     NotificationStructure;
+  UINT8                                                  NumberOfHardwareBanks;
+  UINT8                                                  Reserved1[3];
+} EFI_ACPI_6_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// IA-32 Architecture NMI Error Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  MaxRawDataLength;
+} EFI_ACPI_6_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
+
+///
+/// PCI Express Root Port AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+  UINT32  RootErrorCommand;
+} EFI_ACPI_6_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
+
+///
+/// PCI Express Device AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
+
+///
+/// PCI Express Bridge AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+  UINT32  SecondaryUncorrectableErrorMask;
+  UINT32  SecondaryUncorrectableErrorSeverity;
+  UINT32  SecondaryAdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Structure Definition
+///
+typedef struct {
+  UINT16                                                 Type;
+  UINT16                                                 SourceId;
+  UINT16                                                 RelatedSourceId;
+  UINT8                                                  Flags;
+  UINT8                                                  Enabled;
+  UINT32                                                 NumberOfRecordsToPreAllocate;
+  UINT32                                                 MaxSectionsPerRecord;
+  UINT32                                                 MaxRawDataLength;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE                 ErrorStatusAddress;
+  EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE     NotificationStructure;
+  UINT32                                                 ErrorStatusBlockLength;
+} EFI_ACPI_6_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
+
+///
+/// Generic Error Status Definition
+///
+typedef struct {
+  EFI_ACPI_6_0_ERROR_BLOCK_STATUS              BlockStatus;
+  UINT32                                       RawDataOffset;
+  UINT32                                       RawDataLength;
+  UINT32                                       DataLength;
+  UINT32                                       ErrorSeverity;
+} EFI_ACPI_6_0_GENERIC_ERROR_STATUS_STRUCTURE;
+
+///
+/// ERST - Error Record Serialization Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      SerializationHeaderSize;
+  UINT8                       Reserved0[4];
+  UINT32                      InstructionEntryCount;
+} EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
+
+///
+/// ERST Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+
+///
+/// ERST Serialization Actions
+///
+#define EFI_ACPI_6_0_ERST_BEGIN_WRITE_OPERATION                    0x00
+#define EFI_ACPI_6_0_ERST_BEGIN_READ_OPERATION                     0x01
+#define EFI_ACPI_6_0_ERST_BEGIN_CLEAR_OPERATION                    0x02
+#define EFI_ACPI_6_0_ERST_END_OPERATION                            0x03
+#define EFI_ACPI_6_0_ERST_SET_RECORD_OFFSET                        0x04
+#define EFI_ACPI_6_0_ERST_EXECUTE_OPERATION                        0x05
+#define EFI_ACPI_6_0_ERST_CHECK_BUSY_STATUS                        0x06
+#define EFI_ACPI_6_0_ERST_GET_COMMAND_STATUS                       0x07
+#define EFI_ACPI_6_0_ERST_GET_RECORD_IDENTIFIER                    0x08
+#define EFI_ACPI_6_0_ERST_SET_RECORD_IDENTIFIER                    0x09
+#define EFI_ACPI_6_0_ERST_GET_RECORD_COUNT                         0x0A
+#define EFI_ACPI_6_0_ERST_BEGIN_DUMMY_WRITE_OPERATION              0x0B
+#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE              0x0D
+#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH       0x0E
+#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES   0x0F
+
+///
+/// ERST Action Command Status
+///
+#define EFI_ACPI_6_0_ERST_STATUS_SUCCESS                           0x00
+#define EFI_ACPI_6_0_ERST_STATUS_NOT_ENOUGH_SPACE                  0x01
+#define EFI_ACPI_6_0_ERST_STATUS_HARDWARE_NOT_AVAILABLE            0x02
+#define EFI_ACPI_6_0_ERST_STATUS_FAILED                            0x03
+#define EFI_ACPI_6_0_ERST_STATUS_RECORD_STORE_EMPTY                0x04
+#define EFI_ACPI_6_0_ERST_STATUS_RECORD_NOT_FOUND                  0x05
+
+///
+/// ERST Serialization Instructions
+///
+#define EFI_ACPI_6_0_ERST_READ_REGISTER                            0x00
+#define EFI_ACPI_6_0_ERST_READ_REGISTER_VALUE                      0x01
+#define EFI_ACPI_6_0_ERST_WRITE_REGISTER                           0x02
+#define EFI_ACPI_6_0_ERST_WRITE_REGISTER_VALUE                     0x03
+#define EFI_ACPI_6_0_ERST_NOOP                                     0x04
+#define EFI_ACPI_6_0_ERST_LOAD_VAR1                                0x05
+#define EFI_ACPI_6_0_ERST_LOAD_VAR2                                0x06
+#define EFI_ACPI_6_0_ERST_STORE_VAR1                               0x07
+#define EFI_ACPI_6_0_ERST_ADD                                      0x08
+#define EFI_ACPI_6_0_ERST_SUBTRACT                                 0x09
+#define EFI_ACPI_6_0_ERST_ADD_VALUE                                0x0A
+#define EFI_ACPI_6_0_ERST_SUBTRACT_VALUE                           0x0B
+#define EFI_ACPI_6_0_ERST_STALL                                    0x0C
+#define EFI_ACPI_6_0_ERST_STALL_WHILE_TRUE                         0x0D
+#define EFI_ACPI_6_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE            0x0E
+#define EFI_ACPI_6_0_ERST_GOTO                                     0x0F
+#define EFI_ACPI_6_0_ERST_SET_SRC_ADDRESS_BASE                     0x10
+#define EFI_ACPI_6_0_ERST_SET_DST_ADDRESS_BASE                     0x11
+#define EFI_ACPI_6_0_ERST_MOVE_DATA                                0x12
+
+///
+/// ERST Instruction Flags
+///
+#define EFI_ACPI_6_0_ERST_PRESERVE_REGISTER                        0x01
+
+///
+/// ERST Serialization Instruction Entry
+///
+typedef struct {
+  UINT8                                    SerializationAction;
+  UINT8                                    Instruction;
+  UINT8                                    Flags;
+  UINT8                                    Reserved0;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE   RegisterRegion;
+  UINT64                                   Value;
+  UINT64                                   Mask;
+} EFI_ACPI_6_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ - Error Injection Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      InjectionHeaderSize;
+  UINT8                       InjectionFlags;
+  UINT8                       Reserved0[3];
+  UINT32                      InjectionEntryCount;
+} EFI_ACPI_6_0_ERROR_INJECTION_TABLE_HEADER;
+
+///
+/// EINJ Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_ERROR_INJECTION_TABLE_REVISION 0x01
+
+///
+/// EINJ Error Injection Actions
+///
+#define EFI_ACPI_6_0_EINJ_BEGIN_INJECTION_OPERATION                0x00
+#define EFI_ACPI_6_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE           0x01
+#define EFI_ACPI_6_0_EINJ_SET_ERROR_TYPE                           0x02
+#define EFI_ACPI_6_0_EINJ_GET_ERROR_TYPE                           0x03
+#define EFI_ACPI_6_0_EINJ_END_OPERATION                            0x04
+#define EFI_ACPI_6_0_EINJ_EXECUTE_OPERATION                        0x05
+#define EFI_ACPI_6_0_EINJ_CHECK_BUSY_STATUS                        0x06
+#define EFI_ACPI_6_0_EINJ_GET_COMMAND_STATUS                       0x07
+#define EFI_ACPI_6_0_EINJ_TRIGGER_ERROR                            0xFF
+
+///
+/// EINJ Action Command Status
+///
+#define EFI_ACPI_6_0_EINJ_STATUS_SUCCESS                           0x00
+#define EFI_ACPI_6_0_EINJ_STATUS_UNKNOWN_FAILURE                   0x01
+#define EFI_ACPI_6_0_EINJ_STATUS_INVALID_ACCESS                    0x02
+
+///
+/// EINJ Error Type Definition
+///
+#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_CORRECTABLE                 (1 << 0)
+#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL      (1 << 1)
+#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL         (1 << 2)
+#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_CORRECTABLE                    (1 << 3)
+#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL         (1 << 4)
+#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL            (1 << 5)
+#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE               (1 << 6)
+#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL    (1 << 7)
+#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL       (1 << 8)
+#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_CORRECTABLE                  (1 << 9)
+#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL       (1 << 10)
+#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL          (1 << 11)
+
+///
+/// EINJ Injection Instructions
+///
+#define EFI_ACPI_6_0_EINJ_READ_REGISTER                            0x00
+#define EFI_ACPI_6_0_EINJ_READ_REGISTER_VALUE                      0x01
+#define EFI_ACPI_6_0_EINJ_WRITE_REGISTER                           0x02
+#define EFI_ACPI_6_0_EINJ_WRITE_REGISTER_VALUE                     0x03
+#define EFI_ACPI_6_0_EINJ_NOOP                                     0x04
+
+///
+/// EINJ Instruction Flags
+///
+#define EFI_ACPI_6_0_EINJ_PRESERVE_REGISTER                        0x01
+
+///
+/// EINJ Injection Instruction Entry
+///
+typedef struct {
+  UINT8                                    InjectionAction;
+  UINT8                                    Instruction;
+  UINT8                                    Flags;
+  UINT8                                    Reserved0;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE   RegisterRegion;
+  UINT64                                   Value;
+  UINT64                                   Mask;
+} EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ Trigger Action Table
+///
+typedef struct {
+  UINT32  HeaderSize;
+  UINT32  Revision;
+  UINT32  TableSize;
+  UINT32  EntryCount;
+} EFI_ACPI_6_0_EINJ_TRIGGER_ACTION_TABLE;
+
+///
+/// Platform Communications Channel Table (PCCT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Flags;
+  UINT64                      Reserved;
+} EFI_ACPI_6_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
+
+///
+/// PCCT Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01
+
+///
+/// PCCT Global Flags
+///
+#define EFI_ACPI_6_0_PCCT_FLAGS_SCI_DOORBELL                      BIT0
+
+//
+// PCCT Subspace type
+//
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_GENERIC                         0x00
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS     0x01
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS     0x02
+
+///
+/// PCC Subspace Structure Header
+///
+typedef struct {
+  UINT8        Type;
+  UINT8        Length;
+} EFI_ACPI_6_0_PCCT_SUBSPACE_HEADER;
+
+///
+/// Generic Communications Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT8                                    Reserved[6];
+  UINT64                                   BaseAddress;
+  UINT64                                   AddressLength;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT16                                   MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_0_PCCT_SUBSPACE_GENERIC;
+
+///
+/// Generic Communications Channel Shared Memory Region
+///
+
+typedef struct {
+  UINT8                                    Command;
+  UINT8                                    Reserved:7;
+  UINT8                                    GenerateSci:1;
+} EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
+
+typedef struct {
+  UINT8                                    CommandComplete:1;
+  UINT8                                    SciDoorbell:1;
+  UINT8                                    Error:1;
+  UINT8                                    PlatformNotification:1;  
+  UINT8                                    Reserved:4;
+  UINT8                                    Reserved1;
+} EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
+
+typedef struct {
+  UINT32                                                    Signature;
+  EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND    Command;
+  EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS     Status;
+} EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
+
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_POLARITY    BIT0
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_MODE        BIT1
+
+///
+/// Type 1 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT32                                   DoorbellInterrupt;
+  UINT8                                    DoorbellInterruptFlags;
+  UINT8                                    Reserved;
+  UINT64                                   BaseAddress;
+  UINT64                                   AddressLength;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT16                                   MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_0_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 2 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT32                                   DoorbellInterrupt;
+  UINT8                                    DoorbellInterruptFlags;
+  UINT8                                    Reserved;
+  UINT64                                   BaseAddress;
+  UINT64                                   AddressLength;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT16                                   MinimumRequestTurnaroundTime;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE   DoorbellAckRegister;
+  UINT64                                   DoorbellAckPreserve;
+  UINT64                                   DoorbellAckWrite;
+} EFI_ACPI_6_0_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') 
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "BERT" Boot Error Record Table
+///
+#define EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_SIGNATURE  SIGNATURE_32('B', 'E', 'R', 'T')
+
+///
+/// "BGRT" Boot Graphics Resource Table
+///
+#define EFI_ACPI_6_0_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('B', 'G', 'R', 'T')
+
+///
+/// "CPEP" Corrected Platform Error Polling Table
+///
+#define EFI_ACPI_6_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE  SIGNATURE_32('C', 'P', 'E', 'P')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_6_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_6_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE  SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "EINJ" Error Injection Table
+///
+#define EFI_ACPI_6_0_ERROR_INJECTION_TABLE_SIGNATURE  SIGNATURE_32('E', 'I', 'N', 'J')
+
+///
+/// "ERST" Error Record Serialization Table
+///
+#define EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE  SIGNATURE_32('E', 'R', 'S', 'T')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "FPDT" Firmware Performance Data Table
+///
+#define EFI_ACPI_6_0_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE  SIGNATURE_32('F', 'P', 'D', 'T')
+
+///
+/// "GTDT" Generic Timer Description Table
+///
+#define EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('G', 'T', 'D', 'T')
+
+///
+/// "HEST" Hardware Error Source Table
+///
+#define EFI_ACPI_6_0_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE  SIGNATURE_32('H', 'E', 'S', 'T')
+
+///
+/// "MPST" Memory Power State Table
+///
+#define EFI_ACPI_6_0_MEMORY_POWER_STATE_TABLE_SIGNATURE  SIGNATURE_32('M', 'P', 'S', 'T')
+
+///
+/// "MSCT" Maximum System Characteristics Table
+///
+#define EFI_ACPI_6_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE  SIGNATURE_32('M', 'S', 'C', 'T')
+
+///
+/// "NFIT" NVDIMM Firmware Interface Table
+///
+#define EFI_ACPI_6_0_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE  SIGNATURE_32('N', 'F', 'I', 'T')
+
+///
+/// "PMTT" Platform Memory Topology Table
+///
+#define EFI_ACPI_6_0_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE  SIGNATURE_32('P', 'M', 'T', 'T')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_6_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RASF" ACPI RAS Feature Table
+///
+#define EFI_ACPI_6_0_ACPI_RAS_FEATURE_TABLE_SIGNATURE  SIGNATURE_32('R', 'A', 'S', 'F')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_6_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SRAT" System Resource Affinity Table
+///
+#define EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE  SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_6_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_6_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE  SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "CSRT" MS Core System Resource Table
+///
+#define EFI_ACPI_6_0_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('C', 'S', 'R', 'T')
+
+///
+/// "DBG2" MS Debug Port 2 Spec
+///
+#define EFI_ACPI_6_0_DEBUG_PORT_2_TABLE_SIGNATURE  SIGNATURE_32('D', 'B', 'G', '2')
+
+///
+/// "DBGP" MS Debug Port Spec
+///
+#define EFI_ACPI_6_0_DEBUG_PORT_TABLE_SIGNATURE  SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "DMAR" DMA Remapping Table
+///
+#define EFI_ACPI_6_0_DMA_REMAPPING_TABLE_SIGNATURE  SIGNATURE_32('D', 'M', 'A', 'R')
+
+///
+/// "DRTM" Dynamic Root of Trust for Measurement Table
+///
+#define EFI_ACPI_6_0_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE  SIGNATURE_32('D', 'R', 'T', 'M')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_6_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "HPET" IA-PC High Precision Event Timer Table
+///
+#define EFI_ACPI_6_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE  SIGNATURE_32('H', 'P', 'E', 'T')
+
+///
+/// "iBFT" iSCSI Boot Firmware Table
+///
+#define EFI_ACPI_6_0_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE  SIGNATURE_32('i', 'B', 'F', 'T')
+
+///
+/// "IORT" I/O Remapping Table
+///
+#define EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE  SIGNATURE_32('I', 'O', 'R', 'T')
+
+///
+/// "IVRS" I/O Virtualization Reporting Structure
+///
+#define EFI_ACPI_6_0_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE  SIGNATURE_32('I', 'V', 'R', 'S')
+
+///
+/// "LPIT" Low Power Idle Table
+///
+#define EFI_ACPI_6_0_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE  SIGNATURE_32('L', 'P', 'I', 'T')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_6_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('M', 'C', 'F', 'G')
+
+///
+/// "MCHI" Management Controller Host Interface Table
+///
+#define EFI_ACPI_6_0_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('M', 'C', 'H', 'I')
+
+///
+/// "MSDM" MS Data Management Table
+///
+#define EFI_ACPI_6_0_DATA_MANAGEMENT_TABLE_SIGNATURE  SIGNATURE_32('M', 'S', 'D', 'M')
+
+///
+/// "SLIC" MS Software Licensing Table Specification
+///
+#define EFI_ACPI_6_0_SOFTWARE_LICENSING_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'C')
+
+///
+/// "SPCR" Serial Port Concole Redirection Table
+///
+#define EFI_ACPI_6_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_6_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "STAO" _STA Override Table
+///
+#define EFI_ACPI_6_0_STA_OVERRIDE_TABLE_SIGNATURE  SIGNATURE_32('S', 'T', 'A', 'O')
+
+///
+/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+///
+#define EFI_ACPI_6_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE  SIGNATURE_32('T', 'C', 'P', 'A')
+
+///
+/// "TPM2" Trusted Computing Platform 1 Table
+///
+#define EFI_ACPI_6_0_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE  SIGNATURE_32('T', 'P', 'M', '2')
+
+///
+/// "UEFI" UEFI ACPI Data Table
+///
+#define EFI_ACPI_6_0_UEFI_ACPI_DATA_TABLE_SIGNATURE  SIGNATURE_32('U', 'E', 'F', 'I')
+
+///
+/// "WAET" Windows ACPI Emulated Devices Table
+///
+#define EFI_ACPI_6_0_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE  SIGNATURE_32('W', 'A', 'E', 'T')
+
+///
+/// "WDAT" Watchdog Action Table
+///
+#define EFI_ACPI_6_0_WATCHDOG_ACTION_TABLE_SIGNATURE  SIGNATURE_32('W', 'D', 'A', 'T')
+
+///
+/// "WDRT" Watchdog Resource Table
+///
+#define EFI_ACPI_6_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('W', 'D', 'R', 'T')
+
+///
+/// "WPBT" MS Platform Binary Table
+///
+#define EFI_ACPI_6_0_PLATFORM_BINARY_TABLE_SIGNATURE  SIGNATURE_32('W', 'P', 'B', 'T')
+
+///
+/// "XENV" Xen Project Table
+///
+#define EFI_ACPI_6_0_XEN_PROJECT_TABLE_SIGNATURE  SIGNATURE_32('X', 'E', 'N', 'V')
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi61.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi61.h
new file mode 100644
index 0000000000..71a2f02508
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi61.h
@@ -0,0 +1,2424 @@
+/** @file   
+  ACPI 6.1 definitions from the ACPI Specification Revision 6.1 January, 2016.
+
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+**/
+
+#ifndef _ACPI_6_1_H_
+#define _ACPI_6_1_H_
+
+#include <IndustryStandard/Acpi60.h>
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 6.1 Generic Address Space definition
+///
+typedef struct {
+  UINT8   AddressSpaceId;
+  UINT8   RegisterBitWidth;
+  UINT8   RegisterBitOffset;
+  UINT8   AccessSize;
+  UINT64  Address;
+} EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_6_1_SYSTEM_MEMORY              0
+#define EFI_ACPI_6_1_SYSTEM_IO                  1
+#define EFI_ACPI_6_1_PCI_CONFIGURATION_SPACE    2
+#define EFI_ACPI_6_1_EMBEDDED_CONTROLLER        3
+#define EFI_ACPI_6_1_SMBUS                      4
+#define EFI_ACPI_6_1_PLATFORM_COMMUNICATION_CHANNEL  0x0A
+#define EFI_ACPI_6_1_FUNCTIONAL_FIXED_HARDWARE       0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_6_1_UNDEFINED  0
+#define EFI_ACPI_6_1_BYTE       1
+#define EFI_ACPI_6_1_WORD       2
+#define EFI_ACPI_6_1_DWORD      3
+#define EFI_ACPI_6_1_QWORD      4
+
+//
+// ACPI 6.1 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+  UINT64  Signature;
+  UINT8   Checksum;
+  UINT8   OemId[6];
+  UINT8   Revision;
+  UINT32  RsdtAddress;
+  UINT32  Length;
+  UINT64  XsdtAddress;
+  UINT8   ExtendedChecksum;
+  UINT8   Reserved[3];
+} EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02  ///< ACPISpec (Revision 6.1) says current value is 2
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+} EFI_ACPI_6_1_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with 
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with 
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  UINT32                                  FirmwareCtrl;
+  UINT32                                  Dsdt;
+  UINT8                                   Reserved0;
+  UINT8                                   PreferredPmProfile;
+  UINT16                                  SciInt;
+  UINT32                                  SmiCmd;
+  UINT8                                   AcpiEnable;
+  UINT8                                   AcpiDisable;
+  UINT8                                   S4BiosReq;
+  UINT8                                   PstateCnt;
+  UINT32                                  Pm1aEvtBlk;
+  UINT32                                  Pm1bEvtBlk;
+  UINT32                                  Pm1aCntBlk;
+  UINT32                                  Pm1bCntBlk;
+  UINT32                                  Pm2CntBlk;
+  UINT32                                  PmTmrBlk;
+  UINT32                                  Gpe0Blk;
+  UINT32                                  Gpe1Blk;
+  UINT8                                   Pm1EvtLen;
+  UINT8                                   Pm1CntLen;
+  UINT8                                   Pm2CntLen;
+  UINT8                                   PmTmrLen;
+  UINT8                                   Gpe0BlkLen;
+  UINT8                                   Gpe1BlkLen;
+  UINT8                                   Gpe1Base;
+  UINT8                                   CstCnt;
+  UINT16                                  PLvl2Lat;
+  UINT16                                  PLvl3Lat;
+  UINT16                                  FlushSize;
+  UINT16                                  FlushStride;
+  UINT8                                   DutyOffset;
+  UINT8                                   DutyWidth;
+  UINT8                                   DayAlrm;
+  UINT8                                   MonAlrm;
+  UINT8                                   Century;
+  UINT16                                  IaPcBootArch;
+  UINT8                                   Reserved1;
+  UINT32                                  Flags;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE  ResetReg;
+  UINT8                                   ResetValue;
+  UINT16                                  ArmBootArch;
+  UINT8                                   MinorVersion;
+  UINT64                                  XFirmwareCtrl;
+  UINT64                                  XDsdt;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE  SleepControlReg;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE  SleepStatusReg;
+  UINT64                                  HypervisorVendorIdentity;
+} EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION  0x06
+#define EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION  0x01
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED         0
+#define EFI_ACPI_6_1_PM_PROFILE_DESKTOP             1
+#define EFI_ACPI_6_1_PM_PROFILE_MOBILE              2
+#define EFI_ACPI_6_1_PM_PROFILE_WORKSTATION         3
+#define EFI_ACPI_6_1_PM_PROFILE_ENTERPRISE_SERVER   4
+#define EFI_ACPI_6_1_PM_PROFILE_SOHO_SERVER         5
+#define EFI_ACPI_6_1_PM_PROFILE_APPLIANCE_PC        6
+#define EFI_ACPI_6_1_PM_PROFILE_PERFORMANCE_SERVER  7
+#define EFI_ACPI_6_1_PM_PROFILE_TABLET              8
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_1_LEGACY_DEVICES              BIT0
+#define EFI_ACPI_6_1_8042                        BIT1
+#define EFI_ACPI_6_1_VGA_NOT_PRESENT             BIT2
+#define EFI_ACPI_6_1_MSI_NOT_SUPPORTED           BIT3
+#define EFI_ACPI_6_1_PCIE_ASPM_CONTROLS          BIT4
+#define EFI_ACPI_6_1_CMOS_RTC_NOT_PRESENT        BIT5
+
+//
+// Fixed ACPI Description Table Arm Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_1_ARM_PSCI_COMPLIANT              BIT0
+#define EFI_ACPI_6_1_ARM_PSCI_USE_HVC                BIT1
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_1_WBINVD                                 BIT0
+#define EFI_ACPI_6_1_WBINVD_FLUSH                           BIT1
+#define EFI_ACPI_6_1_PROC_C1                                BIT2
+#define EFI_ACPI_6_1_P_LVL2_UP                              BIT3
+#define EFI_ACPI_6_1_PWR_BUTTON                             BIT4
+#define EFI_ACPI_6_1_SLP_BUTTON                             BIT5
+#define EFI_ACPI_6_1_FIX_RTC                                BIT6
+#define EFI_ACPI_6_1_RTC_S4                                 BIT7
+#define EFI_ACPI_6_1_TMR_VAL_EXT                            BIT8
+#define EFI_ACPI_6_1_DCK_CAP                                BIT9
+#define EFI_ACPI_6_1_RESET_REG_SUP                          BIT10
+#define EFI_ACPI_6_1_SEALED_CASE                            BIT11
+#define EFI_ACPI_6_1_HEADLESS                               BIT12
+#define EFI_ACPI_6_1_CPU_SW_SLP                             BIT13
+#define EFI_ACPI_6_1_PCI_EXP_WAK                            BIT14
+#define EFI_ACPI_6_1_USE_PLATFORM_CLOCK                     BIT15
+#define EFI_ACPI_6_1_S4_RTC_STS_VALID                       BIT16
+#define EFI_ACPI_6_1_REMOTE_POWER_ON_CAPABLE                BIT17
+#define EFI_ACPI_6_1_FORCE_APIC_CLUSTER_MODEL               BIT18
+#define EFI_ACPI_6_1_FORCE_APIC_PHYSICAL_DESTINATION_MODE   BIT19
+#define EFI_ACPI_6_1_HW_REDUCED_ACPI                        BIT20
+#define EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE              BIT21
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+  UINT32  HardwareSignature;
+  UINT32  FirmwareWakingVector;
+  UINT32  GlobalLock;
+  UINT32  Flags;
+  UINT64  XFirmwareWakingVector;
+  UINT8   Version;
+  UINT8   Reserved0[3];
+  UINT32  OspmFlags;
+  UINT8   Reserved1[24];
+} EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION  0x02
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_1_S4BIOS_F                     BIT0
+#define EFI_ACPI_6_1_64BIT_WAKE_SUPPORTED_F       BIT1
+
+///
+/// OSPM Enabled Firmware Control Structure Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_1_OSPM_64BIT_WAKE_F            BIT0
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
+//
+#define EFI_ACPI_6_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION   0x02
+#define EFI_ACPI_6_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION        0x02
+
+///
+/// Multiple APIC Description Table header definition.  The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      LocalApicAddress;
+  UINT32                      Flags;
+} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_1_PCAT_COMPAT         BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x0D and 0x7F are reserved and
+// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.
+//
+#define EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC           0x00
+#define EFI_ACPI_6_1_IO_APIC                        0x01
+#define EFI_ACPI_6_1_INTERRUPT_SOURCE_OVERRIDE      0x02
+#define EFI_ACPI_6_1_NON_MASKABLE_INTERRUPT_SOURCE  0x03
+#define EFI_ACPI_6_1_LOCAL_APIC_NMI                 0x04
+#define EFI_ACPI_6_1_LOCAL_APIC_ADDRESS_OVERRIDE    0x05
+#define EFI_ACPI_6_1_IO_SAPIC                       0x06
+#define EFI_ACPI_6_1_LOCAL_SAPIC                    0x07
+#define EFI_ACPI_6_1_PLATFORM_INTERRUPT_SOURCES     0x08
+#define EFI_ACPI_6_1_PROCESSOR_LOCAL_X2APIC         0x09
+#define EFI_ACPI_6_1_LOCAL_X2APIC_NMI               0x0A
+#define EFI_ACPI_6_1_GIC                            0x0B
+#define EFI_ACPI_6_1_GICD                           0x0C
+#define EFI_ACPI_6_1_GIC_MSI_FRAME                  0x0D
+#define EFI_ACPI_6_1_GICR                           0x0E
+#define EFI_ACPI_6_1_GIC_ITS                        0x0F
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorUid;
+  UINT8   ApicId;
+  UINT32  Flags;
+} EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_1_LOCAL_APIC_ENABLED        BIT0
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  IoApicAddress;
+  UINT32  GlobalSystemInterruptBase;
+} EFI_ACPI_6_1_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Bus;
+  UINT8   Source;
+  UINT32  GlobalSystemInterrupt;
+  UINT16  Flags;
+} EFI_ACPI_6_1_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT8   InterruptType;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT8   IoSapicVector;
+  UINT32  GlobalSystemInterrupt;
+  UINT32  PlatformInterruptSourceFlags;
+  UINT8   CpeiProcessorOverride;
+  UINT8   Reserved[31];
+} EFI_ACPI_6_1_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_1_POLARITY      (3 << 0)
+#define EFI_ACPI_6_1_TRIGGER_MODE  (3 << 2)
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT32  GlobalSystemInterrupt;
+} EFI_ACPI_6_1_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorUid;
+  UINT16  Flags;
+  UINT8   LocalApicLint;
+} EFI_ACPI_6_1_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT64  LocalApicAddress;
+} EFI_ACPI_6_1_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  GlobalSystemInterruptBase;
+  UINT64  IoSapicAddress;
+} EFI_ACPI_6_1_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT8   LocalSapicId;
+  UINT8   LocalSapicEid;
+  UINT8   Reserved[3];
+  UINT32  Flags;
+  UINT32  ACPIProcessorUIDValue;
+} EFI_ACPI_6_1_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT8   InterruptType;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT8   IoSapicVector;
+  UINT32  GlobalSystemInterrupt;
+  UINT32  PlatformInterruptSourceFlags;
+} EFI_ACPI_6_1_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Platform Interrupt Source Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_1_CPEI_PROCESSOR_OVERRIDE          BIT0
+
+///
+/// Processor Local x2APIC Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Reserved[2];
+  UINT32  X2ApicId;
+  UINT32  Flags;
+  UINT32  AcpiProcessorUid;
+} EFI_ACPI_6_1_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
+
+///
+/// Local x2APIC NMI Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT32  AcpiProcessorUid;
+  UINT8   LocalX2ApicLint;
+  UINT8   Reserved[3];
+} EFI_ACPI_6_1_LOCAL_X2APIC_NMI_STRUCTURE;
+
+///
+/// GIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT32  CPUInterfaceNumber;
+  UINT32  AcpiProcessorUid;
+  UINT32  Flags;
+  UINT32  ParkingProtocolVersion;
+  UINT32  PerformanceInterruptGsiv;
+  UINT64  ParkedAddress;
+  UINT64  PhysicalBaseAddress;
+  UINT64  GICV;
+  UINT64  GICH;
+  UINT32  VGICMaintenanceInterrupt;
+  UINT64  GICRBaseAddress;
+  UINT64  MPIDR;
+  UINT8   ProcessorPowerEfficiencyClass;
+  UINT8   Reserved2[3];
+} EFI_ACPI_6_1_GIC_STRUCTURE;
+
+///
+/// GIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_1_GIC_ENABLED                              BIT0
+#define EFI_ACPI_6_1_PERFORMANCE_INTERRUPT_MODEL              BIT1
+#define EFI_ACPI_6_1_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS    BIT2
+
+///
+/// GIC Distributor Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved1;
+  UINT32  GicId;
+  UINT64  PhysicalBaseAddress;
+  UINT32  SystemVectorBase;
+  UINT8   GicVersion;
+  UINT8   Reserved2[3];
+} EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE;
+
+///
+/// GIC Version
+///
+#define EFI_ACPI_6_1_GIC_V1                                   0x01
+#define EFI_ACPI_6_1_GIC_V2                                   0x02
+#define EFI_ACPI_6_1_GIC_V3                                   0x03
+#define EFI_ACPI_6_1_GIC_V4                                   0x04
+
+///
+/// GIC MSI Frame Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved1;
+  UINT32  GicMsiFrameId;
+  UINT64  PhysicalBaseAddress;
+  UINT32  Flags;
+  UINT16  SPICount;
+  UINT16  SPIBase;
+} EFI_ACPI_6_1_GIC_MSI_FRAME_STRUCTURE;
+
+///
+/// GIC MSI Frame Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_1_SPI_COUNT_BASE_SELECT                    BIT0
+
+///
+/// GICR Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT64  DiscoveryRangeBaseAddress;
+  UINT32  DiscoveryRangeLength;
+} EFI_ACPI_6_1_GICR_STRUCTURE;
+
+///
+/// GIC Interrupt Translation Service Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT32  GicItsId;
+  UINT64  PhysicalBaseAddress;
+  UINT32  Reserved2;
+} EFI_ACPI_6_1_GIC_ITS_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      WarningEnergyLevel;
+  UINT32                      LowEnergyLevel;
+  UINT32                      CriticalEnergyLevel;
+} EFI_ACPI_6_1_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE  EcControl;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE  EcData;
+  UINT32                                  Uid;
+  UINT8                                   GpeBit;
+} EFI_ACPI_6_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION  0x01
+
+///
+/// System Resource Affinity Table (SRAT).  The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Reserved1;  ///< Must be set to 1
+  UINT64                      Reserved2;
+} EFI_ACPI_6_1_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+///
+/// SRAT Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION  0x03
+
+//
+// SRAT structure types.
+// All other values between 0x04 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY  0x00
+#define EFI_ACPI_6_1_MEMORY_AFFINITY                      0x01
+#define EFI_ACPI_6_1_PROCESSOR_LOCAL_X2APIC_AFFINITY      0x02
+#define EFI_ACPI_6_1_GICC_AFFINITY                        0x03
+
+///
+/// Processor Local APIC/SAPIC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   ProximityDomain7To0;
+  UINT8   ApicId;
+  UINT32  Flags;
+  UINT8   LocalSapicEid;
+  UINT8   ProximityDomain31To8[3];
+  UINT32  ClockDomain;
+} EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+///
+/// Local APIC/SAPIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+///
+/// Memory Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT32  ProximityDomain;
+  UINT16  Reserved1;
+  UINT32  AddressBaseLow;
+  UINT32  AddressBaseHigh;
+  UINT32  LengthLow;
+  UINT32  LengthHigh;
+  UINT32  Reserved2;
+  UINT32  Flags;
+  UINT64  Reserved3;
+} EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags.  All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_6_1_MEMORY_ENABLED       (1 << 0)
+#define EFI_ACPI_6_1_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_6_1_MEMORY_NONVOLATILE   (1 << 2)
+
+///
+/// Processor Local x2APIC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Reserved1[2];
+  UINT32  ProximityDomain;
+  UINT32  X2ApicId;
+  UINT32  Flags;
+  UINT32  ClockDomain;
+  UINT8   Reserved2[4];
+} EFI_ACPI_6_1_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT32  ProximityDomain;
+  UINT32  AcpiProcessorUid;
+  UINT32  Flags;
+  UINT32  ClockDomain;
+} EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_1_GICC_ENABLED (1 << 0)
+
+///
+/// System Locality Distance Information Table (SLIT).
+/// The rest of the table is a matrix.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT64                      NumberOfSystemLocalities;
+} EFI_ACPI_6_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+///
+/// SLIT Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION  0x01
+
+///
+/// Corrected Platform Error Polling Table (CPEP)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       Reserved[8];
+} EFI_ACPI_6_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
+
+///
+/// CPEP Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+
+//
+// CPEP processor structure types.
+//
+#define EFI_ACPI_6_1_CPEP_PROCESSOR_APIC_SAPIC  0x00
+
+///
+/// Corrected Platform Error Polling Processor Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT32  PollingInterval;
+} EFI_ACPI_6_1_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
+
+///
+/// Maximum System Characteristics Table (MSCT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      OffsetProxDomInfo;
+  UINT32                      MaximumNumberOfProximityDomains;
+  UINT32                      MaximumNumberOfClockDomains;
+  UINT64                      MaximumPhysicalAddress;
+} EFI_ACPI_6_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
+
+///
+/// MSCT Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+
+///
+/// Maximum Proximity Domain Information Structure Definition
+///
+typedef struct {
+  UINT8   Revision;
+  UINT8   Length;
+  UINT32  ProximityDomainRangeLow;
+  UINT32  ProximityDomainRangeHigh;
+  UINT32  MaximumProcessorCapacity;
+  UINT64  MaximumMemoryCapacity;
+} EFI_ACPI_6_1_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
+
+///
+/// ACPI RAS Feature Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       PlatformCommunicationChannelIdentifier[12];
+} EFI_ACPI_6_1_RAS_FEATURE_TABLE;
+
+///
+/// RASF Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_RAS_FEATURE_TABLE_REVISION 0x01
+
+///
+/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+  UINT32                      Signature;
+  UINT16                      Command;
+  UINT16                      Status;
+  UINT16                      Version;
+  UINT8                       RASCapabilities[16];
+  UINT8                       SetRASCapabilities[16];
+  UINT16                      NumberOfRASFParameterBlocks;
+  UINT32                      SetRASCapabilitiesStatus;
+} EFI_ACPI_6_1_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI RASF PCC command code
+///
+#define EFI_ACPI_6_1_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND  0x01
+
+///
+/// ACPI RASF Platform RAS Capabilities
+///
+#define EFI_ACPI_6_1_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED                          0x01
+#define EFI_ACPI_6_1_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED_AND_EXPOSED_TO_SOFTWARE  0x02
+
+///
+/// ACPI RASF Parameter Block structure for PATROL_SCRUB
+///
+typedef struct {
+  UINT16                      Type;
+  UINT16                      Version;
+  UINT16                      Length;
+  UINT16                      PatrolScrubCommand;
+  UINT64                      RequestedAddressRange[2];
+  UINT64                      ActualAddressRange[2];
+  UINT16                      Flags;
+  UINT8                       RequestedSpeed;
+} EFI_ACPI_6_1_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
+
+///
+/// ACPI RASF Patrol Scrub command
+///
+#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS   0x01
+#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER   0x02
+#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER    0x03
+
+///
+/// Memory Power State Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       PlatformCommunicationChannelIdentifier;
+  UINT8                       Reserved[3];
+// Memory Power Node Structure
+// Memory Power State Characteristics
+} EFI_ACPI_6_1_MEMORY_POWER_STATUS_TABLE;
+
+///
+/// MPST Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+
+///
+/// MPST Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+  UINT32                      Signature;
+  UINT16                      Command;
+  UINT16                      Status;
+  UINT32                      MemoryPowerCommandRegister;
+  UINT32                      MemoryPowerStatusRegister;
+  UINT32                      PowerStateId;
+  UINT32                      MemoryPowerNodeId;
+  UINT64                      MemoryEnergyConsumed;
+  UINT64                      ExpectedAveragePowerComsuned;
+} EFI_ACPI_6_1_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI MPST PCC command code
+///
+#define EFI_ACPI_6_1_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND  0x03
+
+///
+/// ACPI MPST Memory Power command
+///
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE       0x01
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE       0x02
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED   0x03
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED   0x04
+
+///
+/// MPST Memory Power Node Table
+///
+typedef struct {
+  UINT8                                             PowerStateValue;
+  UINT8                                             PowerStateInformationIndex;
+} EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE;
+
+typedef struct {
+  UINT8                                             Flag;
+  UINT8                                             Reserved;
+  UINT16                                            MemoryPowerNodeId;
+  UINT32                                            Length;
+  UINT64                                            AddressBase;
+  UINT64                                            AddressLength;
+  UINT32                                            NumberOfPowerStates;
+  UINT32                                            NumberOfPhysicalComponents;
+//EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE              MemoryPowerState[NumberOfPowerStates];
+//UINT16                                            PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+} EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE;
+
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE          0x01
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED   0x02
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE   0x04
+
+typedef struct {
+  UINT16                      MemoryPowerNodeCount;
+  UINT8                       Reserved[2];
+} EFI_ACPI_6_1_MPST_MEMORY_POWER_NODE_TABLE;
+
+///
+/// MPST Memory Power State Characteristics Table
+///
+typedef struct {
+  UINT8                                             PowerStateStructureID;
+  UINT8                                             Flag;
+  UINT16                                            Reserved;
+  UINT32                                            AveragePowerConsumedInMPS0;
+  UINT32                                            RelativePowerSavingToMPS0;
+  UINT64                                            ExitLatencyToMPS0;
+} EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
+
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED              0x01
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY   0x02
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT    0x04
+
+typedef struct {
+  UINT16                      MemoryPowerStateCharacteristicsCount;
+  UINT8                       Reserved[2];
+} EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
+
+///
+/// Memory Topology Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Reserved;
+} EFI_ACPI_6_1_MEMORY_TOPOLOGY_TABLE;
+
+///
+/// PMTT Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
+
+///
+/// Common Memory Aggregator Device Structure.
+///
+typedef struct {
+  UINT8                       Type;
+  UINT8                       Reserved;
+  UINT16                      Length;
+  UINT16                      Flags;
+  UINT16                      Reserved1;
+} EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Memory Aggregator Device Type
+///
+#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET            0x1
+#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x2
+#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM              0x3
+
+///
+/// Socket Memory Aggregator Device Structure.
+///
+typedef struct {
+  EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  Header;
+  UINT16                                                       SocketIdentifier;
+  UINT16                                                       Reserved;
+//EFI_ACPI_6_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  MemoryController[];
+} EFI_ACPI_6_1_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// MemoryController Memory Aggregator Device Structure.
+///
+typedef struct {
+  EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  Header;
+  UINT32                                                       ReadLatency;
+  UINT32                                                       WriteLatency;
+  UINT32                                                       ReadBandwidth;
+  UINT32                                                       WriteBandwidth;
+  UINT16                                                       OptimalAccessUnit;
+  UINT16                                                       OptimalAccessAlignment;
+  UINT16                                                       Reserved;
+  UINT16                                                       NumberOfProximityDomains;
+//UINT32                                                       ProximityDomain[NumberOfProximityDomains];
+//EFI_ACPI_6_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE    PhysicalComponent[];
+} EFI_ACPI_6_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// DIMM Memory Aggregator Device Structure.
+///
+typedef struct {
+  EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  Header;
+  UINT16                                                       PhysicalComponentIdentifier;
+  UINT16                                                       Reserved;
+  UINT32                                                       SizeOfDimm;
+  UINT32                                                       SmbiosHandle;
+} EFI_ACPI_6_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Boot Graphics Resource Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  ///
+  /// 2-bytes (16 bit) version ID. This value must be 1.
+  ///
+  UINT16                      Version;
+  ///
+  /// 1-byte status field indicating current status about the table.
+  ///     Bits[7:1] = Reserved (must be zero)
+  ///     Bit [0] = Valid. A one indicates the boot image graphic is valid.
+  ///
+  UINT8                       Status;
+  ///
+  /// 1-byte enumerated type field indicating format of the image.
+  ///     0 = Bitmap
+  ///     1 - 255  Reserved (for future use)
+  ///
+  UINT8                       ImageType;
+  ///
+  /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
+  /// of the image bitmap.
+  ///
+  UINT64                      ImageAddress;
+  ///
+  /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
+  /// (X, Y) display offset of the top left corner of the boot image.
+  /// The top left corner of the display is at offset (0, 0).
+  ///
+  UINT32                      ImageOffsetX;
+  ///
+  /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
+  /// (X, Y) display offset of the top left corner of the boot image.
+  /// The top left corner of the display is at offset (0, 0).
+  ///
+  UINT32                      ImageOffsetY;
+} EFI_ACPI_6_1_BOOT_GRAPHICS_RESOURCE_TABLE;
+
+///
+/// BGRT Revision
+///
+#define EFI_ACPI_6_1_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+
+///
+/// BGRT Version
+///
+#define EFI_ACPI_6_1_BGRT_VERSION         0x01
+
+///
+/// BGRT Status
+///
+#define EFI_ACPI_6_1_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_6_1_BGRT_STATUS_DISPLAYED     0x01
+
+///
+/// BGRT Image Type
+///
+#define EFI_ACPI_6_1_BGRT_IMAGE_TYPE_BMP  0x00
+
+///
+/// FPDT Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+
+///
+/// FPDT Performance Record Types
+///
+#define EFI_ACPI_6_1_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER      0x0000
+#define EFI_ACPI_6_1_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER     0x0001
+
+///
+/// FPDT Performance Record Revision
+///
+#define EFI_ACPI_6_1_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER  0x01
+#define EFI_ACPI_6_1_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+
+///
+/// FPDT Runtime Performance Record Types
+///
+#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME                0x0000
+#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND               0x0001
+#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT      0x0002
+
+///
+/// FPDT Runtime Performance Record Revision
+///
+#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME            0x01
+#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND           0x01
+#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT  0x02
+
+///
+/// FPDT Performance Record header
+///
+typedef struct {
+  UINT16           Type;
+  UINT8            Length;
+  UINT8            Revision;
+} EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER;
+
+///
+/// FPDT Performance Table header
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+} EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER;
+
+///
+/// FPDT Firmware Basic Boot Performance Pointer Record Structure
+///
+typedef struct {
+  EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  UINT32                                          Reserved;
+  ///
+  /// 64-bit processor-relative physical address of the Basic Boot Performance Table.
+  ///
+  UINT64                                          BootPerformanceTablePointer;
+} EFI_ACPI_6_1_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT S3 Performance Table Pointer Record Structure
+///
+typedef struct {
+  EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  UINT32                                          Reserved;
+  ///
+  /// 64-bit processor-relative physical address of the S3 Performance Table.
+  ///
+  UINT64                                          S3PerformanceTablePointer;
+} EFI_ACPI_6_1_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Record Structure
+///
+typedef struct {
+  EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  UINT32                                          Reserved;
+  ///
+  /// Timer value logged at the beginning of firmware image execution.
+  /// This may not always be zero or near zero.
+  ///
+  UINT64                                          ResetEnd;
+  ///
+  /// Timer value logged just prior to loading the OS boot loader into memory.
+  /// For non-UEFI compatible boots, this field must be zero.
+  ///
+  UINT64                                          OsLoaderLoadImageStart;
+  ///
+  /// Timer value logged just prior to launching the previously loaded OS boot loader image.
+  /// For non-UEFI compatible boots, the timer value logged will be just prior
+  /// to the INT 19h handler invocation.
+  ///
+  UINT64                                          OsLoaderStartImageStart;
+  ///
+  /// Timer value logged at the point when the OS loader calls the
+  /// ExitBootServices function for UEFI compatible firmware.
+  /// For non-UEFI compatible boots, this field must be zero.
+  ///
+  UINT64                                          ExitBootServicesEntry;
+  ///
+  /// Timer value logged at the point just prior towhen the OS loader gaining
+  /// control back from calls the ExitBootServices function for UEFI compatible firmware.
+  /// For non-UEFI compatible boots, this field must be zero.
+  ///
+  UINT64                                          ExitBootServicesExit;
+} EFI_ACPI_6_1_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Table signature
+///
+#define EFI_ACPI_6_1_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE  SIGNATURE_32('F', 'B', 'P', 'T')
+
+//
+// FPDT Firmware Basic Boot Performance Table
+//
+typedef struct {
+  EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER      Header;
+  //
+  // one or more Performance Records.
+  //
+} EFI_ACPI_6_1_FPDT_FIRMWARE_BASIC_BOOT_TABLE;
+
+///
+/// FPDT "S3PT" S3 Performance Table
+///
+#define EFI_ACPI_6_1_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE  SIGNATURE_32('S', '3', 'P', 'T')
+
+//
+// FPDT Firmware S3 Boot Performance Table
+//
+typedef struct {
+  EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER      Header;
+  //
+  // one or more Performance Records.
+  //
+} EFI_ACPI_6_1_FPDT_FIRMWARE_S3_BOOT_TABLE;
+
+///
+/// FPDT Basic S3 Resume Performance Record
+///
+typedef struct {
+  EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  ///
+  /// A count of the number of S3 resume cycles since the last full boot sequence.
+  ///
+  UINT32                                          ResumeCount;
+  ///
+  /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
+  /// OS waking vector. Only the most recent resume cycle's time is retained.
+  ///
+  UINT64                                          FullResume;
+  ///
+  /// Average timer value of all resume cycles logged since the last full boot
+  /// sequence, including the most recent resume.  Note that the entire log of
+  /// timer values does not need to be retained in order to calculate this average.
+  ///
+  UINT64                                          AverageResume;
+} EFI_ACPI_6_1_FPDT_S3_RESUME_RECORD;
+
+///
+/// FPDT Basic S3 Suspend Performance Record
+///
+typedef struct {
+  EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  ///
+  /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
+  /// Only the most recent suspend cycle's timer value is retained.
+  ///
+  UINT64                                          SuspendStart;
+  ///
+  /// Timer value recorded at the final firmware write to SLP_TYP (or other
+  /// mechanism) used to trigger hardware entry to S3.
+  /// Only the most recent suspend cycle's timer value is retained.
+  ///
+  UINT64                                          SuspendEnd;
+} EFI_ACPI_6_1_FPDT_S3_SUSPEND_RECORD;
+
+///
+/// Firmware Performance Record Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_1_FIRMWARE_PERFORMANCE_RECORD_TABLE;
+
+///
+/// Generic Timer Description Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT64                      CntControlBasePhysicalAddress;
+  UINT32                      Reserved;
+  UINT32                      SecurePL1TimerGSIV;
+  UINT32                      SecurePL1TimerFlags;
+  UINT32                      NonSecurePL1TimerGSIV;
+  UINT32                      NonSecurePL1TimerFlags;
+  UINT32                      VirtualTimerGSIV;
+  UINT32                      VirtualTimerFlags;
+  UINT32                      NonSecurePL2TimerGSIV;
+  UINT32                      NonSecurePL2TimerFlags;
+  UINT64                      CntReadBasePhysicalAddress;
+  UINT32                      PlatformTimerCount;
+  UINT32                      PlatformTimerOffset;
+} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE;
+
+///
+/// GTDT Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Timer Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE          BIT0
+#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY      BIT1
+#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY          BIT2
+
+///
+/// Platform Timer Type
+///
+#define EFI_ACPI_6_1_GTDT_GT_BLOCK                       0
+#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG          1
+
+///
+/// GT Block Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT16  Length;
+  UINT8   Reserved;
+  UINT64  CntCtlBase;
+  UINT32  GTBlockTimerCount;
+  UINT32  GTBlockTimerOffset;
+} EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE;
+
+///
+/// GT Block Timer Structure
+///
+typedef struct {
+  UINT8   GTFrameNumber;
+  UINT8   Reserved[3];
+  UINT64  CntBaseX;
+  UINT64  CntEL0BaseX;
+  UINT32  GTxPhysicalTimerGSIV;
+  UINT32  GTxPhysicalTimerFlags;
+  UINT32  GTxVirtualTimerGSIV;
+  UINT32  GTxVirtualTimerFlags;
+  UINT32  GTxCommonFlags;
+} EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE;
+
+///
+/// GT Block Physical Timers and Virtual Timers Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE          BIT0
+#define EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY      BIT1
+
+///
+/// Common Flags Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER              BIT0
+#define EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY      BIT1
+
+///
+/// SBSA Generic Watchdog Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT16  Length;
+  UINT8   Reserved;
+  UINT64  RefreshFramePhysicalAddress;
+  UINT64  WatchdogControlFramePhysicalAddress;
+  UINT32  WatchdogTimerGSIV;
+  UINT32  WatchdogTimerFlags;
+} EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;
+
+///
+/// SBSA Generic Watchdog Timer Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE          BIT0
+#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY      BIT1
+#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER                  BIT2
+
+//
+// NVDIMM Firmware Interface Table definition.
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER    Header;
+  UINT32                         Reserved;
+} EFI_ACPI_6_1_NVDIMM_FIRMWARE_INTERFACE_TABLE;
+
+//
+// NFIT Version (as defined in ACPI 6.1 spec.)
+//
+#define EFI_ACPI_6_1_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
+
+//
+// Definition for NFIT Table Structure Types
+//
+#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE              0
+#define EFI_ACPI_6_1_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE                      1
+#define EFI_ACPI_6_1_NFIT_INTERLEAVE_STRUCTURE_TYPE                                 2
+#define EFI_ACPI_6_1_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE              3
+#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE                      4
+#define EFI_ACPI_6_1_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE            5
+#define EFI_ACPI_6_1_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE                         6
+
+//
+// Definition for NFIT Structure Header
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+} EFI_ACPI_6_1_NFIT_STRUCTURE_HEADER;
+
+//
+// Definition for System Physical Address Range Structure
+//
+#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT      BIT0
+#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID             BIT1
+#define EFI_ACPI_6_1_NFIT_GUID_VOLATILE_MEMORY_REGION                             { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
+#define EFI_ACPI_6_1_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION          { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
+#define EFI_ACPI_6_1_NFIT_GUID_NVDIMM_CONTROL_REGION                              { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
+#define EFI_ACPI_6_1_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION                    { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
+#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE   { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
+#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE     { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
+#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
+#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT   { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D ]}
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT16                                      SPARangeStructureIndex;
+  UINT16                                      Flags;
+  UINT32                                      Reserved_8;
+  UINT32                                      ProximityDomain;
+  GUID                                        AddressRangeTypeGUID;
+  UINT64                                      SystemPhysicalAddressRangeBase;
+  UINT64                                      SystemPhysicalAddressRangeLength;
+  UINT64                                      AddressRangeMemoryMappingAttribute;
+} EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;
+
+//
+// Definition for Memory Device to System Physical Address Range Mapping Structure
+//
+typedef struct {
+  UINT32                                      DIMMNumber:4;
+  UINT32                                      MemoryChannelNumber:4;
+  UINT32                                      MemoryControllerID:4;
+  UINT32                                      SocketID:4;
+  UINT32                                      NodeControllerID:12;
+  UINT32                                      Reserved_28:4;
+} EFI_ACPI_6_1_NFIT_DEVICE_HANDLE;
+
+#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL                                      BIT0
+#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL                                       BIT1
+#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL                                     BIT2
+#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF                        BIT3
+#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF                 BIT4
+#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS  BIT5
+#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA                          BIT6
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  EFI_ACPI_6_1_NFIT_DEVICE_HANDLE             NFITDeviceHandle;
+  UINT16                                      NVDIMMPhysicalID;
+  UINT16                                      NVDIMMRegionID;
+  UINT16                                      SPARangeStructureIndex ;
+  UINT16                                      NVDIMMControlRegionStructureIndex;
+  UINT64                                      NVDIMMRegionSize;
+  UINT64                                      RegionOffset;
+  UINT64                                      NVDIMMPhysicalAddressRegionBase;
+  UINT16                                      InterleaveStructureIndex;
+  UINT16                                      InterleaveWays;
+  UINT16                                      NVDIMMStateFlags;
+  UINT16                                      Reserved_46;
+} EFI_ACPI_6_1_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;
+
+//
+// Definition for Interleave Structure
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT16                                      InterleaveStructureIndex;
+  UINT16                                      Reserved_6;
+  UINT32                                      NumberOfLines;
+  UINT32                                      LineSize;
+//UINT32                                      LineOffset[NumberOfLines];
+} EFI_ACPI_6_1_NFIT_INTERLEAVE_STRUCTURE;
+
+//
+// Definition for SMBIOS Management Information Structure
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT32                                      Reserved_4;
+//UINT8                                       Data[];
+} EFI_ACPI_6_1_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;
+
+//
+// Definition for NVDIMM Control Region Structure
+//
+#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING           BIT0
+
+#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED    BIT0
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT16                                      NVDIMMControlRegionStructureIndex;
+  UINT16                                      VendorID;
+  UINT16                                      DeviceID;
+  UINT16                                      RevisionID;
+  UINT16                                      SubsystemVendorID;
+  UINT16                                      SubsystemDeviceID;
+  UINT16                                      SubsystemRevisionID;
+  UINT8                                       ValidFields;
+  UINT8                                       ManufacturingLocation;
+  UINT16                                      ManufacturingDate;
+  UINT8                                       Reserved_22[2];
+  UINT32                                      SerialNumber;
+  UINT16                                      RegionFormatInterfaceCode;
+  UINT16                                      NumberOfBlockControlWindows;
+  UINT64                                      SizeOfBlockControlWindow;
+  UINT64                                      CommandRegisterOffsetInBlockControlWindow;
+  UINT64                                      SizeOfCommandRegisterInBlockControlWindows;
+  UINT64                                      StatusRegisterOffsetInBlockControlWindow;
+  UINT64                                      SizeOfStatusRegisterInBlockControlWindows;
+  UINT16                                      NVDIMMControlRegionFlag;
+  UINT8                                       Reserved_74[6];
+} EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;
+
+//
+// Definition for NVDIMM Block Data Window Region Structure
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT16                                      NVDIMMControlRegionStructureIndex;
+  UINT16                                      NumberOfBlockDataWindows;
+  UINT64                                      BlockDataWindowStartOffset;
+  UINT64                                      SizeOfBlockDataWindow;
+  UINT64                                      BlockAccessibleMemoryCapacity;
+  UINT64                                      BeginningAddressOfFirstBlockInBlockAccessibleMemory;
+} EFI_ACPI_6_1_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;
+
+//
+// Definition for Flush Hint Address Structure
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  EFI_ACPI_6_1_NFIT_DEVICE_HANDLE             NFITDeviceHandle;
+  UINT16                                      NumberOfFlushHintAddresses;
+  UINT8                                       Reserved_10[6];
+//UINT64                                      FlushHintAddress[NumberOfFlushHintAddresses];
+} EFI_ACPI_6_1_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;
+
+///
+/// Boot Error Record Table (BERT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      BootErrorRegionLength;
+  UINT64                      BootErrorRegion;
+} EFI_ACPI_6_1_BOOT_ERROR_RECORD_TABLE_HEADER;
+
+///
+/// BERT Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+
+///
+/// Boot Error Region Block Status Definition
+///
+typedef struct {
+  UINT32       UncorrectableErrorValid:1;
+  UINT32       CorrectableErrorValid:1;
+  UINT32       MultipleUncorrectableErrors:1;
+  UINT32       MultipleCorrectableErrors:1;
+  UINT32       ErrorDataEntryCount:10;
+  UINT32       Reserved:18;
+} EFI_ACPI_6_1_ERROR_BLOCK_STATUS;
+
+///
+/// Boot Error Region Definition
+///
+typedef struct {
+  EFI_ACPI_6_1_ERROR_BLOCK_STATUS              BlockStatus;
+  UINT32                                       RawDataOffset;
+  UINT32                                       RawDataLength;
+  UINT32                                       DataLength;
+  UINT32                                       ErrorSeverity;
+} EFI_ACPI_6_1_BOOT_ERROR_REGION_STRUCTURE;
+
+//
+// Boot Error Severity types
+//
+#define EFI_ACPI_6_1_ERROR_SEVERITY_CORRECTABLE  0x00
+#define EFI_ACPI_6_1_ERROR_SEVERITY_FATAL        0x01
+#define EFI_ACPI_6_1_ERROR_SEVERITY_CORRECTED    0x02
+#define EFI_ACPI_6_1_ERROR_SEVERITY_NONE         0x03
+
+///
+/// Generic Error Data Entry Definition
+///
+typedef struct {
+  UINT8    SectionType[16];
+  UINT32   ErrorSeverity;
+  UINT16   Revision;
+  UINT8    ValidationBits;
+  UINT8    Flags;
+  UINT32   ErrorDataLength;
+  UINT8    FruId[16];
+  UINT8    FruText[20];
+  UINT8    Timestamp[8];
+} EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
+
+///
+/// Generic Error Data Entry Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_REVISION  0x0300
+
+///
+/// HEST - Hardware Error Source Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      ErrorSourceCount;
+} EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
+
+///
+/// HEST Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+
+//
+// Error Source structure types.
+//
+#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION  0x00
+#define EFI_ACPI_6_1_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK  0x01
+#define EFI_ACPI_6_1_IA32_ARCHITECTURE_NMI_ERROR                0x02
+#define EFI_ACPI_6_1_PCI_EXPRESS_ROOT_PORT_AER                  0x06
+#define EFI_ACPI_6_1_PCI_EXPRESS_DEVICE_AER                     0x07
+#define EFI_ACPI_6_1_PCI_EXPRESS_BRIDGE_AER                     0x08
+#define EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR                     0x09
+#define EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_VERSION_2           0x0A
+
+//
+// Error Source structure flags.
+//
+#define EFI_ACPI_6_1_ERROR_SOURCE_FLAG_FIRMWARE_FIRST       (1 << 0)
+#define EFI_ACPI_6_1_ERROR_SOURCE_FLAG_GLOBAL               (1 << 1)
+
+///
+/// IA-32 Architecture Machine Check Exception Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT64  GlobalCapabilityInitData;
+  UINT64  GlobalControlInitData;
+  UINT8   NumberOfHardwareBanks;
+  UINT8   Reserved1[7];
+} EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure Definition
+///
+typedef struct {
+  UINT8   BankNumber;
+  UINT8   ClearStatusOnInitialization;
+  UINT8   StatusDataFormat;
+  UINT8   Reserved0;
+  UINT32  ControlRegisterMsrAddress;
+  UINT64  ControlInitData;
+  UINT32  StatusRegisterMsrAddress;
+  UINT32  AddressRegisterMsrAddress;
+  UINT32  MiscRegisterMsrAddress;
+} EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure MCA data format
+///
+#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32      0x00
+#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64   0x01
+#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64     0x02
+
+//
+// Hardware Error Notification types. All other values are reserved
+//
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_POLLED                0x00
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT    0x01
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT       0x02
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_SCI                   0x03
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_NMI                   0x04
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CMCI                  0x05
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_MCE                   0x06
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL           0x07
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA             0x08
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI             0x09
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GSIV                  0x0A
+
+///
+/// Hardware Error Notification Configuration Write Enable Structure Definition
+///
+typedef struct {
+  UINT16    Type:1;
+  UINT16    PollInterval:1;
+  UINT16    SwitchToPollingThresholdValue:1;
+  UINT16    SwitchToPollingThresholdWindow:1;
+  UINT16    ErrorThresholdValue:1;
+  UINT16    ErrorThresholdWindow:1;
+  UINT16    Reserved:10;
+} EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
+
+///
+/// Hardware Error Notification Structure Definition
+///
+typedef struct {
+  UINT8                                                                          Type;
+  UINT8                                                                          Length;
+  EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE  ConfigurationWriteEnable;
+  UINT32                                                                         PollInterval;
+  UINT32                                                                         Vector;
+  UINT32                                                                         SwitchToPollingThresholdValue;
+  UINT32                                                                         SwitchToPollingThresholdWindow;
+  UINT32                                                                         ErrorThresholdValue;
+  UINT32                                                                         ErrorThresholdWindow;
+} EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
+
+///
+/// IA-32 Architecture Corrected Machine Check Structure Definition
+///
+typedef struct {
+  UINT16                                                 Type;
+  UINT16                                                 SourceId;
+  UINT8                                                  Reserved0[2];
+  UINT8                                                  Flags;
+  UINT8                                                  Enabled;
+  UINT32                                                 NumberOfRecordsToPreAllocate;
+  UINT32                                                 MaxSectionsPerRecord;
+  EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE     NotificationStructure;
+  UINT8                                                  NumberOfHardwareBanks;
+  UINT8                                                  Reserved1[3];
+} EFI_ACPI_6_1_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// IA-32 Architecture NMI Error Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  MaxRawDataLength;
+} EFI_ACPI_6_1_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
+
+///
+/// PCI Express Root Port AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+  UINT32  RootErrorCommand;
+} EFI_ACPI_6_1_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
+
+///
+/// PCI Express Device AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_1_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
+
+///
+/// PCI Express Bridge AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+  UINT32  SecondaryUncorrectableErrorMask;
+  UINT32  SecondaryUncorrectableErrorSeverity;
+  UINT32  SecondaryAdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_1_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Structure Definition
+///
+typedef struct {
+  UINT16                                                 Type;
+  UINT16                                                 SourceId;
+  UINT16                                                 RelatedSourceId;
+  UINT8                                                  Flags;
+  UINT8                                                  Enabled;
+  UINT32                                                 NumberOfRecordsToPreAllocate;
+  UINT32                                                 MaxSectionsPerRecord;
+  UINT32                                                 MaxRawDataLength;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE                 ErrorStatusAddress;
+  EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE     NotificationStructure;
+  UINT32                                                 ErrorStatusBlockLength;
+} EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Version 2 Structure Definition
+///
+typedef struct {
+  UINT16                                                 Type;
+  UINT16                                                 SourceId;
+  UINT16                                                 RelatedSourceId;
+  UINT8                                                  Flags;
+  UINT8                                                  Enabled;
+  UINT32                                                 NumberOfRecordsToPreAllocate;
+  UINT32                                                 MaxSectionsPerRecord;
+  UINT32                                                 MaxRawDataLength;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE                 ErrorStatusAddress;
+  EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE     NotificationStructure;
+  UINT32                                                 ErrorStatusBlockLength;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE                 ReadAckRegister;
+  UINT64                                                 ReadAckPreserve;
+  UINT64                                                 ReadAckWrite;
+} EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;
+
+///
+/// Generic Error Status Definition
+///
+typedef struct {
+  EFI_ACPI_6_1_ERROR_BLOCK_STATUS              BlockStatus;
+  UINT32                                       RawDataOffset;
+  UINT32                                       RawDataLength;
+  UINT32                                       DataLength;
+  UINT32                                       ErrorSeverity;
+} EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE;
+
+///
+/// ERST - Error Record Serialization Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      SerializationHeaderSize;
+  UINT8                       Reserved0[4];
+  UINT32                      InstructionEntryCount;
+} EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
+
+///
+/// ERST Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+
+///
+/// ERST Serialization Actions
+///
+#define EFI_ACPI_6_1_ERST_BEGIN_WRITE_OPERATION                    0x00
+#define EFI_ACPI_6_1_ERST_BEGIN_READ_OPERATION                     0x01
+#define EFI_ACPI_6_1_ERST_BEGIN_CLEAR_OPERATION                    0x02
+#define EFI_ACPI_6_1_ERST_END_OPERATION                            0x03
+#define EFI_ACPI_6_1_ERST_SET_RECORD_OFFSET                        0x04
+#define EFI_ACPI_6_1_ERST_EXECUTE_OPERATION                        0x05
+#define EFI_ACPI_6_1_ERST_CHECK_BUSY_STATUS                        0x06
+#define EFI_ACPI_6_1_ERST_GET_COMMAND_STATUS                       0x07
+#define EFI_ACPI_6_1_ERST_GET_RECORD_IDENTIFIER                    0x08
+#define EFI_ACPI_6_1_ERST_SET_RECORD_IDENTIFIER                    0x09
+#define EFI_ACPI_6_1_ERST_GET_RECORD_COUNT                         0x0A
+#define EFI_ACPI_6_1_ERST_BEGIN_DUMMY_WRITE_OPERATION              0x0B
+#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE              0x0D
+#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH       0x0E
+#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES   0x0F
+#define EFI_ACPI_6_1_ERST_GET_EXECUTE_OPERATION_TIMINGS            0x10
+
+///
+/// ERST Action Command Status
+///
+#define EFI_ACPI_6_1_ERST_STATUS_SUCCESS                           0x00
+#define EFI_ACPI_6_1_ERST_STATUS_NOT_ENOUGH_SPACE                  0x01
+#define EFI_ACPI_6_1_ERST_STATUS_HARDWARE_NOT_AVAILABLE            0x02
+#define EFI_ACPI_6_1_ERST_STATUS_FAILED                            0x03
+#define EFI_ACPI_6_1_ERST_STATUS_RECORD_STORE_EMPTY                0x04
+#define EFI_ACPI_6_1_ERST_STATUS_RECORD_NOT_FOUND                  0x05
+
+///
+/// ERST Serialization Instructions
+///
+#define EFI_ACPI_6_1_ERST_READ_REGISTER                            0x00
+#define EFI_ACPI_6_1_ERST_READ_REGISTER_VALUE                      0x01
+#define EFI_ACPI_6_1_ERST_WRITE_REGISTER                           0x02
+#define EFI_ACPI_6_1_ERST_WRITE_REGISTER_VALUE                     0x03
+#define EFI_ACPI_6_1_ERST_NOOP                                     0x04
+#define EFI_ACPI_6_1_ERST_LOAD_VAR1                                0x05
+#define EFI_ACPI_6_1_ERST_LOAD_VAR2                                0x06
+#define EFI_ACPI_6_1_ERST_STORE_VAR1                               0x07
+#define EFI_ACPI_6_1_ERST_ADD                                      0x08
+#define EFI_ACPI_6_1_ERST_SUBTRACT                                 0x09
+#define EFI_ACPI_6_1_ERST_ADD_VALUE                                0x0A
+#define EFI_ACPI_6_1_ERST_SUBTRACT_VALUE                           0x0B
+#define EFI_ACPI_6_1_ERST_STALL                                    0x0C
+#define EFI_ACPI_6_1_ERST_STALL_WHILE_TRUE                         0x0D
+#define EFI_ACPI_6_1_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE            0x0E
+#define EFI_ACPI_6_1_ERST_GOTO                                     0x0F
+#define EFI_ACPI_6_1_ERST_SET_SRC_ADDRESS_BASE                     0x10
+#define EFI_ACPI_6_1_ERST_SET_DST_ADDRESS_BASE                     0x11
+#define EFI_ACPI_6_1_ERST_MOVE_DATA                                0x12
+
+///
+/// ERST Instruction Flags
+///
+#define EFI_ACPI_6_1_ERST_PRESERVE_REGISTER                        0x01
+
+///
+/// ERST Serialization Instruction Entry
+///
+typedef struct {
+  UINT8                                    SerializationAction;
+  UINT8                                    Instruction;
+  UINT8                                    Flags;
+  UINT8                                    Reserved0;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE   RegisterRegion;
+  UINT64                                   Value;
+  UINT64                                   Mask;
+} EFI_ACPI_6_1_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ - Error Injection Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      InjectionHeaderSize;
+  UINT8                       InjectionFlags;
+  UINT8                       Reserved0[3];
+  UINT32                      InjectionEntryCount;
+} EFI_ACPI_6_1_ERROR_INJECTION_TABLE_HEADER;
+
+///
+/// EINJ Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_ERROR_INJECTION_TABLE_REVISION 0x01
+
+///
+/// EINJ Error Injection Actions
+///
+#define EFI_ACPI_6_1_EINJ_BEGIN_INJECTION_OPERATION                0x00
+#define EFI_ACPI_6_1_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE           0x01
+#define EFI_ACPI_6_1_EINJ_SET_ERROR_TYPE                           0x02
+#define EFI_ACPI_6_1_EINJ_GET_ERROR_TYPE                           0x03
+#define EFI_ACPI_6_1_EINJ_END_OPERATION                            0x04
+#define EFI_ACPI_6_1_EINJ_EXECUTE_OPERATION                        0x05
+#define EFI_ACPI_6_1_EINJ_CHECK_BUSY_STATUS                        0x06
+#define EFI_ACPI_6_1_EINJ_GET_COMMAND_STATUS                       0x07
+#define EFI_ACPI_6_1_EINJ_TRIGGER_ERROR                            0xFF
+
+///
+/// EINJ Action Command Status
+///
+#define EFI_ACPI_6_1_EINJ_STATUS_SUCCESS                           0x00
+#define EFI_ACPI_6_1_EINJ_STATUS_UNKNOWN_FAILURE                   0x01
+#define EFI_ACPI_6_1_EINJ_STATUS_INVALID_ACCESS                    0x02
+
+///
+/// EINJ Error Type Definition
+///
+#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_CORRECTABLE                 (1 << 0)
+#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL      (1 << 1)
+#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL         (1 << 2)
+#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_CORRECTABLE                    (1 << 3)
+#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL         (1 << 4)
+#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL            (1 << 5)
+#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE               (1 << 6)
+#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL    (1 << 7)
+#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL       (1 << 8)
+#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_CORRECTABLE                  (1 << 9)
+#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL       (1 << 10)
+#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL          (1 << 11)
+
+///
+/// EINJ Injection Instructions
+///
+#define EFI_ACPI_6_1_EINJ_READ_REGISTER                            0x00
+#define EFI_ACPI_6_1_EINJ_READ_REGISTER_VALUE                      0x01
+#define EFI_ACPI_6_1_EINJ_WRITE_REGISTER                           0x02
+#define EFI_ACPI_6_1_EINJ_WRITE_REGISTER_VALUE                     0x03
+#define EFI_ACPI_6_1_EINJ_NOOP                                     0x04
+
+///
+/// EINJ Instruction Flags
+///
+#define EFI_ACPI_6_1_EINJ_PRESERVE_REGISTER                        0x01
+
+///
+/// EINJ Injection Instruction Entry
+///
+typedef struct {
+  UINT8                                    InjectionAction;
+  UINT8                                    Instruction;
+  UINT8                                    Flags;
+  UINT8                                    Reserved0;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE   RegisterRegion;
+  UINT64                                   Value;
+  UINT64                                   Mask;
+} EFI_ACPI_6_1_EINJ_INJECTION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ Trigger Action Table
+///
+typedef struct {
+  UINT32  HeaderSize;
+  UINT32  Revision;
+  UINT32  TableSize;
+  UINT32  EntryCount;
+} EFI_ACPI_6_1_EINJ_TRIGGER_ACTION_TABLE;
+
+///
+/// Platform Communications Channel Table (PCCT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Flags;
+  UINT64                      Reserved;
+} EFI_ACPI_6_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
+
+///
+/// PCCT Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01
+
+///
+/// PCCT Global Flags
+///
+#define EFI_ACPI_6_1_PCCT_FLAGS_SCI_DOORBELL                      BIT0
+
+//
+// PCCT Subspace type
+//
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_GENERIC                         0x00
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS     0x01
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS     0x02
+
+///
+/// PCC Subspace Structure Header
+///
+typedef struct {
+  UINT8        Type;
+  UINT8        Length;
+} EFI_ACPI_6_1_PCCT_SUBSPACE_HEADER;
+
+///
+/// Generic Communications Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT8                                    Reserved[6];
+  UINT64                                   BaseAddress;
+  UINT64                                   AddressLength;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT16                                   MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_1_PCCT_SUBSPACE_GENERIC;
+
+///
+/// Generic Communications Channel Shared Memory Region
+///
+
+typedef struct {
+  UINT8                                    Command;
+  UINT8                                    Reserved:7;
+  UINT8                                    GenerateSci:1;
+} EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
+
+typedef struct {
+  UINT8                                    CommandComplete:1;
+  UINT8                                    SciDoorbell:1;
+  UINT8                                    Error:1;
+  UINT8                                    PlatformNotification:1;  
+  UINT8                                    Reserved:4;
+  UINT8                                    Reserved1;
+} EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
+
+typedef struct {
+  UINT32                                                    Signature;
+  EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND    Command;
+  EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS     Status;
+} EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
+
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_POLARITY    BIT0
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_MODE        BIT1
+
+///
+/// Type 1 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT32                                   DoorbellInterrupt;
+  UINT8                                    DoorbellInterruptFlags;
+  UINT8                                    Reserved;
+  UINT64                                   BaseAddress;
+  UINT64                                   AddressLength;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT16                                   MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_1_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 2 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT32                                   DoorbellInterrupt;
+  UINT8                                    DoorbellInterruptFlags;
+  UINT8                                    Reserved;
+  UINT64                                   BaseAddress;
+  UINT64                                   AddressLength;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT16                                   MinimumRequestTurnaroundTime;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE   DoorbellAckRegister;
+  UINT64                                   DoorbellAckPreserve;
+  UINT64                                   DoorbellAckWrite;
+} EFI_ACPI_6_1_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') 
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "BERT" Boot Error Record Table
+///
+#define EFI_ACPI_6_1_BOOT_ERROR_RECORD_TABLE_SIGNATURE  SIGNATURE_32('B', 'E', 'R', 'T')
+
+///
+/// "BGRT" Boot Graphics Resource Table
+///
+#define EFI_ACPI_6_1_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('B', 'G', 'R', 'T')
+
+///
+/// "CPEP" Corrected Platform Error Polling Table
+///
+#define EFI_ACPI_6_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE  SIGNATURE_32('C', 'P', 'E', 'P')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_6_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_6_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE  SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "EINJ" Error Injection Table
+///
+#define EFI_ACPI_6_1_ERROR_INJECTION_TABLE_SIGNATURE  SIGNATURE_32('E', 'I', 'N', 'J')
+
+///
+/// "ERST" Error Record Serialization Table
+///
+#define EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE  SIGNATURE_32('E', 'R', 'S', 'T')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "FPDT" Firmware Performance Data Table
+///
+#define EFI_ACPI_6_1_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE  SIGNATURE_32('F', 'P', 'D', 'T')
+
+///
+/// "GTDT" Generic Timer Description Table
+///
+#define EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('G', 'T', 'D', 'T')
+
+///
+/// "HEST" Hardware Error Source Table
+///
+#define EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE  SIGNATURE_32('H', 'E', 'S', 'T')
+
+///
+/// "MPST" Memory Power State Table
+///
+#define EFI_ACPI_6_1_MEMORY_POWER_STATE_TABLE_SIGNATURE  SIGNATURE_32('M', 'P', 'S', 'T')
+
+///
+/// "MSCT" Maximum System Characteristics Table
+///
+#define EFI_ACPI_6_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE  SIGNATURE_32('M', 'S', 'C', 'T')
+
+///
+/// "NFIT" NVDIMM Firmware Interface Table
+///
+#define EFI_ACPI_6_1_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE  SIGNATURE_32('N', 'F', 'I', 'T')
+
+///
+/// "PMTT" Platform Memory Topology Table
+///
+#define EFI_ACPI_6_1_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE  SIGNATURE_32('P', 'M', 'T', 'T')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_6_1_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RASF" ACPI RAS Feature Table
+///
+#define EFI_ACPI_6_1_ACPI_RAS_FEATURE_TABLE_SIGNATURE  SIGNATURE_32('R', 'A', 'S', 'F')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_6_1_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_6_1_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SRAT" System Resource Affinity Table
+///
+#define EFI_ACPI_6_1_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE  SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_6_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_6_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_6_1_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE  SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "CSRT" MS Core System Resource Table
+///
+#define EFI_ACPI_6_1_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('C', 'S', 'R', 'T')
+
+///
+/// "DBG2" MS Debug Port 2 Spec
+///
+#define EFI_ACPI_6_1_DEBUG_PORT_2_TABLE_SIGNATURE  SIGNATURE_32('D', 'B', 'G', '2')
+
+///
+/// "DBGP" MS Debug Port Spec
+///
+#define EFI_ACPI_6_1_DEBUG_PORT_TABLE_SIGNATURE  SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "DMAR" DMA Remapping Table
+///
+#define EFI_ACPI_6_1_DMA_REMAPPING_TABLE_SIGNATURE  SIGNATURE_32('D', 'M', 'A', 'R')
+
+///
+/// "DRTM" Dynamic Root of Trust for Measurement Table
+///
+#define EFI_ACPI_6_1_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE  SIGNATURE_32('D', 'R', 'T', 'M')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_6_1_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "HPET" IA-PC High Precision Event Timer Table
+///
+#define EFI_ACPI_6_1_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE  SIGNATURE_32('H', 'P', 'E', 'T')
+
+///
+/// "iBFT" iSCSI Boot Firmware Table
+///
+#define EFI_ACPI_6_1_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE  SIGNATURE_32('i', 'B', 'F', 'T')
+
+///
+/// "IORT" I/O Remapping Table
+///
+#define EFI_ACPI_6_1_IO_REMAPPING_TABLE_SIGNATURE  SIGNATURE_32('I', 'O', 'R', 'T')
+
+///
+/// "IVRS" I/O Virtualization Reporting Structure
+///
+#define EFI_ACPI_6_1_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE  SIGNATURE_32('I', 'V', 'R', 'S')
+
+///
+/// "LPIT" Low Power Idle Table
+///
+#define EFI_ACPI_6_1_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE  SIGNATURE_32('L', 'P', 'I', 'T')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('M', 'C', 'F', 'G')
+
+///
+/// "MCHI" Management Controller Host Interface Table
+///
+#define EFI_ACPI_6_1_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('M', 'C', 'H', 'I')
+
+///
+/// "MSDM" MS Data Management Table
+///
+#define EFI_ACPI_6_1_DATA_MANAGEMENT_TABLE_SIGNATURE  SIGNATURE_32('M', 'S', 'D', 'M')
+
+///
+/// "SLIC" MS Software Licensing Table Specification
+///
+#define EFI_ACPI_6_1_SOFTWARE_LICENSING_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'C')
+
+///
+/// "SPCR" Serial Port Concole Redirection Table
+///
+#define EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_6_1_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "STAO" _STA Override Table
+///
+#define EFI_ACPI_6_1_STA_OVERRIDE_TABLE_SIGNATURE  SIGNATURE_32('S', 'T', 'A', 'O')
+
+///
+/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+///
+#define EFI_ACPI_6_1_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE  SIGNATURE_32('T', 'C', 'P', 'A')
+
+///
+/// "TPM2" Trusted Computing Platform 1 Table
+///
+#define EFI_ACPI_6_1_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE  SIGNATURE_32('T', 'P', 'M', '2')
+
+///
+/// "UEFI" UEFI ACPI Data Table
+///
+#define EFI_ACPI_6_1_UEFI_ACPI_DATA_TABLE_SIGNATURE  SIGNATURE_32('U', 'E', 'F', 'I')
+
+///
+/// "WAET" Windows ACPI Emulated Devices Table
+///
+#define EFI_ACPI_6_1_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE  SIGNATURE_32('W', 'A', 'E', 'T')
+
+///
+/// "WDAT" Watchdog Action Table
+///
+#define EFI_ACPI_6_1_WATCHDOG_ACTION_TABLE_SIGNATURE  SIGNATURE_32('W', 'D', 'A', 'T')
+
+///
+/// "WDRT" Watchdog Resource Table
+///
+#define EFI_ACPI_6_1_WATCHDOG_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('W', 'D', 'R', 'T')
+
+///
+/// "WPBT" MS Platform Binary Table
+///
+#define EFI_ACPI_6_1_PLATFORM_BINARY_TABLE_SIGNATURE  SIGNATURE_32('W', 'P', 'B', 'T')
+
+///
+/// "XENV" Xen Project Table
+///
+#define EFI_ACPI_6_1_XEN_PROJECT_TABLE_SIGNATURE  SIGNATURE_32('X', 'E', 'N', 'V')
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi62.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi62.h
new file mode 100644
index 0000000000..9ddf1590c2
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi62.h
@@ -0,0 +1,2942 @@
+/** @file
+  ACPI 6.2 definitions from the ACPI Specification Revision 6.2 May, 2017.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#ifndef _ACPI_6_2_H_
+#define _ACPI_6_2_H_
+
+#include <IndustryStandard/Acpi61.h>
+
+//
+// Large Item Descriptor Name
+//
+#define ACPI_LARGE_PIN_FUNCTION_DESCRIPTOR_NAME              0x0D
+#define ACPI_LARGE_PIN_CONFIGURATION_DESCRIPTOR_NAME         0x0F
+#define ACPI_LARGE_PIN_GROUP_DESCRIPTOR_NAME                 0x10
+#define ACPI_LARGE_PIN_GROUP_FUNCTION_DESCRIPTOR_NAME        0x11
+#define ACPI_LARGE_PIN_GROUP_CONFIGURATION_DESCRIPTOR_NAME   0x12
+
+//
+// Large Item Descriptor Value
+//
+#define ACPI_PIN_FUNCTION_DESCRIPTOR                         0x8D
+#define ACPI_PIN_CONFIGURATION_DESCRIPTOR                    0x8F
+#define ACPI_PIN_GROUP_DESCRIPTOR                            0x90
+#define ACPI_PIN_GROUP_FUNCTION_DESCRIPTOR                   0x91
+#define ACPI_PIN_GROUP_CONFIGURATION_DESCRIPTOR              0x92
+
+#pragma pack(1)
+
+///
+/// Pin Function Descriptor
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         RevisionId;
+  UINT16                        Flags;
+  UINT8                         PinPullConfiguration;
+  UINT16                        FunctionNumber;
+  UINT16                        PinTableOffset;
+  UINT8                         ResourceSourceIndex;
+  UINT16                        ResourceSourceNameOffset;
+  UINT16                        VendorDataOffset;
+  UINT16                        VendorDataLength;
+} EFI_ACPI_PIN_FUNCTION_DESCRIPTOR;
+
+///
+/// Pin Configuration Descriptor
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         RevisionId;
+  UINT16                        Flags;
+  UINT8                         PinConfigurationType;
+  UINT32                        PinConfigurationValue;
+  UINT16                        PinTableOffset;
+  UINT8                         ResourceSourceIndex;
+  UINT16                        ResourceSourceNameOffset;
+  UINT16                        VendorDataOffset;
+  UINT16                        VendorDataLength;
+} EFI_ACPI_PIN_CONFIGURATION_DESCRIPTOR;
+
+///
+/// Pin Group Descriptor
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         RevisionId;
+  UINT16                        Flags;
+  UINT16                        PinTableOffset;
+  UINT16                        ResourceLabelOffset;
+  UINT16                        VendorDataOffset;
+  UINT16                        VendorDataLength;
+} EFI_ACPI_PIN_GROUP_DESCRIPTOR;
+
+///
+/// Pin Group Function Descriptor
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         RevisionId;
+  UINT16                        Flags;
+  UINT16                        FunctionNumber;
+  UINT8                         ResourceSourceIndex;
+  UINT16                        ResourceSourceNameOffset;
+  UINT16                        ResourceSourceLabelOffset;
+  UINT16                        VendorDataOffset;
+  UINT16                        VendorDataLength;
+} EFI_ACPI_PIN_GROUP_FUNCTION_DESCRIPTOR;
+
+///
+/// Pin Group Configuration Descriptor
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         RevisionId;
+  UINT16                        Flags;
+  UINT8                         PinConfigurationType;
+  UINT32                        PinConfigurationValue;
+  UINT8                         ResourceSourceIndex;
+  UINT16                        ResourceSourceNameOffset;
+  UINT16                        ResourceSourceLabelOffset;
+  UINT16                        VendorDataOffset;
+  UINT16                        VendorDataLength;
+} EFI_ACPI_PIN_GROUP_CONFIGURATION_DESCRIPTOR;
+
+#pragma pack()
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 6.2 Generic Address Space definition
+///
+typedef struct {
+  UINT8   AddressSpaceId;
+  UINT8   RegisterBitWidth;
+  UINT8   RegisterBitOffset;
+  UINT8   AccessSize;
+  UINT64  Address;
+} EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_6_2_SYSTEM_MEMORY              0
+#define EFI_ACPI_6_2_SYSTEM_IO                  1
+#define EFI_ACPI_6_2_PCI_CONFIGURATION_SPACE    2
+#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER        3
+#define EFI_ACPI_6_2_SMBUS                      4
+#define EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL  0x0A
+#define EFI_ACPI_6_2_FUNCTIONAL_FIXED_HARDWARE       0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_6_2_UNDEFINED  0
+#define EFI_ACPI_6_2_BYTE       1
+#define EFI_ACPI_6_2_WORD       2
+#define EFI_ACPI_6_2_DWORD      3
+#define EFI_ACPI_6_2_QWORD      4
+
+//
+// ACPI 6.2 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+  UINT64  Signature;
+  UINT8   Checksum;
+  UINT8   OemId[6];
+  UINT8   Revision;
+  UINT32  RsdtAddress;
+  UINT32  Length;
+  UINT64  XsdtAddress;
+  UINT8   ExtendedChecksum;
+  UINT8   Reserved[3];
+} EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02  ///< ACPISpec (Revision 6.2) says current value is 2
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+} EFI_ACPI_6_2_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  UINT32                                  FirmwareCtrl;
+  UINT32                                  Dsdt;
+  UINT8                                   Reserved0;
+  UINT8                                   PreferredPmProfile;
+  UINT16                                  SciInt;
+  UINT32                                  SmiCmd;
+  UINT8                                   AcpiEnable;
+  UINT8                                   AcpiDisable;
+  UINT8                                   S4BiosReq;
+  UINT8                                   PstateCnt;
+  UINT32                                  Pm1aEvtBlk;
+  UINT32                                  Pm1bEvtBlk;
+  UINT32                                  Pm1aCntBlk;
+  UINT32                                  Pm1bCntBlk;
+  UINT32                                  Pm2CntBlk;
+  UINT32                                  PmTmrBlk;
+  UINT32                                  Gpe0Blk;
+  UINT32                                  Gpe1Blk;
+  UINT8                                   Pm1EvtLen;
+  UINT8                                   Pm1CntLen;
+  UINT8                                   Pm2CntLen;
+  UINT8                                   PmTmrLen;
+  UINT8                                   Gpe0BlkLen;
+  UINT8                                   Gpe1BlkLen;
+  UINT8                                   Gpe1Base;
+  UINT8                                   CstCnt;
+  UINT16                                  PLvl2Lat;
+  UINT16                                  PLvl3Lat;
+  UINT16                                  FlushSize;
+  UINT16                                  FlushStride;
+  UINT8                                   DutyOffset;
+  UINT8                                   DutyWidth;
+  UINT8                                   DayAlrm;
+  UINT8                                   MonAlrm;
+  UINT8                                   Century;
+  UINT16                                  IaPcBootArch;
+  UINT8                                   Reserved1;
+  UINT32                                  Flags;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  ResetReg;
+  UINT8                                   ResetValue;
+  UINT16                                  ArmBootArch;
+  UINT8                                   MinorVersion;
+  UINT64                                  XFirmwareCtrl;
+  UINT64                                  XDsdt;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  SleepControlReg;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  SleepStatusReg;
+  UINT64                                  HypervisorVendorIdentity;
+} EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION  0x06
+#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION  0x02
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_6_2_PM_PROFILE_UNSPECIFIED         0
+#define EFI_ACPI_6_2_PM_PROFILE_DESKTOP             1
+#define EFI_ACPI_6_2_PM_PROFILE_MOBILE              2
+#define EFI_ACPI_6_2_PM_PROFILE_WORKSTATION         3
+#define EFI_ACPI_6_2_PM_PROFILE_ENTERPRISE_SERVER   4
+#define EFI_ACPI_6_2_PM_PROFILE_SOHO_SERVER         5
+#define EFI_ACPI_6_2_PM_PROFILE_APPLIANCE_PC        6
+#define EFI_ACPI_6_2_PM_PROFILE_PERFORMANCE_SERVER  7
+#define EFI_ACPI_6_2_PM_PROFILE_TABLET              8
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_2_LEGACY_DEVICES              BIT0
+#define EFI_ACPI_6_2_8042                        BIT1
+#define EFI_ACPI_6_2_VGA_NOT_PRESENT             BIT2
+#define EFI_ACPI_6_2_MSI_NOT_SUPPORTED           BIT3
+#define EFI_ACPI_6_2_PCIE_ASPM_CONTROLS          BIT4
+#define EFI_ACPI_6_2_CMOS_RTC_NOT_PRESENT        BIT5
+
+//
+// Fixed ACPI Description Table Arm Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_2_ARM_PSCI_COMPLIANT              BIT0
+#define EFI_ACPI_6_2_ARM_PSCI_USE_HVC                BIT1
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_2_WBINVD                                 BIT0
+#define EFI_ACPI_6_2_WBINVD_FLUSH                           BIT1
+#define EFI_ACPI_6_2_PROC_C1                                BIT2
+#define EFI_ACPI_6_2_P_LVL2_UP                              BIT3
+#define EFI_ACPI_6_2_PWR_BUTTON                             BIT4
+#define EFI_ACPI_6_2_SLP_BUTTON                             BIT5
+#define EFI_ACPI_6_2_FIX_RTC                                BIT6
+#define EFI_ACPI_6_2_RTC_S4                                 BIT7
+#define EFI_ACPI_6_2_TMR_VAL_EXT                            BIT8
+#define EFI_ACPI_6_2_DCK_CAP                                BIT9
+#define EFI_ACPI_6_2_RESET_REG_SUP                          BIT10
+#define EFI_ACPI_6_2_SEALED_CASE                            BIT11
+#define EFI_ACPI_6_2_HEADLESS                               BIT12
+#define EFI_ACPI_6_2_CPU_SW_SLP                             BIT13
+#define EFI_ACPI_6_2_PCI_EXP_WAK                            BIT14
+#define EFI_ACPI_6_2_USE_PLATFORM_CLOCK                     BIT15
+#define EFI_ACPI_6_2_S4_RTC_STS_VALID                       BIT16
+#define EFI_ACPI_6_2_REMOTE_POWER_ON_CAPABLE                BIT17
+#define EFI_ACPI_6_2_FORCE_APIC_CLUSTER_MODEL               BIT18
+#define EFI_ACPI_6_2_FORCE_APIC_PHYSICAL_DESTINATION_MODE   BIT19
+#define EFI_ACPI_6_2_HW_REDUCED_ACPI                        BIT20
+#define EFI_ACPI_6_2_LOW_POWER_S0_IDLE_CAPABLE              BIT21
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+  UINT32  HardwareSignature;
+  UINT32  FirmwareWakingVector;
+  UINT32  GlobalLock;
+  UINT32  Flags;
+  UINT64  XFirmwareWakingVector;
+  UINT8   Version;
+  UINT8   Reserved0[3];
+  UINT32  OspmFlags;
+  UINT8   Reserved1[24];
+} EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION  0x02
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_2_S4BIOS_F                     BIT0
+#define EFI_ACPI_6_2_64BIT_WAKE_SUPPORTED_F       BIT1
+
+///
+/// OSPM Enabled Firmware Control Structure Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_2_OSPM_64BIT_WAKE_F            BIT0
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
+//
+#define EFI_ACPI_6_2_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION   0x02
+#define EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION        0x02
+
+///
+/// Multiple APIC Description Table header definition.  The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      LocalApicAddress;
+  UINT32                      Flags;
+} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_2_PCAT_COMPAT         BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x0D and 0x7F are reserved and
+// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.
+//
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC           0x00
+#define EFI_ACPI_6_2_IO_APIC                        0x01
+#define EFI_ACPI_6_2_INTERRUPT_SOURCE_OVERRIDE      0x02
+#define EFI_ACPI_6_2_NON_MASKABLE_INTERRUPT_SOURCE  0x03
+#define EFI_ACPI_6_2_LOCAL_APIC_NMI                 0x04
+#define EFI_ACPI_6_2_LOCAL_APIC_ADDRESS_OVERRIDE    0x05
+#define EFI_ACPI_6_2_IO_SAPIC                       0x06
+#define EFI_ACPI_6_2_LOCAL_SAPIC                    0x07
+#define EFI_ACPI_6_2_PLATFORM_INTERRUPT_SOURCES     0x08
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC         0x09
+#define EFI_ACPI_6_2_LOCAL_X2APIC_NMI               0x0A
+#define EFI_ACPI_6_2_GIC                            0x0B
+#define EFI_ACPI_6_2_GICD                           0x0C
+#define EFI_ACPI_6_2_GIC_MSI_FRAME                  0x0D
+#define EFI_ACPI_6_2_GICR                           0x0E
+#define EFI_ACPI_6_2_GIC_ITS                        0x0F
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorUid;
+  UINT8   ApicId;
+  UINT32  Flags;
+} EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_LOCAL_APIC_ENABLED        BIT0
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  IoApicAddress;
+  UINT32  GlobalSystemInterruptBase;
+} EFI_ACPI_6_2_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Bus;
+  UINT8   Source;
+  UINT32  GlobalSystemInterrupt;
+  UINT16  Flags;
+} EFI_ACPI_6_2_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT8   InterruptType;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT8   IoSapicVector;
+  UINT32  GlobalSystemInterrupt;
+  UINT32  PlatformInterruptSourceFlags;
+  UINT8   CpeiProcessorOverride;
+  UINT8   Reserved[31];
+} EFI_ACPI_6_2_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_2_POLARITY      (3 << 0)
+#define EFI_ACPI_6_2_TRIGGER_MODE  (3 << 2)
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT32  GlobalSystemInterrupt;
+} EFI_ACPI_6_2_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorUid;
+  UINT16  Flags;
+  UINT8   LocalApicLint;
+} EFI_ACPI_6_2_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT64  LocalApicAddress;
+} EFI_ACPI_6_2_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  GlobalSystemInterruptBase;
+  UINT64  IoSapicAddress;
+} EFI_ACPI_6_2_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT8   LocalSapicId;
+  UINT8   LocalSapicEid;
+  UINT8   Reserved[3];
+  UINT32  Flags;
+  UINT32  ACPIProcessorUIDValue;
+} EFI_ACPI_6_2_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT8   InterruptType;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT8   IoSapicVector;
+  UINT32  GlobalSystemInterrupt;
+  UINT32  PlatformInterruptSourceFlags;
+} EFI_ACPI_6_2_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Platform Interrupt Source Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_2_CPEI_PROCESSOR_OVERRIDE          BIT0
+
+///
+/// Processor Local x2APIC Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Reserved[2];
+  UINT32  X2ApicId;
+  UINT32  Flags;
+  UINT32  AcpiProcessorUid;
+} EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
+
+///
+/// Local x2APIC NMI Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT32  AcpiProcessorUid;
+  UINT8   LocalX2ApicLint;
+  UINT8   Reserved[3];
+} EFI_ACPI_6_2_LOCAL_X2APIC_NMI_STRUCTURE;
+
+///
+/// GIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT32  CPUInterfaceNumber;
+  UINT32  AcpiProcessorUid;
+  UINT32  Flags;
+  UINT32  ParkingProtocolVersion;
+  UINT32  PerformanceInterruptGsiv;
+  UINT64  ParkedAddress;
+  UINT64  PhysicalBaseAddress;
+  UINT64  GICV;
+  UINT64  GICH;
+  UINT32  VGICMaintenanceInterrupt;
+  UINT64  GICRBaseAddress;
+  UINT64  MPIDR;
+  UINT8   ProcessorPowerEfficiencyClass;
+  UINT8   Reserved2[3];
+} EFI_ACPI_6_2_GIC_STRUCTURE;
+
+///
+/// GIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GIC_ENABLED                              BIT0
+#define EFI_ACPI_6_2_PERFORMANCE_INTERRUPT_MODEL              BIT1
+#define EFI_ACPI_6_2_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS    BIT2
+
+///
+/// GIC Distributor Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved1;
+  UINT32  GicId;
+  UINT64  PhysicalBaseAddress;
+  UINT32  SystemVectorBase;
+  UINT8   GicVersion;
+  UINT8   Reserved2[3];
+} EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE;
+
+///
+/// GIC Version
+///
+#define EFI_ACPI_6_2_GIC_V1                                   0x01
+#define EFI_ACPI_6_2_GIC_V2                                   0x02
+#define EFI_ACPI_6_2_GIC_V3                                   0x03
+#define EFI_ACPI_6_2_GIC_V4                                   0x04
+
+///
+/// GIC MSI Frame Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved1;
+  UINT32  GicMsiFrameId;
+  UINT64  PhysicalBaseAddress;
+  UINT32  Flags;
+  UINT16  SPICount;
+  UINT16  SPIBase;
+} EFI_ACPI_6_2_GIC_MSI_FRAME_STRUCTURE;
+
+///
+/// GIC MSI Frame Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_SPI_COUNT_BASE_SELECT                    BIT0
+
+///
+/// GICR Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT64  DiscoveryRangeBaseAddress;
+  UINT32  DiscoveryRangeLength;
+} EFI_ACPI_6_2_GICR_STRUCTURE;
+
+///
+/// GIC Interrupt Translation Service Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT32  GicItsId;
+  UINT64  PhysicalBaseAddress;
+  UINT32  Reserved2;
+} EFI_ACPI_6_2_GIC_ITS_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      WarningEnergyLevel;
+  UINT32                      LowEnergyLevel;
+  UINT32                      CriticalEnergyLevel;
+} EFI_ACPI_6_2_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  EcControl;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  EcData;
+  UINT32                                  Uid;
+  UINT8                                   GpeBit;
+} EFI_ACPI_6_2_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION  0x01
+
+///
+/// System Resource Affinity Table (SRAT).  The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Reserved1;  ///< Must be set to 1
+  UINT64                      Reserved2;
+} EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+///
+/// SRAT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION  0x03
+
+//
+// SRAT structure types.
+// All other values between 0x05 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY  0x00
+#define EFI_ACPI_6_2_MEMORY_AFFINITY                      0x01
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_AFFINITY      0x02
+#define EFI_ACPI_6_2_GICC_AFFINITY                        0x03
+#define EFI_ACPI_6_2_GIC_ITS_AFFINITY                     0x04
+
+///
+/// Processor Local APIC/SAPIC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   ProximityDomain7To0;
+  UINT8   ApicId;
+  UINT32  Flags;
+  UINT8   LocalSapicEid;
+  UINT8   ProximityDomain31To8[3];
+  UINT32  ClockDomain;
+} EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+///
+/// Local APIC/SAPIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+///
+/// Memory Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT32  ProximityDomain;
+  UINT16  Reserved1;
+  UINT32  AddressBaseLow;
+  UINT32  AddressBaseHigh;
+  UINT32  LengthLow;
+  UINT32  LengthHigh;
+  UINT32  Reserved2;
+  UINT32  Flags;
+  UINT64  Reserved3;
+} EFI_ACPI_6_2_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags.  All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_6_2_MEMORY_ENABLED       (1 << 0)
+#define EFI_ACPI_6_2_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_6_2_MEMORY_NONVOLATILE   (1 << 2)
+
+///
+/// Processor Local x2APIC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Reserved1[2];
+  UINT32  ProximityDomain;
+  UINT32  X2ApicId;
+  UINT32  Flags;
+  UINT32  ClockDomain;
+  UINT8   Reserved2[4];
+} EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT32  ProximityDomain;
+  UINT32  AcpiProcessorUid;
+  UINT32  Flags;
+  UINT32  ClockDomain;
+} EFI_ACPI_6_2_GICC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GICC_ENABLED (1 << 0)
+
+///
+/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT32  ProximityDomain;
+  UINT8   Reserved[2];
+  UINT32  ItsId;
+} EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE;
+
+///
+/// System Locality Distance Information Table (SLIT).
+/// The rest of the table is a matrix.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT64                      NumberOfSystemLocalities;
+} EFI_ACPI_6_2_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+///
+/// SLIT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION  0x01
+
+///
+/// Corrected Platform Error Polling Table (CPEP)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       Reserved[8];
+} EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
+
+///
+/// CPEP Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+
+//
+// CPEP processor structure types.
+//
+#define EFI_ACPI_6_2_CPEP_PROCESSOR_APIC_SAPIC  0x00
+
+///
+/// Corrected Platform Error Polling Processor Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT32  PollingInterval;
+} EFI_ACPI_6_2_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
+
+///
+/// Maximum System Characteristics Table (MSCT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      OffsetProxDomInfo;
+  UINT32                      MaximumNumberOfProximityDomains;
+  UINT32                      MaximumNumberOfClockDomains;
+  UINT64                      MaximumPhysicalAddress;
+} EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
+
+///
+/// MSCT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+
+///
+/// Maximum Proximity Domain Information Structure Definition
+///
+typedef struct {
+  UINT8   Revision;
+  UINT8   Length;
+  UINT32  ProximityDomainRangeLow;
+  UINT32  ProximityDomainRangeHigh;
+  UINT32  MaximumProcessorCapacity;
+  UINT64  MaximumMemoryCapacity;
+} EFI_ACPI_6_2_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
+
+///
+/// ACPI RAS Feature Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       PlatformCommunicationChannelIdentifier[12];
+} EFI_ACPI_6_2_RAS_FEATURE_TABLE;
+
+///
+/// RASF Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_RAS_FEATURE_TABLE_REVISION 0x01
+
+///
+/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+  UINT32                      Signature;
+  UINT16                      Command;
+  UINT16                      Status;
+  UINT16                      Version;
+  UINT8                       RASCapabilities[16];
+  UINT8                       SetRASCapabilities[16];
+  UINT16                      NumberOfRASFParameterBlocks;
+  UINT32                      SetRASCapabilitiesStatus;
+} EFI_ACPI_6_2_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI RASF PCC command code
+///
+#define EFI_ACPI_6_2_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND  0x01
+
+///
+/// ACPI RASF Platform RAS Capabilities
+///
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED                         BIT0
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS            BIT2
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS    BIT3
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING         BIT4
+
+///
+/// ACPI RASF Parameter Block structure for PATROL_SCRUB
+///
+typedef struct {
+  UINT16                      Type;
+  UINT16                      Version;
+  UINT16                      Length;
+  UINT16                      PatrolScrubCommand;
+  UINT64                      RequestedAddressRange[2];
+  UINT64                      ActualAddressRange[2];
+  UINT16                      Flags;
+  UINT8                       RequestedSpeed;
+} EFI_ACPI_6_2_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
+
+///
+/// ACPI RASF Patrol Scrub command
+///
+#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS   0x01
+#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER   0x02
+#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER    0x03
+
+///
+/// Memory Power State Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       PlatformCommunicationChannelIdentifier;
+  UINT8                       Reserved[3];
+// Memory Power Node Structure
+// Memory Power State Characteristics
+} EFI_ACPI_6_2_MEMORY_POWER_STATUS_TABLE;
+
+///
+/// MPST Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+
+///
+/// MPST Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+  UINT32                      Signature;
+  UINT16                      Command;
+  UINT16                      Status;
+  UINT32                      MemoryPowerCommandRegister;
+  UINT32                      MemoryPowerStatusRegister;
+  UINT32                      PowerStateId;
+  UINT32                      MemoryPowerNodeId;
+  UINT64                      MemoryEnergyConsumed;
+  UINT64                      ExpectedAveragePowerComsuned;
+} EFI_ACPI_6_2_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI MPST PCC command code
+///
+#define EFI_ACPI_6_2_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND  0x03
+
+///
+/// ACPI MPST Memory Power command
+///
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE       0x01
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE       0x02
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED   0x03
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED   0x04
+
+///
+/// MPST Memory Power Node Table
+///
+typedef struct {
+  UINT8                                             PowerStateValue;
+  UINT8                                             PowerStateInformationIndex;
+} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE;
+
+typedef struct {
+  UINT8                                             Flag;
+  UINT8                                             Reserved;
+  UINT16                                            MemoryPowerNodeId;
+  UINT32                                            Length;
+  UINT64                                            AddressBase;
+  UINT64                                            AddressLength;
+  UINT32                                            NumberOfPowerStates;
+  UINT32                                            NumberOfPhysicalComponents;
+//EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE              MemoryPowerState[NumberOfPowerStates];
+//UINT16                                            PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+} EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE;
+
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE          0x01
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED   0x02
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE   0x04
+
+typedef struct {
+  UINT16                      MemoryPowerNodeCount;
+  UINT8                       Reserved[2];
+} EFI_ACPI_6_2_MPST_MEMORY_POWER_NODE_TABLE;
+
+///
+/// MPST Memory Power State Characteristics Table
+///
+typedef struct {
+  UINT8                                             PowerStateStructureID;
+  UINT8                                             Flag;
+  UINT16                                            Reserved;
+  UINT32                                            AveragePowerConsumedInMPS0;
+  UINT32                                            RelativePowerSavingToMPS0;
+  UINT64                                            ExitLatencyToMPS0;
+} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
+
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED              0x01
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY   0x02
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT    0x04
+
+typedef struct {
+  UINT16                      MemoryPowerStateCharacteristicsCount;
+  UINT8                       Reserved[2];
+} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
+
+///
+/// Memory Topology Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Reserved;
+} EFI_ACPI_6_2_MEMORY_TOPOLOGY_TABLE;
+
+///
+/// PMTT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
+
+///
+/// Common Memory Aggregator Device Structure.
+///
+typedef struct {
+  UINT8                       Type;
+  UINT8                       Reserved;
+  UINT16                      Length;
+  UINT16                      Flags;
+  UINT16                      Reserved1;
+} EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Memory Aggregator Device Type
+///
+#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET            0x1
+#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x2
+#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM              0x3
+
+///
+/// Socket Memory Aggregator Device Structure.
+///
+typedef struct {
+  EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  Header;
+  UINT16                                                       SocketIdentifier;
+  UINT16                                                       Reserved;
+//EFI_ACPI_6_2_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  MemoryController[];
+} EFI_ACPI_6_2_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// MemoryController Memory Aggregator Device Structure.
+///
+typedef struct {
+  EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  Header;
+  UINT32                                                       ReadLatency;
+  UINT32                                                       WriteLatency;
+  UINT32                                                       ReadBandwidth;
+  UINT32                                                       WriteBandwidth;
+  UINT16                                                       OptimalAccessUnit;
+  UINT16                                                       OptimalAccessAlignment;
+  UINT16                                                       Reserved;
+  UINT16                                                       NumberOfProximityDomains;
+//UINT32                                                       ProximityDomain[NumberOfProximityDomains];
+//EFI_ACPI_6_2_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE    PhysicalComponent[];
+} EFI_ACPI_6_2_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// DIMM Memory Aggregator Device Structure.
+///
+typedef struct {
+  EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  Header;
+  UINT16                                                       PhysicalComponentIdentifier;
+  UINT16                                                       Reserved;
+  UINT32                                                       SizeOfDimm;
+  UINT32                                                       SmbiosHandle;
+} EFI_ACPI_6_2_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Boot Graphics Resource Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  ///
+  /// 2-bytes (16 bit) version ID. This value must be 1.
+  ///
+  UINT16                      Version;
+  ///
+  /// 1-byte status field indicating current status about the table.
+  ///     Bits[7:1] = Reserved (must be zero)
+  ///     Bit [0] = Valid. A one indicates the boot image graphic is valid.
+  ///
+  UINT8                       Status;
+  ///
+  /// 1-byte enumerated type field indicating format of the image.
+  ///     0 = Bitmap
+  ///     1 - 255  Reserved (for future use)
+  ///
+  UINT8                       ImageType;
+  ///
+  /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
+  /// of the image bitmap.
+  ///
+  UINT64                      ImageAddress;
+  ///
+  /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
+  /// (X, Y) display offset of the top left corner of the boot image.
+  /// The top left corner of the display is at offset (0, 0).
+  ///
+  UINT32                      ImageOffsetX;
+  ///
+  /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
+  /// (X, Y) display offset of the top left corner of the boot image.
+  /// The top left corner of the display is at offset (0, 0).
+  ///
+  UINT32                      ImageOffsetY;
+} EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE;
+
+///
+/// BGRT Revision
+///
+#define EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+
+///
+/// BGRT Version
+///
+#define EFI_ACPI_6_2_BGRT_VERSION         0x01
+
+///
+/// BGRT Status
+///
+#define EFI_ACPI_6_2_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_6_2_BGRT_STATUS_DISPLAYED     0x01
+
+///
+/// BGRT Image Type
+///
+#define EFI_ACPI_6_2_BGRT_IMAGE_TYPE_BMP  0x00
+
+///
+/// FPDT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+
+///
+/// FPDT Performance Record Types
+///
+#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER      0x0000
+#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER     0x0001
+
+///
+/// FPDT Performance Record Revision
+///
+#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER  0x01
+#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+
+///
+/// FPDT Runtime Performance Record Types
+///
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME                0x0000
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND               0x0001
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT      0x0002
+
+///
+/// FPDT Runtime Performance Record Revision
+///
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME            0x01
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND           0x01
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT  0x02
+
+///
+/// FPDT Performance Record header
+///
+typedef struct {
+  UINT16           Type;
+  UINT8            Length;
+  UINT8            Revision;
+} EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER;
+
+///
+/// FPDT Performance Table header
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+} EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER;
+
+///
+/// FPDT Firmware Basic Boot Performance Pointer Record Structure
+///
+typedef struct {
+  EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  UINT32                                          Reserved;
+  ///
+  /// 64-bit processor-relative physical address of the Basic Boot Performance Table.
+  ///
+  UINT64                                          BootPerformanceTablePointer;
+} EFI_ACPI_6_2_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT S3 Performance Table Pointer Record Structure
+///
+typedef struct {
+  EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  UINT32                                          Reserved;
+  ///
+  /// 64-bit processor-relative physical address of the S3 Performance Table.
+  ///
+  UINT64                                          S3PerformanceTablePointer;
+} EFI_ACPI_6_2_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Record Structure
+///
+typedef struct {
+  EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  UINT32                                          Reserved;
+  ///
+  /// Timer value logged at the beginning of firmware image execution.
+  /// This may not always be zero or near zero.
+  ///
+  UINT64                                          ResetEnd;
+  ///
+  /// Timer value logged just prior to loading the OS boot loader into memory.
+  /// For non-UEFI compatible boots, this field must be zero.
+  ///
+  UINT64                                          OsLoaderLoadImageStart;
+  ///
+  /// Timer value logged just prior to launching the previously loaded OS boot loader image.
+  /// For non-UEFI compatible boots, the timer value logged will be just prior
+  /// to the INT 19h handler invocation.
+  ///
+  UINT64                                          OsLoaderStartImageStart;
+  ///
+  /// Timer value logged at the point when the OS loader calls the
+  /// ExitBootServices function for UEFI compatible firmware.
+  /// For non-UEFI compatible boots, this field must be zero.
+  ///
+  UINT64                                          ExitBootServicesEntry;
+  ///
+  /// Timer value logged at the point just prior towhen the OS loader gaining
+  /// control back from calls the ExitBootServices function for UEFI compatible firmware.
+  /// For non-UEFI compatible boots, this field must be zero.
+  ///
+  UINT64                                          ExitBootServicesExit;
+} EFI_ACPI_6_2_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Table signature
+///
+#define EFI_ACPI_6_2_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE  SIGNATURE_32('F', 'B', 'P', 'T')
+
+//
+// FPDT Firmware Basic Boot Performance Table
+//
+typedef struct {
+  EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER      Header;
+  //
+  // one or more Performance Records.
+  //
+} EFI_ACPI_6_2_FPDT_FIRMWARE_BASIC_BOOT_TABLE;
+
+///
+/// FPDT "S3PT" S3 Performance Table
+///
+#define EFI_ACPI_6_2_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE  SIGNATURE_32('S', '3', 'P', 'T')
+
+//
+// FPDT Firmware S3 Boot Performance Table
+//
+typedef struct {
+  EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER      Header;
+  //
+  // one or more Performance Records.
+  //
+} EFI_ACPI_6_2_FPDT_FIRMWARE_S3_BOOT_TABLE;
+
+///
+/// FPDT Basic S3 Resume Performance Record
+///
+typedef struct {
+  EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  ///
+  /// A count of the number of S3 resume cycles since the last full boot sequence.
+  ///
+  UINT32                                          ResumeCount;
+  ///
+  /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
+  /// OS waking vector. Only the most recent resume cycle's time is retained.
+  ///
+  UINT64                                          FullResume;
+  ///
+  /// Average timer value of all resume cycles logged since the last full boot
+  /// sequence, including the most recent resume.  Note that the entire log of
+  /// timer values does not need to be retained in order to calculate this average.
+  ///
+  UINT64                                          AverageResume;
+} EFI_ACPI_6_2_FPDT_S3_RESUME_RECORD;
+
+///
+/// FPDT Basic S3 Suspend Performance Record
+///
+typedef struct {
+  EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  ///
+  /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
+  /// Only the most recent suspend cycle's timer value is retained.
+  ///
+  UINT64                                          SuspendStart;
+  ///
+  /// Timer value recorded at the final firmware write to SLP_TYP (or other
+  /// mechanism) used to trigger hardware entry to S3.
+  /// Only the most recent suspend cycle's timer value is retained.
+  ///
+  UINT64                                          SuspendEnd;
+} EFI_ACPI_6_2_FPDT_S3_SUSPEND_RECORD;
+
+///
+/// Firmware Performance Record Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_RECORD_TABLE;
+
+///
+/// Generic Timer Description Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT64                      CntControlBasePhysicalAddress;
+  UINT32                      Reserved;
+  UINT32                      SecurePL1TimerGSIV;
+  UINT32                      SecurePL1TimerFlags;
+  UINT32                      NonSecurePL1TimerGSIV;
+  UINT32                      NonSecurePL1TimerFlags;
+  UINT32                      VirtualTimerGSIV;
+  UINT32                      VirtualTimerFlags;
+  UINT32                      NonSecurePL2TimerGSIV;
+  UINT32                      NonSecurePL2TimerFlags;
+  UINT64                      CntReadBasePhysicalAddress;
+  UINT32                      PlatformTimerCount;
+  UINT32                      PlatformTimerOffset;
+} EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE;
+
+///
+/// GTDT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Timer Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE          BIT0
+#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY      BIT1
+#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY          BIT2
+
+///
+/// Platform Timer Type
+///
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK                       0
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG          1
+
+///
+/// GT Block Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT16  Length;
+  UINT8   Reserved;
+  UINT64  CntCtlBase;
+  UINT32  GTBlockTimerCount;
+  UINT32  GTBlockTimerOffset;
+} EFI_ACPI_6_2_GTDT_GT_BLOCK_STRUCTURE;
+
+///
+/// GT Block Timer Structure
+///
+typedef struct {
+  UINT8   GTFrameNumber;
+  UINT8   Reserved[3];
+  UINT64  CntBaseX;
+  UINT64  CntEL0BaseX;
+  UINT32  GTxPhysicalTimerGSIV;
+  UINT32  GTxPhysicalTimerFlags;
+  UINT32  GTxVirtualTimerGSIV;
+  UINT32  GTxVirtualTimerFlags;
+  UINT32  GTxCommonFlags;
+} EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_STRUCTURE;
+
+///
+/// GT Block Physical Timers and Virtual Timers Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE          BIT0
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY      BIT1
+
+///
+/// Common Flags Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER              BIT0
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY      BIT1
+
+///
+/// SBSA Generic Watchdog Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT16  Length;
+  UINT8   Reserved;
+  UINT64  RefreshFramePhysicalAddress;
+  UINT64  WatchdogControlFramePhysicalAddress;
+  UINT32  WatchdogTimerGSIV;
+  UINT32  WatchdogTimerFlags;
+} EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;
+
+///
+/// SBSA Generic Watchdog Timer Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE          BIT0
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY      BIT1
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER                  BIT2
+
+//
+// NVDIMM Firmware Interface Table definition.
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER    Header;
+  UINT32                         Reserved;
+} EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE;
+
+//
+// NFIT Version (as defined in ACPI 6.2 spec.)
+//
+#define EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
+
+//
+// Definition for NFIT Table Structure Types
+//
+#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE              0
+#define EFI_ACPI_6_2_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE                      1
+#define EFI_ACPI_6_2_NFIT_INTERLEAVE_STRUCTURE_TYPE                                 2
+#define EFI_ACPI_6_2_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE              3
+#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE                      4
+#define EFI_ACPI_6_2_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE            5
+#define EFI_ACPI_6_2_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE                         6
+
+//
+// Definition for NFIT Structure Header
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+} EFI_ACPI_6_2_NFIT_STRUCTURE_HEADER;
+
+//
+// Definition for System Physical Address Range Structure
+//
+#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT      BIT0
+#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID             BIT1
+#define EFI_ACPI_6_2_NFIT_GUID_VOLATILE_MEMORY_REGION                             { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
+#define EFI_ACPI_6_2_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION          { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
+#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_CONTROL_REGION                              { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
+#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION                    { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE   { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE     { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT   { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D ]}
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT16                                      SPARangeStructureIndex;
+  UINT16                                      Flags;
+  UINT32                                      Reserved_8;
+  UINT32                                      ProximityDomain;
+  GUID                                        AddressRangeTypeGUID;
+  UINT64                                      SystemPhysicalAddressRangeBase;
+  UINT64                                      SystemPhysicalAddressRangeLength;
+  UINT64                                      AddressRangeMemoryMappingAttribute;
+} EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;
+
+//
+// Definition for Memory Device to System Physical Address Range Mapping Structure
+//
+typedef struct {
+  UINT32                                      DIMMNumber:4;
+  UINT32                                      MemoryChannelNumber:4;
+  UINT32                                      MemoryControllerID:4;
+  UINT32                                      SocketID:4;
+  UINT32                                      NodeControllerID:12;
+  UINT32                                      Reserved_28:4;
+} EFI_ACPI_6_2_NFIT_DEVICE_HANDLE;
+
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL                                      BIT0
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL                                       BIT1
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL                                     BIT2
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF                        BIT3
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF                 BIT4
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS  BIT5
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA                          BIT6
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  EFI_ACPI_6_2_NFIT_DEVICE_HANDLE             NFITDeviceHandle;
+  UINT16                                      NVDIMMPhysicalID;
+  UINT16                                      NVDIMMRegionID;
+  UINT16                                      SPARangeStructureIndex ;
+  UINT16                                      NVDIMMControlRegionStructureIndex;
+  UINT64                                      NVDIMMRegionSize;
+  UINT64                                      RegionOffset;
+  UINT64                                      NVDIMMPhysicalAddressRegionBase;
+  UINT16                                      InterleaveStructureIndex;
+  UINT16                                      InterleaveWays;
+  UINT16                                      NVDIMMStateFlags;
+  UINT16                                      Reserved_46;
+} EFI_ACPI_6_2_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;
+
+//
+// Definition for Interleave Structure
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT16                                      InterleaveStructureIndex;
+  UINT16                                      Reserved_6;
+  UINT32                                      NumberOfLines;
+  UINT32                                      LineSize;
+//UINT32                                      LineOffset[NumberOfLines];
+} EFI_ACPI_6_2_NFIT_INTERLEAVE_STRUCTURE;
+
+//
+// Definition for SMBIOS Management Information Structure
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT32                                      Reserved_4;
+//UINT8                                       Data[];
+} EFI_ACPI_6_2_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;
+
+//
+// Definition for NVDIMM Control Region Structure
+//
+#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING           BIT0
+
+#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED    BIT0
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT16                                      NVDIMMControlRegionStructureIndex;
+  UINT16                                      VendorID;
+  UINT16                                      DeviceID;
+  UINT16                                      RevisionID;
+  UINT16                                      SubsystemVendorID;
+  UINT16                                      SubsystemDeviceID;
+  UINT16                                      SubsystemRevisionID;
+  UINT8                                       ValidFields;
+  UINT8                                       ManufacturingLocation;
+  UINT16                                      ManufacturingDate;
+  UINT8                                       Reserved_22[2];
+  UINT32                                      SerialNumber;
+  UINT16                                      RegionFormatInterfaceCode;
+  UINT16                                      NumberOfBlockControlWindows;
+  UINT64                                      SizeOfBlockControlWindow;
+  UINT64                                      CommandRegisterOffsetInBlockControlWindow;
+  UINT64                                      SizeOfCommandRegisterInBlockControlWindows;
+  UINT64                                      StatusRegisterOffsetInBlockControlWindow;
+  UINT64                                      SizeOfStatusRegisterInBlockControlWindows;
+  UINT16                                      NVDIMMControlRegionFlag;
+  UINT8                                       Reserved_74[6];
+} EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;
+
+//
+// Definition for NVDIMM Block Data Window Region Structure
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT16                                      NVDIMMControlRegionStructureIndex;
+  UINT16                                      NumberOfBlockDataWindows;
+  UINT64                                      BlockDataWindowStartOffset;
+  UINT64                                      SizeOfBlockDataWindow;
+  UINT64                                      BlockAccessibleMemoryCapacity;
+  UINT64                                      BeginningAddressOfFirstBlockInBlockAccessibleMemory;
+} EFI_ACPI_6_2_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;
+
+//
+// Definition for Flush Hint Address Structure
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  EFI_ACPI_6_2_NFIT_DEVICE_HANDLE             NFITDeviceHandle;
+  UINT16                                      NumberOfFlushHintAddresses;
+  UINT8                                       Reserved_10[6];
+//UINT64                                      FlushHintAddress[NumberOfFlushHintAddresses];
+} EFI_ACPI_6_2_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;
+
+///
+/// Secure DEVices Table (SDEV)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER   Header;
+} EFI_ACPI_6_2_SECURE_DEVICES_TABLE_HEADER;
+
+///
+/// SDEV Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_SECURE_DEVICES_TABLE_REVISION      0x01
+
+///
+/// Secure Devcice types
+///
+#define EFI_ACPI_6_2_SDEV_TYPE_PCIE_ENDPOINT_DEVICE     0x01
+#define EFI_ACPI_6_2_SDEV_TYPE_ACPI_NAMESPACE_DEVICE    0x00
+
+///
+/// Secure Devcice flags
+///
+#define EFI_ACPI_6_2_SDEV_FLAG_ALLOW_HANDOFF            BIT0
+
+///
+/// SDEV Structure Header
+///
+typedef struct {
+  UINT8                         Type;
+  UINT8                         Flags;
+  UINT16                        Length;
+} EFI_ACPI_6_2_SDEV_STRUCTURE_HEADER;
+
+///
+/// PCIe Endpoint Device based Secure Device Structure
+///
+typedef struct {
+  UINT8                         Type;
+  UINT8                         Flags;
+  UINT16                        Length;
+  UINT16                        PciSegmentNumber;
+  UINT16                        StartBusNumber;
+  UINT16                        PciPathOffset;
+  UINT16                        PciPathLength;
+  UINT16                        VendorSpecificDataOffset;
+  UINT16                        VendorSpecificDataLength;
+} EFI_ACPI_6_2_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE;
+
+///
+/// ACPI_NAMESPACE_DEVICE based Secure Device Structure
+///
+typedef struct {
+  UINT8                         Type;
+  UINT8                         Flags;
+  UINT16                        Length;
+  UINT16                        DeviceIdentifierOffset;
+  UINT16                        DeviceIdentifierLength;
+  UINT16                        VendorSpecificDataOffset;
+  UINT16                        VendorSpecificDataLength;
+} EFI_ACPI_6_2_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE;
+
+///
+/// Boot Error Record Table (BERT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      BootErrorRegionLength;
+  UINT64                      BootErrorRegion;
+} EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_HEADER;
+
+///
+/// BERT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+
+///
+/// Boot Error Region Block Status Definition
+///
+typedef struct {
+  UINT32       UncorrectableErrorValid:1;
+  UINT32       CorrectableErrorValid:1;
+  UINT32       MultipleUncorrectableErrors:1;
+  UINT32       MultipleCorrectableErrors:1;
+  UINT32       ErrorDataEntryCount:10;
+  UINT32       Reserved:18;
+} EFI_ACPI_6_2_ERROR_BLOCK_STATUS;
+
+///
+/// Boot Error Region Definition
+///
+typedef struct {
+  EFI_ACPI_6_2_ERROR_BLOCK_STATUS              BlockStatus;
+  UINT32                                       RawDataOffset;
+  UINT32                                       RawDataLength;
+  UINT32                                       DataLength;
+  UINT32                                       ErrorSeverity;
+} EFI_ACPI_6_2_BOOT_ERROR_REGION_STRUCTURE;
+
+//
+// Boot Error Severity types
+//
+#define EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTABLE  0x00
+#define EFI_ACPI_6_2_ERROR_SEVERITY_FATAL        0x01
+#define EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTED    0x02
+#define EFI_ACPI_6_2_ERROR_SEVERITY_NONE         0x03
+
+///
+/// Generic Error Data Entry Definition
+///
+typedef struct {
+  UINT8    SectionType[16];
+  UINT32   ErrorSeverity;
+  UINT16   Revision;
+  UINT8    ValidationBits;
+  UINT8    Flags;
+  UINT32   ErrorDataLength;
+  UINT8    FruId[16];
+  UINT8    FruText[20];
+  UINT8    Timestamp[8];
+} EFI_ACPI_6_2_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
+
+///
+/// Generic Error Data Entry Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_GENERIC_ERROR_DATA_ENTRY_REVISION  0x0300
+
+///
+/// HEST - Hardware Error Source Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      ErrorSourceCount;
+} EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
+
+///
+/// HEST Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+
+//
+// Error Source structure types.
+//
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION  0x00
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK  0x01
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_NMI_ERROR                0x02
+#define EFI_ACPI_6_2_PCI_EXPRESS_ROOT_PORT_AER                  0x06
+#define EFI_ACPI_6_2_PCI_EXPRESS_DEVICE_AER                     0x07
+#define EFI_ACPI_6_2_PCI_EXPRESS_BRIDGE_AER                     0x08
+#define EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR                     0x09
+#define EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_VERSION_2           0x0A
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK   0x0B
+
+//
+// Error Source structure flags.
+//
+#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_FIRMWARE_FIRST       (1 << 0)
+#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GLOBAL               (1 << 1)
+#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GHES_ASSIST          (1 << 2)
+
+///
+/// IA-32 Architecture Machine Check Exception Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT64  GlobalCapabilityInitData;
+  UINT64  GlobalControlInitData;
+  UINT8   NumberOfHardwareBanks;
+  UINT8   Reserved1[7];
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure Definition
+///
+typedef struct {
+  UINT8   BankNumber;
+  UINT8   ClearStatusOnInitialization;
+  UINT8   StatusDataFormat;
+  UINT8   Reserved0;
+  UINT32  ControlRegisterMsrAddress;
+  UINT64  ControlInitData;
+  UINT32  StatusRegisterMsrAddress;
+  UINT32  AddressRegisterMsrAddress;
+  UINT32  MiscRegisterMsrAddress;
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure MCA data format
+///
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32      0x00
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64   0x01
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64     0x02
+
+//
+// Hardware Error Notification types. All other values are reserved
+//
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_POLLED                         0x00
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT             0x01
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT                0x02
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SCI                            0x03
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_NMI                            0x04
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CMCI                           0x05
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_MCE                            0x06
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL                    0x07
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA                      0x08
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI                      0x09
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GSIV                           0x0A
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION   0x0B
+
+///
+/// Hardware Error Notification Configuration Write Enable Structure Definition
+///
+typedef struct {
+  UINT16    Type:1;
+  UINT16    PollInterval:1;
+  UINT16    SwitchToPollingThresholdValue:1;
+  UINT16    SwitchToPollingThresholdWindow:1;
+  UINT16    ErrorThresholdValue:1;
+  UINT16    ErrorThresholdWindow:1;
+  UINT16    Reserved:10;
+} EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
+
+///
+/// Hardware Error Notification Structure Definition
+///
+typedef struct {
+  UINT8                                                                          Type;
+  UINT8                                                                          Length;
+  EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE  ConfigurationWriteEnable;
+  UINT32                                                                         PollInterval;
+  UINT32                                                                         Vector;
+  UINT32                                                                         SwitchToPollingThresholdValue;
+  UINT32                                                                         SwitchToPollingThresholdWindow;
+  UINT32                                                                         ErrorThresholdValue;
+  UINT32                                                                         ErrorThresholdWindow;
+} EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
+
+///
+/// IA-32 Architecture Corrected Machine Check Structure Definition
+///
+typedef struct {
+  UINT16                                                 Type;
+  UINT16                                                 SourceId;
+  UINT8                                                  Reserved0[2];
+  UINT8                                                  Flags;
+  UINT8                                                  Enabled;
+  UINT32                                                 NumberOfRecordsToPreAllocate;
+  UINT32                                                 MaxSectionsPerRecord;
+  EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE     NotificationStructure;
+  UINT8                                                  NumberOfHardwareBanks;
+  UINT8                                                  Reserved1[3];
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// IA-32 Architecture NMI Error Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  MaxRawDataLength;
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
+
+///
+/// PCI Express Root Port AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+  UINT32  RootErrorCommand;
+} EFI_ACPI_6_2_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
+
+///
+/// PCI Express Device AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_2_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
+
+///
+/// PCI Express Bridge AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+  UINT32  SecondaryUncorrectableErrorMask;
+  UINT32  SecondaryUncorrectableErrorSeverity;
+  UINT32  SecondaryAdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_2_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Structure Definition
+///
+typedef struct {
+  UINT16                                                 Type;
+  UINT16                                                 SourceId;
+  UINT16                                                 RelatedSourceId;
+  UINT8                                                  Flags;
+  UINT8                                                  Enabled;
+  UINT32                                                 NumberOfRecordsToPreAllocate;
+  UINT32                                                 MaxSectionsPerRecord;
+  UINT32                                                 MaxRawDataLength;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE                 ErrorStatusAddress;
+  EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE     NotificationStructure;
+  UINT32                                                 ErrorStatusBlockLength;
+} EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Version 2 Structure Definition
+///
+typedef struct {
+  UINT16                                                 Type;
+  UINT16                                                 SourceId;
+  UINT16                                                 RelatedSourceId;
+  UINT8                                                  Flags;
+  UINT8                                                  Enabled;
+  UINT32                                                 NumberOfRecordsToPreAllocate;
+  UINT32                                                 MaxSectionsPerRecord;
+  UINT32                                                 MaxRawDataLength;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE                 ErrorStatusAddress;
+  EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE     NotificationStructure;
+  UINT32                                                 ErrorStatusBlockLength;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE                 ReadAckRegister;
+  UINT64                                                 ReadAckPreserve;
+  UINT64                                                 ReadAckWrite;
+} EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;
+
+///
+/// Generic Error Status Definition
+///
+typedef struct {
+  EFI_ACPI_6_2_ERROR_BLOCK_STATUS              BlockStatus;
+  UINT32                                       RawDataOffset;
+  UINT32                                       RawDataLength;
+  UINT32                                       DataLength;
+  UINT32                                       ErrorSeverity;
+} EFI_ACPI_6_2_GENERIC_ERROR_STATUS_STRUCTURE;
+
+///
+/// IA-32 Architecture Deferred Machine Check Structure Definition
+///
+typedef struct {
+  UINT16                                                Type;
+  UINT16                                                SourceId;
+  UINT8                                                 Reserved0[2];
+  UINT8                                                 Flags;
+  UINT8                                                 Enabled;
+  UINT32                                                NumberOfRecordsToPreAllocate;
+  UINT32                                                MaxSectionsPerRecord;
+  EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE    NotificationStructure;
+  UINT8                                                 NumberOfHardwareBanks;
+  UINT8                                                 Reserved1[3];
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;;
+
+///
+/// HMAT - Heterogeneous Memory Attribute Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       Reserved[4];
+} EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;
+
+///
+/// HMAT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x01
+
+///
+/// HMAT types
+///
+#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SUBSYSTEM_ADDRESS_RANGE               0x00
+#define EFI_ACPI_6_2_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO   0x01
+#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO                       0x02
+
+///
+/// HMAT Structure Header
+///
+typedef struct {
+  UINT16                        Type;
+  UINT8                         Reserved[2];
+  UINT32                        Length;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_HEADER;
+
+///
+/// Memory Subsystem Address Range Structure flags
+///
+typedef struct {
+  UINT16                        ProcessorProximityDomainValid:1;
+  UINT16                        MemoryProximityDomainValid:1;
+  UINT16                        ReservationHint:1;
+  UINT16                        Reserved:13;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE_FLAGS;
+
+///
+/// Memory Subsystem Address Range Structure
+///
+typedef struct {
+  UINT16                                                            Type;
+  UINT8                                                             Reserved[2];
+  UINT32                                                            Length;
+  EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE_FLAGS  Flags;
+  UINT8                                                             Reserved1[2];
+  UINT32                                                            ProcessorProximityDomain;
+  UINT32                                                            MemoryProximityDomain;
+  UINT8                                                             Reserved2[4];
+  UINT64                                                            SystemPhysicalAddressRangeBase;
+  UINT64                                                            SystemPhysicalAddressRangeLength;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE;
+
+///
+/// System Locality Latency and Bandwidth Information Structure flags
+///
+typedef struct {
+  UINT8                         MemoryHierarchy:5;
+  UINT8                         Reserved:3;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS;
+
+///
+/// System Locality Latency and Bandwidth Information Structure
+///
+typedef struct {
+  UINT16                                                                        Type;
+  UINT8                                                                         Reserved[2];
+  UINT32                                                                        Length;
+  EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS  Flags;
+  UINT8                                                                         DataType;
+  UINT8                                                                         Reserved1[2];
+  UINT32                                                                        NumberOfInitiatorProximityDomains;
+  UINT32                                                                        NumberOfTargetProximityDomains;
+  UINT8                                                                         Reserved2[4];
+  UINT64                                                                        EntryBaseUnit;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO;
+
+///
+/// Memory Side Cache Information Structure cache attributes
+///
+typedef struct {
+  UINT32                        TotalCacheLevels:4;
+  UINT32                        CacheLevel:4;
+  UINT32                        CacheAssociativity:4;
+  UINT32                        WritePolicy:4;
+  UINT32                        CacheLineSize:16;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES;
+
+///
+/// Memory Side Cache Information Structure
+///
+typedef struct {
+  UINT16                                                                Type;
+  UINT8                                                                 Reserved[2];
+  UINT32                                                                Length;
+  UINT32                                                                MemoryProximityDomain;
+  UINT8                                                                 Reserved1[4];
+  UINT64                                                                MemorySideCacheSize;
+  EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES   CacheAttributes;
+  UINT8                                                                 Reserved2[2];
+  UINT16                                                                NumberOfSmbiosHandles;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO;
+
+///
+/// ERST - Error Record Serialization Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      SerializationHeaderSize;
+  UINT8                       Reserved0[4];
+  UINT32                      InstructionEntryCount;
+} EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
+
+///
+/// ERST Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+
+///
+/// ERST Serialization Actions
+///
+#define EFI_ACPI_6_2_ERST_BEGIN_WRITE_OPERATION                    0x00
+#define EFI_ACPI_6_2_ERST_BEGIN_READ_OPERATION                     0x01
+#define EFI_ACPI_6_2_ERST_BEGIN_CLEAR_OPERATION                    0x02
+#define EFI_ACPI_6_2_ERST_END_OPERATION                            0x03
+#define EFI_ACPI_6_2_ERST_SET_RECORD_OFFSET                        0x04
+#define EFI_ACPI_6_2_ERST_EXECUTE_OPERATION                        0x05
+#define EFI_ACPI_6_2_ERST_CHECK_BUSY_STATUS                        0x06
+#define EFI_ACPI_6_2_ERST_GET_COMMAND_STATUS                       0x07
+#define EFI_ACPI_6_2_ERST_GET_RECORD_IDENTIFIER                    0x08
+#define EFI_ACPI_6_2_ERST_SET_RECORD_IDENTIFIER                    0x09
+#define EFI_ACPI_6_2_ERST_GET_RECORD_COUNT                         0x0A
+#define EFI_ACPI_6_2_ERST_BEGIN_DUMMY_WRITE_OPERATION              0x0B
+#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE              0x0D
+#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH       0x0E
+#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES   0x0F
+#define EFI_ACPI_6_2_ERST_GET_EXECUTE_OPERATION_TIMINGS            0x10
+
+///
+/// ERST Action Command Status
+///
+#define EFI_ACPI_6_2_ERST_STATUS_SUCCESS                           0x00
+#define EFI_ACPI_6_2_ERST_STATUS_NOT_ENOUGH_SPACE                  0x01
+#define EFI_ACPI_6_2_ERST_STATUS_HARDWARE_NOT_AVAILABLE            0x02
+#define EFI_ACPI_6_2_ERST_STATUS_FAILED                            0x03
+#define EFI_ACPI_6_2_ERST_STATUS_RECORD_STORE_EMPTY                0x04
+#define EFI_ACPI_6_2_ERST_STATUS_RECORD_NOT_FOUND                  0x05
+
+///
+/// ERST Serialization Instructions
+///
+#define EFI_ACPI_6_2_ERST_READ_REGISTER                            0x00
+#define EFI_ACPI_6_2_ERST_READ_REGISTER_VALUE                      0x01
+#define EFI_ACPI_6_2_ERST_WRITE_REGISTER                           0x02
+#define EFI_ACPI_6_2_ERST_WRITE_REGISTER_VALUE                     0x03
+#define EFI_ACPI_6_2_ERST_NOOP                                     0x04
+#define EFI_ACPI_6_2_ERST_LOAD_VAR1                                0x05
+#define EFI_ACPI_6_2_ERST_LOAD_VAR2                                0x06
+#define EFI_ACPI_6_2_ERST_STORE_VAR1                               0x07
+#define EFI_ACPI_6_2_ERST_ADD                                      0x08
+#define EFI_ACPI_6_2_ERST_SUBTRACT                                 0x09
+#define EFI_ACPI_6_2_ERST_ADD_VALUE                                0x0A
+#define EFI_ACPI_6_2_ERST_SUBTRACT_VALUE                           0x0B
+#define EFI_ACPI_6_2_ERST_STALL                                    0x0C
+#define EFI_ACPI_6_2_ERST_STALL_WHILE_TRUE                         0x0D
+#define EFI_ACPI_6_2_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE            0x0E
+#define EFI_ACPI_6_2_ERST_GOTO                                     0x0F
+#define EFI_ACPI_6_2_ERST_SET_SRC_ADDRESS_BASE                     0x10
+#define EFI_ACPI_6_2_ERST_SET_DST_ADDRESS_BASE                     0x11
+#define EFI_ACPI_6_2_ERST_MOVE_DATA                                0x12
+
+///
+/// ERST Instruction Flags
+///
+#define EFI_ACPI_6_2_ERST_PRESERVE_REGISTER                        0x01
+
+///
+/// ERST Serialization Instruction Entry
+///
+typedef struct {
+  UINT8                                    SerializationAction;
+  UINT8                                    Instruction;
+  UINT8                                    Flags;
+  UINT8                                    Reserved0;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE   RegisterRegion;
+  UINT64                                   Value;
+  UINT64                                   Mask;
+} EFI_ACPI_6_2_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ - Error Injection Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      InjectionHeaderSize;
+  UINT8                       InjectionFlags;
+  UINT8                       Reserved0[3];
+  UINT32                      InjectionEntryCount;
+} EFI_ACPI_6_2_ERROR_INJECTION_TABLE_HEADER;
+
+///
+/// EINJ Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_ERROR_INJECTION_TABLE_REVISION 0x01
+
+///
+/// EINJ Error Injection Actions
+///
+#define EFI_ACPI_6_2_EINJ_BEGIN_INJECTION_OPERATION                0x00
+#define EFI_ACPI_6_2_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE           0x01
+#define EFI_ACPI_6_2_EINJ_SET_ERROR_TYPE                           0x02
+#define EFI_ACPI_6_2_EINJ_GET_ERROR_TYPE                           0x03
+#define EFI_ACPI_6_2_EINJ_END_OPERATION                            0x04
+#define EFI_ACPI_6_2_EINJ_EXECUTE_OPERATION                        0x05
+#define EFI_ACPI_6_2_EINJ_CHECK_BUSY_STATUS                        0x06
+#define EFI_ACPI_6_2_EINJ_GET_COMMAND_STATUS                       0x07
+#define EFI_ACPI_6_2_EINJ_TRIGGER_ERROR                            0xFF
+
+///
+/// EINJ Action Command Status
+///
+#define EFI_ACPI_6_2_EINJ_STATUS_SUCCESS                           0x00
+#define EFI_ACPI_6_2_EINJ_STATUS_UNKNOWN_FAILURE                   0x01
+#define EFI_ACPI_6_2_EINJ_STATUS_INVALID_ACCESS                    0x02
+
+///
+/// EINJ Error Type Definition
+///
+#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_CORRECTABLE                 (1 << 0)
+#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL      (1 << 1)
+#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL         (1 << 2)
+#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_CORRECTABLE                    (1 << 3)
+#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL         (1 << 4)
+#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL            (1 << 5)
+#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE               (1 << 6)
+#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL    (1 << 7)
+#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL       (1 << 8)
+#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_CORRECTABLE                  (1 << 9)
+#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL       (1 << 10)
+#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL          (1 << 11)
+
+///
+/// EINJ Injection Instructions
+///
+#define EFI_ACPI_6_2_EINJ_READ_REGISTER                            0x00
+#define EFI_ACPI_6_2_EINJ_READ_REGISTER_VALUE                      0x01
+#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER                           0x02
+#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER_VALUE                     0x03
+#define EFI_ACPI_6_2_EINJ_NOOP                                     0x04
+
+///
+/// EINJ Instruction Flags
+///
+#define EFI_ACPI_6_2_EINJ_PRESERVE_REGISTER                        0x01
+
+///
+/// EINJ Injection Instruction Entry
+///
+typedef struct {
+  UINT8                                    InjectionAction;
+  UINT8                                    Instruction;
+  UINT8                                    Flags;
+  UINT8                                    Reserved0;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE   RegisterRegion;
+  UINT64                                   Value;
+  UINT64                                   Mask;
+} EFI_ACPI_6_2_EINJ_INJECTION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ Trigger Action Table
+///
+typedef struct {
+  UINT32  HeaderSize;
+  UINT32  Revision;
+  UINT32  TableSize;
+  UINT32  EntryCount;
+} EFI_ACPI_6_2_EINJ_TRIGGER_ACTION_TABLE;
+
+///
+/// Platform Communications Channel Table (PCCT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Flags;
+  UINT64                      Reserved;
+} EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
+
+///
+/// PCCT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02
+
+///
+/// PCCT Global Flags
+///
+#define EFI_ACPI_6_2_PCCT_FLAGS_PLATFORM_INTERRUPT  BIT0
+
+//
+// PCCT Subspace type
+//
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_GENERIC                         0x00
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS     0x01
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS     0x02
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC                  0x03
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC                  0x04
+
+///
+/// PCC Subspace Structure Header
+///
+typedef struct {
+  UINT8        Type;
+  UINT8        Length;
+} EFI_ACPI_6_2_PCCT_SUBSPACE_HEADER;
+
+///
+/// Generic Communications Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT8                                    Reserved[6];
+  UINT64                                   BaseAddress;
+  UINT64                                   AddressLength;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT16                                   MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_2_PCCT_SUBSPACE_GENERIC;
+
+///
+/// Generic Communications Channel Shared Memory Region
+///
+
+typedef struct {
+  UINT8                                    Command;
+  UINT8                                    Reserved:7;
+  UINT8                                    NotifyOnCompletion:1;
+} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
+
+typedef struct {
+  UINT8                                    CommandComplete:1;
+  UINT8                                    PlatformInterrupt:1;
+  UINT8                                    Error:1;
+  UINT8                                    PlatformNotification:1;
+  UINT8                                    Reserved:4;
+  UINT8                                    Reserved1;
+} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
+
+typedef struct {
+  UINT32                                                    Signature;
+  EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND    Command;
+  EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS     Status;
+} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
+
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY    BIT0
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE        BIT1
+
+///
+/// Type 1 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT32                                   PlatformInterrupt;
+  UINT8                                    PlatformInterruptFlags;
+  UINT8                                    Reserved;
+  UINT64                                   BaseAddress;
+  UINT64                                   AddressLength;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT16                                   MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_2_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 2 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT32                                   PlatformInterrupt;
+  UINT8                                    PlatformInterruptFlags;
+  UINT8                                    Reserved;
+  UINT64                                   BaseAddress;
+  UINT64                                   AddressLength;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT16                                   MinimumRequestTurnaroundTime;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE   PlatformInterruptAckRegister;
+  UINT64                                   PlatformInterruptAckPreserve;
+  UINT64                                   PlatformInterruptAckWrite;
+} EFI_ACPI_6_2_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 3 Extended PCC Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT32                                   PlatformInterrupt;
+  UINT8                                    PlatformInterruptFlags;
+  UINT8                                    Reserved;
+  UINT64                                   BaseAddress;
+  UINT32                                   AddressLength;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT32                                   MinimumRequestTurnaroundTime;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE   PlatformInterruptAckRegister;
+  UINT64                                   PlatformInterruptAckPreserve;
+  UINT64                                   PlatformInterruptAckSet;
+  UINT8                                    Reserved1[8];
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE   CommandCompleteCheckRegister;
+  UINT64                                   CommandCompleteCheckMask;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE   CommandCompleteUpdateRegister;
+  UINT64                                   CommandCompleteUpdatePreserve;
+  UINT64                                   CommandCompleteUpdateSet;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE   ErrorStatusRegister;
+  UINT64                                   ErrorStatusMask;
+} EFI_ACPI_6_2_PCCT_SUBSPACE_3_EXTENDED_PCC;
+
+///
+/// Type 4 Extended PCC Subspace Structure
+///
+typedef EFI_ACPI_6_2_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_2_PCCT_SUBSPACE_4_EXTENDED_PCC;
+
+#define EFI_ACPI_6_2_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0
+
+typedef struct {
+  UINT32                                    Signature;
+  UINT32                                    Flags;
+  UINT32                                    Length;
+  UINT32                                    Command;
+} EFI_ACPI_6_2_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER;
+
+///
+/// Platform Debug Trigger Table (PDTT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER   Header;
+  UINT8                         TriggerCount;
+  UINT8                         Reserved[3];
+  UINT32                        TriggerIdentifierArrayOffset;
+} EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER;
+
+///
+/// PDTT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00
+
+///
+/// PDTT Platform Communication Channel Identifier Structure
+///
+typedef struct {
+  UINT16                        SubChannelIdentifer:8;
+  UINT16                        Runtime:1;
+  UINT16                        WaitForCompletion:1;
+  UINT16                        Reserved:6;
+} EFI_ACPI_6_2_PDTT_PCC_IDENTIFIER;
+
+///
+/// PCC Commands Codes used by Platform Debug Trigger Table
+///
+#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_DOORBELL_ONLY     0x00
+#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_VENDOR_SPECIFIC   0x01
+
+///
+/// PPTT Platform Communication Channel
+///
+typedef EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6_2_PDTT_PCC;
+
+///
+/// Processor Properties Topology Table (PPTT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER   Header;
+} EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;
+
+///
+/// PPTT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x01
+
+///
+/// PPTT types
+///
+#define EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR     0x00
+#define EFI_ACPI_6_2_PPTT_TYPE_CACHE         0x01
+#define EFI_ACPI_6_2_PPTT_TYPE_ID            0x02
+
+///
+/// PPTT Structure Header
+///
+typedef struct {
+  UINT8                         Type;
+  UINT8                         Length;
+  UINT8                         Reserved[2];
+} EFI_ACPI_6_2_PPTT_STRUCTURE_HEADER;
+
+///
+/// Processor hierarchy node structure flags
+///
+typedef struct {
+  UINT32                        PhysicalPackage:1;
+  UINT32                        AcpiProcessorIdValid:1;
+  UINT32                        Reserved:30;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS;
+
+///
+/// Processor hierarchy node structure
+///
+typedef struct {
+  UINT32                                        Type;
+  UINT8                                         Length;
+  UINT8                                         Reserved[2];
+  EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS   Flags;
+  UINT32                                        Parent;
+  UINT32                                        AcpiProcessorId;
+  UINT32                                        NumberOfPrivateResources;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR;
+
+///
+/// Cache Type Structure flags
+///
+typedef struct {
+  UINT32                        SizePropertyValid:1;
+  UINT32                        NumberOfSetsValid:1;
+  UINT32                        AssociativityValid:1;
+  UINT32                        AllocationTypeValid:1;
+  UINT32                        CacheTypeValid:1;
+  UINT32                        WritePolicyValid:1;
+  UINT32                        LineSizeValid:1;
+  UINT32                        Reserved:25;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_FLAGS;
+
+///
+/// Cache Type Structure cache attributes
+///
+typedef struct {
+  UINT8                         AllocationType:2;
+  UINT8                         CacheType:2;
+  UINT8                         WritePolicy:1;
+  UINT8                         Reserved:3;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES;
+
+///
+/// Cache Type Structure
+///
+typedef struct {
+  UINT8                                         Type;
+  UINT8                                         Length;
+  UINT8                                         Reserved[2];
+  EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_FLAGS       Flags;
+  UINT32                                        NextLevelOfCache;
+  UINT32                                        Size;
+  UINT32                                        NumberOfSets;
+  UINT8                                         Associativity;
+  EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES  Attributes;
+  UINT16                                        LineSize;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE;
+
+///
+/// ID structure
+///
+typedef struct {
+  UINT8                         Type;
+  UINT8                         Length;
+  UINT8                         Reserved[2];
+  UINT32                        VendorId;
+  UINT64                        Level1Id;
+  UINT64                        Level2Id;
+  UINT16                        MajorRev;
+  UINT16                        MinorRev;
+  UINT16                        SpinRev;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_ID;
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "BERT" Boot Error Record Table
+///
+#define EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_SIGNATURE  SIGNATURE_32('B', 'E', 'R', 'T')
+
+///
+/// "BGRT" Boot Graphics Resource Table
+///
+#define EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('B', 'G', 'R', 'T')
+
+///
+/// "CPEP" Corrected Platform Error Polling Table
+///
+#define EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE  SIGNATURE_32('C', 'P', 'E', 'P')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_6_2_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE  SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "EINJ" Error Injection Table
+///
+#define EFI_ACPI_6_2_ERROR_INJECTION_TABLE_SIGNATURE  SIGNATURE_32('E', 'I', 'N', 'J')
+
+///
+/// "ERST" Error Record Serialization Table
+///
+#define EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE  SIGNATURE_32('E', 'R', 'S', 'T')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "FPDT" Firmware Performance Data Table
+///
+#define EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE  SIGNATURE_32('F', 'P', 'D', 'T')
+
+///
+/// "GTDT" Generic Timer Description Table
+///
+#define EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('G', 'T', 'D', 'T')
+
+///
+/// "HEST" Hardware Error Source Table
+///
+#define EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE  SIGNATURE_32('H', 'E', 'S', 'T')
+
+///
+/// "HMAT" Heterogeneous Memory Attribute Table
+///
+#define EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE  SIGNATURE_32('H', 'M', 'A', 'T')
+
+///
+/// "MPST" Memory Power State Table
+///
+#define EFI_ACPI_6_2_MEMORY_POWER_STATE_TABLE_SIGNATURE  SIGNATURE_32('M', 'P', 'S', 'T')
+
+///
+/// "MSCT" Maximum System Characteristics Table
+///
+#define EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE  SIGNATURE_32('M', 'S', 'C', 'T')
+
+///
+/// "NFIT" NVDIMM Firmware Interface Table
+///
+#define EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE  SIGNATURE_32('N', 'F', 'I', 'T')
+
+///
+/// "PDTT" Platform Debug Trigger Table
+///
+#define EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_STRUCTURE_SIGNATURE  SIGNATURE_32('P', 'D', 'T', 'T')
+
+///
+/// "PMTT" Platform Memory Topology Table
+///
+#define EFI_ACPI_6_2_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE  SIGNATURE_32('P', 'M', 'T', 'T')
+
+///
+/// "PPTT" Processor Properties Topology Table
+///
+#define EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE  SIGNATURE_32('P', 'P', 'T', 'T')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_6_2_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RASF" ACPI RAS Feature Table
+///
+#define EFI_ACPI_6_2_ACPI_RAS_FEATURE_TABLE_SIGNATURE  SIGNATURE_32('R', 'A', 'S', 'F')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_6_2_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SDEV" Secure DEVices Table
+///
+#define EFI_ACPI_6_2_SECURE_DEVICES_TABLE_SIGNATURE  SIGNATURE_32('S', 'D', 'E', 'V')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_6_2_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SRAT" System Resource Affinity Table
+///
+#define EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE  SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_6_2_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_6_2_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE  SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "CSRT" MS Core System Resource Table
+///
+#define EFI_ACPI_6_2_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('C', 'S', 'R', 'T')
+
+///
+/// "DBG2" MS Debug Port 2 Spec
+///
+#define EFI_ACPI_6_2_DEBUG_PORT_2_TABLE_SIGNATURE  SIGNATURE_32('D', 'B', 'G', '2')
+
+///
+/// "DBGP" MS Debug Port Spec
+///
+#define EFI_ACPI_6_2_DEBUG_PORT_TABLE_SIGNATURE  SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "DMAR" DMA Remapping Table
+///
+#define EFI_ACPI_6_2_DMA_REMAPPING_TABLE_SIGNATURE  SIGNATURE_32('D', 'M', 'A', 'R')
+
+///
+/// "DPPT" DMA Protection Policy Table
+///
+#define EFI_ACPI_6_2_DMA_PROTECTION_POLICY_TABLE_SIGNATURE  SIGNATURE_32('D', 'P', 'P', 'T')
+
+///
+/// "DRTM" Dynamic Root of Trust for Measurement Table
+///
+#define EFI_ACPI_6_2_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE  SIGNATURE_32('D', 'R', 'T', 'M')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_6_2_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "HPET" IA-PC High Precision Event Timer Table
+///
+#define EFI_ACPI_6_2_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE  SIGNATURE_32('H', 'P', 'E', 'T')
+
+///
+/// "iBFT" iSCSI Boot Firmware Table
+///
+#define EFI_ACPI_6_2_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE  SIGNATURE_32('i', 'B', 'F', 'T')
+
+///
+/// "IORT" I/O Remapping Table
+///
+#define EFI_ACPI_6_2_IO_REMAPPING_TABLE_SIGNATURE  SIGNATURE_32('I', 'O', 'R', 'T')
+
+///
+/// "IVRS" I/O Virtualization Reporting Structure
+///
+#define EFI_ACPI_6_2_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE  SIGNATURE_32('I', 'V', 'R', 'S')
+
+///
+/// "LPIT" Low Power Idle Table
+///
+#define EFI_ACPI_6_2_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE  SIGNATURE_32('L', 'P', 'I', 'T')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_6_2_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('M', 'C', 'F', 'G')
+
+///
+/// "MCHI" Management Controller Host Interface Table
+///
+#define EFI_ACPI_6_2_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('M', 'C', 'H', 'I')
+
+///
+/// "MSDM" MS Data Management Table
+///
+#define EFI_ACPI_6_2_DATA_MANAGEMENT_TABLE_SIGNATURE  SIGNATURE_32('M', 'S', 'D', 'M')
+
+///
+/// "SDEI" Software Delegated Exceptions Interface Table
+///
+#define EFI_ACPI_6_2_SOFTWARE_DELEGATED_EXCEPTIONS_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('S', 'D', 'E', 'I')
+
+///
+/// "SLIC" MS Software Licensing Table Specification
+///
+#define EFI_ACPI_6_2_SOFTWARE_LICENSING_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'C')
+
+///
+/// "SPCR" Serial Port Concole Redirection Table
+///
+#define EFI_ACPI_6_2_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_6_2_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "STAO" _STA Override Table
+///
+#define EFI_ACPI_6_2_STA_OVERRIDE_TABLE_SIGNATURE  SIGNATURE_32('S', 'T', 'A', 'O')
+
+///
+/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+///
+#define EFI_ACPI_6_2_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE  SIGNATURE_32('T', 'C', 'P', 'A')
+
+///
+/// "TPM2" Trusted Computing Platform 1 Table
+///
+#define EFI_ACPI_6_2_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE  SIGNATURE_32('T', 'P', 'M', '2')
+
+///
+/// "UEFI" UEFI ACPI Data Table
+///
+#define EFI_ACPI_6_2_UEFI_ACPI_DATA_TABLE_SIGNATURE  SIGNATURE_32('U', 'E', 'F', 'I')
+
+///
+/// "WAET" Windows ACPI Emulated Devices Table
+///
+#define EFI_ACPI_6_2_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE  SIGNATURE_32('W', 'A', 'E', 'T')
+
+///
+/// "WDAT" Watchdog Action Table
+///
+#define EFI_ACPI_6_2_WATCHDOG_ACTION_TABLE_SIGNATURE  SIGNATURE_32('W', 'D', 'A', 'T')
+
+///
+/// "WDRT" Watchdog Resource Table
+///
+#define EFI_ACPI_6_2_WATCHDOG_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('W', 'D', 'R', 'T')
+
+///
+/// "WPBT" MS Platform Binary Table
+///
+#define EFI_ACPI_6_2_PLATFORM_BINARY_TABLE_SIGNATURE  SIGNATURE_32('W', 'P', 'B', 'T')
+
+///
+/// "WSMT" Windows SMM Security Mitigation Table
+///
+#define EFI_ACPI_6_2_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE  SIGNATURE_32('W', 'S', 'M', 'T')
+
+///
+/// "XENV" Xen Project Table
+///
+#define EFI_ACPI_6_2_XEN_PROJECT_TABLE_SIGNATURE  SIGNATURE_32('X', 'E', 'N', 'V')
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/AcpiAml.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/AcpiAml.h
new file mode 100644
index 0000000000..19d9684943
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/AcpiAml.h
@@ -0,0 +1,175 @@
+/** @file
+  This file contains AML code definition in the latest ACPI spec.
+
+  Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _ACPI_AML_H_
+#define _ACPI_AML_H_
+
+//
+// ACPI AML definition
+//
+
+//
+// Primary OpCode
+//
+#define AML_ZERO_OP                  0x00
+#define AML_ONE_OP                   0x01
+#define AML_ALIAS_OP                 0x06
+#define AML_NAME_OP                  0x08
+#define AML_BYTE_PREFIX              0x0a
+#define AML_WORD_PREFIX              0x0b
+#define AML_DWORD_PREFIX             0x0c
+#define AML_STRING_PREFIX            0x0d
+#define AML_QWORD_PREFIX             0x0e
+#define AML_SCOPE_OP                 0x10
+#define AML_BUFFER_OP                0x11
+#define AML_PACKAGE_OP               0x12
+#define AML_VAR_PACKAGE_OP           0x13
+#define AML_METHOD_OP                0x14
+#define AML_DUAL_NAME_PREFIX         0x2e
+#define AML_MULTI_NAME_PREFIX        0x2f
+#define AML_NAME_CHAR_A              0x41
+#define AML_NAME_CHAR_B              0x42
+#define AML_NAME_CHAR_C              0x43
+#define AML_NAME_CHAR_D              0x44
+#define AML_NAME_CHAR_E              0x45
+#define AML_NAME_CHAR_F              0x46
+#define AML_NAME_CHAR_G              0x47
+#define AML_NAME_CHAR_H              0x48
+#define AML_NAME_CHAR_I              0x49
+#define AML_NAME_CHAR_J              0x4a
+#define AML_NAME_CHAR_K              0x4b
+#define AML_NAME_CHAR_L              0x4c
+#define AML_NAME_CHAR_M              0x4d
+#define AML_NAME_CHAR_N              0x4e
+#define AML_NAME_CHAR_O              0x4f
+#define AML_NAME_CHAR_P              0x50
+#define AML_NAME_CHAR_Q              0x51
+#define AML_NAME_CHAR_R              0x52
+#define AML_NAME_CHAR_S              0x53
+#define AML_NAME_CHAR_T              0x54
+#define AML_NAME_CHAR_U              0x55
+#define AML_NAME_CHAR_V              0x56
+#define AML_NAME_CHAR_W              0x57
+#define AML_NAME_CHAR_X              0x58
+#define AML_NAME_CHAR_Y              0x59
+#define AML_NAME_CHAR_Z              0x5a
+#define AML_ROOT_CHAR                0x5c
+#define AML_PARENT_PREFIX_CHAR       0x5e
+#define AML_NAME_CHAR__              0x5f
+#define AML_LOCAL0                   0x60
+#define AML_LOCAL1                   0x61
+#define AML_LOCAL2                   0x62
+#define AML_LOCAL3                   0x63
+#define AML_LOCAL4                   0x64
+#define AML_LOCAL5                   0x65
+#define AML_LOCAL6                   0x66
+#define AML_LOCAL7                   0x67
+#define AML_ARG0                     0x68
+#define AML_ARG1                     0x69
+#define AML_ARG2                     0x6a
+#define AML_ARG3                     0x6b
+#define AML_ARG4                     0x6c
+#define AML_ARG5                     0x6d
+#define AML_ARG6                     0x6e
+#define AML_STORE_OP                 0x70
+#define AML_REF_OF_OP                0x71
+#define AML_ADD_OP                   0x72
+#define AML_CONCAT_OP                0x73
+#define AML_SUBTRACT_OP              0x74
+#define AML_INCREMENT_OP             0x75
+#define AML_DECREMENT_OP             0x76
+#define AML_MULTIPLY_OP              0x77
+#define AML_DIVIDE_OP                0x78
+#define AML_SHIFT_LEFT_OP            0x79
+#define AML_SHIFT_RIGHT_OP           0x7a
+#define AML_AND_OP                   0x7b
+#define AML_NAND_OP                  0x7c
+#define AML_OR_OP                    0x7d
+#define AML_NOR_OP                   0x7e
+#define AML_XOR_OP                   0x7f
+#define AML_NOT_OP                   0x80
+#define AML_FIND_SET_LEFT_BIT_OP     0x81
+#define AML_FIND_SET_RIGHT_BIT_OP    0x82
+#define AML_DEREF_OF_OP              0x83
+#define AML_CONCAT_RES_OP            0x84
+#define AML_MOD_OP                   0x85
+#define AML_NOTIFY_OP                0x86
+#define AML_SIZE_OF_OP               0x87
+#define AML_INDEX_OP                 0x88
+#define AML_MATCH_OP                 0x89
+#define AML_CREATE_DWORD_FIELD_OP    0x8a
+#define AML_CREATE_WORD_FIELD_OP     0x8b
+#define AML_CREATE_BYTE_FIELD_OP     0x8c
+#define AML_CREATE_BIT_FIELD_OP      0x8d
+#define AML_OBJECT_TYPE_OP           0x8e
+#define AML_CREATE_QWORD_FIELD_OP    0x8f
+#define AML_LAND_OP                  0x90
+#define AML_LOR_OP                   0x91
+#define AML_LNOT_OP                  0x92
+#define AML_LEQUAL_OP                0x93
+#define AML_LGREATER_OP              0x94
+#define AML_LLESS_OP                 0x95
+#define AML_TO_BUFFER_OP             0x96
+#define AML_TO_DEC_STRING_OP         0x97
+#define AML_TO_HEX_STRING_OP         0x98
+#define AML_TO_INTEGER_OP            0x99
+#define AML_TO_STRING_OP             0x9c
+#define AML_COPY_OBJECT_OP           0x9d
+#define AML_MID_OP                   0x9e
+#define AML_CONTINUE_OP              0x9f
+#define AML_IF_OP                    0xa0
+#define AML_ELSE_OP                  0xa1
+#define AML_WHILE_OP                 0xa2
+#define AML_NOOP_OP                  0xa3
+#define AML_RETURN_OP                0xa4
+#define AML_BREAK_OP                 0xa5
+#define AML_BREAK_POINT_OP           0xcc
+#define AML_ONES_OP                  0xff
+
+//
+// Extended OpCode
+//
+#define AML_EXT_OP                   0x5b
+
+#define AML_EXT_MUTEX_OP             0x01
+#define AML_EXT_EVENT_OP             0x02
+#define AML_EXT_COND_REF_OF_OP       0x12
+#define AML_EXT_CREATE_FIELD_OP      0x13
+#define AML_EXT_LOAD_TABLE_OP        0x1f
+#define AML_EXT_LOAD_OP              0x20
+#define AML_EXT_STALL_OP             0x21
+#define AML_EXT_SLEEP_OP             0x22
+#define AML_EXT_ACQUIRE_OP           0x23
+#define AML_EXT_SIGNAL_OP            0x24
+#define AML_EXT_WAIT_OP              0x25
+#define AML_EXT_RESET_OP             0x26
+#define AML_EXT_RELEASE_OP           0x27
+#define AML_EXT_FROM_BCD_OP          0x28
+#define AML_EXT_TO_BCD_OP            0x29
+#define AML_EXT_UNLOAD_OP            0x2a
+#define AML_EXT_REVISION_OP          0x30
+#define AML_EXT_DEBUG_OP             0x31
+#define AML_EXT_FATAL_OP             0x32
+#define AML_EXT_TIMER_OP             0x33
+#define AML_EXT_REGION_OP            0x80
+#define AML_EXT_FIELD_OP             0x81
+#define AML_EXT_DEVICE_OP            0x82
+#define AML_EXT_PROCESSOR_OP         0x83
+#define AML_EXT_POWER_RES_OP         0x84
+#define AML_EXT_THERMAL_ZONE_OP      0x85
+#define AML_EXT_INDEX_FIELD_OP       0x86
+#define AML_EXT_BANK_FIELD_OP        0x87
+#define AML_EXT_DATA_REGION_OP       0x88
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/AlertStandardFormatTable.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/AlertStandardFormatTable.h
new file mode 100644
index 0000000000..e7658541a3
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/AlertStandardFormatTable.h
@@ -0,0 +1,146 @@
+/** @file   
+  ACPI Alert Standard Format Description Table ASF! as described in the ASF2.0 Specification
+
+  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+**/
+
+#ifndef _ALERT_STANDARD_FORMAT_TABLE_H_
+#define _ALERT_STANDARD_FORMAT_TABLE_H_
+
+#include <IndustryStandard/Acpi.h>
+
+//
+// Ensure proper structure formats
+//
+#pragma pack (1)
+
+///
+/// Information Record header that appears at the beginning of each record
+///
+typedef struct {
+  UINT8                                Type;
+  UINT8                                Reserved;
+  UINT16                               RecordLength;
+} EFI_ACPI_ASF_RECORD_HEADER;
+
+///
+/// This structure contains information that identifies the system's type 
+/// and configuration
+///
+typedef struct {
+  EFI_ACPI_ASF_RECORD_HEADER           RecordHeader;
+  UINT8                                MinWatchDogResetValue;
+  UINT8                                MinPollingInterval;
+  UINT16                               SystemID;
+  UINT32                               IANAManufactureID;
+  UINT8                                FeatureFlags;
+  UINT8                                Reserved[3];
+} EFI_ACPI_ASF_INFO;
+
+///
+/// ASF Alert Data
+///
+typedef struct {
+  UINT8                                DeviceAddress;
+  UINT8                                Command;
+  UINT8                                DataMask;
+  UINT8                                CompareValue;
+  UINT8                                EventSenseType;
+  UINT8                                EventType;
+  UINT8                                EventOffset;
+  UINT8                                EventSourceType;
+  UINT8                                EventSeverity;
+  UINT8                                SensorNumber;
+  UINT8                                Entity;
+  UINT8                                EntityInstance;
+} EFI_ACPI_ASF_ALERTDATA;
+
+///
+/// Alert sensors definition
+///
+typedef struct {
+  EFI_ACPI_ASF_RECORD_HEADER           RecordHeader;
+  UINT8                                AssertionEventBitMask;
+  UINT8                                DeassertionEventBitMask;
+  UINT8                                NumberOfAlerts;
+  UINT8                                ArrayElementLength; ///< For ASF version 1.0 and later, this filed is set to 0x0C
+  ///
+  /// EFI_ACPI_ASF_ALERTDATA           DeviceArray[ANYSIZE_ARRAY];
+  ///
+} EFI_ACPI_ASF_ALRT;
+
+///
+/// Alert Control Data
+///
+typedef struct {
+  UINT8                                Function;
+  UINT8                                DeviceAddress;
+  UINT8                                Command;
+  UINT8                                DataValue;
+} EFI_ACPI_ASF_CONTROLDATA;       
+
+///
+/// Alert Remote Control System Actions
+///
+typedef struct {
+  EFI_ACPI_ASF_RECORD_HEADER           RecordHeader;
+  UINT8                                NumberOfControls;
+  UINT8                                ArrayElementLength; ///< For ASF version 1.0 and later, this filed is set to 0x4
+  UINT16                               RctlReserved;
+  ///
+  /// EFI_ACPI_ASF_CONTROLDATA;        DeviceArray[ANYSIZE_ARRAY];
+  ///
+} EFI_ACPI_ASF_RCTL;
+
+
+///
+/// Remote Control Capabilities
+///
+typedef struct {
+  EFI_ACPI_ASF_RECORD_HEADER           RecordHeader;
+  UINT8                                RemoteControlCapabilities[7];
+  UINT8                                RMCPCompletionCode;
+  UINT32                               RMCPIANA;
+  UINT8                                RMCPSpecialCommand;
+  UINT8                                RMCPSpecialCommandParameter[2];
+  UINT8                                RMCPBootOptions[2];
+  UINT8                                RMCPOEMParameters[2];
+} EFI_ACPI_ASF_RMCP;
+
+///
+/// SMBus Devices with fixed addresses
+///
+typedef struct {
+  EFI_ACPI_ASF_RECORD_HEADER           RecordHeader;
+  UINT8                                SEEPROMAddress;
+  UINT8                                NumberOfDevices;
+  ///
+  /// UINT8                            FixedSmbusAddresses[ANYSIZE_ARRAY];
+  ///
+} EFI_ACPI_ASF_ADDR;
+
+///
+/// ASF! Description Table Header
+///
+typedef EFI_ACPI_DESCRIPTION_HEADER EFI_ACPI_ASF_DESCRIPTION_HEADER;
+
+///
+/// The revision stored in ASF! DESCRIPTION TABLE as BCD value
+///
+#define EFI_ACPI_2_0_ASF_DESCRIPTION_TABLE_REVISION   0x20
+
+///
+/// "ASF!" ASF Description Table Signature
+///
+#define EFI_ACPI_ASF_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32 ('A', 'S', 'F', '!')
+
+#pragma pack ()
+
+#endif // _ALERT_STANDARD_FORMAT_TABLE_H
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Atapi.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Atapi.h
new file mode 100644
index 0000000000..cb1fae429f
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Atapi.h
@@ -0,0 +1,857 @@
+/** @file
+  This file contains just some basic definitions that are needed by drivers
+  that dealing with ATA/ATAPI interface.
+
+Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under 
+the terms and conditions of the BSD License that accompanies this distribution.  
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.                                          
+    
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _ATAPI_H_
+#define _ATAPI_H_
+
+#pragma pack(1)
+
+///
+/// ATA5_IDENTIFY_DATA is defined in ATA-5.
+/// (This structure is provided mainly for backward-compatibility support.
+/// Old drivers may reference fields that are marked "obsolete" in 
+/// ATA_IDENTIFY_DATA, which currently conforms to ATA-8.) 
+///
+typedef struct {    
+  UINT16  config;             ///< General Configuration.
+  UINT16  cylinders;          ///< Number of Cylinders.
+  UINT16  reserved_2; 
+  UINT16  heads;              ///< Number of logical heads. 
+  UINT16  vendor_data1; 
+  UINT16  vendor_data2; 
+  UINT16  sectors_per_track; 
+  UINT16  vendor_specific_7_9[3]; 
+  CHAR8   SerialNo[20];       ///< ASCII  
+  UINT16  vendor_specific_20_21[2];  
+  UINT16  ecc_bytes_available;    
+  CHAR8   FirmwareVer[8];     ///< ASCII  
+  CHAR8   ModelName[40];      ///< ASCII    
+  UINT16  multi_sector_cmd_max_sct_cnt; 
+  UINT16  reserved_48; 
+  UINT16  capabilities; 
+  UINT16  reserved_50;     
+  UINT16  pio_cycle_timing;    
+  UINT16  reserved_52;             
+  UINT16  field_validity;     
+  UINT16  current_cylinders; 
+  UINT16  current_heads; 
+  UINT16  current_sectors;    
+  UINT16  CurrentCapacityLsb; 
+  UINT16  CurrentCapacityMsb;     
+  UINT16  reserved_59;     
+  UINT16  user_addressable_sectors_lo; 
+  UINT16  user_addressable_sectors_hi; 
+  UINT16  reserved_62;     
+  UINT16  multi_word_dma_mode;    
+  UINT16  advanced_pio_modes; 
+  UINT16  min_multi_word_dma_cycle_time; 
+  UINT16  rec_multi_word_dma_cycle_time; 
+  UINT16  min_pio_cycle_time_without_flow_control; 
+  UINT16  min_pio_cycle_time_with_flow_control; 
+  UINT16  reserved_69_79[11];     
+  UINT16  major_version_no; 
+  UINT16  minor_version_no; 
+  UINT16  command_set_supported_82;    ///< word 82 
+  UINT16  command_set_supported_83;    ///< word 83 
+  UINT16  command_set_feature_extn;    ///< word 84 
+  UINT16  command_set_feature_enb_85;  ///< word 85 
+  UINT16  command_set_feature_enb_86;  ///< word 86 
+  UINT16  command_set_feature_default; ///< word 87 
+  UINT16  ultra_dma_mode;              ///< word 88 
+  UINT16  reserved_89_127[39]; 
+  UINT16  security_status; 
+  UINT16  vendor_data_129_159[31]; 
+  UINT16  reserved_160_255[96]; 
+} ATA5_IDENTIFY_DATA;
+
+///
+/// ATA_IDENTIFY_DATA strictly complies with ATA/ATAPI-8 Spec
+/// to define the data returned by an ATA device upon successful
+/// completion of the ATA IDENTIFY_DEVICE command.
+///
+typedef struct {
+  UINT16  config;                                  ///< General Configuration.
+  UINT16  obsolete_1;
+  UINT16  specific_config;                         ///< Specific Configuration.
+  UINT16  obsolete_3;
+  UINT16  retired_4_5[2]; 
+  UINT16  obsolete_6;
+  UINT16  cfa_reserved_7_8[2];
+  UINT16  retired_9; 
+  CHAR8   SerialNo[20];                            ///< word 10~19
+  UINT16  retired_20_21[2];  
+  UINT16  obsolete_22;    
+  CHAR8   FirmwareVer[8];                          ///< word 23~26
+  CHAR8   ModelName[40];                           ///< word 27~46
+  UINT16  multi_sector_cmd_max_sct_cnt;
+  UINT16  trusted_computing_support; 
+  UINT16  capabilities_49;
+  UINT16  capabilities_50;
+  UINT16  obsolete_51_52[2];           
+  UINT16  field_validity;     
+  UINT16  obsolete_54_58[5];     
+  UINT16  multi_sector_setting;
+  UINT16  user_addressable_sectors_lo; 
+  UINT16  user_addressable_sectors_hi; 
+  UINT16  obsolete_62;     
+  UINT16  multi_word_dma_mode;    
+  UINT16  advanced_pio_modes; 
+  UINT16  min_multi_word_dma_cycle_time; 
+  UINT16  rec_multi_word_dma_cycle_time; 
+  UINT16  min_pio_cycle_time_without_flow_control; 
+  UINT16  min_pio_cycle_time_with_flow_control; 
+  UINT16  additional_supported;                    ///< word 69
+  UINT16  reserved_70;
+  UINT16  reserved_71_74[4];                       ///< Reserved for IDENTIFY PACKET DEVICE cmd.
+  UINT16  queue_depth;     
+  UINT16  serial_ata_capabilities;
+  UINT16  reserved_77;                             ///< Reserved for Serial ATA
+  UINT16  serial_ata_features_supported;
+  UINT16  serial_ata_features_enabled;
+  UINT16  major_version_no; 
+  UINT16  minor_version_no; 
+  UINT16  command_set_supported_82;                ///< word 82
+  UINT16  command_set_supported_83;                ///< word 83
+  UINT16  command_set_feature_extn;                ///< word 84
+  UINT16  command_set_feature_enb_85;              ///< word 85
+  UINT16  command_set_feature_enb_86;              ///< word 86
+  UINT16  command_set_feature_default;             ///< word 87
+  UINT16  ultra_dma_mode;                          ///< word 88 
+  UINT16  time_for_security_erase_unit; 
+  UINT16  time_for_enhanced_security_erase_unit;
+  UINT16  advanced_power_management_level;
+  UINT16  master_password_identifier;
+  UINT16  hardware_configuration_test_result;
+  UINT16  obsolete_94;
+  UINT16  stream_minimum_request_size;
+  UINT16  streaming_transfer_time_for_dma;
+  UINT16  streaming_access_latency_for_dma_and_pio;
+  UINT16  streaming_performance_granularity[2];    ///< word 98~99
+  UINT16  maximum_lba_for_48bit_addressing[4];     ///< word 100~103
+  UINT16  streaming_transfer_time_for_pio;
+  UINT16  max_no_of_512byte_blocks_per_data_set_cmd;
+  UINT16  phy_logic_sector_support;                ///< word 106
+  UINT16  interseek_delay_for_iso7779;
+  UINT16  world_wide_name[4];                      ///< word 108~111
+  UINT16  reserved_for_128bit_wwn_112_115[4];
+  UINT16  reserved_for_technical_report;
+  UINT16  logic_sector_size_lo;                    ///< word 117
+  UINT16  logic_sector_size_hi;                    ///< word 118
+  UINT16  features_and_command_sets_supported_ext; ///< word 119
+  UINT16  features_and_command_sets_enabled_ext;   ///< word 120
+  UINT16  reserved_121_126[6];
+  UINT16  obsolete_127;
+  UINT16  security_status;                         ///< word 128
+  UINT16  vendor_specific_129_159[31]; 
+  UINT16  cfa_power_mode;                          ///< word 160
+  UINT16  reserved_for_compactflash_161_167[7];
+  UINT16  device_nominal_form_factor;
+  UINT16  is_data_set_cmd_supported;
+  CHAR8   additional_product_identifier[8];
+  UINT16  reserved_174_175[2];
+  CHAR8   media_serial_number[60];                 ///< word 176~205
+  UINT16  sct_command_transport;                   ///< word 206
+  UINT16  reserved_207_208[2];
+  UINT16  alignment_logic_in_phy_blocks;           ///< word 209
+  UINT16  write_read_verify_sector_count_mode3[2]; ///< word 210~211
+  UINT16  verify_sector_count_mode2[2];
+  UINT16  nv_cache_capabilities;
+  UINT16  nv_cache_size_in_logical_block_lsw;      ///< word 215
+  UINT16  nv_cache_size_in_logical_block_msw;      ///< word 216
+  UINT16  nominal_media_rotation_rate;
+  UINT16  reserved_218;
+  UINT16  nv_cache_options;                        ///< word 219
+  UINT16  write_read_verify_mode;                  ///< word 220
+  UINT16  reserved_221;
+  UINT16  transport_major_revision_number;
+  UINT16  transport_minor_revision_number;
+  UINT16  reserved_224_229[6];
+  UINT64  extended_no_of_addressable_sectors;
+  UINT16  min_number_per_download_microcode_mode3; ///< word 234
+  UINT16  max_number_per_download_microcode_mode3; ///< word 235
+  UINT16  reserved_236_254[19];
+  UINT16  integrity_word;
+} ATA_IDENTIFY_DATA;
+
+///
+/// ATAPI_IDENTIFY_DATA strictly complies with ATA/ATAPI-8 Spec
+/// to define the data returned by an ATAPI device upon successful
+/// completion of the ATA IDENTIFY_PACKET_DEVICE command.
+///
+typedef struct {
+  UINT16  config;                                  ///< General Configuration.
+  UINT16  reserved_1;
+  UINT16  specific_config;                         ///< Specific Configuration.
+  UINT16  reserved_3_9[7];
+  CHAR8   SerialNo[20];                            ///< word 10~19
+  UINT16  reserved_20_22[3];
+  CHAR8   FirmwareVer[8];                          ///< word 23~26
+  CHAR8   ModelName[40];                           ///< word 27~46
+  UINT16  reserved_47_48[2];
+  UINT16  capabilities_49;
+  UINT16  capabilities_50;
+  UINT16  obsolete_51;
+  UINT16  reserved_52;
+  UINT16  field_validity;                          ///< word 53
+  UINT16  reserved_54_61[8];
+  UINT16  dma_dir;
+  UINT16  multi_word_dma_mode;                     ///< word 63
+  UINT16  advanced_pio_modes;                      ///< word 64
+  UINT16  min_multi_word_dma_cycle_time;
+  UINT16  rec_multi_word_dma_cycle_time;
+  UINT16  min_pio_cycle_time_without_flow_control;
+  UINT16  min_pio_cycle_time_with_flow_control;
+  UINT16  reserved_69_70[2];
+  UINT16  obsolete_71_72[2];
+  UINT16  reserved_73_74[2];
+  UINT16  obsolete_75;
+  UINT16  serial_ata_capabilities;
+  UINT16  reserved_77;                             ///< Reserved for Serial ATA
+  UINT16  serial_ata_features_supported;
+  UINT16  serial_ata_features_enabled;
+  UINT16  major_version_no;                        ///< word 80
+  UINT16  minor_version_no;                        ///< word 81
+  UINT16  cmd_set_support_82;
+  UINT16  cmd_set_support_83;
+  UINT16  cmd_feature_support;
+  UINT16  cmd_feature_enable_85;
+  UINT16  cmd_feature_enable_86;
+  UINT16  cmd_feature_default;
+  UINT16  ultra_dma_select;
+  UINT16  time_required_for_sec_erase;             ///< word 89
+  UINT16  time_required_for_enhanced_sec_erase;    ///< word 90
+  UINT16  advanced_power_management_level;
+  UINT16  master_pwd_revison_code;
+  UINT16  hardware_reset_result;                   ///< word 93
+  UINT16  obsolete_94;
+  UINT16  reserved_95_107[13];
+  UINT16  world_wide_name[4];                      ///< word 108~111
+  UINT16  reserved_for_128bit_wwn_112_115[4];
+  UINT16  reserved_116_118[3];  
+  UINT16  command_and_feature_sets_supported;      ///< word 119
+  UINT16  command_and_feature_sets_supported_enabled;
+  UINT16  reserved_121_124[4];
+  UINT16  atapi_byte_count_0_behavior;             ///< word 125
+  UINT16  obsolete_126_127[2];
+  UINT16  security_status;
+  UINT16  reserved_129_159[31];
+  UINT16  cfa_reserved_160_175[16];
+  UINT16  reserved_176_221[46];
+  UINT16  transport_major_version;
+  UINT16  transport_minor_version;
+  UINT16  reserved_224_254[31];
+  UINT16  integrity_word;
+} ATAPI_IDENTIFY_DATA;
+
+
+///
+/// Standard Quiry Data format, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
+///
+typedef struct {
+  UINT8 peripheral_type;
+  UINT8 RMB;
+  UINT8 version;
+  UINT8 response_data_format;
+  UINT8 addnl_length;     ///< n - 4, Numbers of bytes following this one.
+  UINT8 reserved_5;
+  UINT8 reserved_6;
+  UINT8 reserved_7;
+  UINT8 vendor_info[8];
+  UINT8 product_id[16];
+  UINT8 product_revision_level[4];
+  UINT8 vendor_specific_36_55[55 - 36 + 1];
+  UINT8 reserved_56_95[95 - 56 + 1];
+  ///
+  /// Vendor-specific parameters fields. The sizeof (ATAPI_INQUIRY_DATA) is 254
+  /// since allocation_length is one byte in ATAPI_INQUIRY_CMD.
+  ///
+  UINT8 vendor_specific_96_253[253 - 96 + 1];
+} ATAPI_INQUIRY_DATA;
+
+///
+/// Request Sense Standard Data, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
+///
+typedef struct {
+  UINT8 error_code : 7;
+  UINT8 valid : 1;
+  UINT8 reserved_1;
+  UINT8 sense_key : 4;
+  UINT8 reserved_2 : 1;
+  UINT8 Vendor_specifc_1 : 3;
+  UINT8 vendor_specific_3;
+  UINT8 vendor_specific_4;
+  UINT8 vendor_specific_5;
+  UINT8 vendor_specific_6;
+  UINT8 addnl_sense_length;           ///< n - 7
+  UINT8 vendor_specific_8;
+  UINT8 vendor_specific_9;
+  UINT8 vendor_specific_10;
+  UINT8 vendor_specific_11;
+  UINT8 addnl_sense_code;             ///< mandatory
+  UINT8 addnl_sense_code_qualifier;   ///< mandatory
+  UINT8 field_replaceable_unit_code;  ///< optional
+  UINT8 sense_key_specific_15 : 7;
+  UINT8 SKSV : 1;
+  UINT8 sense_key_specific_16;
+  UINT8 sense_key_specific_17;
+} ATAPI_REQUEST_SENSE_DATA;
+
+///
+/// READ CAPACITY Data, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
+///
+typedef struct {
+  UINT8 LastLba3;
+  UINT8 LastLba2;
+  UINT8 LastLba1;
+  UINT8 LastLba0;
+  UINT8 BlockSize3;
+  UINT8 BlockSize2;
+  UINT8 BlockSize1;
+  UINT8 BlockSize0;
+} ATAPI_READ_CAPACITY_DATA;
+
+///
+/// Capacity List Header + Current/Maximum Capacity Descriptor,
+/// defined in SFF-8070i(ATAPI Removable Rewritable Specification).
+///
+typedef struct {
+  UINT8 reserved_0;
+  UINT8 reserved_1;
+  UINT8 reserved_2;
+  UINT8 Capacity_Length;
+  UINT8 LastLba3;
+  UINT8 LastLba2;
+  UINT8 LastLba1;
+  UINT8 LastLba0;
+  UINT8 DesCode : 2;
+  UINT8 reserved_9 : 6;
+  UINT8 BlockSize2;
+  UINT8 BlockSize1;
+  UINT8 BlockSize0;
+} ATAPI_READ_FORMAT_CAPACITY_DATA;
+
+///
+/// Test Unit Ready Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
+///
+typedef struct {
+  UINT8 opcode;
+  UINT8 reserved_1;
+  UINT8 reserved_2;
+  UINT8 reserved_3;
+  UINT8 reserved_4;
+  UINT8 reserved_5;
+  UINT8 reserved_6;
+  UINT8 reserved_7;
+  UINT8 reserved_8;
+  UINT8 reserved_9;
+  UINT8 reserved_10;
+  UINT8 reserved_11;
+} ATAPI_TEST_UNIT_READY_CMD;
+
+///
+/// INQUIRY Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
+///
+typedef struct {
+  UINT8 opcode;
+  UINT8 reserved_1 : 5;
+  UINT8 lun : 3;
+  UINT8 page_code;        ///< defined in SFF8090i, V6
+  UINT8 reserved_3;
+  UINT8 allocation_length;
+  UINT8 reserved_5;
+  UINT8 reserved_6;
+  UINT8 reserved_7;
+  UINT8 reserved_8;
+  UINT8 reserved_9;
+  UINT8 reserved_10;
+  UINT8 reserved_11;
+} ATAPI_INQUIRY_CMD;
+
+///
+/// REQUEST SENSE Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
+///
+typedef struct {
+  UINT8 opcode;
+  UINT8 reserved_1 : 5;
+  UINT8 lun : 3;
+  UINT8 reserved_2;
+  UINT8 reserved_3;
+  UINT8 allocation_length;
+  UINT8 reserved_5;
+  UINT8 reserved_6;
+  UINT8 reserved_7;
+  UINT8 reserved_8;
+  UINT8 reserved_9;
+  UINT8 reserved_10;
+  UINT8 reserved_11;
+} ATAPI_REQUEST_SENSE_CMD;
+
+///
+/// READ (10) Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
+///
+typedef struct {
+  UINT8 opcode;
+  UINT8 reserved_1 : 5;
+  UINT8 lun : 3;
+  UINT8 Lba0;
+  UINT8 Lba1;
+  UINT8 Lba2;
+  UINT8 Lba3;
+  UINT8 reserved_6;
+  UINT8 TranLen0;
+  UINT8 TranLen1;
+  UINT8 reserved_9;
+  UINT8 reserved_10;
+  UINT8 reserved_11;
+} ATAPI_READ10_CMD;
+
+///
+/// READ Format Capacity Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
+///
+typedef struct {
+  UINT8 opcode;
+  UINT8 reserved_1 : 5;
+  UINT8 lun : 3;
+  UINT8 reserved_2;
+  UINT8 reserved_3;
+  UINT8 reserved_4;
+  UINT8 reserved_5;
+  UINT8 reserved_6;
+  UINT8 allocation_length_hi;
+  UINT8 allocation_length_lo;
+  UINT8 reserved_9;
+  UINT8 reserved_10;
+  UINT8 reserved_11;
+} ATAPI_READ_FORMAT_CAP_CMD;
+
+///
+/// MODE SENSE Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
+///
+typedef struct {
+  UINT8 opcode;
+  UINT8 reserved_1 : 5;
+  UINT8 lun : 3;
+  UINT8 page_code : 6;
+  UINT8 page_control : 2;
+  UINT8 reserved_3;
+  UINT8 reserved_4;
+  UINT8 reserved_5;
+  UINT8 reserved_6;
+  UINT8 parameter_list_length_hi;
+  UINT8 parameter_list_length_lo;
+  UINT8 reserved_9;
+  UINT8 reserved_10;
+  UINT8 reserved_11;
+} ATAPI_MODE_SENSE_CMD;
+
+///
+/// ATAPI_PACKET_COMMAND is not defined in the ATA specification.
+/// We add it here for the convenience of ATA/ATAPI module writers. 
+///
+typedef union {
+  UINT16                    Data16[6];
+  ATAPI_TEST_UNIT_READY_CMD TestUnitReady;
+  ATAPI_READ10_CMD          Read10;
+  ATAPI_REQUEST_SENSE_CMD   RequestSence;
+  ATAPI_INQUIRY_CMD         Inquiry;
+  ATAPI_MODE_SENSE_CMD      ModeSense;
+  ATAPI_READ_FORMAT_CAP_CMD ReadFormatCapacity;
+} ATAPI_PACKET_COMMAND;
+
+#pragma pack()
+
+
+#define ATAPI_MAX_DMA_EXT_CMD_SECTORS                   0x10000
+#define ATAPI_MAX_DMA_CMD_SECTORS                       0x100
+
+//  ATA/ATAPI Signature equates
+#define ATA_SIGNATURE                                   0x0101       ///< defined in ACS-3  
+#define ATAPI_SIGNATURE                                 0xeb14       ///< defined in ACS-3
+#define ATAPI_SIGNATURE_32                              0xeb140101   ///< defined in ACS-3
+
+//  Spin Up Configuration definitions
+#define ATA_SPINUP_CFG_REQUIRED_IDD_INCOMPLETE          0x37c8   ///< defined in ACS-3
+#define ATA_SPINUP_CFG_REQUIRED_IDD_COMPLETE            0x738c   ///< defined in ACS-3
+#define ATA_SPINUP_CFG_NOT_REQUIRED_IDD_INCOMPLETE      0x8c73   ///< defined in ACS-3
+#define ATA_SPINUP_CFG_NOT_REQUIRED_IDD_COMPLETE        0xc837   ///< defined in ACS-3
+
+//
+// ATA Packet Command Code
+//
+#define ATA_CMD_FORMAT_UNIT                             0x04   ///< defined in ATAPI Removable Rewritable Media Devcies
+#define ATA_CMD_SOFT_RESET                              0x08   ///< defined from ATA-3
+#define ATA_CMD_PACKET                                  0xA0   ///< defined from ATA-3
+#define ATA_CMD_IDENTIFY_DEVICE                         0xA1   ///< defined from ATA-3
+#define ATA_CMD_SERVICE                                 0xA2   ///< defined from ATA-3
+#define ATA_CMD_TEST_UNIT_READY                         0x00   ///< defined from ATA-1
+#define ATA_CMD_REQUEST_SENSE                           0x03   ///< defined from ATA-4
+#define ATA_CMD_INQUIRY                                 0x12   ///< defined in ATAPI Removable Rewritable Media Devcies
+#define ATA_CMD_READ_FORMAT_CAPACITY                    0x23   ///< defined in ATAPI Removable Rewritable Media Devcies
+#define ATA_CMD_READ_CAPACITY                           0x25   ///< defined in ATAPI Removable Rewritable Media Devcies
+#define ATA_CMD_READ_10                                 0x28   ///< defined in ATAPI Removable Rewritable Media Devcies
+#define ATA_CMD_WRITE_10                                0x2A   ///< defined in ATAPI Removable Rewritable Media Devcies
+#define ATA_CMD_ATAPI_SEEK                              0x2B   ///< defined in ATAPI Removable Rewritable Media Devcies
+#define ATA_CMD_WRITE_AND_VERIFY                        0x2E   ///< defined in ATAPI Removable Rewritable Media Devcies
+#define ATA_CMD_VERIFY                                  0x2F   ///< defined in ATAPI Removable Rewritable Media Devcies
+#define ATA_CMD_READ_12                                 0xA8   ///< defined in ATAPI Removable Rewritable Media Devcies
+#define ATA_CMD_WRITE_12                                0xAA   ///< defined in ATAPI Removable Rewritable Media Devcies
+#define ATA_CMD_START_STOP_UNIT                         0x1B   ///< defined in ATAPI Removable Rewritable Media Devcies
+#define ATA_CMD_PREVENT_ALLOW_MEDIA_REMOVAL             0x1E   ///< defined in ATAPI Removable Rewritable Media Devcies
+#define ATA_CMD_MODE_SELECT                             0x55   ///< defined in ATAPI Removable Rewritable Media Devcies
+
+#define ATA_CMD_MODE_SENSE                              0x5A   ///< defined in ATAPI Removable Rewritable Media Devcies
+    #define ATA_PAGE_CODE_READ_WRITE_ERROR                  0x01   ///< defined in ATAPI Removable Rewritable Media Devcies
+    #define ATA_PAGE_CODE_CACHING_PAGE                      0x08   ///< defined in ATAPI Removable Rewritable Media Devcies
+    #define ATA_PAGE_CODE_REMOVABLE_BLOCK_CAPABILITIES      0x1B   ///< defined in ATAPI Removable Rewritable Media Devcies
+    #define ATA_PAGE_CODE_TIMER_PROTECT_PAGE                0x1C   ///< defined in ATAPI Removable Rewritable Media Devcies
+    #define ATA_PAGE_CODE_RETURN_ALL_PAGES                  0x3F   ///< defined in ATAPI Removable Rewritable Media Devcies
+
+#define ATA_CMD_GET_CONFIGURATION                       0x46   ///< defined in ATAPI Multimedia Devices
+   #define ATA_GCCD_RT_FIELD_VALUE_ALL                      0x00   ///< defined in ATAPI Multimedia Devices
+   #define ATA_GCCD_RT_FIELD_VALUE_CURRENT                  0x01   ///< defined in ATAPI Multimedia Devices
+   #define ATA_GCCD_RT_FIELD_VALUE_SINGLE                   0x02   ///< defined in ATAPI Multimedia Devices 
+   #define ATA_GCCD_RT_FIELD_VALUE_RESERVED                 0x03   ///< defined in ATAPI Multimedia Devices 
+   
+   #define ATA_FEATURE_LIST_PROFILE_LIST                    0x0000   ///< defined in ATAPI Multimedia Devices
+   #define ATA_FEATURE_LIST_CORE                            0x0001   ///< defined in ATAPI Multimedia Devices   
+   #define ATA_FEATURE_LIST_MORPHING                        0x0002   ///< defined in ATAPI Multimedia Devices
+   #define ATA_FEATURE_LIST_REMOVEABLE_MEDIUM               0x0003   ///< defined in ATAPI Multimedia Devices
+   #define ATA_FEATURE_LIST_WRITE_PROTECT                   0x0004   ///< defined in ATAPI Multimedia Devices
+
+///
+/// Start/Stop and Eject Operations
+///
+///@{
+#define ATA_CMD_SUBOP_STOP_DISC                         0x00   ///< Stop the Disc
+#define ATA_CMD_SUBOP_START_DISC                        0x01   ///< Start the Disc and acquire the format type
+#define ATA_CMD_SUBOP_EJECT_DISC                        0x02   ///< Eject the Disc if possible
+#define ATA_CMD_SUBOP_CLOSE_TRAY                        0x03   ///< Load the Disc (Close Tray)
+///@}
+
+//
+// ATA Commands Code
+//
+
+//
+// Class 1: PIO Data-In Commands
+//
+#define ATA_CMD_IDENTIFY_DRIVE                          0xec   ///< defined from ATA-3
+#define ATA_CMD_READ_BUFFER                             0xe4   ///< defined from ATA-1
+#define ATA_CMD_READ_SECTORS                            0x20   ///< defined from ATA-1     
+#define ATA_CMD_READ_SECTORS_WITH_RETRY                 0x21   ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_READ_LONG                               0x22   ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_READ_LONG_WITH_RETRY                    0x23   ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_READ_SECTORS_EXT                        0x24   ///< defined from ATA-6
+#define ATA_CMD_READ_MULTIPLE                           0xc4   ///< defined in ACS-3  
+#define ATA_CMD_READ_MULTIPLE_EXT                       0x29   ///< defined in ACS-3  
+#define ATA_CMD_READ_LOG_EXT                            0x2f   ///< defined in ACS-3  
+
+//
+// Class 2: PIO Data-Out Commands
+//
+#define ATA_CMD_FORMAT_TRACK                            0x50  ///< defined from ATA-1, obsoleted from ATA-4
+#define ATA_CMD_WRITE_BUFFER                            0xe8  ///< defined from ATA-1  
+#define ATA_CMD_WRITE_SECTORS                           0x30  ///< defined from ATA-1
+#define ATA_CMD_WRITE_SECTORS_WITH_RETRY                0x31  ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_WRITE_LONG                              0x32  ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_WRITE_LONG_WITH_RETRY                   0x33  ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_WRITE_VERIFY                            0x3c  ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_WRITE_SECTORS_EXT                       0x34  ///< defined from ATA-6
+#define ATA_CMD_WRITE_MULTIPLE                          0xc5  ///< defined in ACS-3  
+#define ATA_CMD_WRITE_MULTIPLE_EXT                      0x39  ///< defined in ACS-3  
+
+//
+// Class 3 No Data Command
+//
+#define ATA_CMD_ACK_MEDIA_CHANGE                        0xdb  ///< defined from ATA-1, obsoleted from ATA-5 
+#define ATA_CMD_BOOT_POST_BOOT                          0xdc  ///< defined from ATA-1, obsoleted from ATA-3
+#define ATA_CMD_BOOT_PRE_BOOT                           0xdd  ///< defined from ATA-1, obsoleted from ATA-3
+#define ATA_CMD_CHECK_POWER_MODE                        0x98  ///< defined from ATA-1, obsoleted from ATA-4
+#define ATA_CMD_CHECK_POWER_MODE_ALIAS                  0xe5  ///< defined from ATA-1
+#define ATA_CMD_DOOR_LOCK                               0xde  ///< defined from ATA-1
+#define ATA_CMD_DOOR_UNLOCK                             0xdf  ///< defined from ATA-1
+#define ATA_CMD_EXEC_DRIVE_DIAG                         0x90  ///< defined from ATA-1
+#define ATA_CMD_IDLE_ALIAS                              0x97  ///< defined from ATA-1, obsoleted from ATA-4
+#define ATA_CMD_IDLE                                    0xe3  ///< defined from ATA-1
+#define ATA_CMD_IDLE_IMMEDIATE                          0x95  ///< defined from ATA-1, obsoleted from ATA-4
+#define ATA_CMD_IDLE_IMMEDIATE_ALIAS                    0xe1  ///< defined from ATA-1
+#define ATA_CMD_INIT_DRIVE_PARAM                        0x91  ///< defined from ATA-1, obsoleted from ATA-6
+#define ATA_CMD_RECALIBRATE                             0x10  ///< defined from ATA-1, obsoleted from ATA-4
+#define ATA_CMD_READ_DRIVE_STATE                        0xe9  ///< defined from ATA-1, obsoleted from ATA-3
+#define ATA_CMD_SET_MULTIPLE_MODE                       0xC6  ///< defined from ATA-2
+#define ATA_CMD_READ_VERIFY                             0x40  ///< defined from ATA-1
+#define ATA_CMD_READ_VERIFY_WITH_RETRY                  0x41  ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_SEEK                                    0x70  ///< defined from ATA-1
+#define ATA_CMD_SET_FEATURES                            0xef  ///< defined from ATA-1
+#define ATA_CMD_STANDBY                                 0x96  ///< defined from ATA-1, obsoleted from ATA-4
+#define ATA_CMD_STANDBY_ALIAS                           0xe2  ///< defined from ATA-1
+#define ATA_CMD_STANDBY_IMMEDIATE                       0x94  ///< defined from ATA-1, obsoleted from ATA-4
+#define ATA_CMD_STANDBY_IMMEDIATE_ALIAS                 0xe0  ///< defined from ATA-1
+#define ATA_CMD_SLEEP                                   0xe6  ///< defined in ACS-3  
+#define ATA_CMD_READ_NATIVE_MAX_ADDRESS                 0xf8  ///< defined in ATA-6  
+#define ATA_CMD_READ_NATIVE_MAX_ADDRESS_EXT             0x27  ///< defined in ATA-6  
+
+//
+// Set Features Sub Command
+//
+#define ATA_SUB_CMD_ENABLE_VOLATILE_WRITE_CACHE             0x02   ///< defined in ACS-3 
+#define ATA_SUB_CMD_SET_TRANSFER_MODE                       0x03   ///< defined in ACS-3 
+#define ATA_SUB_CMD_ENABLE_APM                              0x05   ///< defined in ACS-3 
+#define ATA_SUB_CMD_ENABLE_PUIS                             0x06   ///< defined in ACS-3 
+#define ATA_SUB_CMD_PUIS_SET_DEVICE_SPINUP                  0x07   ///< defined in ACS-3 
+#define ATA_SUB_CMD_ENABLE_WRITE_READ_VERIFY                0x0b   ///< defined in ACS-3 
+#define ATA_SUB_CMD_ENABLE_SATA_FEATURE                     0x10   ///< defined in ACS-3 
+#define ATA_SUB_CMD_DISABLE_MEDIA_STATUS_NOTIFICATION       0x31   ///< defined in ACS-3 
+#define ATA_SUB_CMD_ENABLE_FREE_FALL_CONTROL                0x41   ///< defined in ACS-3 
+#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_ENABLE              0x42   ///< defined in ACS-3 
+#define ATA_SUB_CMD_SET_MAX_HOST_INTERFACE_SECTOR_TIMES     0x43   ///< defined in ACS-3 
+#define ATA_SUB_CMD_EXTENDED_POWER_CONDITIONS               0x4a   ///< defined in ACS-3 
+#define ATA_SUB_CMD_DISABLE_READ_LOOK_AHEAD                 0x55   ///< defined in ACS-3 
+#define ATA_SUB_CMD_EN_DIS_DSN_FEATURE                      0x63   ///< defined in ACS-3 
+#define ATA_SUB_CMD_DISABLE_REVERT_TO_POWER_ON_DEFAULTS     0x66   ///< defined in ACS-3 
+#define ATA_SUB_CMD_DISABLE_VOLATILE_WRITE_CACHE            0x82   ///< defined in ACS-3 
+#define ATA_SUB_CMD_DISABLE_APM                             0x85   ///< defined in ACS-3 
+#define ATA_SUB_CMD_DISABLE_PUIS                            0x86   ///< defined in ACS-3 
+#define ATA_SUB_CMD_DISABLE_WRITE_READ_VERIFY               0x8b   ///< defined in ACS-3 
+#define ATA_SUB_CMD_DISABLE_SATA_FEATURE                    0x90   ///< defined in ACS-3 
+#define ATA_SUB_CMD_ENABLE_MEDIA_STATUS_NOTIFICATION        0x95   ///< defined in ACS-3 
+#define ATA_SUB_CMD_ENABLE_READ_LOOK_AHEAD                  0xaa   ///< defined in ACS-3 
+#define ATA_SUB_CMD_DISABLE_FREE_FALL_CONTROL               0xc1   ///< defined in ACS-3 
+#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_DISABLE             0xc2   ///< defined in ACS-3 
+#define ATA_SUB_CMD_EN_DIS_SENSE_DATA_REPORTING             0xc3   ///< defined in ACS-3 
+#define ATA_SUB_CMD_ENABLE_REVERT_TO_POWER_ON_DEFAULTS      0xcc   ///< defined in ACS-3 
+
+//
+// S.M.A.R.T
+//
+#define ATA_CMD_SMART                                   0xb0  ///< defined from ATA-3
+#define ATA_CONSTANT_C2                                 0xc2  ///< reserved
+#define ATA_CONSTANT_4F                                 0x4f  ///< reserved
+
+#define ATA_SMART_READ_DATA                             0xd0   ///< defined in ACS-3 
+
+#define ATA_SMART_AUTOSAVE                              0xd2  ///< defined in ACS-3 
+    #define ATA_AUTOSAVE_DISABLE_ATTR                       0x00
+    #define ATA_AUTOSAVE_ENABLE_ATTR                        0xf1
+
+#define ATA_SMART_EXECUTE_OFFLINE_IMMEDIATE             0xd4  ///< defined in ACS-3 
+    #define ATA_EXECUTE_SMART_OFFLINE_ROUTINE               0x00  ///< defined in ACS-3
+    #define ATA_EXECUTE_SMART_OFFLINE_SHORT_SELFTEST        0x01  ///< defined in ACS-3
+    #define ATA_EXECUTE_SMART_OFFLINE_EXTENDED_SELFTEST     0x02  ///< defined in ACS-3
+    #define ATA_EXECUTE_SMART_OFFLINE_CONVEYANCE_SELFTEST   0x03  ///< defined in ACS-3
+    #define ATA_EXECUTE_SMART_OFFLINE_SELECTIVE_SELFTEST    0x04  ///< defined in ACS-3
+    #define ATA_SMART_ABORT_SELF_TEST_SUBROUTINE            0x7f  ///< defined in ACS-3
+    #define ATA_EXECUTE_SMART_CAPTIVE_SHORT_SELFTEST        0x81  ///< defined in ACS-3
+    #define ATA_EXECUTE_SMART_CAPTIVE_EXTENDED_SELFTEST     0x82  ///< defined in ACS-3
+    #define ATA_EXECUTE_SMART_CAPTIVE_CONVEYANCE_SELFTEST   0x83  ///< defined in ACS-3
+    #define ATA_EXECUTE_SMART_CAPTIVE_SELECTIVE_SELFTEST    0x84  ///< defined in ACS-3
+
+#define ATA_SMART_READLOG                               0xd5  ///< defined in ACS-3 
+#define ATA_SMART_WRITELOG                              0xd6  ///< defined in ACS-3 
+#define ATA_SMART_ENABLE_OPERATION                      0xd8  ///< reserved
+#define ATA_SMART_DISABLE_OPERATION                     0xd9  ///< defined in ACS-3 
+#define ATA_SMART_RETURN_STATUS                         0xda  ///< defined from ATA-3
+
+#define ATA_SMART_THRESHOLD_NOT_EXCEEDED_VALUE              0xc24f  ///< defined in ACS-3 
+#define ATA_SMART_THRESHOLD_EXCEEDED_VALUE                  0x2cf4  ///< defined in ACS-3 
+
+// SMART Log Definitions
+#define ATA_SMART_LOG_DIRECTORY                             0x00  ///< defined in ACS-3 
+#define ATA_SMART_SUM_SMART_ERROR_LOG                       0x01  ///< defined in ACS-3 
+#define ATA_SMART_COMP_SMART_ERROR_LOG                      0x02  ///< defined in ACS-3 
+#define ATA_SMART_EXT_COMP_SMART_ERROR_LOG                  0x03  ///< defined in ACS-3 
+#define ATA_SMART_SMART_SELFTEST_LOG                        0x06  ///< defined in ACS-3 
+#define ATA_SMART_EXT_SMART_SELFTEST_LOG                    0x07  ///< defined in ACS-3 
+#define ATA_SMART_SELECTIVE_SELFTEST_LOG                    0x09  ///< defined in ACS-3 
+#define ATA_SMART_HOST_VENDOR_SPECIFIC                      0x80  ///< defined in ACS-3 
+#define ATA_SMART_DEVICE_VENDOR_SPECIFIC                    0xa0  ///< defined in ACS-3 
+
+//
+// Class 4: DMA Command
+//
+#define ATA_CMD_READ_DMA                                0xc8   ///< defined from ATA-1
+#define ATA_CMD_READ_DMA_WITH_RETRY                     0xc9   ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_READ_DMA_EXT                            0x25   ///< defined from ATA-6
+#define ATA_CMD_WRITE_DMA                               0xca   ///< defined from ATA-1
+#define ATA_CMD_WRITE_DMA_WITH_RETRY                    0xcb   ///< defined from ATA-1, obsoleted from ATA-
+#define ATA_CMD_WRITE_DMA_EXT                           0x35   ///< defined from ATA-6
+  
+//
+//  ATA Security commands
+//
+#define ATA_CMD_SECURITY_SET_PASSWORD                   0xf1  ///< defined in ACS-3 
+#define ATA_CMD_SECURITY_UNLOCK                         0xf2  ///< defined in ACS-3 
+#define ATA_CMD_SECURITY_ERASE_PREPARE                  0xf3  ///< defined in ACS-3 
+#define ATA_CMD_SECURITY_ERASE_UNIT                     0xf4  ///< defined in ACS-3 
+#define ATA_CMD_SECURITY_FREEZE_LOCK                    0xf5  ///< defined in ACS-3 
+#define ATA_CMD_SECURITY_DISABLE_PASSWORD               0xf6  ///< defined in ACS-3 
+
+#define ATA_SECURITY_BUFFER_LENGTH                          512  ///< defined in ACS-3 
+
+//
+//  ATA Device Config Overlay
+//
+#define ATA_CMD_DEV_CONFIG_OVERLAY                      0xb1   ///< defined from ATA-6
+    #define ATA_CMD_DEV_CONFIG_RESTORE_FEATURE              0xc0   ///< defined from ATA-6
+    #define ATA_CMD_DEV_CONFIG_FREEZELOCK_FEATURE           0xc1   ///< defined from ATA-6
+    #define ATA_CMD_DEV_CONFIG_IDENTIFY_FEATURE             0xc2   ///< defined from ATA-6
+    #define ATA_CMD_DEV_CONFIG_SET_FEATURE                  0xc3   ///< defined from ATA-6
+
+//
+//  ATA Trusted Computing Feature Set Commands
+//
+#define ATA_CMD_TRUSTED_NON_DATA                        0x5b  ///< defined in ACS-3 
+#define ATA_CMD_TRUSTED_RECEIVE                         0x5c  ///< defined in ACS-3 
+#define ATA_CMD_TRUSTED_RECEIVE_DMA                     0x5d  ///< defined in ACS-3 
+#define ATA_CMD_TRUSTED_SEND                            0x5e  ///< defined in ACS-3 
+#define ATA_CMD_TRUSTED_SEND_DMA                        0x5f  ///< defined in ACS-3 
+
+//
+//  ATA Trusted Receive Fields
+//
+#define ATA_TR_RETURN_SECURITY_PROTOCOL_INFORMATION     0x00  ///< defined in ACS-3 
+#define ATA_TR_SECURITY_PROTOCOL_JEDEC_RESERVED         0xec  ///< defined in ACS-3 
+#define ATA_TR_SECURITY_PROTOCOL_SDCARD_RESERVED        0xed  ///< defined in ACS-3 
+#define ATA_TR_SECURITY_PROTOCOL_IEEE1667_RESERVED      0xee  ///< defined in ACS-3 
+
+//
+//  Equates used for Acoustic Flags
+//
+#define ATA_ACOUSTIC_LEVEL_BYPASS                       0xff   ///< defined from ATA-6
+#define ATA_ACOUSTIC_LEVEL_MAXIMUM_PERFORMANCE          0xfe   ///< defined from ATA-6
+#define ATA_ACOUSTIC_LEVEL_QUIET                        0x80   ///< defined from ATA-6
+    	
+//
+//  Equates used for DiPM Support
+//
+#define ATA_CMD_DIPM_SUB                                0x03   // defined in ACS-3 : Count value in SetFeature identification : 03h  Device-initiated interface power state transitions 
+    #define ATA_DIPM_ENABLE                                 0x10   // defined in ACS-3 
+    #define ATA_DIPM_DISABLE                                0x90   // defined in ACS-3 
+
+//
+//  Equates used for DevSleep Support
+//
+#define ATA_CMD_DEVSLEEP_SUB                            0x09   // defined in SATA 3.2 Gold Spec :  Count value in SetFeature identification : 09h  Device Sleep 
+    #define ATA_DEVSLEEP_ENABLE                             0x10   // defined in SATA 3.2 Gold Spec
+    #define ATA_DEVSLEEP_DISABLE                            0x90   // defined in SATA 3.2 Gold Spec
+
+#define ATA_DEVSLP_EXIT_TIMEOUT                             20 // MDAT - 20 ms
+#define ATA_DEVSLP_MINIMUM_DETECTION_TIME                   10 // DMDT - 10 us
+#define ATA_DEVSLP_MINIMUM_ASSERTION_TIME                   10 // DETO - 10 ms
+
+//
+//  Set MAX Commands
+//
+#define ATA_CMD_SET_MAX_ADDRESS_EXT                     0x37   ///< defined from ATA-6
+#define ATA_CMD_SET_MAX_ADDRESS                         0xf9   ///< defined from ATA-6
+    #define ATA_SET_MAX_SET_PASSWORD                        0x01   ///< defined from ATA-6
+    #define ATA_SET_MAX_LOCK                                0x02   ///< defined from ATA-6
+    #define ATA_SET_MAX_UNLOCK                              0x03   ///< defined from ATA-6
+    #define ATA_SET_MAX_FREEZE_LOCK                         0x04   ///< defined from ATA-6
+
+///
+/// Default content of device control register, disable INT,
+/// Bit3 is set to 1 according ATA-1
+///
+#define ATA_DEFAULT_CTL                                 (0x0a)  
+///
+/// Default context of Device/Head Register,
+/// Bit7 and Bit5 are set to 1 for back-compatibilities.
+///
+#define ATA_DEFAULT_CMD                                 (0xa0)
+
+#define ATAPI_MAX_BYTE_COUNT                            (0xfffe)
+
+#define ATA_REQUEST_SENSE_ERROR                         (0x70) ///< defined in SFF-8070i
+
+//
+// Sense Key, Additional Sense Codes and Additional Sense Code Qualifier
+// defined in MultiMedia Commands (MMC, MMC-2) 
+//
+// Sense Key 
+//
+#define ATA_SK_NO_SENSE                                 (0x0)
+#define ATA_SK_RECOVERY_ERROR                           (0x1)
+#define ATA_SK_NOT_READY                                (0x2)
+#define ATA_SK_MEDIUM_ERROR                             (0x3)
+#define ATA_SK_HARDWARE_ERROR                           (0x4)
+#define ATA_SK_ILLEGAL_REQUEST                          (0x5)
+#define ATA_SK_UNIT_ATTENTION                           (0x6)
+#define ATA_SK_DATA_PROTECT                             (0x7)
+#define ATA_SK_BLANK_CHECK                              (0x8)
+#define ATA_SK_VENDOR_SPECIFIC                          (0x9)
+#define ATA_SK_RESERVED_A                               (0xA)
+#define ATA_SK_ABORT                                    (0xB)
+#define ATA_SK_RESERVED_C                               (0xC)
+#define ATA_SK_OVERFLOW                                 (0xD)
+#define ATA_SK_MISCOMPARE                               (0xE)
+#define ATA_SK_RESERVED_F                               (0xF)
+
+//
+// Additional Sense Codes
+//
+#define ATA_ASC_NOT_READY                               (0x04)
+#define ATA_ASC_MEDIA_ERR1                              (0x10)
+#define ATA_ASC_MEDIA_ERR2                              (0x11)
+#define ATA_ASC_MEDIA_ERR3                              (0x14)
+#define ATA_ASC_MEDIA_ERR4                              (0x30)
+#define ATA_ASC_MEDIA_UPSIDE_DOWN                       (0x06)
+#define ATA_ASC_INVALID_CMD                             (0x20)
+#define ATA_ASC_LBA_OUT_OF_RANGE                        (0x21)
+#define ATA_ASC_INVALID_FIELD                           (0x24)
+#define ATA_ASC_WRITE_PROTECTED                         (0x27)
+#define ATA_ASC_MEDIA_CHANGE                            (0x28)
+#define ATA_ASC_RESET                                   (0x29)  ///< Power On Reset or Bus Reset occurred.
+#define ATA_ASC_ILLEGAL_FIELD                           (0x26)
+#define ATA_ASC_NO_MEDIA                                (0x3A)
+#define ATA_ASC_ILLEGAL_MODE_FOR_THIS_TRACK             (0x64)
+
+//
+// Additional Sense Code Qualifier
+//
+#define ATA_ASCQ_IN_PROGRESS                            (0x01)
+
+//
+// Error Register
+//  
+#define ATA_ERRREG_BBK                                  BIT7  ///< Bad block detected      defined from ATA-1, obsoleted from ATA-2
+#define ATA_ERRREG_UNC                                  BIT6  ///< Uncorrectable Data      defined from ATA-1, obsoleted from ATA-4
+#define ATA_ERRREG_MC                                   BIT5  ///< Media Change            defined from ATA-1, obsoleted from ATA-4
+#define ATA_ERRREG_IDNF                                 BIT4  ///< ID Not Found            defined from ATA-1, obsoleted from ATA-4
+#define ATA_ERRREG_MCR                                  BIT3  ///< Media Change Requested  defined from ATA-1, obsoleted from ATA-4
+#define ATA_ERRREG_ABRT                                 BIT2  ///< Aborted Command         defined from ATA-1
+#define ATA_ERRREG_TK0NF                                BIT1  ///< Track 0 Not Found       defined from ATA-1, obsoleted from ATA-4
+#define ATA_ERRREG_AMNF                                 BIT0  ///< Address Mark Not Found  defined from ATA-1, obsoleted from ATA-4
+
+//
+// Status Register
+//
+#define ATA_STSREG_BSY                                  BIT7  ///< Controller Busy         defined from ATA-1
+#define ATA_STSREG_DRDY                                 BIT6  ///< Drive Ready             defined from ATA-1
+#define ATA_STSREG_DWF                                  BIT5  ///< Drive Write Fault       defined from ATA-1, obsoleted from ATA-4
+#define ATA_STSREG_DF                                   BIT5  ///< Drive Fault             defined from ATA-6
+#define ATA_STSREG_DSC                                  BIT4  ///< Disk Seek Complete      defined from ATA-1, obsoleted from ATA-4
+#define ATA_STSREG_DRQ                                  BIT3  ///< Data Request            defined from ATA-1
+#define ATA_STSREG_CORR                                 BIT2  ///< Corrected Data          defined from ATA-1, obsoleted from ATA-4
+#define ATA_STSREG_IDX                                  BIT1  ///< Index                   defined from ATA-1, obsoleted from ATA-4
+#define ATA_STSREG_ERR                                  BIT0  ///< Error                   defined from ATA-1
+
+//
+// Device Control Register
+//
+#define ATA_CTLREG_SRST                                 BIT2  ///< Software Reset.
+#define ATA_CTLREG_IEN_L                                BIT1  ///< Interrupt Enable #.
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Bluetooth.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Bluetooth.h
new file mode 100644
index 0000000000..f0b6db10fe
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Bluetooth.h
@@ -0,0 +1,62 @@
+/** @file
+  This file contains the Bluetooth definitions that are consumed by drivers.
+  These definitions are from Bluetooth Core Specification Version 4.0 June, 2010
+
+  Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _BLUETOOTH_H_
+#define _BLUETOOTH_H_
+
+#pragma pack(1)
+
+///
+/// BLUETOOTH_ADDRESS
+///
+typedef struct {
+  ///
+  /// 48bit Bluetooth device address.
+  ///
+  UINT8      Address[6];
+} BLUETOOTH_ADDRESS;
+
+///
+/// BLUETOOTH_CLASS_OF_DEVICE. See Bluetooth specification for detail.
+///
+typedef struct {
+  UINT8      FormatType:2;
+  UINT8      MinorDeviceClass: 6;
+  UINT16     MajorDeviceClass: 5;
+  UINT16     MajorServiceClass:11;
+} BLUETOOTH_CLASS_OF_DEVICE;
+
+///
+/// BLUETOOTH_LE_ADDRESS
+///
+typedef struct {
+  ///
+  /// 48-bit Bluetooth device address
+  ///
+  UINT8      Address[6];
+  ///
+  /// 0x00 - Public Device Address
+  /// 0x01 - Random Device Address
+  ///
+  UINT8      Type;
+} BLUETOOTH_LE_ADDRESS;
+
+#pragma pack()
+
+#define BLUETOOTH_HCI_COMMAND_LOCAL_READABLE_NAME_MAX_SIZE    248
+
+#define BLUETOOTH_HCI_LINK_KEY_SIZE                           16
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Bmp.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Bmp.h
new file mode 100644
index 0000000000..25393911c4
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Bmp.h
@@ -0,0 +1,48 @@
+/** @file
+  This file defines BMP file header data structures.
+
+Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _BMP_H_
+#define _BMP_H_
+
+#pragma pack(1)
+
+typedef struct {
+  UINT8   Blue;
+  UINT8   Green;
+  UINT8   Red;
+  UINT8   Reserved;
+} BMP_COLOR_MAP;
+
+typedef struct {
+  CHAR8         CharB;
+  CHAR8         CharM;
+  UINT32        Size;
+  UINT16        Reserved[2];
+  UINT32        ImageOffset;
+  UINT32        HeaderSize;
+  UINT32        PixelWidth;
+  UINT32        PixelHeight;
+  UINT16        Planes;          ///< Must be 1
+  UINT16        BitPerPixel;     ///< 1, 4, 8, or 24
+  UINT32        CompressionType;
+  UINT32        ImageSize;       ///< Compressed image size in bytes
+  UINT32        XPixelsPerMeter;
+  UINT32        YPixelsPerMeter;
+  UINT32        NumberOfColors;
+  UINT32        ImportantColors;
+} BMP_IMAGE_HEADER;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/DebugPort2Table.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/DebugPort2Table.h
new file mode 100644
index 0000000000..03331069fc
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/DebugPort2Table.h
@@ -0,0 +1,79 @@
+/** @file   
+  ACPI debug port 2 table definition, defined at 
+  Microsoft DebugPort2Specification.
+
+  Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#ifndef _DEBUG_PORT_2_TABLE_H_
+#define _DEBUG_PORT_2_TABLE_H_
+
+#include <IndustryStandard/Acpi.h>
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+//
+// Debug Device Information structure.
+//
+typedef struct {
+  UINT8                                     Revision;
+  UINT16                                    Length;
+  UINT8                                     NumberofGenericAddressRegisters;
+  UINT16                                    NameSpaceStringLength;
+  UINT16                                    NameSpaceStringOffset;
+  UINT16                                    OemDataLength;
+  UINT16                                    OemDataOffset;
+  UINT16                                    PortType;
+  UINT16                                    PortSubtype;
+  UINT8                                     Reserved[2];
+  UINT16                                    BaseAddressRegisterOffset;
+  UINT16                                    AddressSizeOffset;
+} EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT;
+
+#define EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION      0x00
+
+#define EFI_ACPI_DBG2_PORT_TYPE_SERIAL                                                 0x8000
+#define   EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_FULL_16550                                 0x0000
+#define   EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_16550_SUBSET_COMPATIBLE_WITH_MS_DBGP_SPEC  0x0001
+#define   EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART                             0x0003
+#define   EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART_2X                   0x000d
+#define   EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART                      0x000e
+#define   EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_DCC                                        0x000f
+#define   EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_BCM2835_UART                               0x0010
+#define EFI_ACPI_DBG2_PORT_TYPE_1394                                                   0x8001
+#define   EFI_ACPI_DBG2_PORT_SUBTYPE_1394_STANDARD                                     0x0000
+#define EFI_ACPI_DBG2_PORT_TYPE_USB                                                    0x8002
+#define   EFI_ACPI_DBG2_PORT_SUBTYPE_USB_XHCI                                          0x0000
+#define   EFI_ACPI_DBG2_PORT_SUBTYPE_USB_EHCI                                          0x0001
+#define EFI_ACPI_DBG2_PORT_TYPE_NET                                                    0x8003
+
+//
+// Debug Port 2 Table definition.
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER               Header;
+  UINT32                                    OffsetDbgDeviceInfo;
+  UINT32                                    NumberDbgDeviceInfo;
+} EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE;
+
+#pragma pack()
+
+//
+// DBG2 Revision (defined in spec)
+//
+#define EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION      0x00
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/DebugPortTable.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/DebugPortTable.h
new file mode 100644
index 0000000000..99791c5133
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/DebugPortTable.h
@@ -0,0 +1,50 @@
+/** @file   
+  ACPI debug port table definition, defined at 
+  Microsoft DebugPortSpecification.
+
+  Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#ifndef _DEBUG_PORT_TABLE_H_
+#define _DEBUG_PORT_TABLE_H_
+
+#include <IndustryStandard/Acpi.h>
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+//
+// Debug Port Table definition.
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER               Header;
+  UINT8                                     InterfaceType;
+  UINT8                                     Reserved_37[3];
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE    BaseAddress;
+} EFI_ACPI_DEBUG_PORT_DESCRIPTION_TABLE;
+
+#pragma pack()
+
+//
+// DBGP Revision (defined in spec)
+//
+#define EFI_ACPI_DEBUG_PORT_TABLE_REVISION      0x01
+
+//
+// Interface Type
+//
+#define EFI_ACPI_DBGP_INTERFACE_TYPE_FULL_16550                                 0
+#define EFI_ACPI_DBGP_INTERFACE_TYPE_16550_SUBSET_COMPATIBLE_WITH_MS_DBGP_SPEC  1
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Dhcp.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Dhcp.h
new file mode 100644
index 0000000000..9f09753624
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Dhcp.h
@@ -0,0 +1,282 @@
+/** @file
+  This file contains the DHCPv4 and DHCPv6 option definitions and other configuration.
+  They are used to carry additional information and parameters in DHCP messages.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#ifndef _DHCP_H_
+#define _DHCP_H_
+
+///
+/// Dynamic Host Configuration Protocol for IPv4 (DHCPv4)
+///
+/// Dhcpv4 Options, definitions from RFC 2132
+///
+#define DHCP4_TAG_PAD                0    /// Pad Option
+#define DHCP4_TAG_EOP                255  /// End Option
+#define DHCP4_TAG_NETMASK            1    /// Subnet Mask
+#define DHCP4_TAG_TIME_OFFSET        2    /// Time Offset from UTC
+#define DHCP4_TAG_ROUTER             3    /// Router option,
+#define DHCP4_TAG_TIME_SERVER        4    /// Time Server
+#define DHCP4_TAG_NAME_SERVER        5    /// Name Server
+#define DHCP4_TAG_DNS_SERVER         6    /// Domain Name Server
+#define DHCP4_TAG_LOG_SERVER         7    /// Log Server
+#define DHCP4_TAG_COOKIE_SERVER      8    /// Cookie Server
+#define DHCP4_TAG_LPR_SERVER         9    /// LPR Print Server
+#define DHCP4_TAG_IMPRESS_SERVER     10   /// Impress Server
+#define DHCP4_TAG_RL_SERVER          11   /// Resource Location Server
+#define DHCP4_TAG_HOSTNAME           12   /// Host Name
+#define DHCP4_TAG_BOOTFILE_LEN       13   /// Boot File Size
+#define DHCP4_TAG_DUMP               14   /// Merit Dump File
+#define DHCP4_TAG_DOMAINNAME         15   /// Domain Name
+#define DHCP4_TAG_SWAP_SERVER        16   /// Swap Server
+#define DHCP4_TAG_ROOTPATH           17   /// Root path
+#define DHCP4_TAG_EXTEND_PATH        18   /// Extensions Path
+#define DHCP4_TAG_IPFORWARD          19   /// IP Forwarding Enable/Disable
+#define DHCP4_TAG_NONLOCAL_SRR       20   /// on-Local Source Routing Enable/Disable
+#define DHCP4_TAG_POLICY_SRR         21   /// Policy Filter
+#define DHCP4_TAG_EMTU               22   /// Maximum Datagram Reassembly Size
+#define DHCP4_TAG_TTL                23   /// Default IP Time-to-live
+#define DHCP4_TAG_PATHMTU_AGE        24   /// Path MTU Aging Timeout
+#define DHCP4_TAG_PATHMTU_PLATEAU    25   /// Path MTU Plateau Table
+#define DHCP4_TAG_IFMTU              26   /// Interface MTU
+#define DHCP4_TAG_SUBNET_LOCAL       27   /// All Subnets are Local
+#define DHCP4_TAG_BROADCAST          28   /// Broadcast Address
+#define DHCP4_TAG_DISCOVER_MASK      29   /// Perform Mask Discovery
+#define DHCP4_TAG_SUPPLY_MASK        30   /// Mask Supplier
+#define DHCP4_TAG_DISCOVER_ROUTE     31   /// Perform Router Discovery
+#define DHCP4_TAG_ROUTER_SOLICIT     32   /// Router Solicitation Address
+#define DHCP4_TAG_STATIC_ROUTE       33   /// Static Route
+#define DHCP4_TAG_TRAILER            34   /// Trailer Encapsulation
+#define DHCP4_TAG_ARPAGE             35   /// ARP Cache Timeout
+#define DHCP4_TAG_ETHER_ENCAP        36   /// Ethernet Encapsulation
+#define DHCP4_TAG_TCP_TTL            37   /// TCP Default TTL
+#define DHCP4_TAG_KEEP_INTERVAL      38   /// TCP Keepalive Interval
+#define DHCP4_TAG_KEEP_GARBAGE       39   /// TCP Keepalive Garbage
+#define DHCP4_TAG_NIS_DOMAIN         40   /// Network Information Service Domain
+#define DHCP4_TAG_NIS_SERVER         41   /// Network Information Servers
+#define DHCP4_TAG_NTP_SERVER         42   /// Network Time Protocol Servers
+#define DHCP4_TAG_VENDOR             43   /// Vendor Specific Information
+#define DHCP4_TAG_NBNS               44   /// NetBIOS over TCP/IP Name Server
+#define DHCP4_TAG_NBDD               45   /// NetBIOS Datagram Distribution Server
+#define DHCP4_TAG_NBTYPE             46   /// NetBIOS over TCP/IP Node Type
+#define DHCP4_TAG_NBSCOPE            47   /// NetBIOS over TCP/IP Scope
+#define DHCP4_TAG_XFONT              48   /// X Window System Font Server
+#define DHCP4_TAG_XDM                49   /// X Window System Display Manager
+#define DHCP4_TAG_REQUEST_IP         50   /// Requested IP Address
+#define DHCP4_TAG_LEASE              51   /// IP Address Lease Time
+#define DHCP4_TAG_OVERLOAD           52   /// Option Overload
+#define DHCP4_TAG_MSG_TYPE           53   /// DHCP Message Type
+#define DHCP4_TAG_SERVER_ID          54   /// Server Identifier
+#define DHCP4_TAG_PARA_LIST          55   /// Parameter Request List
+#define DHCP4_TAG_MESSAGE            56   /// Message
+#define DHCP4_TAG_MAXMSG             57   /// Maximum DHCP Message Size
+#define DHCP4_TAG_T1                 58   /// Renewal (T1) Time Value
+#define DHCP4_TAG_T2                 59   /// Rebinding (T2) Time Value
+#define DHCP4_TAG_VENDOR_CLASS_ID    60   /// Vendor class identifier
+#define DHCP4_TAG_CLIENT_ID          61   /// Client-identifier
+#define DHCP4_TAG_NISPLUS            64   /// Network Information Service+ Domain
+#define DHCP4_TAG_NISPLUS_SERVER     65   /// Network Information Service+ Servers
+#define DHCP4_TAG_TFTP               66   /// TFTP server name
+#define DHCP4_TAG_BOOTFILE           67   /// Bootfile name
+#define DHCP4_TAG_MOBILEIP           68   /// Mobile IP Home Agent
+#define DHCP4_TAG_SMTP               69   /// Simple Mail Transport Protocol Server
+#define DHCP4_TAG_POP3               70   /// Post Office Protocol (POP3) Server
+#define DHCP4_TAG_NNTP               71   /// Network News Transport Protocol Server
+#define DHCP4_TAG_WWW                72   /// Default World Wide Web (WWW) Server
+#define DHCP4_TAG_FINGER             73   /// Default Finger Server
+#define DHCP4_TAG_IRC                74   /// Default Internet Relay Chat (IRC) Server
+#define DHCP4_TAG_STTALK             75   /// StreetTalk Server
+#define DHCP4_TAG_STDA               76   /// StreetTalk Directory Assistance Server
+#define DHCP4_TAG_USER_CLASS_ID      77   /// User class identifier
+#define DHCP4_TAG_ARCH               93   /// Client System Architecture Type, RFC 4578
+#define DHCP4_TAG_UNDI               94   /// Client Network Interface Identifier, RFC 4578
+#define DHCP4_TAG_UUID               97   /// Client Machine Identifier, RFC 4578
+#define DHCP4_TAG_CLASSLESS_ROUTE    121  /// Classless Route
+
+
+///
+/// Dynamic Host Configuration Protocol for IPv6 (DHCPv6)
+///
+/// Enumeration of Dhcp6 message type, refers to section-5.3 of rfc-3315.
+///
+typedef enum {
+  Dhcp6MsgSolicit               = 1,
+  Dhcp6MsgAdvertise             = 2,
+  Dhcp6MsgRequest               = 3,
+  Dhcp6MsgConfirm               = 4,
+  Dhcp6MsgRenew                 = 5,
+  Dhcp6MsgRebind                = 6,
+  Dhcp6MsgReply                 = 7,
+  Dhcp6MsgRelease               = 8,
+  Dhcp6MsgDecline               = 9,
+  Dhcp6MsgReconfigure           = 10,
+  Dhcp6MsgInfoRequest           = 11
+} DHCP6_MSG_TYPE;
+
+///
+/// Enumeration of option code in Dhcp6 packet, refers to section-24.3 of rfc-3315.
+///
+typedef enum {
+  Dhcp6OptClientId              = 1,
+  Dhcp6OptServerId              = 2,
+  Dhcp6OptIana                  = 3,
+  Dhcp6OptIata                  = 4,
+  Dhcp6OptIaAddr                = 5,
+  Dhcp6OptRequestOption         = 6,
+  Dhcp6OptPreference            = 7,
+  Dhcp6OptElapsedTime           = 8,
+  Dhcp6OptReplayMessage         = 9,
+  Dhcp6OptAuthentication        = 11,
+  Dhcp6OptServerUnicast         = 12,
+  Dhcp6OptStatusCode            = 13,
+  Dhcp6OptRapidCommit           = 14,
+  Dhcp6OptUserClass             = 15,
+  Dhcp6OptVendorClass           = 16,
+  Dhcp6OptVendorInfo            = 17,
+  Dhcp6OptInterfaceId           = 18,
+  Dhcp6OptReconfigMessage       = 19,
+  Dhcp6OptReconfigureAccept     = 20
+} DHCP6_OPT_CODE;
+
+///
+/// Enumeration of status code recorded by IANA, refers to section-24.4 of rfc-3315.
+///
+typedef enum {
+  Dhcp6StsSuccess               = 0,
+  Dhcp6StsUnspecFail            = 1,
+  Dhcp6StsNoAddrsAvail          = 2,
+  Dhcp6StsNoBinding             = 3,
+  Dhcp6StsNotOnLink             = 4,
+  Dhcp6StsUseMulticast          = 5
+} DHCP6_STS_CODE;
+
+///
+/// Enumeration of Duid type recorded by IANA, refers to section-24.5 of rfc-3315.
+///
+typedef enum {
+  Dhcp6DuidTypeLlt              = 1,
+  Dhcp6DuidTypeEn               = 2,
+  Dhcp6DuidTypeLl               = 3,
+  Dhcp6DuidTypeUuid             = 4
+} DHCP6_DUID_TYPE;
+
+/// Transmission and Retransmission Parameters
+/// This section presents a table of values used to describe the message
+/// transmission behavior of clients and servers.
+///
+/// Transmit parameters of solicit message, refers to section-5.5 of rfc-3315.
+///
+#define DHCP6_SOL_MAX_DELAY       1
+#define DHCP6_SOL_IRT             1
+#define DHCP6_SOL_MRC             0
+#define DHCP6_SOL_MRT             120
+#define DHCP6_SOL_MRD             0
+///
+/// Transmit parameters of request message, refers to section-5.5 of rfc-3315.
+///
+#define DHCP6_REQ_IRT             1
+#define DHCP6_REQ_MRC             10
+#define DHCP6_REQ_MRT             30
+#define DHCP6_REQ_MRD             0
+///
+/// Transmit parameters of confirm message, refers to section-5.5 of rfc-3315.
+///
+#define DHCP6_CNF_MAX_DELAY       1
+#define DHCP6_CNF_IRT             1
+#define DHCP6_CNF_MRC             0
+#define DHCP6_CNF_MRT             4
+#define DHCP6_CNF_MRD             10
+///
+/// Transmit parameters of renew message, refers to section-5.5 of rfc-3315.
+///
+#define DHCP6_REN_IRT             10
+#define DHCP6_REN_MRC             0
+#define DHCP6_REN_MRT             600
+#define DHCP6_REN_MRD             0
+///
+/// Transmit parameters of rebind message, refers to section-5.5 of rfc-3315.
+///
+#define DHCP6_REB_IRT             10
+#define DHCP6_REB_MRC             0
+#define DHCP6_REB_MRT             600
+#define DHCP6_REB_MRD             0
+///
+/// Transmit parameters of information request message, refers to section-5.5 of rfc-3315.
+///
+#define DHCP6_INF_MAX_DELAY       1
+#define DHCP6_INF_IRT             1
+#define DHCP6_INF_MRC             0
+#define DHCP6_INF_MRT             120
+#define DHCP6_INF_MRD             0
+///
+/// Transmit parameters of release message, refers to section-5.5 of rfc-3315.
+///
+#define DHCP6_REL_IRT             1
+#define DHCP6_REL_MRC             5
+#define DHCP6_REL_MRT             0
+#define DHCP6_REL_MRD             0
+///
+/// Transmit parameters of decline message, refers to section-5.5 of rfc-3315.
+///
+#define DHCP6_DEC_IRT             1
+#define DHCP6_DEC_MRC             5
+#define DHCP6_DEC_MRT             0
+#define DHCP6_DEC_MRD             0
+
+////
+//// DHCPv6 Options, definitions from RFC 3315,RFC 5970 and RFC 3646.
+////
+#define DHCP6_OPT_CLIENT_ID         1    /// Client Identifier Option
+#define DHCP6_OPT_SERVER_ID         2    /// Server Identifier Option
+#define DHCP6_OPT_IA_NA             3    /// The Identity Association for Non-temporary Addresses option
+#define DHCP6_OPT_IA_TA             4    /// The Identity Association for the Temporary Addresses
+#define DHCP6_OPT_IAADDR            5    /// IA Address option
+#define DHCP6_OPT_ORO               6    /// Request option
+#define DHCP6_OPT_PREFERENCE        7    /// Preference option
+#define DHCP6_OPT_ELAPSED_TIME      8    /// Elapsed Time Option
+#define DHCP6_OPT_REPLAY_MSG        9    /// Relay Message option
+#define DHCP6_OPT_AUTH              11   /// Authentication option
+#define DHCP6_OPT_UNICAST           12   /// Server Unicast Option
+#define DHCP6_OPT_STATUS_CODE       13   /// Status Code Option
+#define DHCP6_OPT_RAPID_COMMIT      14   /// Rapid Commit option
+#define DHCP6_OPT_USER_CLASS        15   /// User Class option
+#define DHCP6_OPT_VENDOR_CLASS      16   /// Vendor Class Option
+#define DHCP6_OPT_VENDOR_OPTS       17   /// Vendor-specific Information Option
+#define DHCP6_OPT_INTERFACE_ID      18   /// Interface-Id Option
+#define DHCP6_OPT_RECONFIG_MSG      19   /// Reconfigure Message Option
+#define DHCP6_OPT_RECONFIG_ACCEPT   20   /// Reconfigure Accept Option
+#define DHCP6_OPT_DNS_SERVERS       23   /// DNS Configuration options, RFC 3646
+#define DHCP6_OPT_BOOT_FILE_URL     59   /// Assigned by IANA, RFC 5970
+#define DHCP6_OPT_BOOT_FILE_PARAM   60   /// Assigned by IANA, RFC 5970
+#define DHCP6_OPT_ARCH              61   /// Assigned by IANA, RFC 5970
+#define DHCP6_OPT_UNDI              62   /// Assigned by IANA, RFC 5970
+
+///
+/// Processor Architecture Types
+/// These identifiers are defined by IETF:
+/// http://www.ietf.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml
+///
+#define PXE_CLIENT_ARCH_X86_BIOS         0x0000    /// x86 BIOS for PXE
+#define PXE_CLIENT_ARCH_IPF              0x0002    /// Itanium for PXE
+#define PXE_CLIENT_ARCH_IA32             0x0006    /// x86 uefi for PXE
+#define PXE_CLIENT_ARCH_X64              0x0007    /// x64 uefi for PXE
+#define PXE_CLIENT_ARCH_EBC              0x0009    /// EBC for PXE
+#define PXE_CLIENT_ARCH_ARM              0x000A    /// Arm uefi 32 for PXE
+#define PXE_CLIENT_ARCH_AARCH64          0x000B    /// Arm uefi 64 for PXE
+
+#define HTTP_CLIENT_ARCH_IA32            0x000F    /// x86 uefi boot from http
+#define HTTP_CLIENT_ARCH_X64             0x0010    /// x64 uefi boot from http
+#define HTTP_CLIENT_ARCH_EBC             0x0011    /// EBC boot from http
+#define HTTP_CLIENT_ARCH_ARM             0x0012    /// Arm uefi 32 boot from http
+#define HTTP_CLIENT_ARCH_AARCH64         0x0013    /// Arm uefi 64 boot from http
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h
new file mode 100644
index 0000000000..0b87ad2494
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h
@@ -0,0 +1,269 @@
+/** @file
+  DMA Remapping Reporting (DMAR) ACPI table definition from Intel(R)
+  Virtualization Technology for Directed I/O (VT-D) Architecture Specification.
+
+  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Revision Reference:
+    - Intel(R) Virtualization Technology for Directed I/O (VT-D) Architecture
+      Specification v2.5, Dated November 2017.
+      http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf
+
+  @par Glossary:
+    - HPET - High Precision Event Timer
+    - NUMA - Non-uniform Memory Access
+**/
+#ifndef _DMA_REMAPPING_REPORTING_TABLE_H_
+#define _DMA_REMAPPING_REPORTING_TABLE_H_
+
+#include <IndustryStandard/Acpi.h>
+
+#pragma pack(1)
+
+///
+/// DMA-Remapping Reporting Structure definitions from section 8.1
+///@{
+#define EFI_ACPI_DMAR_REVISION                             0x01
+
+#define EFI_ACPI_DMAR_FLAGS_INTR_REMAP                     BIT0
+#define EFI_ACPI_DMAR_FLAGS_X2APIC_OPT_OUT                 BIT1
+#define EFI_ACPI_DMAR_FLAGS_DMA_CTRL_PLATFORM_OPT_IN_FLAG  BIT2
+///@}
+
+///
+/// Remapping Structure Types definitions from section 8.2
+///@{
+#define EFI_ACPI_DMAR_TYPE_DRHD                   0x00
+#define EFI_ACPI_DMAR_TYPE_RMRR                   0x01
+#define EFI_ACPI_DMAR_TYPE_ATSR                   0x02
+#define EFI_ACPI_DMAR_TYPE_RHSA                   0x03
+#define EFI_ACPI_DMAR_TYPE_ANDD                   0x04
+///@}
+
+///
+/// DMA-Remapping Hardware Unit definitions from section 8.3
+///
+#define EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL  BIT0
+
+///
+/// DMA-Remapping Device Scope Entry Structure definitions from section 8.3.1
+///@{
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT           0x01
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE             0x02
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_IOAPIC                 0x03
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_MSI_CAPABLE_HPET       0x04
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_ACPI_NAMESPACE_DEVICE  0x05
+///@}
+
+///
+/// Root Port ATS Capability Reporting Structure definitions from section 8.5
+///
+#define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS                      BIT0
+
+///
+/// Definition for DMA Remapping Structure Header
+///
+typedef struct {
+  UINT16        Type;
+  UINT16        Length;
+} EFI_ACPI_DMAR_STRUCTURE_HEADER;
+
+///
+/// Definition for DMA-Remapping PCI Path
+///
+typedef struct {
+  UINT8         Device;
+  UINT8         Function;
+} EFI_ACPI_DMAR_PCI_PATH;
+
+///
+/// Device Scope Structure is defined in section 8.3.1
+///
+typedef struct {
+  UINT8         Type;
+  UINT8         Length;
+  UINT16        Reserved2;
+  UINT8         EnumerationId;
+  UINT8         StartBusNumber;
+} EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER;
+
+/**
+  DMA-remapping hardware unit definition (DRHD) structure is defined in
+  section 8.3. This uniquely represents a remapping hardware unit present
+  in the platform. There must be at least one instance of this structure
+  for each PCI segment in the platform.
+**/
+typedef struct {
+  EFI_ACPI_DMAR_STRUCTURE_HEADER  Header;
+  /**
+    - Bit[0]: INCLUDE_PCI_ALL
+              - If Set, this remapping hardware unit has under its scope all
+                PCI compatible devices in the specified Segment, except devices
+                reported under the scope of other remapping hardware units for
+                the same Segment.
+              - If Clear, this remapping hardware unit has under its scope only
+                devices in the specified Segment that are explicitly identified
+                through the DeviceScope field.
+    - Bits[7:1] Reserved.
+  **/
+  UINT8                           Flags;
+  UINT8                           Reserved;
+  ///
+  /// The PCI Segment associated with this unit.
+  ///
+  UINT16                          SegmentNumber;
+  ///
+  /// Base address of remapping hardware register-set for this unit.
+  ///
+  UINT64                          RegisterBaseAddress;
+} EFI_ACPI_DMAR_DRHD_HEADER;
+
+/**
+  Reserved Memory Region Reporting Structure (RMRR) is described in section 8.4
+  Reserved memory ranges that may be DMA targets may be reported through the
+  RMRR structures, along with the devices that requires access to the specified
+  reserved memory region.
+**/
+typedef struct {
+  EFI_ACPI_DMAR_STRUCTURE_HEADER  Header;
+  UINT8                           Reserved[2];
+  ///
+  /// PCI Segment Number associated with devices identified through
+  /// the Device Scope field.
+  ///
+  UINT16                          SegmentNumber;
+  ///
+  /// Base address of 4KB-aligned reserved memory region
+  ///
+  UINT64                          ReservedMemoryRegionBaseAddress;
+  /**
+    Last address of the reserved memory region. Value in this field must be
+    greater than the value in Reserved Memory Region Base Address field.
+    The reserved memory region size (Limit - Base + 1) must be an integer
+    multiple of 4KB.
+  **/
+  UINT64                          ReservedMemoryRegionLimitAddress;
+} EFI_ACPI_DMAR_RMRR_HEADER;
+
+/**
+  Root Port ATS Capability Reporting (ATSR) structure is defined in section 8.5.
+  This structure is applicable only for platforms supporting Device-TLBs as
+  reported through the Extended Capability Register. For each PCI Segment in
+  the platform that supports Device-TLBs, BIOS provides an ATSR structure. The
+  ATSR structures identifies PCI-Express Root-Ports supporting Address
+  Translation Services (ATS) transactions. Software must enable ATS on endpoint
+  devices behind a Root Port only if the Root Port is reported as supporting
+  ATS transactions.
+**/
+typedef struct {
+  EFI_ACPI_DMAR_STRUCTURE_HEADER  Header;
+  /**
+    - Bit[0]: ALL_PORTS:
+              - If Set, indicates all PCI Express Root Ports in the specified
+                PCI Segment supports ATS transactions.
+              - If Clear, indicates ATS transactions are supported only on
+                Root Ports identified through the Device Scope field.
+    - Bits[7:1] Reserved.
+  **/
+  UINT8                           Flags;
+  UINT8                           Reserved;
+  ///
+  /// The PCI Segment associated with this ATSR structure
+  ///
+  UINT16                          SegmentNumber;
+} EFI_ACPI_DMAR_ATSR_HEADER;
+
+/**
+  Remapping Hardware Static Affinity (RHSA) is an optional structure defined
+  in section 8.6. This is intended to be used only on NUMA platforms with
+  Remapping hardware units and memory spanned across multiple nodes.
+  When used, there must be a RHSA structure for each Remapping hardware unit
+  reported through DRHD structure.
+**/
+typedef struct {
+  EFI_ACPI_DMAR_STRUCTURE_HEADER  Header;
+  UINT8                           Reserved[4];
+  ///
+  /// Register Base Address of this Remap hardware unit reported in the
+  /// corresponding DRHD structure.
+  ///
+  UINT64                          RegisterBaseAddress;
+  ///
+  /// Proximity Domain to which the Remap hardware unit identified by the
+  /// Register Base Address field belongs.
+  ///
+  UINT32                          ProximityDomain;
+} EFI_ACPI_DMAR_RHSA_HEADER;
+
+/**
+  An ACPI Name-space Device Declaration (ANDD) structure is defined in section
+  8.7 and uniquely represents an ACPI name-space enumerated device capable of
+  issuing DMA requests in the platform. ANDD structures are used in conjunction
+  with Device-Scope entries of type ACPI_NAMESPACE_DEVICE.
+**/
+typedef struct {
+  EFI_ACPI_DMAR_STRUCTURE_HEADER  Header;
+  UINT8                           Reserved[3];
+  /**
+    Each ACPI device enumerated through an ANDD structure must have a unique
+    value for this field. To report an ACPI device with ACPI Device Number
+    value of X, under the scope of a DRHD unit, a Device-Scope entry of type
+    ACPI_NAMESPACE_DEVICE is used with value of X in the Enumeration ID field.
+    The Start Bus Number and Path fields in the Device-Scope together
+    provides the 16-bit source-id allocated by platform for the ACPI device.
+  **/
+  UINT8                           AcpiDeviceNumber;
+} EFI_ACPI_DMAR_ANDD_HEADER;
+
+/**
+  DMA Remapping Reporting Structure Header as defined in section 8.1
+  This header will be followed by list of Remapping Structures listed below
+    - DMA Remapping Hardware Unit Definition (DRHD)
+    - Reserved Memory Region Reporting (RMRR)
+    - Root Port ATS Capability Reporting (ATSR)
+    - Remapping Hardware Static Affinity (RHSA)
+    - ACPI Name-space Device Declaration (ANDD)
+  These structure types must by reported in numerical order.
+  i.e., All remapping structures of type 0 (DRHD) enumerated before remapping
+  structures of type 1 (RMRR), and so forth.
+**/
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER     Header;
+  /**
+    This field indicates the maximum DMA physical addressability supported by
+    this platform. The system address map reported by the BIOS indicates what
+    portions of this addresses are populated. The Host Address Width (HAW) of
+    the platform is computed as (N+1), where N is the value reported in this
+    field.
+    For example, for a platform supporting 40 bits of physical addressability,
+    the value of 100111b is reported in this field.
+  **/
+  UINT8                           HostAddressWidth;
+  /**
+    - Bit[0]:   INTR_REMAP - If Clear, the platform does not support interrupt
+                remapping. If Set, the platform supports interrupt remapping.
+    - Bit[1]:   X2APIC_OPT_OUT - For firmware compatibility reasons, platform
+                firmware may Set this field to request system software to opt
+                out of enabling Extended xAPIC (X2APIC) mode. This field is
+                valid only when the INTR_REMAP field (bit 0) is Set.
+    - Bit[2]:   DMA_CTRL_PLATFORM_OPT_IN_FLAG - Platform firmware is
+                recommended to Set this field to report any platform initiated
+                DMA is restricted to only reserved memory regions (reported in
+                RMRR structures) when transferring control to system software
+                such as on ExitBootServices().
+    - Bits[7:3] Reserved.
+  **/
+  UINT8                           Flags;
+  UINT8                           Reserved[10];
+} EFI_ACPI_DMAR_HEADER;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/ElTorito.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/ElTorito.h
new file mode 100644
index 0000000000..3a3d018ac7
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/ElTorito.h
@@ -0,0 +1,147 @@
+/** @file
+  ElTorito Partitions Format Definition. 
+  This file includes some defintions from 
+  1. "El Torito" Bootable CD-ROM Format Specification, Version 1.0.
+  2. Volume and File Structure of CDROM for Information Interchange, 
+     Standard ECMA-119. (IS0 9660)
+
+Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+**/
+
+#ifndef _ELTORITO_H_
+#define _ELTORITO_H_
+
+//
+// CDROM_VOLUME_DESCRIPTOR.Types, defined in ISO 9660
+//
+#define CDVOL_TYPE_STANDARD 0x0
+#define CDVOL_TYPE_CODED    0x1
+#define CDVOL_TYPE_END      0xFF
+
+///
+/// CDROM_VOLUME_DESCRIPTOR.Id
+///
+#define CDVOL_ID  "CD001"
+
+///
+/// CDROM_VOLUME_DESCRIPTOR.SystemId
+///
+#define CDVOL_ELTORITO_ID "EL TORITO SPECIFICATION"
+
+//
+// Indicator types
+//
+#define ELTORITO_ID_CATALOG               0x01
+#define ELTORITO_ID_SECTION_BOOTABLE      0x88
+#define ELTORITO_ID_SECTION_NOT_BOOTABLE  0x00
+#define ELTORITO_ID_SECTION_HEADER        0x90
+#define ELTORITO_ID_SECTION_HEADER_FINAL  0x91
+
+//
+// ELTORITO_CATALOG.Boot.MediaTypes
+//
+#define ELTORITO_NO_EMULATION 0x00
+#define ELTORITO_12_DISKETTE  0x01
+#define ELTORITO_14_DISKETTE  0x02
+#define ELTORITO_28_DISKETTE  0x03
+#define ELTORITO_HARD_DISK    0x04
+
+
+#pragma pack(1)
+
+/// 
+/// CD-ROM Volume Descriptor
+/// 
+typedef union { 
+  struct {
+    UINT8   Type;     
+    CHAR8   Id[5];           ///< "CD001"    
+    CHAR8   Reserved[82];
+  } Unknown;
+
+  ///
+  /// Boot Record Volume Descriptor, defined in "El Torito" Specification.
+  ///
+  struct {
+    UINT8   Type;            ///< Must be 0
+    CHAR8   Id[5];           ///< "CD001" 
+    UINT8   Version;         ///< Must be 1 
+    CHAR8   SystemId[32];    ///< "EL TORITO SPECIFICATION" 
+    CHAR8   Unused[32];      ///< Must be 0 
+    UINT8   EltCatalog[4];   ///< Absolute pointer to first sector of Boot Catalog
+    CHAR8   Unused2[13];     ///< Must be 0
+  } BootRecordVolume;
+ 
+  ///
+  /// Primary Volumn Descriptor, defined in ISO 9660.
+  ///
+  struct {
+    UINT8   Type; 
+    CHAR8   Id[5];           ///< "CD001"
+    UINT8   Version; 
+    UINT8   Unused;          ///< Must be 0
+    CHAR8   SystemId[32];    
+    CHAR8   VolumeId[32];    
+    UINT8   Unused2[8];      ///< Must be 0 
+    UINT32  VolSpaceSize[2]; ///< the number of Logical Blocks
+  } PrimaryVolume;
+
+} CDROM_VOLUME_DESCRIPTOR; 
+
+///
+/// Catalog Entry
+///
+typedef union {
+  struct {
+    CHAR8       Reserved[0x20];
+  } Unknown;
+
+  ///
+  /// Catalog validation entry (Catalog header)
+  ///
+  struct {
+    UINT8   Indicator;       ///< Must be 01
+    UINT8   PlatformId;
+    UINT16  Reserved;
+    CHAR8   ManufacId[24];
+    UINT16  Checksum;
+    UINT16  Id55AA;
+  } Catalog;
+
+  ///
+  /// Initial/Default Entry or Section Entry
+  ///
+  struct {
+    UINT8   Indicator;       ///< 88 = Bootable, 00 = Not Bootable
+    UINT8   MediaType : 4;
+    UINT8   Reserved1 : 4;   ///< Must be 0
+    UINT16  LoadSegment;
+    UINT8   SystemType;
+    UINT8   Reserved2;       ///< Must be 0
+    UINT16  SectorCount;
+    UINT32  Lba;
+  } Boot;
+
+  ///
+  /// Section Header Entry
+  ///
+  struct {
+    UINT8   Indicator;       ///< 90 - Header, more header follw, 91 - Final Header
+    UINT8   PlatformId;
+    UINT16  SectionEntries;  ///< Number of section entries following this header
+    CHAR8   Id[28];
+  } Section;
+
+} ELTORITO_CATALOG;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Emmc.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Emmc.h
new file mode 100644
index 0000000000..ad0ca55d77
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Emmc.h
@@ -0,0 +1,297 @@
+/** @file
+  Header file for eMMC support.
+
+  This header file contains some definitions defined in EMMC4.5/EMMC5.0 spec.
+
+  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __EMMC_H__
+#define __EMMC_H__
+
+//
+// EMMC command index
+//
+#define  EMMC_GO_IDLE_STATE           0
+#define  EMMC_SEND_OP_COND            1
+#define  EMMC_ALL_SEND_CID            2
+#define  EMMC_SET_RELATIVE_ADDR       3
+#define  EMMC_SET_DSR                 4
+#define  EMMC_SLEEP_AWAKE             5
+#define  EMMC_SWITCH                  6
+#define  EMMC_SELECT_DESELECT_CARD    7
+#define  EMMC_SEND_EXT_CSD            8
+#define  EMMC_SEND_CSD                9
+#define  EMMC_SEND_CID                10
+#define  EMMC_STOP_TRANSMISSION       12
+#define  EMMC_SEND_STATUS             13
+#define  EMMC_BUSTEST_R               14
+#define  EMMC_GO_INACTIVE_STATE       15
+#define  EMMC_SET_BLOCKLEN            16
+#define  EMMC_READ_SINGLE_BLOCK       17
+#define  EMMC_READ_MULTIPLE_BLOCK     18
+#define  EMMC_BUSTEST_W               19
+#define  EMMC_SEND_TUNING_BLOCK       21
+#define  EMMC_SET_BLOCK_COUNT         23
+#define  EMMC_WRITE_BLOCK             24
+#define  EMMC_WRITE_MULTIPLE_BLOCK    25
+#define  EMMC_PROGRAM_CID             26
+#define  EMMC_PROGRAM_CSD             27
+#define  EMMC_SET_WRITE_PROT          28
+#define  EMMC_CLR_WRITE_PROT          29
+#define  EMMC_SEND_WRITE_PROT         30
+#define  EMMC_SEND_WRITE_PROT_TYPE    31
+#define  EMMC_ERASE_GROUP_START       35
+#define  EMMC_ERASE_GROUP_END         36
+#define  EMMC_ERASE                   38
+#define  EMMC_FAST_IO                 39
+#define  EMMC_GO_IRQ_STATE            40
+#define  EMMC_LOCK_UNLOCK             42
+#define  EMMC_SET_TIME                49
+#define  EMMC_PROTOCOL_RD             53
+#define  EMMC_PROTOCOL_WR             54
+#define  EMMC_APP_CMD                 55
+#define  EMMC_GEN_CMD                 56
+
+typedef enum {
+  EmmcPartitionUserData              = 0,
+  EmmcPartitionBoot1                 = 1,
+  EmmcPartitionBoot2                 = 2,
+  EmmcPartitionRPMB                  = 3,
+  EmmcPartitionGP1                   = 4,
+  EmmcPartitionGP2                   = 5,
+  EmmcPartitionGP3                   = 6,
+  EmmcPartitionGP4                   = 7,
+  EmmcPartitionUnknown
+} EMMC_PARTITION_TYPE;
+
+#pragma pack(1)
+typedef struct {
+  UINT8   NotUsed:1;                              // Not used [0:0]
+  UINT8   Crc:7;                                  // CRC [7:1]
+  UINT8   ManufacturingDate;                      // Manufacturing date [15:8]
+  UINT8   ProductSerialNumber[4];                 // Product serial number [47:16]
+  UINT8   ProductRevision;                        // Product revision [55:48]
+  UINT8   ProductName[6];                         // Product name [103:56]
+  UINT8   OemId;                                  // OEM/Application ID [111:104]
+  UINT8   DeviceType:2;                           // Device/BGA [113:112]
+  UINT8   Reserved:6;                             // Reserved [119:114]
+  UINT8   ManufacturerId;                         // Manufacturer ID [127:120]
+} EMMC_CID;
+
+typedef struct {
+  UINT32  NotUsed:1;                              // Not used [0:0]
+  UINT32  Crc:7;                                  // CRC [7:1]
+  UINT32  Ecc:2;                                  // ECC code [9:8]
+  UINT32  FileFormat:2;                           // File format [11:10]
+  UINT32  TmpWriteProtect:1;                      // Temporary write protection [12:12]
+  UINT32  PermWriteProtect:1;                     // Permanent write protection [13:13]
+  UINT32  Copy:1;                                 // Copy flag (OTP) [14:14]
+  UINT32  FileFormatGrp:1;                        // File format group [15:15]
+  UINT32  ContentProtApp:1;                       // Content protection application [16:16]
+  UINT32  Reserved:4;                             // Reserved [20:17]
+  UINT32  WriteBlPartial:1;                       // Partial blocks for write allowed [21:21]
+  UINT32  WriteBlLen:4;                           // Max. write data block length [25:22]
+  UINT32  R2WFactor:3;                            // Write speed factor [28:26]
+  UINT32  DefaultEcc:2;                           // Manufacturer default ECC [30:29]
+  UINT32  WpGrpEnable:1;                          // Write protect group enable [31:31]
+
+  UINT32  WpGrpSize:5;                            // Write protect group size [36:32]
+  UINT32  EraseGrpMult:5;                         // Erase group size multiplier [41:37]
+  UINT32  EraseGrpSize:5;                         // Erase group size [46:42]
+  UINT32  CSizeMult:3;                            // Device size multiplier [49:47]
+  UINT32  VddWCurrMax:3;                          // Max. write current @ VDD max [52:50]
+  UINT32  VddWCurrMin:3;                          // Max. write current @ VDD min [55:53]
+  UINT32  VddRCurrMax:3;                          // Max. read current @ VDD max [58:56]
+  UINT32  VddRCurrMin:3;                          // Max. read current @ VDD min [61:59]
+  UINT32  CSizeLow:2;                             // Device size low two bits [63:62]
+
+  UINT32  CSizeHigh:10;                           // Device size high eight bits [73:64]
+  UINT32  Reserved1:2;                            // Reserved [75:74]
+  UINT32  DsrImp:1;                               // DSR implemented [76:76]
+  UINT32  ReadBlkMisalign:1;                      // Read block misalignment [77:77]
+  UINT32  WriteBlkMisalign:1;                     // Write block misalignment [78:78]
+  UINT32  ReadBlPartial:1;                        // Partial blocks for read allowed [79:79]
+  UINT32  ReadBlLen:4;                            // Max. read data block length [83:80]
+  UINT32  Ccc:12;                                 // Device command classes [95:84]
+
+  UINT32  TranSpeed:8;                            // Max. bus clock frequency [103:96]
+  UINT32  Nsac:8;                                 // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
+  UINT32  Taac:8;                                 // Data read access-time 1 [119:112]
+  UINT32  Reserved2:2;                            // Reserved [121:120]
+  UINT32  SpecVers:4;                             // System specification version [125:122]
+  UINT32  CsdStructure:2;                         // CSD structure [127:126]
+} EMMC_CSD;
+
+typedef struct {
+  //
+  // Modes Segment
+  //
+  UINT8   Reserved[16];                           // Reserved [15:0]
+  UINT8   SecureRemovalType;                      // Secure Removal Type R/W & R [16]
+  UINT8   ProductStateAwarenessEnablement;        // Product state awareness enablement R/W/E & R [17]
+  UINT8   MaxPreLoadingDataSize[4];               // Max pre loading data size R [21:18]
+  UINT8   PreLoadingDataSize[4];                  // Pre loading data size R/W/EP [25:22]
+  UINT8   FfuStatus;                              // FFU status R [26]
+  UINT8   Reserved1[2];                           // Reserved [28:27]
+  UINT8   ModeOperationCodes;                     // Mode operation codes W/EP [29]
+  UINT8   ModeConfig;                             // Mode config R/W/EP [30]
+  UINT8   Reserved2;                              // Reserved [31]
+  UINT8   FlushCache;                             // Flushing of the cache W/EP [32]
+  UINT8   CacheCtrl;                              // Control to turn the Cache ON/OFF R/W/EP [33]
+  UINT8   PowerOffNotification;                   // Power Off Notification R/W/EP [34]
+  UINT8   PackedFailureIndex;                     // Packed command failure index R [35]
+  UINT8   PackedCommandStatus;                    // Packed command status R [36]
+  UINT8   ContextConf[15];                        // Context configuration R/W/EP [51:37]
+  UINT8   ExtPartitionsAttribute[2];              // Extended Partitions Attribute R/W [53:52]
+  UINT8   ExceptionEventsStatus[2];               // Exception events status R [55:54]
+  UINT8   ExceptionEventsCtrl[2];                 // Exception events control R/W/EP [57:56]
+  UINT8   DyncapNeeded;                           // Number of addressed group to be Released R [58]
+  UINT8   Class6Ctrl;                             // Class 6 commands control R/W/EP [59]
+  UINT8   IniTimeoutEmu;                          // 1st initialization after disabling sector size emulation R [60]
+  UINT8   DataSectorSize;                         // Sector size R [61]
+  UINT8   UseNativeSector;                        // Sector size emulation R/W [62]
+  UINT8   NativeSectorSize;                       // Native sector size R [63]
+  UINT8   VendorSpecificField[64];                // Vendor Specific Fields <vendor specific> [127:64]
+  UINT8   Reserved3[2];                           // Reserved [129:128]
+  UINT8   ProgramCidCsdDdrSupport;                // Program CID/CSD in DDR mode support R [130]
+  UINT8   PeriodicWakeup;                         // Periodic Wake-up R/W/E [131]
+  UINT8   TcaseSupport;                           // Package Case Temperature is controlled W/EP [132]
+  UINT8   ProductionStateAwareness;               // Production state awareness R/W/E [133]
+  UINT8   SecBadBlkMgmnt;                         // Bad Block Management mode R/W [134]
+  UINT8   Reserved4;                              // Reserved [135]
+  UINT8   EnhStartAddr[4];                        // Enhanced User Data Start Address R/W [139:136]
+  UINT8   EnhSizeMult[3];                         // Enhanced User Data Area Size R/W [142:140]
+  UINT8   GpSizeMult[12];                         // General Purpose Partition Size R/W [154:143]
+  UINT8   PartitionSettingCompleted;              // Partitioning Setting R/W [155]
+  UINT8   PartitionsAttribute;                    // Partitions attribute R/W [156]
+  UINT8   MaxEnhSizeMult[3];                      // Max Enhanced Area Size R [159:157]
+  UINT8   PartitioningSupport;                    // Partitioning Support R [160]
+  UINT8   HpiMgmt;                                // HPI management R/W/EP [161]
+  UINT8   RstFunction;                            // H/W reset function R/W [162]
+  UINT8   BkopsEn;                                // Enable background operations handshake R/W [163]
+  UINT8   BkopsStart;                             // Manually start background operations W/EP [164]
+  UINT8   SanitizeStart;                          // Start Sanitize operation W/EP [165]
+  UINT8   WrRelParam;                             // Write reliability parameter register R [166]
+  UINT8   WrRelSet;                               // Write reliability setting register R/W [167]
+  UINT8   RpmbSizeMult;                           // RPMB Size R [168]
+  UINT8   FwConfig;                               // FW configuration R/W [169]
+  UINT8   Reserved5;                              // Reserved [170]
+  UINT8   UserWp;                                 // User area write protection register R/W,R/W/CP&R/W/EP [171]
+  UINT8   Reserved6;                              // Reserved [172]
+  UINT8   BootWp;                                 // Boot area write protection register R/W&R/W/CP[173]
+  UINT8   BootWpStatus;                           // Boot write protection status registers R [174]
+  UINT8   EraseGroupDef;                          // High-density erase group definition R/W/EP [175]
+  UINT8   Reserved7;                              // Reserved [176]
+  UINT8   BootBusConditions;                      // Boot bus Conditions R/W/E [177]
+  UINT8   BootConfigProt;                         // Boot config protection R/W&R/W/CP[178]
+  UINT8   PartitionConfig;                        // Partition configuration R/W/E&R/W/EP[179]
+  UINT8   Reserved8;                              // Reserved [180]
+  UINT8   ErasedMemCont;                          // Erased memory content R [181]
+  UINT8   Reserved9;                              // Reserved [182]
+  UINT8   BusWidth;                               // Bus width mode W/EP [183]
+  UINT8   Reserved10;                             // Reserved [184]
+  UINT8   HsTiming;                               // High-speed interface timing R/W/EP [185]
+  UINT8   Reserved11;                             // Reserved [186]
+  UINT8   PowerClass;                             // Power class R/W/EP [187]
+  UINT8   Reserved12;                             // Reserved [188]
+  UINT8   CmdSetRev;                              // Command set revision R [189]
+  UINT8   Reserved13;                             // Reserved [190]
+  UINT8   CmdSet;                                 // Command set R/W/EP [191]
+  //
+  // Properties Segment
+  //
+  UINT8   ExtCsdRev;                              // Extended CSD revision [192]
+  UINT8   Reserved14;                             // Reserved [193]
+  UINT8   CsdStructure;                           // CSD STRUCTURE [194]
+  UINT8   Reserved15;                             // Reserved [195]
+  UINT8   DeviceType;                             // Device type [196]
+  UINT8   DriverStrength;                         // I/O Driver Strength [197]
+  UINT8   OutOfInterruptTime;                     // Out-of-interrupt busy timing[198]
+  UINT8   PartitionSwitchTime;                    // Partition switching timing [199]
+  UINT8   PwrCl52M195V;                           // Power class for 52MHz at 1.95V [200]
+  UINT8   PwrCl26M195V;                           // Power class for 26MHz at 1.95V [201]
+  UINT8   PwrCl52M360V;                           // Power class for 52MHz at 3.6V [202]
+  UINT8   PwrCl26M360V;                           // Power class for 26MHz at 3.6V [203]
+  UINT8   Reserved16;                             // Reserved [204]
+  UINT8   MinPerfR4B26M;                          // Minimum Read Performance for 4bit at 26MHz [205]
+  UINT8   MinPerfW4B26M;                          // Minimum Write Performance for 4bit at 26MHz [206]
+  UINT8   MinPerfR8B26M4B52M;                     // Minimum Read Performance for 8bit at 26MHz, for 4bit at 52MHz [207]
+  UINT8   MinPerfW8B26M4B52M;                     // Minimum Write Performance for 8bit at 26MHz, for 4bit at 52MHz [208]
+  UINT8   MinPerfR8B52M;                          // Minimum Read Performance for 8bit at 52MHz [209]
+  UINT8   MinPerfW8B52M;                          // Minimum Write Performance for 8bit at 52MHz [210]
+  UINT8   Reserved17;                             // Reserved [211]
+  UINT8   SecCount[4];                            // Sector Count [215:212]
+  UINT8   SleepNotificationTime;                  // Sleep Notification Timout [216]
+  UINT8   SATimeout;                              // Sleep/awake timeout [217]
+  UINT8   ProductionStateAwarenessTimeout;        // Production state awareness timeout [218]
+  UINT8   SCVccq;                                 // Sleep current (VCCQ) [219]
+  UINT8   SCVcc;                                  // Sleep current (VCC) [220]
+  UINT8   HcWpGrpSize;                            // High-capacity write protect group size [221]
+  UINT8   RelWrSecC;                              // Reliable write sector count [222]
+  UINT8   EraseTimeoutMult;                       // High-capacity erase timeout [223]
+  UINT8   HcEraseGrpSize;                         // High-capacity erase unit size [224]
+  UINT8   AccSize;                                // Access size [225]
+  UINT8   BootSizeMult;                           // Boot partition size [226]
+  UINT8   Reserved18;                             // Reserved [227]
+  UINT8   BootInfo;                               // Boot information [228]
+  UINT8   SecTrimMult;                            // Secure TRIM Multiplier [229]
+  UINT8   SecEraseMult;                           // Secure Erase Multiplier [230]
+  UINT8   SecFeatureSupport;                      // Secure Feature support [231]
+  UINT8   TrimMult;                               // TRIM Multiplier [232]
+  UINT8   Reserved19;                             // Reserved [233]
+  UINT8   MinPerfDdrR8b52M;                       // Minimum Read Performance for 8bit at 52MHz in DDR mode [234]
+  UINT8   MinPerfDdrW8b52M;                       // Minimum Write Performance for 8bit at 52MHz in DDR mode [235]
+  UINT8   PwrCl200M130V;                          // Power class for 200MHz, at VCCQ=1.3V, VCC = 3.6V [236]
+  UINT8   PwrCl200M195V;                          // Power class for 200MHz at VCCQ=1.95V, VCC = 3.6V [237]
+  UINT8   PwrClDdr52M195V;                        // Power class for 52MHz, DDR at VCC= 1.95V [238]
+  UINT8   PwrClDdr52M360V;                        // Power class for 52MHz, DDR at VCC= 3.6V [239]
+  UINT8   Reserved20;                             // Reserved [240]
+  UINT8   IniTimeoutAp;                           // 1st initialization time after partitioning [241]
+  UINT8   CorrectlyPrgSectorsNum[4];              // Number of correctly programmed sectors [245:242]
+  UINT8   BkopsStatus;                            // Background operations status [246]
+  UINT8   PowerOffLongTime;                       // Power off notification(long) timeout [247]
+  UINT8   GenericCmd6Time;                        // Generic CMD6 timeout [248]
+  UINT8   CacheSize[4];                           // Cache size [252:249]
+  UINT8   PwrClDdr200M360V;                       // Power class for 200MHz, DDR at VCC= 3.6V [253]
+  UINT8   FirmwareVersion[8];                     // Firmware version [261:254]
+  UINT8   DeviceVersion[2];                       // Device version [263:262]
+  UINT8   OptimalTrimUnitSize;                    // Optimal trim unit size[264]
+  UINT8   OptimalWriteSize;                       // Optimal write size [265]
+  UINT8   OptimalReadSize;                        // Optimal read size [266]
+  UINT8   PreEolInfo;                             // Pre EOL information [267]
+  UINT8   DeviceLifeTimeEstTypA;                  // Device life time estimation type A [268]
+  UINT8   DeviceLifeTimeEstTypB;                  // Device life time estimation type B [269]
+  UINT8   VendorProprietaryHealthReport[32];      // Vendor proprietary health report [301:270]
+  UINT8   NumOfFwSectorsProgrammed[4];            // Number of FW sectors correctly programmed [305:302]
+  UINT8   Reserved21[181];                        // Reserved [486:306]
+  UINT8   FfuArg[4];                              // FFU Argument [490:487]
+  UINT8   OperationCodeTimeout;                   // Operation codes timeout [491]
+  UINT8   FfuFeatures;                            // FFU features [492]
+  UINT8   SupportedModes;                         // Supported modes [493]
+  UINT8   ExtSupport;                             // Extended partitions attribute support [494]
+  UINT8   LargeUnitSizeM1;                        // Large Unit size [495]
+  UINT8   ContextCapabilities;                    // Context management capabilities [496]
+  UINT8   TagResSize;                             // Tag Resources Size [497]
+  UINT8   TagUnitSize;                            // Tag Unit Size [498]
+  UINT8   DataTagSupport;                         // Data Tag Support [499]
+  UINT8   MaxPackedWrites;                        // Max packed write commands [500]
+  UINT8   MaxPackedReads;                         // Max packed read commands[501]
+  UINT8   BkOpsSupport;                           // Background operations support [502]
+  UINT8   HpiFeatures;                            // HPI features [503]
+  UINT8   SupportedCmdSet;                        // Supported Command Sets [504]
+  UINT8   ExtSecurityErr;                         // Extended Security Commands Error [505]
+  UINT8   Reserved22[6];                          // Reserved [511:506]
+} EMMC_EXT_CSD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h
new file mode 100644
index 0000000000..97b1c45edf
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h
@@ -0,0 +1,52 @@
+/** @file
+  ACPI high precision event timer table definition, at www.intel.com
+  Specification name is IA-PC HPET (High Precision Event Timers) Specification.
+    
+  Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+**/
+
+#ifndef _HIGH_PRECISION_EVENT_TIMER_TABLE_H_
+#define _HIGH_PRECISION_EVENT_TIMER_TABLE_H_
+
+#include <IndustryStandard/Acpi.h>
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// High Precision Event Timer Table header definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  UINT32                                  EventTimerBlockId;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  BaseAddressLower32Bit;
+  UINT8                                   HpetNumber;
+  UINT16                                  MainCounterMinimumClockTickInPeriodicMode;
+  UINT8                                   PageProtectionAndOemAttribute;
+} EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER;
+
+///
+/// HPET Revision (defined in spec)
+///
+#define EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION  0x01
+
+//
+// Page protection setting
+// Values 3 through 15 are reserved for use by the specification
+//
+#define EFI_ACPI_NO_PAGE_PROTECTION   0
+#define EFI_ACPI_4KB_PAGE_PROTECTION  1
+#define EFI_ACPI_64KB_PAGE_PROTECTION 2
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Hsti.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Hsti.h
new file mode 100644
index 0000000000..711e2523e1
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Hsti.h
@@ -0,0 +1,82 @@
+/** @file
+  Support for HSTI 1.1a specification, defined at
+  Microsoft Hardware Security Testability Specification.
+
+  Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __HSTI_H__
+#define __HSTI_H__
+
+#pragma pack(1)
+
+#define ADAPTER_INFO_PLATFORM_SECURITY_GUID \
+  {0x6be272c7, 0x1320, 0x4ccd, { 0x90, 0x17, 0xd4, 0x61, 0x2c, 0x01, 0x2b, 0x25 }}
+
+#define PLATFORM_SECURITY_VERSION_VNEXTCS         0x00000003
+
+#define PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE 0x00000001  // IHV
+#define PLATFORM_SECURITY_ROLE_PLATFORM_IBV       0x00000002
+#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_OEM    0x00000003 
+#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_ODM    0x00000004  
+
+typedef struct {
+  //
+  //  Return PLATFORM_SECURITY_VERSION_VNEXTCS
+  //
+  UINT32  Version;
+  //
+  // The role of the publisher of this interface.  Reference platform designers
+  // such as IHVs and IBVs are expected to return PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE
+  // and PLATFORM_SECURITY_ROLE_PLATFORM_IBV respectively.
+  // If the test modules from the designers are unable to fully verify all
+  // security features, then the platform implementers, OEMs and ODMs, will
+  // need to publish this interface with a role of Implementer.
+  //
+  UINT32  Role;
+  //
+  // Human readable vendor, model, & version of this implementation.
+  //
+  CHAR16  ImplementationID[256];
+  //
+  // The size in bytes of the SecurityFeaturesRequired and SecurityFeaturesEnabled arrays.
+  // The arrays must be the same size.
+  //
+  UINT32  SecurityFeaturesSize;
+  //
+  // IHV-defined bitfield corresponding to all security features which must be
+  // implemented to meet the security requirements defined by PLATFORM_SECURITY_VERSION Version.
+  //
+//UINT8   SecurityFeaturesRequired[];     //Ignored for non-IHV
+  //
+  // Publisher-defined bitfield corresponding to all security features which
+  // have implemented programmatic tests in this module.
+  //
+//UINT8   SecurityFeaturesImplemented[];
+  //
+  // Publisher-defined bitfield corresponding to all security features which
+  // have been verified implemented by this implementation.
+  //
+//UINT8   SecurityFeaturesVerified[];
+  //
+  // A Null-terminated string, one failure per line (CR/LF terminated), with a
+  // unique identifier that the OEM/ODM can use to locate the documentation
+  // which will describe the steps to remediate the failure - a URL to the
+  // documentation is recommended.
+  //
+//CHAR16  ErrorString[];
+} ADAPTER_INFO_PLATFORM_SECURITY;
+
+#pragma pack()
+
+extern EFI_GUID gAdapterInfoPlatformSecurityGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Http11.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Http11.h
new file mode 100644
index 0000000000..797e74e4d4
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Http11.h
@@ -0,0 +1,254 @@
+/** @file
+  Hypertext Transfer Protocol -- HTTP/1.1 Standard definitions, from RFC 2616    
+
+  This file contains common HTTP 1.1 definitions from RFC 2616 
+   
+  (C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#ifndef __HTTP_11_H__
+#define __HTTP_11_H__
+
+#pragma pack(1)
+
+///
+/// HTTP Version (currently HTTP 1.1)
+/// 
+/// The version of an HTTP message is indicated by an HTTP-Version field
+/// in the first line of the message.
+///
+#define HTTP_VERSION        "HTTP/1.1"
+
+///
+/// HTTP Request Method definitions
+/// 
+/// The Method  token indicates the method to be performed on the
+/// resource identified by the Request-URI. The method is case-sensitive.
+///
+#define HTTP_METHOD_OPTIONS "OPTIONS"
+#define HTTP_METHOD_GET     "GET"
+#define HTTP_METHOD_HEAD    "HEAD"
+#define HTTP_METHOD_POST    "POST"
+#define HTTP_METHOD_PUT     "PUT"
+#define HTTP_METHOD_DELETE  "DELETE"
+#define HTTP_METHOD_TRACE   "TRACE"
+#define HTTP_METHOD_CONNECT "CONNECT"
+#define HTTP_METHOD_PATCH   "PATCH"
+
+///
+/// Connect method has maximum length according to EFI_HTTP_METHOD defined in
+/// UEFI2.5 spec so use this.
+///
+#define HTTP_METHOD_MAXIMUM_LEN  sizeof (HTTP_METHOD_CONNECT)
+
+///
+/// Accept Request Header
+/// The Accept request-header field can be used to specify certain media types which are 
+/// acceptable for the response. Accept headers can be used to indicate that the request 
+/// is specifically limited to a small set of desired types, as in the case of a request 
+/// for an in-line image.
+///
+#define HTTP_HEADER_ACCEPT             "Accept"
+
+
+/// 
+/// Accept-Charset Request Header
+/// The Accept-Charset request-header field can be used to indicate what character sets 
+/// are acceptable for the response. This field allows clients capable of understanding 
+/// more comprehensive or special-purpose character sets to signal that capability to a 
+/// server which is capable of representing documents in those character sets.
+///
+#define HTTP_HEADER_ACCEPT_CHARSET     "Accept-Charset"
+
+/// 
+/// Accept-Language Request Header
+/// The Accept-Language request-header field is similar to Accept, 
+/// but restricts the set of natural languages that are preferred 
+/// as a response to the request.
+///
+#define HTTP_HEADER_ACCEPT_LANGUAGE    "Accept-Language"
+
+///
+/// Accept-Ranges Request Header
+/// The Accept-Ranges response-header field allows the server to
+/// indicate its acceptance of range requests for a resource:
+///
+#define HTTP_HEADER_ACCEPT_RANGES      "Accept-Ranges"
+
+
+/// 
+/// Accept-Encoding Request Header
+/// The Accept-Encoding request-header field is similar to Accept, 
+/// but restricts the content-codings that are acceptable in the response.
+///
+#define HTTP_HEADER_ACCEPT_ENCODING    "Accept-Encoding"
+
+///
+/// Content-Encoding Header
+/// The Content-Encoding entity-header field is used as a modifier to the media-type. 
+/// When present, its value indicates what additional content codings have been applied 
+/// to the entity-body, and thus what decoding mechanisms must be applied in order to 
+/// obtain the media-type referenced by the Content-Type header field. Content-Encoding 
+/// is primarily used to allow a document to be compressed without losing the identity 
+/// of its underlying media type.
+///
+#define HTTP_HEADER_CONTENT_ENCODING   "Content-Encoding"
+
+/// 
+/// HTTP Content-Encoding Compression types
+///
+
+#define HTTP_CONTENT_ENCODING_IDENTITY "identity"  /// No transformation is used. This is the default value for content coding.
+#define HTTP_CONTENT_ENCODING_GZIP     "gzip"      /// Content-Encoding: GNU zip format (described in RFC 1952).
+#define HTTP_CONTENT_ENCODING_COMPRESS "compress"  /// encoding format produced by the common UNIX file compression program "compress". 
+#define HTTP_CONTENT_ENCODING_DEFLATE  "deflate"   /// The "zlib" format defined in RFC 1950 in combination with the "deflate" 
+                                                   /// compression mechanism described in RFC 1951.
+
+
+///
+/// Content-Type Header
+/// The Content-Type entity-header field indicates the media type of the entity-body sent to 
+/// the recipient or, in the case of the HEAD method, the media type that would have been sent 
+/// had the request been a GET.
+///
+#define HTTP_HEADER_CONTENT_TYPE       "Content-Type"
+//
+// Common Media Types defined in http://www.iana.org/assignments/media-types/media-types.xhtml
+//
+#define HTTP_CONTENT_TYPE_APP_JSON          "application/json"
+#define HTTP_CONTENT_TYPE_APP_OCTET_STREAM  "application/octet-stream"
+                                           
+#define HTTP_CONTENT_TYPE_TEXT_HTML         "text/html"
+#define HTTP_CONTENT_TYPE_TEXT_PLAIN        "text/plain"
+#define HTTP_CONTENT_TYPE_TEXT_CSS          "text/css"
+#define HTTP_CONTENT_TYPE_TEXT_XML          "text/xml"
+                                           
+#define HTTP_CONTENT_TYPE_IMAGE_GIF         "image/gif"
+#define HTTP_CONTENT_TYPE_IMAGE_JPEG        "image/jpeg"
+#define HTTP_CONTENT_TYPE_IMAGE_PNG         "image/png"
+#define HTTP_CONTENT_TYPE_IMAGE_SVG_XML     "image/svg+xml"
+
+
+///
+/// Content-Length Header
+/// The Content-Length entity-header field indicates the size of the entity-body, 
+/// in decimal number of OCTETs, sent to the recipient or, in the case of the HEAD 
+/// method, the size of the entity-body that would have been sent had the request been a GET.
+///
+#define HTTP_HEADER_CONTENT_LENGTH     "Content-Length"
+                                                                                                              
+///
+/// Transfer-Encoding Header
+/// The Transfer-Encoding general-header field indicates what (if any) type of transformation 
+/// has been applied to the message body in order to safely transfer it between the sender 
+/// and the recipient. This differs from the content-coding in that the transfer-coding 
+/// is a property of the message, not of the entity.
+///
+#define HTTP_HEADER_TRANSFER_ENCODING  "Transfer-Encoding"
+
+
+///
+/// User Agent Request Header
+/// 
+/// The User-Agent request-header field contains information about the user agent originating 
+/// the request. This is for statistical purposes, the tracing of protocol violations, and 
+/// automated recognition of user agents for the sake of tailoring responses to avoid 
+/// particular user agent limitations. User agents SHOULD include this field with requests. 
+/// The field can contain multiple product tokens and comments identifying the agent and any 
+/// subproducts which form a significant part of the user agent. 
+/// By convention, the product tokens are listed in order of their significance for 
+/// identifying the application.
+///
+#define HTTP_HEADER_USER_AGENT         "User-Agent"
+
+///
+/// Host Request Header
+///
+/// The Host request-header field specifies the Internet host and port number of the resource 
+/// being requested, as obtained from the original URI given by the user or referring resource 
+///
+#define HTTP_HEADER_HOST              "Host"
+
+///
+/// Location Response Header
+/// 
+/// The Location response-header field is used to redirect the recipient to a location other than 
+/// the Request-URI for completion of the request or identification of a new resource. 
+/// For 201 (Created) responses, the Location is that of the new resource which was created by 
+/// the request. For 3xx responses, the location SHOULD indicate the server's preferred URI for 
+/// automatic redirection to the resource. The field value consists of a single absolute URI.
+///
+#define HTTP_HEADER_LOCATION           "Location"
+
+///
+/// The If-Match request-header field is used with a method to make it conditional.
+/// A client that has one or more entities previously obtained from the resource 
+/// can verify that one of those entities is current by including a list of their 
+/// associated entity tags in the If-Match header field. 
+/// The purpose of this feature is to allow efficient updates of cached information 
+/// with a minimum amount of transaction overhead. It is also used, on updating requests, 
+/// to prevent inadvertent modification of the wrong version of a resource. 
+/// As a special case, the value "*" matches any current entity of the resource.
+///
+#define HTTP_HEADER_IF_MATCH          "If-Match"
+
+
+///
+/// The If-None-Match request-header field is used with a method to make it conditional. 
+/// A client that has one or more entities previously obtained from the resource can verify 
+/// that none of those entities is current by including a list of their associated entity 
+/// tags in the If-None-Match header field. The purpose of this feature is to allow efficient 
+/// updates of cached information with a minimum amount of transaction overhead. It is also used 
+/// to prevent a method (e.g. PUT) from inadvertently modifying an existing resource when the 
+/// client believes that the resource does not exist.
+///
+#define HTTP_HEADER_IF_NONE_MATCH     "If-None-Match"
+
+
+
+/// 
+/// Authorization Request Header
+/// The Authorization field value consists of credentials
+/// containing the authentication information of the user agent for
+/// the realm of the resource being requested.
+///
+#define HTTP_HEADER_AUTHORIZATION     "Authorization"
+
+///
+/// ETAG Response Header
+/// The ETag response-header field provides the current value of the entity tag 
+/// for the requested variant. 
+///
+#define HTTP_HEADER_ETAG              "ETag"
+
+///
+/// Custom header field checked by the iLO web server to
+/// specify a client session key.
+/// Example:     X-Auth-Token: 24de6b1f8fa147ad59f6452def628798
+///
+#define  HTTP_HEADER_X_AUTH_TOKEN      "X-Auth-Token"
+
+///
+/// Expect Header
+/// The "Expect" header field in a request indicates a certain set of
+/// behaviors (expectations) that need to be supported by the server in
+/// order to properly handle this request. The only such expectation
+/// defined by this specification is 100-continue.
+///
+#define  HTTP_HEADER_EXPECT            "Expect"
+
+///
+/// Expect Header Value
+///
+#define  HTTP_EXPECT_100_CONTINUE       "100-continue"
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h
new file mode 100644
index 0000000000..d542b2c412
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h
@@ -0,0 +1,167 @@
+/** @file
+  The definition for iSCSI Boot Firmware Table, it's defined in Microsoft's
+  iSCSI Boot Firmware Table(iBFT) as Defined in ACPI 3.0b Specification. 
+  
+  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+**/
+
+#ifndef _ISCSI_BOOT_FIRMWARE_TABLE_H_
+#define _ISCSI_BOOT_FIRMWARE_TABLE_H_
+
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_REVISION            0x01
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_ALIGNMENT 8
+
+///
+/// Structure Type/ID
+///
+#define  EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_RESERVED_STRUCTURE_ID         0
+#define  EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_ID          1
+#define  EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_ID        2
+#define  EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_ID              3
+#define  EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_ID           4
+#define  EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_EXTERNSIONS_STRUCTURE_ID      5
+
+///
+/// from the definition of IP_PREFIX_ORIGIN Enumeration in MSDN,
+/// not defined in Microsoft iBFT document.
+///
+typedef enum {
+  IpPrefixOriginOther = 0,
+  IpPrefixOriginManual,
+  IpPrefixOriginWellKnown,
+  IpPrefixOriginDhcp,
+  IpPrefixOriginRouterAdvertisement,
+  IpPrefixOriginUnchanged = 16
+} IP_PREFIX_VALUE;
+
+#pragma pack(1)
+
+///
+/// iBF Table Header
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+  UINT8   Revision;
+  UINT8   Checksum;
+  UINT8   OemId[6];
+  UINT64  OemTableId;
+  UINT8   Reserved[24];
+} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_HEADER;
+
+///
+/// Common Header of Boot Firmware Table Structure 
+///
+typedef struct {
+  UINT8   StructureId;
+  UINT8   Version;
+  UINT16  Length;
+  UINT8   Index;
+  UINT8   Flags;
+} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER;
+
+///
+/// Control Structure
+///
+typedef struct {
+  EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER  Header;
+  UINT16                                               Extensions;
+  UINT16                                               InitiatorOffset;
+  UINT16                                               NIC0Offset;
+  UINT16                                               Target0Offset;
+  UINT16                                               NIC1Offset;
+  UINT16                                               Target1Offset;  
+} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE;
+
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_VERSION              0x1
+
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_FLAG_BOOT_FAILOVER   BIT0
+
+///
+/// Initiator Structure
+///
+typedef struct {
+  EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER  Header;
+  EFI_IPv6_ADDRESS                                     ISnsServer;
+  EFI_IPv6_ADDRESS                                     SlpServer;
+  EFI_IPv6_ADDRESS                                     PrimaryRadiusServer;
+  EFI_IPv6_ADDRESS                                     SecondaryRadiusServer;
+  UINT16                                               IScsiNameLength;
+  UINT16                                               IScsiNameOffset;
+} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE;
+
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_VERSION             0x1
+
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BLOCK_VALID    BIT0 
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BOOT_SELECTED  BIT1 
+
+///
+/// NIC Structure
+///
+typedef struct {
+  EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER  Header;
+  EFI_IPv6_ADDRESS                                     Ip;
+  UINT8                                                SubnetMaskPrefixLength;
+  UINT8                                                Origin;
+  EFI_IPv6_ADDRESS                                     Gateway;
+  EFI_IPv6_ADDRESS                                     PrimaryDns;
+  EFI_IPv6_ADDRESS                                     SecondaryDns;
+  EFI_IPv6_ADDRESS                                     DhcpServer;
+  UINT16                                               VLanTag;
+  UINT8                                                Mac[6];
+  UINT16                                               PciLocation;
+  UINT16                                               HostNameLength;
+  UINT16                                               HostNameOffset;
+} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE;
+
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_VERSION                 0x1
+
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BLOCK_VALID        BIT0
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BOOT_SELECTED      BIT1
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_GLOBAL             BIT2
+
+///
+/// Target Structure
+///
+typedef struct {
+  EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER  Header;
+  EFI_IPv6_ADDRESS                                     Ip;
+  UINT16                                               Port;
+  UINT8                                                BootLun[8];
+  UINT8                                                CHAPType;
+  UINT8                                                NicIndex;
+  UINT16                                               IScsiNameLength;
+  UINT16                                               IScsiNameOffset;
+  UINT16                                               CHAPNameLength;
+  UINT16                                               CHAPNameOffset;
+  UINT16                                               CHAPSecretLength;
+  UINT16                                               CHAPSecretOffset;
+  UINT16                                               ReverseCHAPNameLength;
+  UINT16                                               ReverseCHAPNameOffset;
+  UINT16                                               ReverseCHAPSecretLength;
+  UINT16                                               ReverseCHAPSecretOffset;
+} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE;
+
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_VERSION               0x1
+
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BLOCK_VALID      BIT0
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BOOT_SELECTED    BIT1
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_CHAP      BIT2
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_RCHAP     BIT3
+
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_CHAP_TYPE_NO_CHAP        0
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_CHAP_TYPE_CHAP           1
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_CHAP_TYPE_MUTUAL_CHAP    2
+
+#pragma pack()
+
+#endif
+
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IoRemappingTable.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IoRemappingTable.h
new file mode 100644
index 0000000000..bed8e1d7d3
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IoRemappingTable.h
@@ -0,0 +1,198 @@
+/** @file
+  ACPI IO Remapping Table (IORT) as specified in ARM spec DEN0049C
+
+  http://infocenter.arm.com/help/topic/com.arm.doc.den0049c/DEN0049C_IO_Remapping_Table.pdf
+
+  Copyright (c) 2017, Linaro Limited. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#ifndef __IO_REMAPPING_TABLE_H__
+#define __IO_REMAPPING_TABLE_H__
+
+#include <IndustryStandard/Acpi.h>
+
+#define EFI_ACPI_IO_REMAPPING_TABLE_REVISION        0x0
+
+#define EFI_ACPI_IORT_TYPE_ITS_GROUP                0x0
+#define EFI_ACPI_IORT_TYPE_NAMED_COMP               0x1
+#define EFI_ACPI_IORT_TYPE_ROOT_COMPLEX             0x2
+#define EFI_ACPI_IORT_TYPE_SMMUv1v2                 0x3
+#define EFI_ACPI_IORT_TYPE_SMMUv3                   0x4
+#define EFI_ACPI_IORT_TYPE_PMCG                     0x5
+
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA           BIT0
+
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_TR         BIT0
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_WA         BIT1
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_RA         BIT2
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_AHO        BIT3
+
+#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM          BIT0
+#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS         BIT1
+
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v1             0x0
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v2             0x1
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU400         0x2
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500         0x3
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU401         0x4
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_CAVIUM_THX_v2  0x5
+
+#define EFI_ACPI_IORT_SMMUv1v2_FLAG_DVM             BIT0
+#define EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK        BIT1
+
+#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL       0x0
+#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_EDGE        0x1
+
+#define EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE    BIT0
+#define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE     BIT1
+
+#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED  0x0
+#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED    0x1
+
+#define EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE       BIT0
+
+#pragma pack(1)
+
+///
+/// Table header
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  UINT32                                  NumNodes;
+  UINT32                                  NodeOffset;
+  UINT32                                  Reserved;
+} EFI_ACPI_6_0_IO_REMAPPING_TABLE;
+
+///
+/// Definition for ID mapping table shared by all node types
+///
+typedef struct {
+  UINT32                                  InputBase;
+  UINT32                                  NumIds;
+  UINT32                                  OutputBase;
+  UINT32                                  OutputReference;
+  UINT32                                  Flags;
+} EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE;
+
+///
+/// Node header definition shared by all node types
+///
+typedef struct {
+  UINT8                                   Type;
+  UINT16                                  Length;
+  UINT8                                   Revision;
+  UINT32                                  Reserved;
+  UINT32                                  NumIdMappings;
+  UINT32                                  IdReference;
+} EFI_ACPI_6_0_IO_REMAPPING_NODE;
+
+///
+/// Node type 0: ITS node
+///
+typedef struct {
+  EFI_ACPI_6_0_IO_REMAPPING_NODE          Node;
+
+  UINT32                                  NumItsIdentifiers;
+//UINT32                                  ItsIdentifiers[NumItsIdentifiers];
+} EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE;
+
+///
+/// Node type 1: root complex node
+///
+typedef struct {
+  EFI_ACPI_6_0_IO_REMAPPING_NODE          Node;
+
+  UINT32                                  CacheCoherent;
+  UINT8                                   AllocationHints;
+  UINT16                                  Reserved;
+  UINT8                                   MemoryAccessFlags;
+
+  UINT32                                  AtsAttribute;
+  UINT32                                  PciSegmentNumber;
+} EFI_ACPI_6_0_IO_REMAPPING_RC_NODE;
+
+///
+/// Node type 2: named component node
+///
+typedef struct {
+  EFI_ACPI_6_0_IO_REMAPPING_NODE          Node;
+
+  UINT32                                  Flags;
+  UINT32                                  CacheCoherent;
+  UINT8                                   AllocationHints;
+  UINT16                                  Reserved;
+  UINT8                                   MemoryAccessFlags;
+  UINT8                                   AddressSizeLimit;
+//UINT8                                   ObjectName[];
+} EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE;
+
+///
+/// Node type 3: SMMUv1 or SMMUv2 node
+///
+typedef struct {
+  UINT32                                  Interrupt;
+  UINT32                                  InterruptFlags;
+} EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT;
+
+typedef struct {
+  EFI_ACPI_6_0_IO_REMAPPING_NODE          Node;
+
+  UINT64                                  Base;
+  UINT64                                  Span;
+  UINT32                                  Model;
+  UINT32                                  Flags;
+  UINT32                                  GlobalInterruptArrayRef;
+  UINT32                                  NumContextInterrupts;
+  UINT32                                  ContextInterruptArrayRef;
+  UINT32                                  NumPmuInterrupts;
+  UINT32                                  PmuInterruptArrayRef;
+
+  UINT32                                  SMMU_NSgIrpt;
+  UINT32                                  SMMU_NSgIrptFlags;
+  UINT32                                  SMMU_NSgCfgIrpt;
+  UINT32                                  SMMU_NSgCfgIrptFlags;
+
+//EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT  ContextInterrupt[NumContextInterrupts];
+//EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT  PmuInterrupt[NumPmuInterrupts];
+} EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE;
+
+///
+/// Node type 4: SMMUv4 node
+///
+typedef struct {
+  EFI_ACPI_6_0_IO_REMAPPING_NODE          Node;
+
+  UINT64                                  Base;
+  UINT32                                  Flags;
+  UINT32                                  Reserved;
+  UINT64                                  VatosAddress;
+  UINT32                                  Model;
+  UINT32                                  Event;
+  UINT32                                  Pri;
+  UINT32                                  Gerr;
+  UINT32                                  Sync;
+} EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE;
+
+///
+/// Node type 5: PMCG node
+///
+typedef struct {
+  EFI_ACPI_6_0_IO_REMAPPING_NODE          Node;
+
+  UINT64                                  Base;
+  UINT32                                  OverflowInterruptGsiv;
+  UINT32                                  NodeReference;
+//EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE      OverflowInterruptMsiMapping[1];
+} EFI_ACPI_6_0_IO_REMAPPING_PMCG_NODE;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Ipmi.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Ipmi.h
new file mode 100644
index 0000000000..4cb7494d7b
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Ipmi.h
@@ -0,0 +1,29 @@
+/** @file
+  IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
+
+  See IPMI specification, Appendix G, Command Assignments
+  and Appendix H, Sub-function Assignments.
+
+  Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#ifndef _IPMI_H_
+#define _IPMI_H_
+
+#include <IndustryStandard/IpmiNetFnChassis.h>
+#include <IndustryStandard/IpmiNetFnBridge.h>
+#include <IndustryStandard/IpmiNetFnSensorEvent.h>
+#include <IndustryStandard/IpmiNetFnApp.h>
+#include <IndustryStandard/IpmiNetFnFirmware.h>
+#include <IndustryStandard/IpmiNetFnStorage.h>
+#include <IndustryStandard/IpmiNetFnTransport.h>
+#include <IndustryStandard/IpmiNetFnGroupExtension.h>
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnApp.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnApp.h
new file mode 100644
index 0000000000..2d2d8e7c36
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnApp.h
@@ -0,0 +1,623 @@
+/** @file
+  IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
+
+  This file contains all NetFn App commands, including:
+    IPM Device "Global" Commands (Chapter 20)
+    Firmware Firewall & Command Discovery Commands (Chapter 21)
+    BMC Watchdog Timer Commands (Chapter 27)
+    IPMI Messaging Support Commands (Chapter 22)
+    RMCP+ Support and Payload Commands (Chapter 24)
+
+  See IPMI specification, Appendix G, Command Assignments
+  and Appendix H, Sub-function Assignments.
+
+  Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#ifndef _IPMI_NET_FN_APP_H_
+#define _IPMI_NET_FN_APP_H_
+
+#pragma pack(1)
+//
+// Net function definition for App command
+//
+#define IPMI_NETFN_APP  0x06
+
+//
+//  Below is Definitions for IPM Device "Global" Commands  (Chapter 20)
+//
+
+//
+//  Definitions for Get Device ID command
+//
+#define IPMI_APP_GET_DEVICE_ID 0x1
+
+//
+//  Constants and Structure definitions for "Get Device ID" command to follow here
+//
+typedef struct {
+  UINT8   CompletionCode;
+  UINT8   DeviceId;
+  UINT8   DeviceRevision : 4;
+  UINT8   Reserved : 3;
+  UINT8   DeviceSdr : 1;
+  UINT8   MajorFirmwareRev : 7;
+  UINT8   UpdateMode : 1;
+  UINT8   MinorFirmwareRev;
+  UINT8   SpecificationVersion;
+  UINT8   SensorDeviceSupport : 1;
+  UINT8   SdrRepositorySupport : 1;
+  UINT8   SelDeviceSupport : 1;
+  UINT8   FruInventorySupport : 1;
+  UINT8   IpmbMessageReceiver : 1;
+  UINT8   IpmbMessageGenerator : 1;
+  UINT8   BridgeSupport : 1;
+  UINT8   ChassisSupport : 1;
+  UINT8   ManufacturerId[3];
+  UINT16  ProductId;
+  UINT32  AuxFirmwareRevInfo;
+} IPMI_GET_DEVICE_ID_RESPONSE;
+
+
+//
+//  Definitions for Cold Reset command
+//
+#define IPMI_APP_COLD_RESET  0x2
+
+//
+//  Constants and Structure definitions for "Cold Reset" command to follow here
+//
+
+//
+//  Definitions for Warm Reset command
+//
+#define IPMI_APP_WARM_RESET  0x3
+
+//
+//  Constants and Structure definitions for "Warm Reset" command to follow here
+//
+
+//
+//  Definitions for Get Self Results command
+//
+#define IPMI_APP_GET_SELFTEST_RESULTS  0x4
+
+//
+//  Constants and Structure definitions for "Get Self Test Results" command to follow here
+//
+typedef struct {
+  UINT8  CompletionCode;
+  UINT8  Result;
+  UINT8  Param;
+} IPMI_SELF_TEST_RESULT_RESPONSE;
+
+#define IPMI_APP_SELFTEST_NO_ERROR             0x55
+#define IPMI_APP_SELFTEST_NOT_IMPLEMENTED      0x56
+#define IPMI_APP_SELFTEST_ERROR                0x57
+#define IPMI_APP_SELFTEST_FATAL_HW_ERROR       0x58
+#define IPMI_APP_SELFTEST_INACCESSIBLE_SEL     0x80
+#define IPMI_APP_SELFTEST_INACCESSIBLE_SDR     0x40
+#define IPMI_APP_SELFTEST_INACCESSIBLE_FRU     0x20
+#define IPMI_APP_SELFTEST_IPMB_SIGNAL_FAIL     0x10
+#define IPMI_APP_SELFTEST_SDR_REPOSITORY_EMPTY 0x08
+#define IPMI_APP_SELFTEST_FRU_CORRUPT          0x04
+#define IPMI_APP_SELFTEST_FW_BOOTBLOCK_CORRUPT 0x02
+#define IPMI_APP_SELFTEST_FW_CORRUPT           0x01
+
+//
+//  Definitions for Manufacturing Test ON command
+//
+#define IPMI_APP_MANUFACTURING_TEST_ON 0x5
+
+//
+//  Constants and Structure definitions for "Manufacturing Test ON" command to follow here
+//
+
+//
+//  Definitions for Set ACPI Power State command
+//
+#define IPMI_APP_SET_ACPI_POWERSTATE 0x6
+
+//
+//  Constants and Structure definitions for "Set ACPI Power State" command to follow here
+//
+typedef struct {
+  UINT8  AcpiSystemPowerState  : 7;
+  UINT8  AcpiSystemStateChange : 1;
+  UINT8  AcpiDevicePowerState  : 7;
+  UINT8  AcpiDeviceStateChange : 1;
+} IPMI_SET_ACPI_POWER_STATE_REQUEST;
+
+//
+//  Definitions for Get ACPI Power State command
+//
+#define IPMI_APP_GET_ACPI_POWERSTATE 0x7
+
+//
+//  Constants and Structure definitions for "Get ACPI Power State" command to follow here
+//
+
+//
+//  Definitions for Get Device GUID command
+//
+#define IPMI_APP_GET_DEVICE_GUID 0x8
+
+//
+//  Constants and Structure definitions for "Get Device GUID" command to follow here
+//
+//
+//  Message structure definition for "Get Device Guid" IPMI command
+//
+typedef struct {
+  UINT8  CompletionCode;
+  UINT8  Guid[16];
+} IPMI_GET_DEVICE_GUID_RESPONSE;
+
+//
+//  Below is Definitions for BMC Watchdog Timer Commands (Chapter 27)
+//
+
+//
+//  Definitions for Reset WatchDog Timer command
+//
+#define IPMI_APP_RESET_WATCHDOG_TIMER  0x22
+
+//
+//  Constants and Structure definitions for "Reset WatchDog Timer" command to follow here
+//
+typedef struct {
+  UINT8 TimerUse : 3;
+  UINT8 Reserved : 3;
+  UINT8 TimerRunning : 1;
+  UINT8 TimerUseExpirationFlagLog : 1;
+} IPMI_WATCHDOG_TIMER_USE;
+
+//
+//  Definitions for Set WatchDog Timer command
+//
+#define IPMI_APP_SET_WATCHDOG_TIMER  0x24
+
+//
+//  Constants and Structure definitions for "Set WatchDog Timer" command to follow here
+//
+typedef struct {
+  IPMI_WATCHDOG_TIMER_USE         TimerUse;
+  UINT8                           TimerActions;
+  UINT8                           PretimeoutInterval;
+  UINT8                           TimerUseExpirationFlagsClear;
+  UINT16                          InitialCountdownValue;
+} IPMI_SET_WATCHDOG_TIMER_REQUEST;
+
+//
+//  Definitions for Get WatchDog Timer command
+//
+#define IPMI_APP_GET_WATCHDOG_TIMER  0x25
+
+//
+//  Constants and Structure definitions for "Get WatchDog Timer" command to follow here
+//
+typedef struct {
+  UINT8                           CompletionCode;
+  IPMI_WATCHDOG_TIMER_USE         TimerUse;
+  UINT8                           TimerActions;
+  UINT8                           PretimeoutInterval;
+  UINT8                           TimerUseExpirationFlagsClear;
+  UINT16                          InitialCountdownValue;
+  UINT16                          PresentCountdownValue;
+} IPMI_GET_WATCHDOG_TIMER_RESPONSE;
+
+//
+//  Below is Definitions for IPMI Messaging Support Commands (Chapter 22)
+//
+
+//
+//  Definitions for Set BMC Global Enables command
+//
+#define IPMI_APP_SET_BMC_GLOBAL_ENABLES  0x2E
+
+//
+//  Constants and Structure definitions for "Set BMC Global Enables " command to follow here
+//
+
+//
+//  Definitions for Get BMC Global Enables command
+//
+#define IPMI_APP_GET_BMC_GLOBAL_ENABLES  0x2F
+
+//
+//  Constants and Structure definitions for "Get BMC Global Enables " command to follow here
+//
+
+//
+//  Definitions for Clear Message Flags command
+//
+#define IPMI_APP_CLEAR_MESSAGE_FLAGS 0x30
+
+//
+//  Constants and Structure definitions for "Clear Message Flags" command to follow here
+//
+
+//
+//  Definitions for Get Message Flags command
+//
+#define IPMI_APP_GET_MESSAGE_FLAGS 0x31
+
+//
+//  Constants and Structure definitions for "Get Message Flags" command to follow here
+//
+
+//
+//  Definitions for Enable Message Channel Receive command
+//
+#define IPMI_APP_ENABLE_MESSAGE_CHANNEL_RECEIVE  0x32
+
+//
+//  Constants and Structure definitions for "Enable Message Channel Receive" command to follow here
+//
+
+//
+//  Definitions for Get Message command
+//
+#define IPMI_APP_GET_MESSAGE 0x33
+
+//
+//  Constants and Structure definitions for "Get Message" command to follow here
+//
+
+//
+//  Definitions for Send Message command
+//
+#define IPMI_APP_SEND_MESSAGE  0x34
+
+//
+//  Constants and Structure definitions for "Send Message" command to follow here
+//
+
+//
+//  Definitions for Read Event Message Buffer command
+//
+#define IPMI_APP_READ_EVENT_MSG_BUFFER 0x35
+
+//
+//  Constants and Structure definitions for "Read Event Message Buffer" command to follow here
+//
+
+//
+//  Definitions for Get BT Interface Capabilities command
+//
+#define IPMI_APP_GET_BT_INTERFACE_CAPABILITY 0x36
+
+//
+//  Constants and Structure definitions for "Get BT Interface Capabilities" command to follow here
+//
+
+//
+//  Definitions for Get System GUID command
+//
+#define IPMI_APP_GET_SYSTEM_GUID 0x37
+
+//
+//  Constants and Structure definitions for "Get System GUID" command to follow here
+//
+
+//
+//  Definitions for Get Channel Authentication Capabilities command
+//
+#define IPMI_APP_GET_CHANNEL_AUTHENTICATION_CAPABILITIES 0x38
+
+//
+//  Constants and Structure definitions for "Get Channel Authentication Capabilities" command to follow here
+//
+
+//
+//  Definitions for Get Session Challenge command
+//
+#define IPMI_APP_GET_SESSION_CHALLENGE 0x39
+
+//
+//  Constants and Structure definitions for "Get Session Challenge" command to follow here
+//
+
+//
+//  Definitions for Activate Session command
+//
+#define IPMI_APP_ACTIVATE_SESSION  0x3A
+
+//
+//  Constants and Structure definitions for "Activate Session" command to follow here
+//
+
+//
+//  Definitions for Set Session Privelege Level command
+//
+#define IPMI_APP_SET_SESSION_PRIVELEGE_LEVEL 0x3B
+
+//
+//  Constants and Structure definitions for "Set Session Privelege Level" command to follow here
+//
+
+//
+//  Definitions for Close Session command
+//
+#define IPMI_APP_CLOSE_SESSION 0x3C
+
+//
+//  Constants and Structure definitions for "Close Session" command to follow here
+//
+
+//
+//  Definitions for Get Session Info command
+//
+#define IPMI_APP_GET_SESSION_INFO  0x3D
+
+//
+//  Constants and Structure definitions for "Get Session Info" command to follow here
+//
+
+//
+//  Definitions for Get Auth Code command
+//
+#define IPMI_APP_GET_AUTHCODE  0x3F
+
+//
+//  Constants and Structure definitions for "Get AuthCode" command to follow here
+//
+
+//
+//  Definitions for Set Channel Access command
+//
+#define IPMI_APP_SET_CHANNEL_ACCESS  0x40
+
+//
+//  Constants and Structure definitions for "Set Channel Access" command to follow here
+//
+
+//
+//  Definitions for Get Channel Access command
+//
+#define IPMI_APP_GET_CHANNEL_ACCESS  0x41
+
+//
+//  Constants and Structure definitions for "Get Channel Access" command to follow here
+//
+typedef struct {
+  UINT8  ChannelNo : 4;
+  UINT8  Reserve1 : 4;
+  UINT8  Reserve2 : 6;
+  UINT8  MemoryType : 2;
+} IPMI_GET_CHANNEL_ACCESS_REQUEST;
+
+typedef struct {
+  UINT8  CompletionCode;
+  UINT8  AccessMode : 3;
+  UINT8  UserLevelAuthEnabled : 1;
+  UINT8  MessageAuthEnable : 1;
+  UINT8  Alert : 1;
+  UINT8  Reserve1 : 2;
+  UINT8  ChannelPriviledgeLimit : 4;
+  UINT8  Reserve2 : 4;
+} IPMI_GET_CHANNEL_ACCESS_RESPONSE;
+
+//
+//  Definitions for Get Channel Info command
+//
+#define IPMI_APP_GET_CHANNEL_INFO  0x42
+
+//
+//  Constants and Structure definitions for "Get Channel Info" command to follow here
+//
+typedef struct {
+  UINT8   CompletionCode;
+  UINT8   ChannelNo : 4;
+  UINT8   Reserve1 : 4;
+  UINT8   ChannelMediumType : 7;
+  UINT8   Reserve2 : 1;
+  UINT8   ChannelProtocolType : 5;
+  UINT8   Reserve3 : 3;
+  UINT8   ActiveSessionCount : 6;
+  UINT8   SessionSupport : 2;
+  UINT8   VendorId[3];
+  UINT16  AuxChannelInfo;
+} IPMI_GET_CHANNEL_INFO_RESPONSE;
+
+//
+//  Definitions for Get Channel Info command
+//
+#define IPMI_APP_GET_CHANNEL_INFO  0x42
+
+//
+//  Constants and Structure definitions for "Get Channel Info" command to follow here
+//
+
+//
+//  Definitions for Set User Access command
+//
+#define IPMI_APP_SET_USER_ACCESS 0x43
+
+//
+//  Constants and Structure definitions for "Set User Access" command to follow here
+//
+
+//
+//  Definitions for Get User Access command
+//
+#define IPMI_APP_GET_USER_ACCESS 0x44
+
+//
+//  Constants and Structure definitions for "Get User Access" command to follow here
+//
+
+//
+//  Definitions for Set User Name command
+//
+#define IPMI_APP_SET_USER_NAME 0x45
+
+//
+//  Constants and Structure definitions for "Set User Name" command to follow here
+//
+
+//
+//  Definitions for Get User Name command
+//
+#define IPMI_APP_GET_USER_NAME 0x46
+
+//
+//  Constants and Structure definitions for "Get User Name" command to follow here
+//
+
+//
+//  Definitions for Set User Password command
+//
+#define IPMI_APP_SET_USER_PASSWORD 0x47
+
+//
+//  Constants and Structure definitions for "Set User Password" command to follow here
+//
+
+//
+//  Below is Definitions for RMCP+ Support and Payload Commands (Chapter 24)
+//
+
+//
+//  Definitions for Activate Payload command
+//
+#define IPMI_APP_ACTIVATE_PAYLOAD  0x48
+
+//
+//  Constants and Structure definitions for "Activate Payload" command to follow here
+//
+
+//
+//  Definitions for De-Activate Payload command
+//
+#define IPMI_APP_DEACTIVATE_PAYLOAD  0x49
+
+//
+//  Constants and Structure definitions for "DeActivate Payload" command to follow here
+//
+
+//
+//  Definitions for Get Payload activation Status command
+//
+#define IPMI_APP_GET_PAYLOAD_ACTIVATION_STATUS 0x4a
+
+//
+//  Constants and Structure definitions for "Get Payload activation Status" command to follow here
+//
+
+//
+//  Definitions for Get Payload Instance Info command
+//
+#define IPMI_APP_GET_PAYLOAD_INSTANCE_INFO 0x4b
+
+//
+//  Constants and Structure definitions for "Get Payload Instance Info" command to follow here
+//
+
+//
+//  Definitions for Set User Payload Access command
+//
+#define IPMI_APP_SET_USER_PAYLOAD_ACCESS 0x4C
+
+//
+//  Constants and Structure definitions for "Set User Payload Access" command to follow here
+//
+
+//
+//  Definitions for Get User Payload Access command
+//
+#define IPMI_APP_GET_USER_PAYLOAD_ACCESS 0x4D
+
+//
+//  Constants and Structure definitions for "Get User Payload Access" command to follow here
+//
+
+//
+//  Definitions for Get Channel Payload Support command
+//
+#define IPMI_APP_GET_CHANNEL_PAYLOAD_SUPPORT 0x4E
+
+//
+//  Constants and Structure definitions for "Get Channel Payload Support" command to follow here
+//
+
+//
+//  Definitions for Get Channel Payload Version command
+//
+#define IPMI_APP_GET_CHANNEL_PAYLOAD_VERSION 0x4F
+
+//
+//  Constants and Structure definitions for "Get Channel Payload Version" command to follow here
+//
+
+//
+//  Definitions for Get Channel OEM Payload Info command
+//
+#define IPMI_APP_GET_CHANNEL_OEM_PAYLOAD_INFO  0x50
+
+//
+//  Constants and Structure definitions for "Get Channel OEM Payload Info" command to follow here
+//
+
+//
+//  Definitions for  Master Write-Read command
+//
+#define IPMI_APP_MASTER_WRITE_READ 0x52
+
+//
+//  Constants and Structure definitions for "Master Write Read" command to follow here
+//
+
+//
+//  Definitions for  Get Channel Cipher Suites command
+//
+#define IPMI_APP_GET_CHANNEL_CIPHER_SUITES 0x54
+
+//
+//  Constants and Structure definitions for "Get Channel Cipher Suites" command to follow here
+//
+
+//
+//  Below is Definitions for RMCP+ Support and Payload Commands (Chapter 24, Section 3)
+//
+
+//
+//  Definitions for  Suspend-Resume Payload Encryption command
+//
+#define IPMI_APP_SUSPEND_RESUME_PAYLOAD_ENCRYPTION 0x55
+
+//
+//  Constants and Structure definitions for "Suspend-Resume Payload Encryption" command to follow here
+//
+
+//
+//  Below is Definitions for IPMI Messaging Support Commands (Chapter 22, Section 25 and 9)
+//
+
+//
+//  Definitions for  Set Channel Security Keys command
+//
+#define IPMI_APP_SET_CHANNEL_SECURITY_KEYS 0x56
+
+//
+//  Constants and Structure definitions for "Set Channel Security Keys" command to follow here
+//
+
+//
+//  Definitions for  Get System Interface Capabilities command
+//
+#define IPMI_APP_GET_SYSTEM_INTERFACE_CAPABILITIES 0x57
+
+//
+//  Constants and Structure definitions for "Get System Interface Capabilities" command to follow here
+//
+
+#pragma pack()
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnBridge.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnBridge.h
new file mode 100644
index 0000000000..7f174fdc69
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnBridge.h
@@ -0,0 +1,243 @@
+/** @file
+  IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
+  IPMI Intelligent Chassis Management Bus Bridge Specification Version 1.0,
+  Revision 1.3.
+
+  See IPMI specification, Appendix G, Command Assignments
+  and Appendix H, Sub-function Assignments.
+
+  Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#ifndef _IPMI_NET_FN_BRIDGE_H_
+#define _IPMI_NET_FN_BRIDGE_H_
+
+//
+// Net function definition for Bridge command
+//
+#define IPMI_NETFN_BRIDGE 0x02
+
+//
+//  Definitions for Get Bridge State command
+//
+#define IPMI_BRIDGE_GET_STATE  0x00
+
+//
+//  Constants and Structure definitions for "Get Bridge State" command to follow here
+//
+
+//
+//  Definitions for Set Bridge State command
+//
+#define IPMI_BRIDGE_SET_STATE  0x01
+
+//
+//  Constants and Structure definitions for "Set Bridge State" command to follow here
+//
+
+//
+//  Definitions for Get ICMB Address command
+//
+#define IPMI_BRIDGE_GET_ICMB_ADDRESS 0x02
+
+//
+//  Constants and Structure definitions for "Get ICMB Address" command to follow here
+//
+
+//
+//  Definitions for Set ICMB Address command
+//
+#define IPMI_BRIDGE_SET_ICMB_ADDRESS 0x03
+
+//
+//  Constants and Structure definitions for "Set ICMB Address" command to follow here
+//
+
+//
+//  Definitions for Set Bridge Proxy Address command
+//
+#define IPMI_BRIDGE_SET_PROXY_ADDRESS  0x04
+
+//
+//  Constants and Structure definitions for "Set Bridge Proxy Address" command to follow here
+//
+
+//
+//  Definitions for Get Bridge Statistics command
+//
+#define IPMI_BRIDGE_GET_BRIDGE_STATISTICS  0x05
+
+//
+//  Constants and Structure definitions for "Get Bridge Statistics" command to follow here
+//
+
+//
+//  Definitions for Get ICMB Capabilities command
+//
+#define IPMI_BRIDGE_GET_ICMB_CAPABILITIES  0x06
+
+//
+//  Constants and Structure definitions for "Get ICMB Capabilities" command to follow here
+//
+
+//
+//  Definitions for Clear Bridge Statistics command
+//
+#define IPMI_BRIDGE_CLEAR_STATISTICS 0x08
+
+//
+//  Constants and Structure definitions for "Clear Bridge Statistics" command to follow here
+//
+
+//
+//  Definitions for Get Bridge Proxy Address command
+//
+#define IPMI_BRIDGE_GET_PROXY_ADDRESS  0x09
+
+//
+//  Constants and Structure definitions for "Get Bridge Proxy Address" command to follow here
+//
+
+//
+//  Definitions for Get ICMB Connector Info command
+//
+#define IPMI_BRIDGE_GET_ICMB_CONNECTOR_INFO  0x0A
+
+//
+//  Constants and Structure definitions for "Get ICMB Connector Info " command to follow here
+//
+
+//
+//  Definitions for Get ICMB Connection ID command
+//
+#define IPMI_BRIDGE_GET_ICMB_CONNECTION_ID 0x0B
+
+//
+//  Constants and Structure definitions for "Get ICMB Connection ID" command to follow here
+//
+
+//
+//  Definitions for Get ICMB Connection ID command
+//
+#define IPMI_BRIDGE_SEND_ICMB_CONNECTION_ID  0x0C
+
+//
+//  Constants and Structure definitions for "Send ICMB Connection ID" command to follow here
+//
+
+//
+//  Definitions for Prepare for Discoveery command
+//
+#define IPMI_BRIDGE_PREPARE_FOR_DISCOVERY  0x10
+
+//
+//  Constants and Structure definitions for "Prepare for Discoveery" command to follow here
+//
+
+//
+//  Definitions for Get Addresses command
+//
+#define IPMI_BRIDGE_GET_ADDRESSES  0x11
+
+//
+//  Constants and Structure definitions for "Get Addresses" command to follow here
+//
+
+//
+//  Definitions for Set Discovered command
+//
+#define IPMI_BRIDGE_SET_DISCOVERED 0x12
+
+//
+//  Constants and Structure definitions for "Set Discovered" command to follow here
+//
+
+//
+//  Definitions for Get Chassis Device ID command
+//
+#define IPMI_BRIDGE_GET_CHASSIS_DEVICEID 0x13
+
+//
+//  Constants and Structure definitions for "Get Chassis Device ID" command to follow here
+//
+
+//
+//  Definitions for Set Chassis Device ID command
+//
+#define IPMI_BRIDGE_SET_CHASSIS_DEVICEID 0x14
+
+//
+//  Constants and Structure definitions for "Set Chassis Device ID" command to follow here
+//
+
+//
+//  Definitions for Bridge Request command
+//
+#define IPMI_BRIDGE_REQUEST  0x20
+
+//
+//  Constants and Structure definitions for "Bridge Request" command to follow here
+//
+
+//
+//  Definitions for Bridge Message command
+//
+#define IPMI_BRIDGE_MESSAGE  0x21
+
+//
+//  Constants and Structure definitions for "Bridge Message" command to follow here
+//
+
+//
+//  Definitions for Get Event Count command
+//
+#define IPMI_BRIDGE_GET_EVENT_COUNT  0x30
+
+//
+//  Constants and Structure definitions for "Get Event Count" command to follow here
+//
+
+//
+//  Definitions for Set Event Destination command
+//
+#define IPMI_BRIDGE_SET_EVENT_DESTINATION  0x31
+
+//
+//  Constants and Structure definitions for "Set Event Destination" command to follow here
+//
+
+//
+//  Definitions for Set Event Reception State command
+//
+#define IPMI_BRIDGE_SET_EVENT_RECEPTION_STATE  0x32
+
+//
+//  Constants and Structure definitions for "Set Event Reception State" command to follow here
+//
+
+//
+//  Definitions for Set Event Reception State command
+//
+#define IPMI_BRIDGE_SET_EVENT_RECEPTION_STATE  0x32
+
+//
+//  Constants and Structure definitions for "Set Event Reception State" command to follow here
+//
+
+//
+//  Definitions for Send ICMB Event Message command
+//
+#define IPMI_BRIDGE_SEND_ICMB_EVENT_MESSAGE  0x33
+
+//
+//  Constants and Structure definitions for "Send ICMB Event Message" command to follow here
+//
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
new file mode 100644
index 0000000000..833feeb9dd
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
@@ -0,0 +1,303 @@
+/** @file
+  IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
+
+  This file contains all NetFn Chassis commands, including:
+    Chassis Commands (Chapter 28)
+
+  See IPMI specification, Appendix G, Command Assignments
+  and Appendix H, Sub-function Assignments.
+
+  Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#ifndef _IPMI_NET_FN_CHASSIS_H_
+#define _IPMI_NET_FN_CHASSIS_H_
+
+#pragma pack (1)
+//
+// Net function definition for Chassis command
+//
+#define IPMI_NETFN_CHASSIS  0x00
+
+//
+//  Below is Definitions for Chassis commands (Chapter 28)
+//
+
+//
+//  Definitions for Get Chassis Capabilities command
+//
+#define IPMI_CHASSIS_GET_CAPABILITIES  0x00
+
+//
+//  Constants and Structure definitions for "Get Chassis Capabilities" command to follow here
+//
+
+//
+//  Definitions for Get Chassis Status command
+//
+#define IPMI_CHASSIS_GET_STATUS  0x01
+
+//
+//  Constants and Structure definitions for "Get Chassis Status" command to follow here
+//
+
+//
+//  Definitions for Chassis Control command
+//
+#define IPMI_CHASSIS_CONTROL 0x02
+
+//
+//  Constants and Structure definitions for "Chassis Control" command to follow here
+//
+
+//
+//  Definitions for Chassis Reset command
+//
+#define IPMI_CHASSIS_RESET 0x03
+
+//
+//  Constants and Structure definitions for "Chassis Reset" command to follow here
+//
+
+//
+//  Definitions for Chassis Identify command
+//
+#define IPMI_CHASSIS_IDENTIFY  0x04
+
+//
+//  Constants and Structure definitions for "Chassis Identify" command to follow here
+//
+
+//
+//  Definitions for Set Chassis Capabilities command
+//
+#define IPMI_CHASSIS_SET_CAPABILITIES  0x05
+
+//
+//  Constants and Structure definitions for "Set Chassis Capabilities" command to follow here
+//
+
+//
+//  Definitions for Set Power Restore Policy command
+//
+#define IPMI_CHASSIS_SET_POWER_RESTORE_POLICY  0x06
+
+//
+//  Constants and Structure definitions for "Set Power Restore Policy" command to follow here
+//
+
+//
+//  Definitions for Get System Restart Cause command
+//
+#define IPMI_CHASSIS_GET_SYSTEM_RESTART_CAUSE  0x07
+
+//
+//  Constants and Structure definitions for "Get System Restart Cause" command to follow here
+//
+typedef enum {
+  Unknown,
+  ChassisControlCommand,
+  ResetViaPushButton,
+  PowerupViaPowerButton,
+  WatchdogExpiration,
+  Oem,
+  AutoPowerOnAlwaysRestore,
+  AutoPowerOnRestorePrevious,
+  ResetViaPef,
+  PowerCycleViaPef,
+  SoftReset,
+  PowerUpViaRtc
+} IPMI_SYSTEM_RESTART_CAUSE;
+
+typedef struct {
+  UINT8  CompletionCode;
+  UINT8  Cause:4;
+  UINT8  Reserved:4;
+  UINT8  ChannelNumber;
+} IPMI_GET_SYSTEM_RESTART_CAUSE_RESPONSE;
+
+//
+//  Definitions for Set System BOOT options command
+//
+#define IPMI_CHASSIS_SET_SYSTEM_BOOT_OPTIONS 0x08
+
+//
+//  Constants and Structure definitions for "Set System boot options" command to follow here
+//
+typedef struct {
+  UINT8    ParameterSelector:7;
+  UINT8    MarkParameterInvalid:1;
+  UINT8    ParameterData[1];
+} IPMI_SET_BOOT_OPTIONS_REQUEST;
+
+//
+//  Definitions for Get System BOOT options command
+//
+#define IPMI_CHASSIS_GET_SYSTEM_BOOT_OPTIONS 0x09
+
+//
+//  Constants and Structure definitions for "Get System boot options" command to follow here
+//
+typedef struct {
+  UINT8    ParameterSelector:7;
+  UINT8    Reserved:1;
+  UINT8    SetSelector;
+  UINT8    BlockSelector;
+} IPMI_GET_BOOT_OPTIONS_REQUEST;
+
+typedef struct {
+  UINT8 Parameter;
+  UINT8 Valid;
+  UINT8 Data1;
+  UINT8 Data2;
+  UINT8 Data3;
+  UINT8 Data4;
+  UINT8 Data5;
+} IPMI_GET_THE_SYSTEM_BOOT_OPTIONS;
+
+typedef struct {
+  UINT8   ParameterVersion;
+  UINT8   ParameterValid;
+  UINT8   ChannelNumber;
+  UINT32  SessionId;
+  UINT32  TimeStamp;
+  UINT8   Reserved[3];
+} IPMI_BOOT_INITIATOR;
+
+//
+// Response Parameters for IPMI Get Boot Options
+//
+typedef struct {
+  UINT8   SetInProgress: 2;
+  UINT8   Reserved: 6;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_0;
+
+typedef struct {
+  UINT8   ServicePartitionSelector;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_1;
+
+typedef struct {
+  UINT8   ServicePartitionDiscovered:1;
+  UINT8   ServicePartitionScanRequest:1;
+  UINT8   Reserved: 5;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_2;
+
+typedef struct {
+  UINT8   BmcBootFlagValid: 5;
+  UINT8   Reserved: 3;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_3;
+
+typedef struct {
+  UINT8   WriteMask;
+  UINT8   BootInitiatorAcknowledgeData;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_4;
+
+#define BOOT_OPTION_HANDLED_BY_BIOS 0x01
+
+typedef struct {
+  //
+  // Data 1
+  //
+  UINT8   Reserved0:6;
+  UINT8   PersistentOptions:1;
+  UINT8   BootFlagValid:1;
+  //
+  // Data 2
+  //
+  UINT8   LockReset:1;
+  UINT8   ScreenBlank:1;
+  UINT8   BootDeviceSelector:4;
+  UINT8   LockKeyboard:1;
+  UINT8   CmosClear:1;
+  //
+  //
+  // Data 3
+  UINT8   ConsoleRedirection:2;
+  UINT8   LockSleep:1;
+  UINT8   UserPasswordBypass:1;
+  UINT8   ForceProgressEventTrap:1;
+  UINT8   BiosVerbosity:2;
+  UINT8   LockPower:1;
+  //
+  // Data 4
+  //
+  UINT8   BiosMuxControlOverride:2;
+  UINT8   BiosSharedModeOverride:1;
+  UINT8   Reserved1:4;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5;
+
+typedef struct {
+  UINT8   ChannelNumber:4;
+  UINT8   Reserved:4;
+  UINT8   SessionId[4];
+  UINT8   BootInfoTimeStamp[4];
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_6;
+
+typedef struct {
+  UINT8   SetSelector;
+  UINT8   BlockData[16];
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_7;
+
+typedef union {
+  IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_0   Parm0;
+  IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_1   Parm1;
+  IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_2   Parm2;
+  IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_3   Parm3;
+  IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_4   Parm4;
+  IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5   Parm5;
+  IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_6   Parm6;
+  IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_7   Parm7;
+} IPMI_BOOT_OPTIONS_PARAMETERS;
+
+typedef struct {
+  UINT8    CompletionCode;
+  UINT8    ParameterVersion:4;
+  UINT8    Reserved:4;
+  UINT8    ParameterSelector:7;
+  UINT8    ParameterValid:1;
+  UINT8    ParameterData[1];
+} IPMI_GET_BOOT_OPTIONS_RESPONSE;
+
+//
+//  Definitions for Set front panel button enables command
+//
+#define IPMI_CHASSIS_SET_FRONT_PANEL_BUTTON_ENABLES 0x0A
+
+typedef struct {
+  UINT8    DisablePoweroffButton:1;
+  UINT8    DisableResetButton:1;
+  UINT8    DisableDiagnosticInterruptButton:1;
+  UINT8    DisableStandbyButton:1;
+  UINT8    Reserved:4;
+} IPMI_CHASSIS_SET_FRONT_PANEL_BUTTON_ENABLES_REQUEST;
+
+//
+//  Constants and Structure definitions for "Set front panel button enables" command to follow here
+//
+
+//
+//  Definitions for Set Power Cycle Interval command
+//
+#define IPMI_CHASSIS_SET_POWER_CYCLE_INTERVALS 0x0B
+
+//
+//  Constants and Structure definitions for "Set Power Cycle Interval" command to follow here
+//
+
+//
+//  Definitions for Get POH Counter command
+//
+#define IPMI_CHASSIS_GET_POH_COUNTER 0x0F
+
+//
+//  Constants and Structure definitions for "Get POH Counter" command to follow here
+//
+#pragma pack()
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
new file mode 100644
index 0000000000..aba3c41d06
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
@@ -0,0 +1,26 @@
+/** @file
+  IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
+
+  Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#ifndef _IPMI_NET_FN_FIRMWARE_H_
+#define _IPMI_NET_FN_FIRMWARE_H_
+
+//
+// Net function definition for Firmware command
+//
+#define IPMI_NETFN_FIRMWARE 0x08
+
+//
+// All Firmware commands and their structure definitions to follow here
+//
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h
new file mode 100644
index 0000000000..2a8ec69567
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h
@@ -0,0 +1,26 @@
+/** @file
+  IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
+
+  Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#ifndef _IPMI_NET_FN_GROUP_EXTENSION_H_
+#define _IPMI_NET_FN_GROUP_EXTENSION_H_
+
+//
+// Net function definition for Group Extension command
+//
+#define IPMI_NETFN_GROUP_EXT  0x2C
+
+//
+// All Group Extension commands and their structure definitions to follow here
+//
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h
new file mode 100644
index 0000000000..f9d851e6ca
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h
@@ -0,0 +1,52 @@
+/** @file
+  IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
+
+  This file contains all NetFn Sensor/Event commands, including:
+    Event Commands (Chapter 29)
+    PEF and Alerting Commands (Chapter 30)
+    Sensor Device Commands (Chapter 35)
+
+  See IPMI specification, Appendix G, Command Assignments
+  and Appendix H, Sub-function Assignments.
+
+  Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#ifndef _IPMI_NET_FN_SENSOR_EVENT_H_
+#define _IPMI_NET_FN_SENSOR_EVENT_H_
+
+#pragma pack(1)
+//
+// Net function definition for Sensor command
+//
+#define IPMI_NETFN_SENSOR_EVENT 0x04
+
+//
+// All Sensor commands and their structure definitions to follow here
+//
+
+//
+//  Definitions for Send Platform Event Message command
+//
+#define IPMI_SENSOR_PLATFORM_EVENT_MESSAGE   0x02
+
+typedef struct {
+  UINT8   GeneratorId;
+  UINT8   EvMRevision;
+  UINT8   SensorType;
+  UINT8   SensorNumber;
+  UINT8   EventDirType;
+  UINT8   OEMEvData1;
+  UINT8   OEMEvData2;
+  UINT8   OEMEvData3;
+} IPMI_PLATFORM_EVENT_MESSAGE_DATA_REQUEST;
+
+#pragma pack()
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnStorage.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnStorage.h
new file mode 100644
index 0000000000..210db1e7e9
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnStorage.h
@@ -0,0 +1,542 @@
+/** @file
+  IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
+
+  This file contains all NetFn Storage commands, including:
+    FRU Inventory Commands (Chapter 34)
+    SDR Repository (Chapter 33)
+    System Event Log(SEL) Commands (Chapter 31)
+    SEL Record Formats (Chapter 32)
+
+  See IPMI specification, Appendix G, Command Assignments
+  and Appendix H, Sub-function Assignments.
+
+  Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#ifndef _IPMI_NET_FN_STORAGE_H_
+#define _IPMI_NET_FN_STORAGE_H_
+
+#pragma pack(1)
+//
+// Net function definition for Storage command
+//
+#define IPMI_NETFN_STORAGE  0x0A
+
+//
+// All Storage commands and their structure definitions to follow here
+//
+
+//
+//  Below is Definitions for FRU Inventory Commands (Chapter 34)
+//
+
+//
+//  Definitions for Get Fru Inventory Area Info command
+//
+#define IPMI_STORAGE_GET_FRU_INVENTORY_AREAINFO  0x10
+
+//
+//  Constants and Structure definitions for "Get Fru Inventory Area Info" command to follow here
+//
+
+//
+//  Definitions for Get Fru Data command
+//
+#define IPMI_STORAGE_READ_FRU_DATA 0x11
+
+//
+//  Constants and Structure definitions for "Get Fru Data" command to follow here
+//
+typedef struct {
+  UINT8   FruDeviceId;
+  UINT16  FruOffset;
+} IPMI_FRU_COMMON_DATA;
+
+typedef struct {
+  IPMI_FRU_COMMON_DATA Data;
+  UINT8                Count;
+} IPMI_FRU_READ_COMMAND;
+
+//
+//  Definitions for Write Fru Data command
+//
+#define IPMI_STORAGE_WRITE_FRU_DATA  0x12
+
+//
+//  Constants and Structure definitions for "Write Fru Data" command to follow here
+//
+typedef struct {
+  IPMI_FRU_COMMON_DATA Data;
+  UINT8                FruData[16];
+} IPMI_FRU_WRITE_COMMAND;
+
+//
+//  Below is Definitions for SDR Repository (Chapter 33)
+//
+
+//
+//  Definitions for Get SDR Repository Info command
+//
+#define IPMI_STORAGE_GET_SDR_REPOSITORY_INFO 0x20
+
+//
+//  Constants and Structure definitions for "Get SDR Repository Info" command to follow here
+//
+typedef struct {
+  UINT8   CompletionCode;
+  UINT8   Version;
+  UINT16  RecordCount;
+  UINT16  FreeSpace;
+  UINT32  RecentAdditionTimeStamp;
+  UINT32  RecentEraseTimeStamp;
+  UINT8   SdrRepAllocInfoCmd : 1;
+  UINT8   SdrRepReserveCmd : 1;
+  UINT8   PartialAddSdrCmd : 1;
+  UINT8   DeleteSdrRepCmd : 1;
+  UINT8   Reserved : 1;
+  UINT8   SdrRepUpdateOp : 2;
+  UINT8   Overflow : 1;
+} IPMI_GET_SDR_REPOSITORY_INFO;
+
+//
+//  Definitions for Get SDR Repository Allocateion Info command
+//
+#define IPMI_STORAGE_GET_SDR_REPOSITORY_ALLOCATION_INFO  0x21
+
+//
+//  Constants and Structure definitions for "Get SDR Repository Allocateion Info" command to follow here
+//
+
+//
+//  Definitions for Reserve SDR Repository command
+//
+#define IPMI_STORAGE_RESERVE_SDR_REPOSITORY  0x22
+
+//
+//  Constants and Structure definitions for "Reserve SDR Repository" command to follow here
+//
+
+//
+//  Definitions for Get SDR command
+//
+#define IPMI_STORAGE_GET_SDR 0x23
+
+//
+//  Constants and Structure definitions for "Get SDR" command to follow here
+//
+
+typedef struct {
+  UINT16  RecordId;                     // 1
+  UINT8   Version;                      // 3
+  UINT8   RecordType;                   // 4
+  UINT8   RecordLength;                 // 5
+  UINT8   OwnerId;                      // 6
+  UINT8   OwnerLun;                     // 7
+  UINT8   SensorNumber;                 // 8
+  UINT8   EntityId;                     // 9
+  UINT8   EntityInstance;               // 10
+  UINT8   EventScanningEnabled : 1;     // 11
+  UINT8   EventScanningDisabled : 1;    // 11
+  UINT8   InitSensorType : 1;           // 11
+  UINT8   InitHysteresis : 1;           // 11
+  UINT8   InitThresholds : 1;           // 11
+  UINT8   InitEvent : 1;                // 11
+  UINT8   InitScanning : 1;             // 11
+  UINT8   Reserved : 1;                 // 11
+  UINT8   EventMessageControl : 2;      // 12
+  UINT8   ThresholdAccessSupport : 2;   // 12
+  UINT8   HysteresisSupport : 2;        // 12
+  UINT8   ReArmSupport : 1;             // 12
+  UINT8   IgnoreSensor : 1;             // 12
+  UINT8   SensorType;                   // 13
+  UINT8   EventType;                    // 14
+  UINT8   Reserved1[7];                 // 15
+  UINT8   UnitType;                     // 22
+  UINT8   Reserved2;                    // 23
+  UINT8   Linearization : 7;            // 24
+  UINT8   Reserved3 : 1;                // 24
+  UINT8   MLo;                          // 25
+  UINT8   Toleremce : 6;                // 26
+  UINT8   MHi : 2;                      // 26
+  UINT8   BLo;                          // 27
+  UINT8   AccuracyLow : 6;              // 28
+  UINT8   BHi : 2;                      // 28
+  UINT8   Reserved4 : 2;                // 29
+  UINT8   AccuracyExp : 2;              // 29
+  UINT8   AccuracyHi : 4;               // 29
+  UINT8   BExp : 4;                     // 30
+  UINT8   RExp : 4;                     // 30
+  UINT8   NominalReadingSpscified : 1;  // 31
+  UINT8   NominalMaxSpscified : 1;      // 31
+  UINT8   NominalMinSpscified : 1;      // 31
+  UINT8   Reserved5 : 5;                // 31
+  UINT8   NominalReading;               // 32
+  UINT8   Reserved6[4];                 // 33
+  UINT8   UpperNonRecoverThreshold;     // 37
+  UINT8   UpperCriticalThreshold;       // 38
+  UINT8   UpperNonCriticalThreshold;    // 39
+  UINT8   LowerNonRecoverThreshold;     // 40
+  UINT8   LowerCriticalThreshold;       // 41
+  UINT8   LowerNonCriticalThreshold;    // 42
+  UINT8   Reserved7[5];                 // 43
+  UINT8   IdStringLength;               // 48
+  UINT8   AsciiIdString[16];            // 49 - 64
+} IPMI_SDR_RECORD_STRUCT_1;
+
+typedef struct {
+  UINT16  RecordId;                     // 1
+  UINT8   Version;                      // 3
+  UINT8   RecordType;                   // 4
+  UINT8   RecordLength;                 // 5
+  UINT8   OwnerId;                      // 6
+  UINT8   OwnerLun;                     // 7
+  UINT8   SensorNumber;                 // 8
+  UINT8   EntityId;                     // 9
+  UINT8   EntityInstance;               // 10
+  UINT8   SensorScanning : 1;           // 11
+  UINT8   EventScanning : 1;            // 11
+  UINT8   InitSensorType : 1;           // 11
+  UINT8   InitHysteresis : 1;           // 11
+  UINT8   InitThresholds : 1;           // 11
+  UINT8   InitEvent : 1;                // 11
+  UINT8   InitScanning : 1;             // 11
+  UINT8   Reserved : 1;                 // 11
+  UINT8   EventMessageControl : 2;      // 12
+  UINT8   ThresholdAccessSupport : 2;   // 12
+  UINT8   HysteresisSupport : 2;        // 12
+  UINT8   ReArmSupport : 1;             // 12
+  UINT8   IgnoreSensor : 1;             // 12
+  UINT8   SensorType;                   // 13
+  UINT8   EventType;                    // 14
+  UINT8   Reserved1[7];                 // 15
+  UINT8   UnitType;                     // 22
+  UINT8   Reserved2[9];                 // 23
+  UINT8   IdStringLength;               // 32
+  UINT8   AsciiIdString[16];            // 33 - 48
+} IPMI_SDR_RECORD_STRUCT_2;
+
+typedef struct {
+  UINT8 Reserved1 : 1;
+  UINT8 ControllerSlaveAddress : 7;
+  UINT8 FruDeviceId;
+  UINT8 BusId : 3;
+  UINT8 Lun : 2;
+  UINT8 Reserved : 2;
+  UINT8 LogicalFruDevice : 1;
+  UINT8 Reserved3 : 4;
+  UINT8 ChannelNumber : 4;
+} IPMI_FRU_DATA_INFO;
+
+typedef struct {
+  UINT16            RecordId;           // 1
+  UINT8             Version;            // 3
+  UINT8             RecordType;         // 4
+  UINT8             RecordLength;       // 5
+  IPMI_FRU_DATA_INFO FruDeviceData;      // 6
+  UINT8             Reserved1;          // 10
+  UINT8             DeviceType;         // 11
+  UINT8             DeviceTypeModifier; // 12
+  UINT8             FruEntityId;        // 13
+  UINT8             FruEntityInstance;  // 14
+  UINT8             OemReserved;        // 15
+  UINT8             Length : 4;         // 16
+  UINT8             Reserved2 : 1;      // 16
+  UINT8             StringType : 3;     // 16
+  UINT8             String[16];         // 17
+} IPMI_SDR_RECORD_STRUCT_11;
+
+typedef struct {
+  UINT16              NextRecordId;       //1
+  UINT16              RecordId;           //3
+  UINT8               Version;            //5
+  UINT8               RecordType;         //6
+  UINT8               RecordLength;       //7
+  UINT8               ManufacturerId[3];  //8
+  UINT8               StringChars[20];
+} IPMI_SDR_RECORD_STRUCT_C0;
+
+typedef struct {
+  UINT16              NextRecordId;       //1
+  UINT16              RecordId;           //3
+  UINT8               Version;            //5
+  UINT8               RecordType;         //6
+  UINT8               RecordLength;       //7
+} IPMI_SDR_RECORD_STRUCT_HEADER;
+
+typedef union {
+  IPMI_SDR_RECORD_STRUCT_1  SensorType1;
+  IPMI_SDR_RECORD_STRUCT_2  SensorType2;
+  IPMI_SDR_RECORD_STRUCT_11 SensorType11;
+  IPMI_SDR_RECORD_STRUCT_C0       SensorTypeC0;
+  IPMI_SDR_RECORD_STRUCT_HEADER   SensorHeader;
+} IPMI_SENSOR_RECORD_STRUCT;
+
+typedef struct {
+  UINT16      ReservationId;
+  UINT16      RecordId;
+  UINT8       RecordOffset;
+  UINT8       BytesToRead;
+} IPMI_GET_SDR_REQUEST;
+
+//
+//  Definitions for Add SDR command
+//
+#define IPMI_STORAGE_ADD_SDR 0x24
+
+//
+//  Constants and Structure definitions for "Add SDR" command to follow here
+//
+
+//
+//  Definitions for Partial Add SDR command
+//
+#define IPMI_STORAGE_PARTIAL_ADD_SDR 0x25
+
+//
+//  Constants and Structure definitions for "Partial Add SDR" command to follow here
+//
+
+//
+//  Definitions for Delete SDR command
+//
+#define IPMI_STORAGE_DELETE_SDR  0x26
+
+//
+//  Constants and Structure definitions for "Delete SDR" command to follow here
+//
+
+//
+//  Definitions for Clear SDR Repository command
+//
+#define IPMI_STORAGE_CLEAR_SDR 0x27
+
+//
+//  Constants and Structure definitions for "Clear SDR Repository" command to follow here
+//
+
+//
+//  Definitions for Get SDR Repository Time command
+//
+#define IPMI_STORAGE_GET_SDR_REPOSITORY_TIME 0x28
+
+//
+//  Constants and Structure definitions for "Get SDR Repository Time" command to follow here
+//
+
+//
+//  Definitions for Set SDR Repository Time command
+//
+#define IPMI_STORAGE_SET_SDR_REPOSITORY_TIME 0x29
+
+//
+//  Constants and Structure definitions for "Set SDR Repository Time" command to follow here
+//
+
+//
+//  Definitions for Enter SDR Repository Update Mode command
+//
+#define IPMI_STORAGE_ENTER_SDR_UPDATE_MODE 0x2A
+
+//
+//  Constants and Structure definitions for "Enter SDR Repository Update Mode" command to follow here
+//
+
+//
+//  Definitions for Exit SDR Repository Update Mode command
+//
+#define IPMI_STORAGE_EXIT_SDR_UPDATE_MODE  0x2B
+
+//
+//  Constants and Structure definitions for "Exit SDR Repository Update Mode" command to follow here
+//
+
+//
+//  Definitions for Run Initialize Agent command
+//
+#define IPMI_STORAGE_RUN_INIT_AGENT  0x2C
+
+//
+//  Constants and Structure definitions for "Run Initialize Agent" command to follow here
+//
+
+//
+//  Below is Definitions for System Event Log(SEL) Commands (Chapter 31)
+//
+
+//
+//  Definitions for Get SEL Info command
+//
+#define IPMI_STORAGE_GET_SEL_INFO  0x40
+
+//
+//  Constants and Structure definitions for "Get SEL Info" command to follow here
+//
+typedef struct {
+  UINT8   CompletionCode;
+  UINT8   Version;              // Version of SEL
+  UINT16  NoOfEntries;          // No of Entries in the SEL
+  UINT16  FreeSpace;            // Free space in Bytes
+  UINT32  RecentAddTimeStamp;   // Most Recent Addition of Time Stamp
+  UINT32  RecentEraseTimeStamp; // Most Recent Erasure of Time Stamp
+  UINT8   OperationSupport;     // Operation Support
+} IPMI_GET_SEL_INFO_RESPONSE;
+
+//
+//  Definitions for Get SEL Allocation Info command
+//
+#define IPMI_STORAGE_GET_SEL_ALLOCATION_INFO 0x41
+
+//
+//  Constants and Structure definitions for "Get SEL Allocation Info" command to follow here
+//
+
+//
+//  Definitions for Reserve SEL command
+//
+#define IPMI_STORAGE_RESERVE_SEL 0x42
+
+//
+//  Constants and Structure definitions for "Reserve SEL" command to follow here
+//
+
+//
+//  Definitions for Get SEL Entry command
+//
+#define IPMI_STORAGE_GET_SEL_ENTRY 0x43
+
+//
+//  Constants and Structure definitions for "Get SEL Entry" command to follow here
+//
+typedef struct {
+  UINT8 ReserveId[2]; // Reservation ID, LS Byte First
+  UINT8 SelRecID[2];  // Sel Record ID, LS Byte First
+  UINT8 Offset;       // Offset Into Record
+  UINT8 BytesToRead;  // Bytes to be Read, 0xFF for entire record
+} IPMI_GET_SEL_ENTRY_REQUEST;
+
+//
+//  Definitions for Add SEL Entry command
+//
+#define IPMI_STORAGE_ADD_SEL_ENTRY 0x44
+
+//
+//  Constants and Structure definitions for "Add SEL Entry" command to follow here
+//
+
+//
+//  Definitions for Partial Add SEL Entry command
+//
+#define IPMI_STORAGE_PARTIAL_ADD_SEL_ENTRY 0x45
+
+//
+//  Constants and Structure definitions for "Partial Add SEL Entry" command to follow here
+//
+
+//
+//  Definitions for Delete SEL Entry command
+//
+#define IPMI_STORAGE_DELETE_SEL_ENTRY  0x46
+
+//
+//  Constants and Structure definitions for "Delete SEL Entry" command to follow here
+//
+typedef struct {
+  UINT8 ReserveId[2];       // Reservation ID, LS byte first
+  UINT8 RecordToDelete[2];  // Record to Delete, LS Byte First
+} IPMI_DELETE_SEL_REQUEST;
+
+//
+//  Definitions for Clear SEL command
+//
+#define IPMI_STORAGE_CLEAR_SEL 0x47
+
+//
+//  Constants and Structure definitions for "Clear SEL" command to follow here
+//
+typedef struct {
+  UINT8 Reserve[2]; // Reserve ID, LSB first
+  UINT8 AscC;       // Ascii for 'C' (0x43)
+  UINT8 AscL;       // Ascii for 'L' (0x4c)
+  UINT8 AscR;       // Ascii for 'R' (0x52)
+  UINT8 Erase;      // 0xAA, Initiate Erase, 0x00 Get Erase Status
+} IPMI_CLEAR_SEL_REQUEST;
+
+//
+//  Definitions for Get SEL Time command
+//
+#define IPMI_STORAGE_GET_SEL_TIME  0x48
+
+//
+//  Constants and Structure definitions for "Get SEL Time" command to follow here
+//
+
+//
+//  Definitions for Set SEL Time command
+//
+#define IPMI_STORAGE_SET_SEL_TIME  0x49
+
+//
+//  Constants and Structure definitions for "Set SEL Time" command to follow here
+//
+
+//
+//  Definitions for Get Auxillary Log Status command
+//
+#define IPMI_STORAGE_GET_AUXILLARY_LOG_STATUS  0x5A
+
+//
+//  Constants and Structure definitions for "Get Auxillary Log Status" command to follow here
+//
+
+//
+//  Definitions for Set Auxillary Log Status command
+//
+#define IPMI_STORAGE_SET_AUXILLARY_LOG_STATUS  0x5B
+
+//
+//  Constants and Structure definitions for "Set Auxillary Log Status" command to follow here
+//
+
+#define IPMI_COMPLETE_SEL_RECORD 0xFF
+
+//
+//  Below is Definitions for SEL Record Formats (Chapter 32)
+//
+typedef struct {
+  UINT16  RecordId;
+  UINT8   RecordType;
+  UINT32  TimeStamp;
+  UINT16  GeneratorId;
+  UINT8   EvMRevision;
+  UINT8   SensorType;
+  UINT8   SensorNumber;
+  UINT8   EventDirType;
+  UINT8   OEMEvData1;
+  UINT8   OEMEvData2;
+  UINT8   OEMEvData3;
+} IPMI_SEL_EVENT_RECORD_DATA;
+
+#define IPMI_SEL_SYSTEM_RECORD                     0x02
+
+#define IPMI_EVM_REVISION                          0x04
+#define IPMI_BIOS_ID                               0x18
+#define IPMI_FORMAT_REV                            0x00
+#define IPMI_FORMAT_REV1                           0x01
+#define IPMI_SOFTWARE_ID                           0x01
+#define IPMI_PLATFORM_VAL_ID                       0x01
+#define IPMI_GENERATOR_ID(i,f)                     ((i << 1) | (f << 1) | IPMI_SOFTWARE_ID)
+
+#define IPMI_SENSOR_TYPE_EVENT_CODE_DISCRETE       0x6F
+
+#define IPMI_OEM_SPECIFIC_DATA                     0x02
+#define IPMI_SENSOR_SPECIFIC_DATA                  0x03
+
+#pragma pack()
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnTransport.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnTransport.h
new file mode 100644
index 0000000000..ad1a9aad70
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IpmiNetFnTransport.h
@@ -0,0 +1,566 @@
+/** @file
+  IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
+
+  This file contains all NetFn Transport commands, including:
+    IPM LAN Commands (Chapter 23)
+    IPMI Serial/Modem Commands (Chapter 25)
+    SOL Commands (Chapter 26)
+    Command Forwarding Commands (Chapter 35b)
+
+  See IPMI specification, Appendix G, Command Assignments
+  and Appendix H, Sub-function Assignments.
+
+  Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#ifndef _IPMI_NET_FN_TRANSPORT_H_
+#define _IPMI_NET_FN_TRANSPORT_H_
+
+#pragma pack(1)
+//
+// Net function definition for Transport command
+//
+#define IPMI_NETFN_TRANSPORT  0x0C
+
+//
+//  Below is Definitions for IPM LAN Commands (Chapter 23)
+//
+
+//
+//  Definitions for Set Lan Configuration Parameters command
+//
+#define IPMI_TRANSPORT_SET_LAN_CONFIG_PARAMETERS 0x01
+
+//
+//  Constants and Structure definitions for "Set Lan Configuration Parameters" command to follow here
+//
+
+//
+// LAN Management Structure
+//
+typedef enum {
+  IpmiLanReserved1,
+  IpmiLanReserved2,
+  IpmiLanAuthType,
+  IpmiLanIpAddress,
+  IpmiLanIpAddressSource,
+  IpmiLanMacAddress,
+  IpmiLanSubnetMask,
+  IpmiLanIpv4HeaderParam,
+  IpmiLanPrimaryRcmpPort,
+  IpmiLanSecondaryRcmpPort,
+  IpmiLanBmcGeneratedArpCtrl,
+  IpmiLanArpInterval,
+  IpmiLanDefaultGateway,
+  IpmiLanDefaultGatewayMac,
+  IpmiLanBackupGateway,
+  IpmiLanBackupGatewayMac,
+  IpmiLanCommunityString,
+  IpmiLanReserved3,
+  IpmiLanDestinationType,
+  IpmiLanDestinationAddress
+} IPMI_LAN_OPTION_TYPE;
+
+//
+// IP Address Source
+//
+typedef enum {
+  IpmiUnspecified,
+  IpmiStaticAddrsss,
+  IpmiDynamicAddressBmcDhcp,
+  IpmiDynamicAddressBiosDhcp,
+  IpmiDynamicAddressBmcNonDhcp
+} IPMI_IP_ADDRESS_SRC;
+
+//
+// Destination Type
+//
+typedef enum {
+  IpmiPetTrapDestination,
+  IpmiDirectedEventDestination,
+  IpmiReserved1,
+  IpmiReserved2,
+  IpmiReserved3,
+  IpmiReserved4,
+  IpmiReserved5,
+  IpmiOem1,
+  IpmiOem2
+} IPMI_LAN_DEST_TYPE_DEST_TYPE;
+
+typedef struct {
+  UINT8 NoAuth : 1;
+  UINT8 MD2Auth : 1;
+  UINT8 MD5Auth : 1;
+  UINT8 Reserved1 : 1;
+  UINT8 StraightPswd : 1;
+  UINT8 OemType : 1;
+  UINT8 Reserved2 : 2;
+} IPMI_LAN_AUTH_TYPE;
+
+typedef struct {
+  UINT8 IpAddress[4];
+} IPMI_LAN_IP_ADDRESS;
+
+typedef struct {
+  UINT8 AddressSrc : 4;
+  UINT8 Reserved : 4;
+} IPMI_LAN_IP_ADDRESS_SRC;
+
+typedef struct {
+  UINT8 MacAddress[6];
+} IPMI_LAN_MAC_ADDRESS;
+
+typedef struct {
+  UINT8 IpAddress[4];
+} IPMI_LAN_SUBNET_MASK;
+
+typedef struct {
+  UINT8 TimeToLive;
+  UINT8 IpFlag : 3;
+  UINT8 Reserved1 : 5;
+  UINT8 Precedence : 3;
+  UINT8 Reserved2 : 1;
+  UINT8 ServiceType : 4;
+} IPMI_LAN_IPV4_HDR_PARAM;
+
+typedef struct {
+  UINT8 RcmpPortMsb;
+  UINT8 RcmpPortLsb;
+} IPMI_LAN_RCMP_PORT;
+
+typedef struct {
+  UINT8 EnableBmcArpResponse : 1;
+  UINT8 EnableBmcGratuitousArp : 1;
+  UINT8 Reserved : 6;
+} IPMI_LAN_BMC_GENERATED_ARP_CONTROL;
+
+typedef struct {
+  UINT8 ArpInterval;
+} IPMI_LAN_ARP_INTERVAL;
+
+typedef struct {
+  UINT8 Data[18];
+} IPMI_LAN_COMMUNITY_STRING;
+
+typedef struct {
+  UINT8 DestinationSelector : 4;
+  UINT8 Reserved2 : 4;
+  UINT8 DestinationType : 3;
+  UINT8 Reserved1 : 4;
+  UINT8 AlertAcknowledged : 1;
+} IPMI_LAN_DEST_TYPE;
+
+typedef struct {
+  UINT8               DestinationSelector : 4;
+  UINT8               Reserved1 : 4;
+  UINT8               AlertingIpAddressSelector : 4;
+  UINT8               AddressFormat : 4;
+  UINT8               UseDefaultGateway : 1;
+  UINT8               Reserved2 : 7;
+  IPMI_LAN_IP_ADDRESS  AlertingIpAddress;
+  IPMI_LAN_MAC_ADDRESS AlertingMacAddress;
+} IPMI_LAN_DEST_ADDRESS;
+
+typedef union {
+  IPMI_LAN_AUTH_TYPE                 IpmiLanAuthType;
+  IPMI_LAN_IP_ADDRESS                IpmiLanIpAddress;
+  IPMI_LAN_IP_ADDRESS_SRC            IpmiLanIpAddressSrc;
+  IPMI_LAN_MAC_ADDRESS               IpmiLanMacAddress;
+  IPMI_LAN_SUBNET_MASK               IpmiLanSubnetMask;
+  IPMI_LAN_IPV4_HDR_PARAM            IpmiLanIpv4HdrParam;
+  IPMI_LAN_RCMP_PORT                 IpmiLanPrimaryRcmpPort;
+  IPMI_LAN_BMC_GENERATED_ARP_CONTROL IpmiLanArpControl;
+  IPMI_LAN_ARP_INTERVAL              IpmiLanArpInterval;
+  IPMI_LAN_COMMUNITY_STRING          IpmiLanCommunityString;
+  IPMI_LAN_DEST_TYPE                 IpmiLanDestType;
+  IPMI_LAN_DEST_ADDRESS              IpmiLanDestAddress;
+} IPMI_LAN_OPTIONS;
+
+//
+//  Definitions for Get Lan Configuration Parameters command
+//
+#define IPMI_TRANSPORT_GET_LAN_CONFIG_PARAMETERS 0x02
+
+//
+//  Constants and Structure definitions for "Get Lan Configuration Parameters" command to follow here
+//
+
+//
+//  Definitions for Suspend BMC ARPs command
+//
+#define IPMI_TRANSPORT_SUSPEND_BMC_ARPS  0x03
+
+//
+//  Constants and Structure definitions for "Suspend BMC ARPs" command to follow here
+//
+
+//
+//  Definitions for Get IP-UDP-RMCP Statistics command
+//
+#define IPMI_TRANSPORT_GET_PACKET_STATISTICS 0x04
+
+//
+//  Constants and Structure definitions for "Get IP-UDP-RMCP Statistics" command to follow here
+//
+
+//
+//  Below is Definitions for IPMI Serial/Modem Commands (Chapter 25)
+//
+
+//
+//  Definitions for Set Serial/Modem Configuration command
+//
+#define IPMI_TRANSPORT_SET_SERIAL_CONFIGURATION  0x10
+
+//
+//  Constants and Structure definitions for "Set Serial/Modem Configuration" command to follow here
+//
+
+//
+// EMP OPTION DATA
+//
+typedef struct {
+  UINT8 NoAuthentication : 1;
+  UINT8 MD2Authentication : 1;
+  UINT8 MD5Authentication : 1;
+  UINT8 Reserved1 : 1;
+  UINT8 StraightPassword : 1;
+  UINT8 OemProprietary : 1;
+  UINT8 Reservd2 : 2;
+} IPMI_EMP_AUTH_TYPE;
+
+typedef struct {
+  UINT8 EnableBasicMode : 1;
+  UINT8 EnablePPPMode : 1;
+  UINT8 EnableTerminalMode : 1;
+  UINT8 Reserved1 : 2;
+  UINT8 SnoopOsPPPNegotiation : 1;
+  UINT8 Reserved2 : 1;
+  UINT8 DirectConnect : 1;
+} IPMI_EMP_CONNECTION_TYPE;
+
+typedef struct {
+  UINT8 InactivityTimeout : 4;
+  UINT8 Reserved : 4;
+} IPMI_EMP_INACTIVITY_TIMEOUT;
+
+typedef struct {
+  UINT8 IpmiCallback : 1;
+  UINT8 CBCPCallback : 1;
+  UINT8 Reserved1 : 6;
+  UINT8 CbcpEnableNoCallback : 1;
+  UINT8 CbcpEnablePreSpecifiedNumber : 1;
+  UINT8 CbcpEnableUserSpecifiedNumber : 1;
+  UINT8 CbcpEnableCallbackFromList : 1;
+  UINT8 Reserved : 4;
+  UINT8 CallbackDestination1;
+  UINT8 CallbackDestination2;
+  UINT8 CallbackDestination3;
+} IPMI_EMP_CHANNEL_CALLBACK_CONTROL;
+
+typedef struct {
+  UINT8 CloseSessionOnDCDLoss : 1;
+  UINT8 EnableSessionInactivityTimeout : 1;
+  UINT8 Reserved : 6;
+} IPMI_EMP_SESSION_TERMINATION;
+
+typedef struct {
+  UINT8 Reserved1 : 5;
+  UINT8 EnableDtrHangup : 1;
+  UINT8 FlowControl : 2;
+  UINT8 BitRate : 4;
+  UINT8 Reserved2 : 4;
+  UINT8 SaveSetting : 1;
+  UINT8 SetComPort : 1;
+  UINT8 Reserved3 : 6;
+} IPMI_EMP_MESSAGING_COM_SETTING;
+
+typedef struct {
+  UINT8 RingDurationInterval : 6;
+  UINT8 Reserved1 : 2;
+  UINT8 RingDeadTime : 4;
+  UINT8 Reserved : 4;
+} IPMI_EMP_MODEM_RING_TIME;
+
+typedef struct {
+  UINT8 Reserved;
+  UINT8 InitString[48];
+} IPMI_EMP_MODEM_INIT_STRING;
+
+typedef struct {
+  UINT8 EscapeSequence[5];
+} IPMI_EMP_MODEM_ESC_SEQUENCE;
+
+typedef struct {
+  UINT8 HangupSequence[8];
+} IPMI_EMP_MODEM_HANGUP_SEQUENCE;
+
+typedef struct {
+  UINT8 ModelDialCommend[8];
+} IPMI_MODEM_DIALUP_COMMAND;
+
+typedef struct {
+  UINT8 PageBlackoutInterval;
+} IPMI_PAGE_BLACKOUT_INTERVAL;
+
+typedef struct {
+  UINT8 CommunityString[18];
+} IPMI_EMP_COMMUNITY_STRING;
+
+typedef struct {
+  UINT8 Reserved5 : 4;
+  UINT8 DialStringSelector : 4;
+} IPMI_DIAL_PAGE_DESTINATION;
+
+typedef struct {
+  UINT8 TapAccountSelector : 4;
+  UINT8 Reserved : 4;
+} IPMI_TAP_PAGE_DESTINATION;
+
+typedef struct {
+  UINT8 PPPAccountSetSelector;
+  UINT8 DialStringSelector;
+} IPMI_PPP_ALERT_DESTINATION;
+
+typedef union {
+  IPMI_DIAL_PAGE_DESTINATION    DialPageDestination;
+  IPMI_TAP_PAGE_DESTINATION     TapPageDestination;
+  IPMI_PPP_ALERT_DESTINATION    PppAlertDestination;
+} IPMI_DEST_TYPE_SPECIFIC;
+
+typedef struct {
+  UINT8 DestinationSelector : 4;
+  UINT8 Reserved1 : 4;
+  UINT8 DestinationType : 4;
+  UINT8 Reserved2 : 3;
+  UINT8 AlertAckRequired : 1;
+  UINT8 AlertAckTimeoutSeconds;
+  UINT8 NumRetriesCall : 3;
+  UINT8 Reserved3 : 1;
+  UINT8 NumRetryAlert : 3;
+  UINT8 Reserved4 : 1;
+  IPMI_DEST_TYPE_SPECIFIC DestinationTypeSpecific;
+} IPMI_EMP_DESTINATION_INFO;
+
+typedef struct {
+  UINT8 DestinationSelector : 4;
+  UINT8 Reserved1 : 4;
+  UINT8 Parity : 3;
+  UINT8 CharacterSize : 1;
+  UINT8 StopBit : 1;
+  UINT8 DtrHangup : 1;
+  UINT8 FlowControl : 2;
+  UINT8 BitRate : 4;
+  UINT8 Reserved2 : 4;
+  UINT8 SaveSetting : 1;
+  UINT8 SetComPort : 1;
+  UINT8 Reserved3 : 6;
+} IPMI_EMP_DESTINATION_COM_SETTING;
+
+typedef struct {
+  UINT8 DialStringSelector : 4;
+  UINT8 Reserved1 : 4;
+  UINT8 Reserved2;
+  UINT8 DialString[48];
+} IPMI_DESTINATION_DIAL_STRING;
+
+typedef union {
+  UINT32  IpAddressLong;
+  UINT8   IpAddress[4];
+} IPMI_PPP_IP_ADDRESS;
+
+typedef struct {
+  UINT8 IpAddressSelector : 4;
+  UINT8 Reserved1 : 4;
+  IPMI_PPP_IP_ADDRESS PppIpAddress;
+} IPMI_DESTINATION_IP_ADDRESS;
+
+typedef struct {
+  UINT8 TapSelector;
+  UINT8 TapServiceSelector : 4;
+  UINT8 TapDialStringSelector : 4;
+} IPMI_DESTINATION_TAP_ACCOUNT;
+
+typedef struct {
+  UINT8 TapSelector;
+  UINT8 PagerIdString[16];
+} IPMI_TAP_PAGER_ID_STRING;
+
+typedef union {
+  UINT8                              OptionData;
+  IPMI_EMP_AUTH_TYPE                 EmpAuthType;
+  IPMI_EMP_CONNECTION_TYPE           EmpConnectionType;
+  IPMI_EMP_INACTIVITY_TIMEOUT        EmpInactivityTimeout;
+  IPMI_EMP_CHANNEL_CALLBACK_CONTROL  EmpCallbackControl;
+  IPMI_EMP_SESSION_TERMINATION       EmpSessionTermination;
+  IPMI_EMP_MESSAGING_COM_SETTING     EmpMessagingComSetting;
+  IPMI_EMP_MODEM_RING_TIME           EmpModemRingTime;
+  IPMI_EMP_MODEM_INIT_STRING         EmpModemInitString;
+  IPMI_EMP_MODEM_ESC_SEQUENCE        EmpModemEscSequence;
+  IPMI_EMP_MODEM_HANGUP_SEQUENCE     EmpModemHangupSequence;
+  IPMI_MODEM_DIALUP_COMMAND          EmpModemDialupCommand;
+  IPMI_PAGE_BLACKOUT_INTERVAL        EmpPageBlackoutInterval;
+  IPMI_EMP_COMMUNITY_STRING          EmpCommunityString;
+  IPMI_EMP_DESTINATION_INFO          EmpDestinationInfo;
+  IPMI_EMP_DESTINATION_COM_SETTING   EmpDestinationComSetting;
+  UINT8                              CallRetryBusySignalInterval;
+  IPMI_DESTINATION_DIAL_STRING       DestinationDialString;
+  IPMI_DESTINATION_IP_ADDRESS        DestinationIpAddress;
+  IPMI_DESTINATION_TAP_ACCOUNT       DestinationTapAccount;
+  IPMI_TAP_PAGER_ID_STRING           TapPagerIdString;
+} IPMI_EMP_OPTIONS;
+
+//
+//  Definitions for Get Serial/Modem Configuration command
+//
+#define IPMI_TRANSPORT_GET_SERIAL_CONFIGURATION  0x11
+
+//
+//  Constants and Structure definitions for "Get Serial/Modem Configuration" command to follow here
+//
+
+//
+//  Definitions for Set Serial/Modem Mux command
+//
+#define IPMI_TRANSPORT_SET_SERIAL_MUX  0x12
+
+//
+//  Constants and Structure definitions for "Set Serial/Modem Mux" command to follow here
+//
+typedef struct {
+  UINT8 ChannelNo : 4;
+  UINT8 Reserved1 : 4;
+  UINT8 MuxSetting : 4;
+  UINT8 Reserved2 : 4;
+} IPMI_SET_SERIAL_MODEM_MUX_COMMAND_REQUEST;
+
+typedef struct {
+  UINT8 MuxSetToBmc : 1;
+  UINT8 CommandStatus : 1;
+  UINT8 MessagingSessionActive : 1;
+  UINT8 AlertInProgress : 1;
+  UINT8 Reserved2 : 2;
+  UINT8 MuxToBmcAllowed : 1;
+  UINT8 MuxToSystemBlocked : 1;
+} IPMI_SET_SERIAL_MODEM_MUX_COMMAND_RESPONSE;
+
+//
+//  Definitions for Get TAP Response Code command
+//
+#define IPMI_TRANSPORT_GET_TAP_RESPONSE_CODE 0x13
+
+//
+//  Constants and Structure definitions for "Get TAP Response Code" command to follow here
+//
+
+//
+//  Definitions for Set PPP UDP Proxy Transmit Data command
+//
+#define IPMI_TRANSPORT_SET_PPP_UDP_PROXY_TXDATA  0x14
+
+//
+//  Constants and Structure definitions for "Set PPP UDP Proxy Transmit Data" command to follow here
+//
+
+//
+//  Definitions for Get PPP UDP Proxy Transmit Data command
+//
+#define IPMI_TRANSPORT_GET_PPP_UDP_PROXY_TXDATA  0x15
+
+//
+//  Constants and Structure definitions for "Get PPP UDP Proxy Transmit Data" command to follow here
+//
+
+//
+//  Definitions for Send PPP UDP Proxy Packet command
+//
+#define IPMI_TRANSPORT_SEND_PPP_UDP_PROXY_PACKET 0x16
+
+//
+//  Constants and Structure definitions for "Send PPP UDP Proxy Packet" command to follow here
+//
+
+//
+//  Definitions for Get PPP UDP Proxy Receive Data command
+//
+#define IPMI_TRANSPORT_GET_PPP_UDP_PROXY_RX  0x17
+
+//
+//  Constants and Structure definitions for "Get PPP UDP Proxy Receive Data" command to follow here
+//
+
+//
+//  Definitions for Serial/Modem connection active command
+//
+#define IPMI_TRANSPORT_SERIAL_CONNECTION_ACTIVE  0x18
+
+//
+//  Constants and Structure definitions for "Serial/Modem connection active" command to follow here
+//
+
+//
+//  Definitions for Callback command
+//
+#define IPMI_TRANSPORT_CALLBACK  0x19
+
+//
+//  Constants and Structure definitions for "Callback" command to follow here
+//
+
+//
+//  Definitions for Set user Callback Options command
+//
+#define IPMI_TRANSPORT_SET_USER_CALLBACK_OPTIONS 0x1A
+
+//
+//  Constants and Structure definitions for "Set user Callback Options" command to follow here
+//
+
+//
+//  Definitions for Get user Callback Options command
+//
+#define IPMI_TRANSPORT_GET_USER_CALLBACK_OPTIONS 0x1B
+
+//
+//  Constants and Structure definitions for "Get user Callback Options" command to follow here
+//
+
+//
+//  Below is Definitions for SOL Commands (Chapter 26)
+//
+
+//
+//  Definitions for SOL activating command
+//
+#define IPMI_TRANSPORT_SOL_ACTIVATING  0x20
+
+//
+//  Constants and Structure definitions for "SOL activating" command to follow here
+//
+
+//
+//  Definitions for Set SOL Configuration Parameters command
+//
+#define IPMI_TRANSPORT_SET_SOL_CONFIG_PARAM  0x21
+
+//
+//  Constants and Structure definitions for "Set SOL Configuration Parameters" command to follow here
+//
+
+//
+//  Definitions for Get SOL Configuration Parameters command
+//
+#define IPMI_TRANSPORT_GET_SOL_CONFIG_PARAM  0x22
+
+//
+//  Constants and Structure definitions for "Get SOL Configuration Parameters" command to follow here
+//
+#pragma pack()
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/LegacyBiosMpTable.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/LegacyBiosMpTable.h
new file mode 100644
index 0000000000..41045bd976
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/LegacyBiosMpTable.h
@@ -0,0 +1,294 @@
+/** @file
+  Defives data structures per MultiProcessor Specification Ver 1.4.
+  
+  The MultiProcessor Specification defines an enhancement to the standard 
+  to which PC manufacturers design DOS-compatible systems.
+
+Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php                                            
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+**/
+
+#ifndef _LEGACY_BIOS_MPTABLE_H_
+#define _LEGACY_BIOS_MPTABLE_H_
+
+#define EFI_LEGACY_MP_TABLE_REV_1_4 0x04
+
+//
+// Define MP table structures. All are packed.
+//
+#pragma pack(1)
+
+#define EFI_LEGACY_MP_TABLE_FLOATING_POINTER_SIGNATURE  SIGNATURE_32 ('_', 'M', 'P', '_')
+typedef struct {
+  UINT32  Reserved1 : 6;
+  UINT32  MutipleClk : 1;
+  UINT32  Imcr : 1;
+  UINT32  Reserved2 : 24;
+} FEATUREBYTE2_5;
+
+typedef struct {
+  UINT32  Signature;
+  UINT32  PhysicalAddress;
+  UINT8   Length;
+  UINT8   SpecRev;
+  UINT8   Checksum;
+  UINT8   FeatureByte1;
+  FEATUREBYTE2_5 FeatureByte2_5;
+} EFI_LEGACY_MP_TABLE_FLOATING_POINTER;
+
+#define EFI_LEGACY_MP_TABLE_HEADER_SIGNATURE  SIGNATURE_32 ('P', 'C', 'M', 'P')
+typedef struct {
+  UINT32  Signature;
+  UINT16  BaseTableLength;
+  UINT8   SpecRev;
+  UINT8   Checksum;
+  CHAR8   OemId[8];
+  CHAR8   OemProductId[12];
+  UINT32  OemTablePointer;
+  UINT16  OemTableSize;
+  UINT16  EntryCount;
+  UINT32  LocalApicAddress;
+  UINT16  ExtendedTableLength;
+  UINT8   ExtendedChecksum;
+  UINT8   Reserved;
+} EFI_LEGACY_MP_TABLE_HEADER;
+
+typedef struct {
+  UINT8 EntryType;
+} EFI_LEGACY_MP_TABLE_ENTRY_TYPE;
+
+//
+// Entry Type 0: Processor.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_PROCESSOR  0x00
+typedef struct {
+  UINT8 Enabled : 1;
+  UINT8 Bsp : 1;
+  UINT8 Reserved : 6;
+} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_FLAGS;
+
+typedef struct {
+  UINT32  Stepping : 4;
+  UINT32  Model : 4;
+  UINT32  Family : 4;
+  UINT32  Reserved : 20;
+} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_SIGNATURE;
+
+typedef struct {
+  UINT32  Fpu : 1;
+  UINT32  Reserved1 : 6;
+  UINT32  Mce : 1;
+  UINT32  Cx8 : 1;
+  UINT32  Apic : 1;
+  UINT32  Reserved2 : 22;
+} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_FEATURES;
+
+typedef struct {
+  UINT8 EntryType;
+  UINT8 Id;
+  UINT8 Ver;
+  EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_FLAGS     Flags;
+  EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_SIGNATURE Signature;
+  EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_FEATURES  Features;
+  UINT32  Reserved1;
+  UINT32  Reserved2;
+} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR;
+
+//
+// Entry Type 1: Bus.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_BUS  0x01
+typedef struct {
+  UINT8 EntryType;
+  UINT8 Id;
+  CHAR8 TypeString[6];
+} EFI_LEGACY_MP_TABLE_ENTRY_BUS;
+
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUS   "CBUS  "  // Corollary CBus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUSII "CBUSII"  // Corollary CBUS II
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_EISA   "EISA  "  // Extended ISA
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_FUTURE "FUTURE"  // IEEE FutureBus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_INTERN "INTERN"  // Internal bus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_ISA    "ISA   "  // Industry Standard Architecture
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBI    "MBI   "  // Multibus I
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBII   "MBII  "  // Multibus II
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MCA    "MCA   "  // Micro Channel Architecture
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPI    "MPI   "  // MPI
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPSA   "MPSA  "  // MPSA
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_NUBUS  "NUBUS "  // Apple Macintosh NuBus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCI    "PCI   "  // Peripheral Component Interconnect
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCMCIA "PCMCIA"  // PC Memory Card International Assoc.
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_TC     "TC    "  // DEC TurboChannel
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VL     "VL    "  // VESA Local Bus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VME    "VME   "  // VMEbus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_XPRESS "XPRESS"  // Express System Bus
+//
+// Entry Type 2: I/O APIC.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IOAPIC 0x02
+typedef struct {
+  UINT8 Enabled : 1;
+  UINT8 Reserved : 7;
+} EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC_FLAGS;
+
+typedef struct {
+  UINT8 EntryType;
+  UINT8 Id;
+  UINT8 Ver;
+  EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC_FLAGS Flags;
+  UINT32  Address;
+} EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC;
+
+//
+// Entry Type 3: I/O Interrupt Assignment.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IO_INT 0x03
+typedef struct {
+  UINT16  Polarity : 2;
+  UINT16  Trigger : 2;
+  UINT16  Reserved : 12;
+} EFI_LEGACY_MP_TABLE_ENTRY_INT_FLAGS;
+
+typedef struct {
+  UINT8 IntNo : 2;
+  UINT8 Dev : 5;
+  UINT8 Reserved : 1;
+} EFI_LEGACY_MP_TABLE_ENTRY_INT_FIELDS;
+
+typedef union {
+  EFI_LEGACY_MP_TABLE_ENTRY_INT_FIELDS fields;
+  UINT8 byte;
+} EFI_LEGACY_MP_TABLE_ENTRY_INT_SOURCE_BUS_IRQ;
+
+typedef struct {
+  UINT8 EntryType;
+  UINT8 IntType;
+  EFI_LEGACY_MP_TABLE_ENTRY_INT_FLAGS Flags;
+  UINT8 SourceBusId;
+  EFI_LEGACY_MP_TABLE_ENTRY_INT_SOURCE_BUS_IRQ SourceBusIrq;
+  UINT8 DestApicId;
+  UINT8 DestApicIntIn;
+} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT;
+
+typedef enum {
+  EfiLegacyMpTableEntryIoIntTypeInt   = 0,
+  EfiLegacyMpTableEntryIoIntTypeNmi   = 1,
+  EfiLegacyMpTableEntryIoIntTypeSmi   = 2,
+  EfiLegacyMpTableEntryIoIntTypeExtInt= 3,
+} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_TYPE;
+
+typedef enum {
+  EfiLegacyMpTableEntryIoIntFlagsPolaritySpec       = 0x0,
+  EfiLegacyMpTableEntryIoIntFlagsPolarityActiveHigh = 0x1,
+  EfiLegacyMpTableEntryIoIntFlagsPolarityReserved   = 0x2,
+  EfiLegacyMpTableEntryIoIntFlagsPolarityActiveLow  = 0x3,
+} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_POLARITY;
+
+typedef enum {
+  EfiLegacyMpTableEntryIoIntFlagsTriggerSpec        = 0x0,
+  EfiLegacyMpTableEntryIoIntFlagsTriggerEdge        = 0x1,
+  EfiLegacyMpTableEntryIoIntFlagsTriggerReserved    = 0x2,
+  EfiLegacyMpTableEntryIoIntFlagsTriggerLevel       = 0x3,
+} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_TRIGGER;
+
+//
+// Entry Type 4: Local Interrupt Assignment.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_LOCAL_INT  0x04
+typedef struct {
+  UINT8 EntryType;
+  UINT8 IntType;
+  EFI_LEGACY_MP_TABLE_ENTRY_INT_FLAGS Flags;
+  UINT8 SourceBusId;
+  EFI_LEGACY_MP_TABLE_ENTRY_INT_SOURCE_BUS_IRQ SourceBusIrq;
+  UINT8 DestApicId;
+  UINT8 DestApicIntIn;
+} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT;
+
+typedef enum {
+  EfiLegacyMpTableEntryLocalIntTypeInt              = 0,
+  EfiLegacyMpTableEntryLocalIntTypeNmi              = 1,
+  EfiLegacyMpTableEntryLocalIntTypeSmi              = 2,
+  EfiLegacyMpTableEntryLocalIntTypeExtInt           = 3,
+} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_TYPE;
+
+typedef enum {
+  EfiLegacyMpTableEntryLocalIntFlagsPolaritySpec      = 0x0,
+  EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveHigh= 0x1,
+  EfiLegacyMpTableEntryLocalIntFlagsPolarityReserved  = 0x2,
+  EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveLow = 0x3,
+} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_POLARITY;
+
+typedef enum {
+  EfiLegacyMpTableEntryLocalIntFlagsTriggerSpec       = 0x0,
+  EfiLegacyMpTableEntryLocalIntFlagsTriggerEdge       = 0x1,
+  EfiLegacyMpTableEntryLocalIntFlagsTriggerReserved   = 0x2,
+  EfiLegacyMpTableEntryLocalIntFlagsTriggerLevel      = 0x3,
+} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_TRIGGER;
+
+//
+// Entry Type 128: System Address Space Mapping.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_SYS_ADDR_SPACE_MAPPING 0x80
+typedef struct {
+  UINT8   EntryType;
+  UINT8   Length;
+  UINT8   BusId;
+  UINT8   AddressType;
+  UINT64  AddressBase;
+  UINT64  AddressLength;
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING;
+
+typedef enum {
+  EfiLegacyMpTableEntryExtSysAddrSpaceMappingIo       = 0,
+  EfiLegacyMpTableEntryExtSysAddrSpaceMappingMemory   = 1,
+  EfiLegacyMpTableEntryExtSysAddrSpaceMappingPrefetch = 2,
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING_TYPE;
+
+//
+// Entry Type 129: Bus Hierarchy.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_BUS_HIERARCHY  0x81
+typedef struct {
+  UINT8 SubtractiveDecode : 1;
+  UINT8 Reserved : 7;
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY_BUSINFO;
+
+typedef struct {
+  UINT8 EntryType;
+  UINT8 Length;
+  UINT8 BusId;
+  EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY_BUSINFO BusInfo;
+  UINT8 ParentBus;
+  UINT8 Reserved1;
+  UINT8 Reserved2;
+  UINT8 Reserved3;
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY;
+
+//
+// Entry Type 130: Compatibility Bus Address Space Modifier.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_COMPAT_BUS_ADDR_SPACE_MODIFIER 0x82
+typedef struct {
+  UINT8 RangeMode : 1;
+  UINT8 Reserved : 7;
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER_ADDR_MODE;
+
+typedef struct {
+  UINT8 EntryType;
+  UINT8 Length;
+  UINT8 BusId;
+  EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER_ADDR_MODE AddrMode;
+  UINT32  PredefinedRangeList;
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h
new file mode 100644
index 0000000000..2b361ed390
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h
@@ -0,0 +1,82 @@
+/** @file
+  ACPI Low Power Idle Table (LPIT) definitions
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Revision Reference:
+    - ACPI Low Power Idle Table (LPIT) Revision 001, dated July 2014
+      http://www.uefi.org/sites/default/files/resources/ACPI_Low_Power_Idle_Table.pdf
+
+  @par Glossary:
+    - GAS - Generic Address Structure
+    - LPI - Low Power Idle
+**/
+#ifndef _LOW_POWER_IDLE_TABLE_H_
+#define _LOW_POWER_IDLE_TABLE_H_
+
+#include <IndustryStandard/Acpi.h>
+
+#pragma pack(1)
+
+///
+/// LPI Structure Types
+///
+#define ACPI_LPI_STRUCTURE_TYPE_NATIVE_CSTATE     0x00
+
+///
+/// Low Power Idle (LPI) State Flags
+///
+typedef union {
+  struct {
+    UINT32 Disabled           : 1;  ///< If set, LPI state is not used
+    /**
+      If set, Residency counter is not available for this LPI state and
+      Residency Counter Frequency is invalid
+    **/
+    UINT32 CounterUnavailable : 1;
+    UINT32 Reserved           : 30; ///< Reserved for future use. Must be zero
+  } Bits;
+  UINT32 Data32;
+} ACPI_LPI_STATE_FLAGS;
+
+///
+/// Low Power Idle (LPI) structure with Native C-state instruction entry trigger descriptor
+///
+typedef struct {
+  UINT32                                  Type;   ///< LPI State descriptor Type 0
+  UINT32                                  Length; ///< Length of LPI state Descriptor Structure
+  ///
+  /// Unique LPI state identifier: zero based, monotonically increasing identifier
+  ///
+  UINT16                                  UniqueId;
+  UINT8                                   Reserved[2];  ///< Must be Zero
+  ACPI_LPI_STATE_FLAGS                    Flags;        ///< LPI state flags
+  /**
+    The LPI entry trigger, matching an existing _CST.Register object, represented as a
+    Generic Address Structure. All processors must request this state or deeper to trigger.
+  **/
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE  EntryTrigger;
+  UINT32                                  Residency;  ///< Minimum residency or break-even in uSec
+  UINT32                                  Latency;    ///< Worst case exit latency in uSec
+  /**
+    [optional] Residency counter, represented as a Generic Address Structure.
+    If not present, Flags[1] bit should be set.
+  **/
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE  ResidencyCounter;
+  /**
+    [optional] Residency counter frequency in cycles per second. Value 0 indicates that
+    counter runs at TSC frequency. Valid only if Residency Counter is present.
+  **/
+  UINT64                                  ResidencyCounterFrequency;
+} ACPI_LPI_NATIVE_CSTATE_DESCRIPTOR;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Mbr.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Mbr.h
new file mode 100644
index 0000000000..302e44d773
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Mbr.h
@@ -0,0 +1,60 @@
+/** @file
+  Legacy Master Boot Record Format Definition.
+
+Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php
+                                                                                          
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+**/
+
+#ifndef _MBR_H_
+#define _MBR_H_
+
+#define MBR_SIGNATURE               0xaa55
+
+#define EXTENDED_DOS_PARTITION      0x05
+#define EXTENDED_WINDOWS_PARTITION  0x0F
+
+#define MAX_MBR_PARTITIONS          4
+
+#define PMBR_GPT_PARTITION          0xEE
+#define EFI_PARTITION               0xEF
+
+#define MBR_SIZE                    512
+
+#pragma pack(1)
+///
+/// MBR Partition Entry
+///
+typedef struct {
+  UINT8 BootIndicator;
+  UINT8 StartHead;
+  UINT8 StartSector;
+  UINT8 StartTrack;
+  UINT8 OSIndicator;
+  UINT8 EndHead;
+  UINT8 EndSector;
+  UINT8 EndTrack;
+  UINT8 StartingLBA[4];
+  UINT8 SizeInLBA[4];
+} MBR_PARTITION_RECORD;
+
+///
+/// MBR Partition Table
+///
+typedef struct {
+  UINT8                 BootStrapCode[440];
+  UINT8                 UniqueMbrSignature[4];
+  UINT8                 Unknown[2];
+  MBR_PARTITION_RECORD  Partition[MAX_MBR_PARTITIONS];
+  UINT16                Signature;
+} MASTER_BOOT_RECORD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h
new file mode 100644
index 0000000000..d855d9b271
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h
@@ -0,0 +1,53 @@
+/** @file
+  ACPI memory mapped configuration space access table definition, defined at 
+  in the PCI Firmware Specification, version 3.0.
+  Specification is available at http://www.pcisig.com.
+    
+  Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+**/
+
+#ifndef _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_
+#define _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// Memory Mapped Configuration Space Access Table (MCFG)
+/// This table is a basic description table header followed by
+/// a number of base address allocation structures.
+///
+typedef struct {
+  UINT64  BaseAddress;
+  UINT16  PciSegmentGroupNumber;
+  UINT8   StartBusNumber;
+  UINT8   EndBusNumber;
+  UINT32  Reserved;
+} EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE;
+
+///
+/// MCFG Table header definition.  The rest of the table 
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER                       Header;
+  UINT64                                            Reserved;
+} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER;
+
+///
+/// MCFG Revision (defined in spec)
+///
+#define EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION  0x01
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/MemoryOverwriteRequestControlLock.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/MemoryOverwriteRequestControlLock.h
new file mode 100644
index 0000000000..415c134779
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/MemoryOverwriteRequestControlLock.h
@@ -0,0 +1,43 @@
+/** @file
+  Support for Microsoft Secure MOR implementation, defined at 
+  Microsoft Secure MOR implementation.
+  https://msdn.microsoft.com/en-us/library/windows/hardware/mt270973(v=vs.85).aspx
+
+  Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __MEMORY_OVERWRITE_REQUEST_CONTROL_LOCK_H__
+#define __MEMORY_OVERWRITE_REQUEST_CONTROL_LOCK_H__
+
+#define MEMORY_OVERWRITE_REQUEST_CONTROL_LOCK_GUID \
+  { \
+    0xBB983CCF, 0x151D, 0x40E1, {0xA0, 0x7B, 0x4A, 0x17, 0xBE, 0x16, 0x82, 0x92} \
+  }
+
+#define MEMORY_OVERWRITE_REQUEST_CONTROL_LOCK_NAME L"MemoryOverwriteRequestControlLock"
+
+//
+// VendorGuid: {BB983CCF-151D-40E1-A07B-4A17BE168292}
+// Name:       MemoryOverwriteRequestControlLock
+// Attributes: NV+BS+RT
+// GetVariable value in Data parameter: 0x0 (unlocked); 0x1 (locked without key); 0x2 (locked with key)
+// SetVariable value in Data parameter: 0x0 (unlocked); 0x1 (locked);
+//                                      Revision 2 additionally accepts an 8-byte value that represents a shared secret key.
+//
+
+//
+// Note: Setting MemoryOverwriteRequestControlLock does not commit to flash (just changes the internal lock state).
+// Getting the variable returns the internal state and never exposes the key.
+//
+
+extern EFI_GUID gEfiMemoryOverwriteRequestControlLockGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Nvme.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Nvme.h
new file mode 100644
index 0000000000..49ce876805
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Nvme.h
@@ -0,0 +1,939 @@
+/** @file
+  Definitions based on NVMe spec. version 1.1.
+
+  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  NVMe Specification 1.1
+
+**/
+
+#ifndef __NVM_E_H__
+#define __NVM_E_H__
+
+#pragma pack(1)
+
+//
+// controller register offsets
+//
+#define NVME_CAP_OFFSET          0x0000  // Controller Capabilities
+#define NVME_VER_OFFSET          0x0008  // Version
+#define NVME_INTMS_OFFSET        0x000c  // Interrupt Mask Set
+#define NVME_INTMC_OFFSET        0x0010  // Interrupt Mask Clear
+#define NVME_CC_OFFSET           0x0014  // Controller Configuration
+#define NVME_CSTS_OFFSET         0x001c  // Controller Status
+#define NVME_NSSR_OFFSET         0x0020  // NVM Subsystem Reset
+#define NVME_AQA_OFFSET          0x0024  // Admin Queue Attributes
+#define NVME_ASQ_OFFSET          0x0028  // Admin Submission Queue Base Address
+#define NVME_ACQ_OFFSET          0x0030  // Admin Completion Queue Base Address
+#define NVME_SQ0_OFFSET          0x1000  // Submission Queue 0 (admin) Tail Doorbell
+#define NVME_CQ0_OFFSET          0x1004  // Completion Queue 0 (admin) Head Doorbell
+
+//
+// These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))
+// Get the doorbell stride bit shift value from the controller capabilities.
+//
+#define NVME_SQTDBL_OFFSET(QID, DSTRD)    0x1000 + ((2 * (QID)) * (4 << (DSTRD)))       // Submission Queue y (NVM) Tail Doorbell
+#define NVME_CQHDBL_OFFSET(QID, DSTRD)    0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell
+
+
+#pragma pack(1)
+
+//
+// 3.1.1 Offset 00h: CAP - Controller Capabilities
+//
+typedef struct {
+  UINT16 Mqes;      // Maximum Queue Entries Supported
+  UINT8  Cqr:1;     // Contiguous Queues Required
+  UINT8  Ams:2;     // Arbitration Mechanism Supported
+  UINT8  Rsvd1:5;
+  UINT8  To;        // Timeout
+  UINT16 Dstrd:4;
+  UINT16 Nssrs:1;   // NVM Subsystem Reset Supported NSSRS
+  UINT16 Css:4;     // Command Sets Supported - Bit 37
+  UINT16 Rsvd3:7;
+  UINT8  Mpsmin:4;
+  UINT8  Mpsmax:4;
+  UINT8  Rsvd4;
+} NVME_CAP;
+
+//
+// 3.1.2 Offset 08h: VS - Version
+//
+typedef struct {
+  UINT16 Mnr;       // Minor version number
+  UINT16 Mjr;       // Major version number
+} NVME_VER;
+
+//
+// 3.1.5 Offset 14h: CC - Controller Configuration
+//
+typedef struct {
+  UINT16 En:1;       // Enable
+  UINT16 Rsvd1:3;
+  UINT16 Css:3;      // I/O Command Set Selected
+  UINT16 Mps:4;      // Memory Page Size
+  UINT16 Ams:3;      // Arbitration Mechanism Selected
+  UINT16 Shn:2;      // Shutdown Notification
+  UINT8  Iosqes:4;   // I/O Submission Queue Entry Size
+  UINT8  Iocqes:4;   // I/O Completion Queue Entry Size
+  UINT8  Rsvd2;
+} NVME_CC;
+#define NVME_CC_SHN_NORMAL_SHUTDOWN    1
+#define NVME_CC_SHN_ABRUPT_SHUTDOWN    2
+
+//
+// 3.1.6 Offset 1Ch: CSTS - Controller Status
+//
+typedef struct {
+  UINT32 Rdy:1;      // Ready
+  UINT32 Cfs:1;      // Controller Fatal Status
+  UINT32 Shst:2;     // Shutdown Status
+  UINT32 Nssro:1;    // NVM Subsystem Reset Occurred
+  UINT32 Rsvd1:27;
+} NVME_CSTS;
+#define NVME_CSTS_SHST_SHUTDOWN_OCCURRING 1
+#define NVME_CSTS_SHST_SHUTDOWN_COMPLETED 2
+//
+// 3.1.8 Offset 24h: AQA - Admin Queue Attributes
+//
+typedef struct {
+  UINT16 Asqs:12;    // Submission Queue Size
+  UINT16 Rsvd1:4;
+  UINT16 Acqs:12;    // Completion Queue Size
+  UINT16 Rsvd2:4;
+} NVME_AQA;
+
+//
+// 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address
+//
+#define NVME_ASQ      UINT64
+//
+// 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address
+//
+#define NVME_ACQ      UINT64
+
+//
+// 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell
+//
+typedef struct {
+  UINT16 Sqt;
+  UINT16 Rsvd1;
+} NVME_SQTDBL;
+
+//
+// 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell
+//
+typedef struct {
+  UINT16 Cqh;
+  UINT16 Rsvd1;
+} NVME_CQHDBL;
+
+//
+// NVM command set structures
+//
+// Read Command
+//
+typedef struct {
+  //
+  // CDW 10, 11
+  //
+  UINT64 Slba;                /* Starting Sector Address */
+  //
+  // CDW 12
+  //
+  UINT16 Nlb;                 /* Number of Sectors */
+  UINT16 Rsvd1:10;
+  UINT16 Prinfo:4;            /* Protection Info Check */
+  UINT16 Fua:1;               /* Force Unit Access */
+  UINT16 Lr:1;                /* Limited Retry */
+  //
+  // CDW 13
+  //
+  UINT32 Af:4;                /* Access Frequency */
+  UINT32 Al:2;                /* Access Latency */
+  UINT32 Sr:1;                /* Sequential Request */
+  UINT32 In:1;                /* Incompressible */
+  UINT32 Rsvd2:24;
+  //
+  // CDW 14
+  //
+  UINT32 Eilbrt;              /* Expected Initial Logical Block Reference Tag */
+  //
+  // CDW 15
+  //
+  UINT16 Elbat;               /* Expected Logical Block Application Tag */
+  UINT16 Elbatm;              /* Expected Logical Block Application Tag Mask */
+} NVME_READ;
+
+//
+// Write Command
+//
+typedef struct {
+  //
+  // CDW 10, 11
+  //
+  UINT64 Slba;                /* Starting Sector Address */
+  //
+  // CDW 12
+  //
+  UINT16 Nlb;                 /* Number of Sectors */
+  UINT16 Rsvd1:10;
+  UINT16 Prinfo:4;            /* Protection Info Check */
+  UINT16 Fua:1;               /* Force Unit Access */
+  UINT16 Lr:1;                /* Limited Retry */
+  //
+  // CDW 13
+  //
+  UINT32 Af:4;                /* Access Frequency */
+  UINT32 Al:2;                /* Access Latency */
+  UINT32 Sr:1;                /* Sequential Request */
+  UINT32 In:1;                /* Incompressible */
+  UINT32 Rsvd2:24;
+  //
+  // CDW 14
+  //
+  UINT32 Ilbrt;               /* Initial Logical Block Reference Tag */
+  //
+  // CDW 15
+  //
+  UINT16 Lbat;                /* Logical Block Application Tag */
+  UINT16 Lbatm;               /* Logical Block Application Tag Mask */
+} NVME_WRITE;
+
+//
+// Flush
+//
+typedef struct {
+  //
+  // CDW 10
+  //
+  UINT32 Flush;               /* Flush */
+} NVME_FLUSH;
+
+//
+// Write Uncorrectable command
+//
+typedef struct {
+  //
+  // CDW 10, 11
+  //
+  UINT64 Slba;                /* Starting LBA */
+  //
+  // CDW 12
+  //
+  UINT32 Nlb:16;              /* Number of  Logical Blocks */
+  UINT32 Rsvd1:16;
+} NVME_WRITE_UNCORRECTABLE;
+
+//
+// Write Zeroes command
+//
+typedef struct {
+  //
+  // CDW 10, 11
+  //
+  UINT64 Slba;                /* Starting LBA */
+  //
+  // CDW 12
+  //
+  UINT16 Nlb;                 /* Number of Logical Blocks */
+  UINT16 Rsvd1:10;
+  UINT16 Prinfo:4;            /* Protection Info Check */
+  UINT16 Fua:1;               /* Force Unit Access */
+  UINT16 Lr:1;                /* Limited Retry */
+  //
+  // CDW 13
+  //
+  UINT32 Rsvd2;
+  //
+  // CDW 14
+  //
+  UINT32 Ilbrt;               /* Initial Logical Block Reference Tag */
+  //
+  // CDW 15
+  //
+  UINT16 Lbat;                /* Logical Block Application Tag */
+  UINT16 Lbatm;               /* Logical Block Application Tag Mask */
+} NVME_WRITE_ZEROES;
+
+//
+// Compare command
+//
+typedef struct {
+  //
+  // CDW 10, 11
+  //
+  UINT64 Slba;                /* Starting LBA */
+  //
+  // CDW 12
+  //
+  UINT16 Nlb;                 /* Number of Logical Blocks */
+  UINT16 Rsvd1:10;
+  UINT16 Prinfo:4;            /* Protection Info Check */
+  UINT16 Fua:1;               /* Force Unit Access */
+  UINT16 Lr:1;                /* Limited Retry */
+  //
+  // CDW 13
+  //
+  UINT32 Rsvd2;
+  //
+  // CDW 14
+  //
+  UINT32 Eilbrt;              /* Expected Initial Logical Block Reference Tag */
+  //
+  // CDW 15
+  //
+  UINT16 Elbat;               /* Expected Logical Block Application Tag */
+  UINT16 Elbatm;              /* Expected Logical Block Application Tag Mask */
+} NVME_COMPARE;
+
+typedef union {
+  NVME_READ                   Read;
+  NVME_WRITE                  Write;
+  NVME_FLUSH                  Flush;
+  NVME_WRITE_UNCORRECTABLE    WriteUncorrectable;
+  NVME_WRITE_ZEROES           WriteZeros;
+  NVME_COMPARE                Compare;
+} NVME_CMD;
+
+typedef struct {
+  UINT16 Mp;                /* Maximum Power */
+  UINT8  Rsvd1;             /* Reserved as of Nvm Express 1.1 Spec */
+  UINT8  Mps:1;             /* Max Power Scale */
+  UINT8  Nops:1;            /* Non-Operational State */
+  UINT8  Rsvd2:6;           /* Reserved as of Nvm Express 1.1 Spec */
+  UINT32 Enlat;             /* Entry Latency */
+  UINT32 Exlat;             /* Exit Latency */
+  UINT8  Rrt:5;             /* Relative Read Throughput */
+  UINT8  Rsvd3:3;           /* Reserved as of Nvm Express 1.1 Spec */
+  UINT8  Rrl:5;             /* Relative Read Leatency */
+  UINT8  Rsvd4:3;           /* Reserved as of Nvm Express 1.1 Spec */
+  UINT8  Rwt:5;             /* Relative Write Throughput */
+  UINT8  Rsvd5:3;           /* Reserved as of Nvm Express 1.1 Spec */
+  UINT8  Rwl:5;             /* Relative Write Leatency */
+  UINT8  Rsvd6:3;           /* Reserved as of Nvm Express 1.1 Spec */
+  UINT8  Rsvd7[16];         /* Reserved as of Nvm Express 1.1 Spec */
+} NVME_PSDESCRIPTOR;
+
+//
+//  Identify Controller Data
+//
+typedef struct {
+  //
+  // Controller Capabilities and Features 0-255
+  //
+  UINT16 Vid;                 /* PCI Vendor ID */
+  UINT16 Ssvid;               /* PCI sub-system vendor ID */
+  UINT8  Sn[20];              /* Product serial number */
+
+  UINT8  Mn[40];              /* Proeduct model number */
+  UINT8  Fr[8];               /* Firmware Revision */
+  UINT8  Rab;                 /* Recommended Arbitration Burst */
+  UINT8  Ieee_oui[3];         /* Organization Unique Identifier */
+  UINT8  Cmic;                /* Multi-interface Capabilities */
+  UINT8  Mdts;                /* Maximum Data Transfer Size */
+  UINT8  Cntlid[2];           /* Controller ID */
+  UINT8  Rsvd1[176];          /* Reserved as of Nvm Express 1.1 Spec */
+  //
+  // Admin Command Set Attributes
+  //
+  UINT16 Oacs;                /* Optional Admin Command Support */
+    #define NAMESPACE_MANAGEMENT_SUPPORTED  BIT3
+    #define FW_DOWNLOAD_ACTIVATE_SUPPORTED  BIT2
+    #define FORMAT_NVM_SUPPORTED            BIT1
+    #define SECURITY_SEND_RECEIVE_SUPPORTED BIT0
+  UINT8  Acl;                 /* Abort Command Limit */
+  UINT8  Aerl;                /* Async Event Request Limit */
+  UINT8  Frmw;                /* Firmware updates */
+  UINT8  Lpa;                 /* Log Page Attributes */
+  UINT8  Elpe;                /* Error Log Page Entries */
+  UINT8  Npss;                /* Number of Power States Support */
+  UINT8  Avscc;               /* Admin Vendor Specific Command Configuration */
+  UINT8  Apsta;               /* Autonomous Power State Transition Attributes */
+  UINT8  Rsvd2[246];          /* Reserved as of Nvm Express 1.1 Spec */
+  //
+  // NVM Command Set Attributes
+  //
+  UINT8  Sqes;                /* Submission Queue Entry Size */
+  UINT8  Cqes;                /* Completion Queue Entry Size */
+  UINT16 Rsvd3;               /* Reserved as of Nvm Express 1.1 Spec */
+  UINT32 Nn;                  /* Number of Namespaces */
+  UINT16 Oncs;                /* Optional NVM Command Support */
+  UINT16 Fuses;               /* Fused Operation Support */
+  UINT8  Fna;                 /* Format NVM Attributes */
+  UINT8  Vwc;                 /* Volatile Write Cache */
+  UINT16 Awun;                /* Atomic Write Unit Normal */
+  UINT16 Awupf;               /* Atomic Write Unit Power Fail */
+  UINT8  Nvscc;               /* NVM Vendor Specific Command Configuration */
+  UINT8  Rsvd4;               /* Reserved as of Nvm Express 1.1 Spec */
+  UINT16 Acwu;                /* Atomic Compare & Write Unit */
+  UINT16 Rsvd5;               /* Reserved as of Nvm Express 1.1 Spec */
+  UINT32 Sgls;                /* SGL Support  */
+  UINT8  Rsvd6[164];          /* Reserved as of Nvm Express 1.1 Spec */
+  //
+  // I/O Command set Attributes
+  //
+  UINT8 Rsvd7[1344];          /* Reserved as of Nvm Express 1.1 Spec */
+  //
+  // Power State Descriptors
+  //
+  NVME_PSDESCRIPTOR PsDescriptor[32];
+
+  UINT8  VendorData[1024];    /* Vendor specific data */
+} NVME_ADMIN_CONTROLLER_DATA;
+
+typedef struct {
+  UINT16 Ms;                /* Metadata Size */
+  UINT8  Lbads;             /* LBA Data Size */
+  UINT8  Rp:2;              /* Relative Performance */
+    #define LBAF_RP_BEST      00b
+    #define LBAF_RP_BETTER    01b
+    #define LBAF_RP_GOOD      10b
+    #define LBAF_RP_DEGRADED  11b
+  UINT8  Rsvd1:6;           /* Reserved as of Nvm Express 1.1 Spec */
+} NVME_LBAFORMAT;
+
+//
+// Identify Namespace Data
+//
+typedef struct {
+  //
+  // NVM Command Set Specific
+  //
+  UINT64 Nsze;                /* Namespace Size (total number of blocks in formatted namespace) */
+  UINT64 Ncap;                /* Namespace Capacity (max number of logical blocks) */
+  UINT64 Nuse;                /* Namespace Utilization */
+  UINT8  Nsfeat;              /* Namespace Features */
+  UINT8  Nlbaf;               /* Number of LBA Formats */
+  UINT8  Flbas;               /* Formatted LBA size */
+  UINT8  Mc;                  /* Metadata Capabilities */
+  UINT8  Dpc;                 /* End-to-end Data Protection capabilities */
+  UINT8  Dps;                 /* End-to-end Data Protection Type Settings */
+  UINT8  Nmic;                /* Namespace Multi-path I/O and Namespace Sharing Capabilities */
+  UINT8  Rescap;              /* Reservation Capabilities */
+  UINT8  Rsvd1[88];           /* Reserved as of Nvm Express 1.1 Spec */
+  UINT64 Eui64;               /* IEEE Extended Unique Identifier */
+  //
+  // LBA Format
+  //
+  NVME_LBAFORMAT LbaFormat[16];
+
+  UINT8 Rsvd2[192];           /* Reserved as of Nvm Express 1.1 Spec */
+  UINT8 VendorData[3712];     /* Vendor specific data */
+} NVME_ADMIN_NAMESPACE_DATA;
+
+//
+// NvmExpress Admin Identify Cmd
+//
+typedef struct {
+  //
+  // CDW 10
+  //
+  UINT32 Cns:2;
+  UINT32 Rsvd1:30;
+} NVME_ADMIN_IDENTIFY;
+
+//
+// NvmExpress Admin Create I/O Completion Queue
+//
+typedef struct {
+  //
+  // CDW 10
+  //
+  UINT32 Qid:16;              /* Queue Identifier */
+  UINT32 Qsize:16;            /* Queue Size */
+
+  //
+  // CDW 11
+  //
+  UINT32 Pc:1;                /* Physically Contiguous */
+  UINT32 Ien:1;               /* Interrupts Enabled */
+  UINT32 Rsvd1:14;            /* reserved as of Nvm Express 1.1 Spec */
+  UINT32 Iv:16;               /* Interrupt Vector for MSI-X or MSI*/
+} NVME_ADMIN_CRIOCQ;
+
+//
+// NvmExpress Admin Create I/O Submission Queue
+//
+typedef struct {
+  //
+  // CDW 10
+  //
+  UINT32 Qid:16;              /* Queue Identifier */
+  UINT32 Qsize:16;            /* Queue Size */
+
+  //
+  // CDW 11
+  //
+  UINT32 Pc:1;                /* Physically Contiguous */
+  UINT32 Qprio:2;             /* Queue Priority */
+  UINT32 Rsvd1:13;            /* Reserved as of Nvm Express 1.1 Spec */
+  UINT32 Cqid:16;             /* Completion Queue ID */
+} NVME_ADMIN_CRIOSQ;
+
+//
+// NvmExpress Admin Delete I/O Completion Queue
+//
+typedef struct {
+  //
+  // CDW 10
+  //
+  UINT16 Qid;
+  UINT16 Rsvd1;
+} NVME_ADMIN_DEIOCQ;
+
+//
+// NvmExpress Admin Delete I/O Submission Queue
+//
+typedef struct {
+  //
+  // CDW 10
+  //
+  UINT16 Qid;
+  UINT16 Rsvd1;
+} NVME_ADMIN_DEIOSQ;
+
+//
+// NvmExpress Admin Abort Command
+//
+typedef struct {
+  //
+  // CDW 10
+  //
+  UINT32 Sqid:16;             /* Submission Queue identifier */
+  UINT32 Cid:16;              /* Command Identifier */
+} NVME_ADMIN_ABORT;
+
+//
+// NvmExpress Admin Firmware Activate Command
+//
+typedef struct {
+  //
+  // CDW 10
+  //
+  UINT32 Fs:3;                /* Submission Queue identifier */
+  UINT32 Aa:2;                /* Command Identifier */
+  UINT32 Rsvd1:27;
+} NVME_ADMIN_FIRMWARE_ACTIVATE;
+
+//
+// NvmExpress Admin Firmware Image Download Command
+//
+typedef struct {
+  //
+  // CDW 10
+  //
+  UINT32 Numd;                /* Number of Dwords */
+  //
+  // CDW 11
+  //
+  UINT32 Ofst;                /* Offset */
+} NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;
+
+//
+// NvmExpress Admin Get Features Command
+//
+typedef struct {
+  //
+  // CDW 10
+  //
+  UINT32 Fid:8;                /* Feature Identifier */
+  UINT32 Sel:3;                /* Select */
+  UINT32 Rsvd1:21;
+} NVME_ADMIN_GET_FEATURES;
+
+//
+// NvmExpress Admin Get Log Page Command
+//
+typedef struct {
+  //
+  // CDW 10
+  //
+  UINT32 Lid:8;               /* Log Page Identifier */
+    #define LID_ERROR_INFO   0x1
+    #define LID_SMART_INFO   0x2
+    #define LID_FW_SLOT_INFO 0x3
+  UINT32 Rsvd1:8;
+  UINT32 Numd:12;             /* Number of Dwords */
+  UINT32 Rsvd2:4;             /* Reserved as of Nvm Express 1.1 Spec */
+} NVME_ADMIN_GET_LOG_PAGE;
+
+//
+// NvmExpress Admin Set Features Command
+//
+typedef struct {
+  //
+  // CDW 10
+  //
+  UINT32 Fid:8;               /* Feature Identifier */
+  UINT32 Rsvd1:23;
+  UINT32 Sv:1;                /* Save */
+} NVME_ADMIN_SET_FEATURES;
+
+//
+// NvmExpress Admin Format NVM Command
+//
+typedef struct {
+  //
+  // CDW 10
+  //
+  UINT32 Lbaf:4;              /* LBA Format */
+  UINT32 Ms:1;                /* Metadata Settings */
+  UINT32 Pi:3;                /* Protection Information */
+  UINT32 Pil:1;               /* Protection Information Location */
+  UINT32 Ses:3;               /* Secure Erase Settings */
+  UINT32 Rsvd1:20;
+} NVME_ADMIN_FORMAT_NVM;
+
+//
+// NvmExpress Admin Security Receive Command
+//
+typedef struct {
+  //
+  // CDW 10
+  //
+  UINT32 Rsvd1:8;
+  UINT32 Spsp:16;             /* SP Specific */
+  UINT32 Secp:8;              /* Security Protocol */
+  //
+  // CDW 11
+  //
+  UINT32 Al;                  /* Allocation Length */
+} NVME_ADMIN_SECURITY_RECEIVE;
+
+//
+// NvmExpress Admin Security Send Command
+//
+typedef struct {
+  //
+  // CDW 10
+  //
+  UINT32 Rsvd1:8;
+  UINT32 Spsp:16;             /* SP Specific */
+  UINT32 Secp:8;              /* Security Protocol */
+  //
+  // CDW 11
+  //
+  UINT32 Tl;                  /* Transfer Length */
+} NVME_ADMIN_SECURITY_SEND;
+
+typedef union {
+  NVME_ADMIN_IDENTIFY                   Identify;
+  NVME_ADMIN_CRIOCQ                     CrIoCq;
+  NVME_ADMIN_CRIOSQ                     CrIoSq;
+  NVME_ADMIN_DEIOCQ                     DeIoCq;
+  NVME_ADMIN_DEIOSQ                     DeIoSq;
+  NVME_ADMIN_ABORT                      Abort;
+  NVME_ADMIN_FIRMWARE_ACTIVATE          Activate;
+  NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD    FirmwareImageDownload;
+  NVME_ADMIN_GET_FEATURES               GetFeatures;
+  NVME_ADMIN_GET_LOG_PAGE               GetLogPage;
+  NVME_ADMIN_SET_FEATURES               SetFeatures;
+  NVME_ADMIN_FORMAT_NVM                 FormatNvm;
+  NVME_ADMIN_SECURITY_RECEIVE           SecurityReceive;
+  NVME_ADMIN_SECURITY_SEND              SecuritySend;
+} NVME_ADMIN_CMD;
+
+typedef struct {
+  UINT32 Cdw10;
+  UINT32 Cdw11;
+  UINT32 Cdw12;
+  UINT32 Cdw13;
+  UINT32 Cdw14;
+  UINT32 Cdw15;
+} NVME_RAW;
+
+typedef union {
+  NVME_ADMIN_CMD Admin;   // Union of Admin commands
+  NVME_CMD       Nvm;     // Union of Nvm commands
+  NVME_RAW       Raw;
+} NVME_PAYLOAD;
+
+//
+// Submission Queue
+//
+typedef struct {
+  //
+  // CDW 0, Common to all comnmands
+  //
+  UINT8  Opc;               // Opcode
+  UINT8  Fuse:2;            // Fused Operation
+  UINT8  Rsvd1:5;
+  UINT8  Psdt:1;            // PRP or SGL for Data Transfer
+  UINT16 Cid;               // Command Identifier
+
+  //
+  // CDW 1
+  //
+  UINT32 Nsid;              // Namespace Identifier
+
+  //
+  // CDW 2,3
+  //
+  UINT64 Rsvd2;
+
+  //
+  // CDW 4,5
+  //
+  UINT64 Mptr;              // Metadata Pointer
+
+  //
+  // CDW 6-9
+  //
+  UINT64 Prp[2];            // First and second PRP entries
+
+  NVME_PAYLOAD Payload;
+
+} NVME_SQ;
+
+//
+// Completion Queue
+//
+typedef struct {
+  //
+  // CDW 0
+  //
+  UINT32 Dword0;
+  //
+  // CDW 1
+  //
+  UINT32 Rsvd1;
+  //
+  // CDW 2
+  //
+  UINT16 Sqhd;              // Submission Queue Head Pointer
+  UINT16 Sqid;              // Submission Queue Identifier
+  //
+  // CDW 3
+  //
+  UINT16 Cid;               // Command Identifier
+  UINT16 Pt:1;              // Phase Tag
+  UINT16 Sc:8;              // Status Code
+  UINT16 Sct:3;             // Status Code Type
+  UINT16 Rsvd2:2;
+  UINT16 Mo:1;              // More
+  UINT16 Dnr:1;             // Do Not Retry
+} NVME_CQ;
+
+//
+// Nvm Express Admin cmd opcodes
+//
+#define NVME_ADMIN_DEIOSQ_CMD                0x00
+#define NVME_ADMIN_CRIOSQ_CMD                0x01
+#define NVME_ADMIN_GET_LOG_PAGE_CMD          0x02
+#define NVME_ADMIN_DEIOCQ_CMD                0x04
+#define NVME_ADMIN_CRIOCQ_CMD                0x05
+#define NVME_ADMIN_IDENTIFY_CMD              0x06
+#define NVME_ADMIN_ABORT_CMD                 0x08
+#define NVME_ADMIN_SET_FEATURES_CMD          0x09
+#define NVME_ADMIN_GET_FEATURES_CMD          0x0A
+#define NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD   0x0C
+#define NVME_ADMIN_NAMESACE_MANAGEMENT_CMD   0x0D
+#define NVME_ADMIN_FW_COMMIT_CMD             0x10
+#define NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD     0x11
+#define NVME_ADMIN_NAMESACE_ATTACHMENT_CMD   0x15
+#define NVME_ADMIN_FORMAT_NVM_CMD            0x80
+#define NVME_ADMIN_SECURITY_SEND_CMD         0x81
+#define NVME_ADMIN_SECURITY_RECEIVE_CMD      0x82
+
+#define NVME_IO_FLUSH_OPC                    0
+#define NVME_IO_WRITE_OPC                    1
+#define NVME_IO_READ_OPC                     2
+
+typedef enum {
+  DeleteIOSubmissionQueueOpcode = NVME_ADMIN_DEIOSQ_CMD,
+  CreateIOSubmissionQueueOpcode = NVME_ADMIN_CRIOSQ_CMD,
+  GetLogPageOpcode = NVME_ADMIN_GET_LOG_PAGE_CMD,
+  DeleteIOCompletionQueueOpcode = NVME_ADMIN_DEIOCQ_CMD,
+  CreateIOCompletionQueueOpcode = NVME_ADMIN_CRIOCQ_CMD,
+  IdentifyOpcode = NVME_ADMIN_IDENTIFY_CMD,
+  AbortOpcode = NVME_ADMIN_ABORT_CMD,
+  SetFeaturesOpcode = NVME_ADMIN_SET_FEATURES_CMD,
+  GetFeaturesOpcode = NVME_ADMIN_GET_FEATURES_CMD,
+  AsyncEventRequestOpcode = NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD,
+  NamespaceManagementOpcode = NVME_ADMIN_NAMESACE_MANAGEMENT_CMD,
+  FirmwareCommitOpcode = NVME_ADMIN_FW_COMMIT_CMD,
+  FirmwareImageDownloadOpcode = NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD,
+  NamespaceAttachmentOpcode = NVME_ADMIN_NAMESACE_ATTACHMENT_CMD,
+  FormatNvmOpcode = NVME_ADMIN_FORMAT_NVM_CMD,
+  SecuritySendOpcode = NVME_ADMIN_SECURITY_SEND_CMD,
+  SecurityReceiveOpcode = NVME_ADMIN_SECURITY_RECEIVE_CMD
+} NVME_ADMIN_COMMAND_OPCODE;
+
+//
+// Controller or Namespace Structure (CNS) field
+// (ref. spec. v1.1 figure 82).
+//
+typedef enum {
+IdentifyNamespaceCns = 0x0,
+IdentifyControllerCns = 0x1,
+IdentifyActiveNsListCns = 0x2
+} NVME_ADMIN_IDENTIFY_CNS;
+
+//
+// Commit Action
+// (ref. spec. 1.1 figure 60).
+//
+typedef enum {
+  ActivateActionReplace = 0x0,
+  ActivateActionReplaceActivate = 0x1,
+  ActivateActionActivate = 0x2
+} NVME_FW_ACTIVATE_ACTION;
+
+//
+// Firmware Slot
+// (ref. spec. 1.1 Figure 60).
+//
+typedef enum {
+  FirmwareSlotCtrlChooses = 0x0,
+  FirmwareSlot1 = 0x1,
+  FirmwareSlot2 = 0x2,
+  FirmwareSlot3 = 0x3,
+  FirmwareSlot4 = 0x4,
+  FirmwareSlot5 = 0x5,
+  FirmwareSlot6 = 0x6,
+  FirmwareSlot7 = 0x7
+} NVME_FW_ACTIVATE_SLOT;
+
+//
+// Get Log Page ? Log Page Identifiers
+// (ref. spec. v1.1 Figure 73).
+//
+typedef enum {
+  ErrorInfoLogID = LID_ERROR_INFO,
+  SmartHealthInfoLogID = LID_SMART_INFO,
+  FirmwareSlotInfoLogID = LID_FW_SLOT_INFO
+} NVME_LOG_ID;
+
+//
+// Get Log Page ? Firmware Slot Information Log
+// (ref. spec. v1.1 Figure 77).
+//
+typedef struct {
+  //
+  // Indicates the firmware slot from which the actively running firmware revision was loaded.
+  //
+  UINT8 ActivelyRunningFwSlot:3;
+  UINT8 :1;
+  //
+  // Indicates the firmware slot that is going to be activated at the next controller reset. If this field is 0h, then the controller does not indicate the firmware slot that is going to be activated at the next controller reset.
+  //
+  UINT8 NextActiveFwSlot:3;
+  UINT8 :1;
+} NVME_ACTIVE_FW_INFO;
+
+//
+// Get Log Page ? Firmware Slot Information Log
+// (ref. spec. v1.1 Figure 77).
+//
+typedef struct {
+  //
+  // Specifies information about the active firmware revision.
+  //s
+  NVME_ACTIVE_FW_INFO  ActiveFwInfo;
+  UINT8                Reserved1[7];
+  //
+  // Contains the revision of the firmware downloaded to firmware slot 1/7. If no valid firmware revision is present or if this slot is unsupported, all zeros shall be returned.
+  //
+  CHAR8                FwRevisionSlot[7][8];
+  UINT8                Reserved2[448];
+} NVME_FW_SLOT_INFO_LOG;
+
+//
+// SMART / Health Information (Log Identifier 02h)
+// (ref. spec. v1.1 5.10.1.2)
+//
+typedef struct {
+  //
+  // This field indicates critical warnings for the state of the controller.
+  //
+  UINT8  CriticalWarningAvailableSpare:1;
+  UINT8  CriticalWarningTemperature:1;
+  UINT8  CriticalWarningReliability:1;
+  UINT8  CriticalWarningMediaReadOnly:1;
+  UINT8  CriticalWarningVolatileBackup:1;
+  UINT8  CriticalWarningReserved:3;
+  //
+  // Contains a value corresponding to a temperature in degrees Kelvin that represents the current composite temperature of the controller and namespace(s) associated with that controller. The manner in which this value is computed is implementation specific and may not represent the actual temperature of any physical point in the NVM subsystem.
+  //
+  UINT16 CompositeTemp;
+  //
+  // Contains a normalized percentage (0 to 100%) of the remaining spare capacity available.
+  //
+  UINT8  AvailableSpare;
+  //
+  // When the Available Spare falls below the threshold indicated in this field, an asynchronous event completion may occur. The value is indicated as a normalized percentage (0 to 100%).
+  //
+  UINT8  AvailableSpareThreshold;
+  //
+  // Contains a vendor specific estimate of the percentage of NVM subsystem life used based on the actual usage and the manufacturer?s prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value is allowed to exceed 100. Percentages greater than 254 shall be represented as 255. This value shall be updated once per power-on hour (when the controller is not in a sleep state).
+  //
+  UINT8  PercentageUsed;
+  UINT8  Reserved1[26];
+  //
+  // Contains the number of 512 byte data units the host has read from the controller; this value does not include metadata.
+  //
+  UINT8  DataUnitsRead[16];
+  //
+  // Contains the number of 512 byte data units the host has written to the controller; this value does not include metadata.
+  //
+  UINT8  DataUnitsWritten[16];
+  //
+  // Contains the number of read commands completed by the controller.
+  //
+  UINT8  HostReadCommands[16];
+  //
+  // Contains the number of write commands completed by the controller.
+  //
+  UINT8  HostWriteCommands[16];
+  //
+  // Contains the amount of time the controller is busy with I/O commands. This value is reported in minutes.
+  //
+  UINT8  ControllerBusyTime[16];
+  //
+  // Contains the number of power cycles.
+  //
+  UINT8  PowerCycles[16];
+  //
+  // Contains the number of power-on hours.
+  //
+  UINT8  PowerOnHours[16];
+  //
+  // Contains the number of unsafe shutdowns.
+  //
+  UINT8  UnsafeShutdowns[16];
+  //
+  // Contains the number of occurrences where the controller detected an unrecovered data integrity error.
+  //
+  UINT8  MediaAndDataIntegrityErrors[16];
+  //
+  // Contains the number of Error Information log entries over the life of the controller.
+  //
+  UINT8  NumberErrorInformationLogEntries[16];
+  //
+  // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater than or equal to the Warning Composite Temperature Threshold (WCTEMP) field and less than the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.
+  //
+  UINT32 WarningCompositeTemperatureTime;
+  //
+  // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.
+  //
+  UINT32 CriticalCompositeTemperatureTime;
+  //
+  // Contains the current temperature in degrees Kelvin reported by the temperature sensor.  An implementation that does not implement the temperature sensor reports a temperature of zero degrees Kelvin.
+  //
+  UINT16 TemperatureSensor[8];
+  UINT8  Reserved2[296];
+} NVME_SMART_HEALTH_INFO_LOG;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pal.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pal.h
new file mode 100644
index 0000000000..5dc26a2f7b
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pal.h
@@ -0,0 +1,3302 @@
+/** @file
+  Main PAL API's defined in Intel Itanium Architecture Software Developer's Manual.
+
+  Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+**/
+
+#ifndef __PAL_API_H__
+#define __PAL_API_H__
+
+#define PAL_SUCCESS             0x0
+
+///
+/// CacheType of PAL_CACHE_FLUSH.
+///
+#define PAL_CACHE_FLUSH_INSTRUCTION_ALL   1
+#define PAL_CACHE_FLUSH_DATA_ALL          2
+#define PAL_CACHE_FLUSH_ALL               3
+#define PAL_CACHE_FLUSH_SYNC_TO_DATA      4
+
+
+///
+/// Bitmask of Opearation of PAL_CACHE_FLUSH.
+///
+#define PAL_CACHE_FLUSH_INVALIDATE_LINES     BIT0
+#define PAL_CACHE_FLUSH_NO_INVALIDATE_LINES  0
+#define PAL_CACHE_FLUSH_POLL_INTERRUPT       BIT1
+#define PAL_CACHE_FLUSH_NO_INTERRUPT         0
+
+/**
+  PAL Procedure - PAL_CACHE_FLUSH.
+
+  Flush the instruction or data caches. It is required by Itanium processors.
+  The PAL procedure supports the Static Registers calling
+  convention. It could be called at virtual mode and physical
+  mode.
+
+  @param Index              Index of PAL_CACHE_FLUSH within the
+                            list of PAL procedures.
+  @param CacheType          Unsigned 64-bit integer indicating
+                            which cache to flush.
+  @param Operation          Formatted bit vector indicating the
+                            operation of this call.
+  @param ProgressIndicator  Unsigned 64-bit integer specifying
+                            the starting position of the flush
+                            operation.
+
+  @retval 2                 Call completed without error, but a PMI
+                            was taken during the execution of this
+                            procedure.
+  @retval 1                 Call has not completed flushing due to
+                            a pending interrupt.
+  @retval 0                 Call completed without error
+  @retval -2                Invalid argument
+  @retval -3                Call completed with error
+
+  @return R9                Unsigned 64-bit integer specifying the vector
+                            number of the pending interrupt.
+  @return R10               Unsigned 64-bit integer specifying the
+                            starting position of the flush operation.
+  @return R11               Unsigned 64-bit integer specifying the vector
+                            number of the pending interrupt.
+
+**/
+#define PAL_CACHE_FLUSH   1
+
+
+///
+/// Attributes of PAL_CACHE_CONFIG_INFO1
+///
+#define PAL_CACHE_ATTR_WT   0
+#define PAL_CACHE_ATTR_WB   1
+
+///
+/// PAL_CACHE_CONFIG_INFO1.StoreHint
+///
+#define PAL_CACHE_STORE_TEMPORAL      0
+#define PAL_CACHE_STORE_NONE_TEMPORAL 3
+
+///
+/// PAL_CACHE_CONFIG_INFO1.StoreHint
+///
+#define PAL_CACHE_STORE_TEMPORAL_LVL_1        0
+#define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3
+
+///
+/// PAL_CACHE_CONFIG_INFO1.StoreHint
+///
+#define PAL_CACHE_LOAD_TEMPORAL_LVL_1         0
+#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1    1
+#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL  3
+
+///
+/// Detail the characteristics of a given processor controlled
+/// cache in the cache hierarchy.
+///
+typedef struct {
+  UINT64  IsUnified   : 1;
+  UINT64  Attributes  : 2;
+  UINT64  Associativity:8;
+  UINT64  LineSize:8;
+  UINT64  Stride:8;
+  UINT64  StoreLatency:8;
+  UINT64  StoreHint:8;
+  UINT64  LoadHint:8;
+} PAL_CACHE_INFO_RETURN1;
+
+///
+/// Detail the characteristics of a given processor controlled
+/// cache in the cache hierarchy.
+///
+typedef struct {
+  UINT64  CacheSize:32;
+  UINT64  AliasBoundary:8;
+  UINT64  TagLsBits:8;
+  UINT64  TagMsBits:8;
+} PAL_CACHE_INFO_RETURN2;
+
+/**
+  PAL Procedure - PAL_CACHE_INFO.
+
+  Return detailed instruction or data cache information. It is
+  required by Itanium processors. The PAL procedure supports the Static
+  Registers calling convention. It could be called at virtual
+  mode and physical mode.
+
+  @param Index        Index of PAL_CACHE_INFO within the list of
+                      PAL procedures.
+  @param CacheLevel   Unsigned 64-bit integer specifying the
+                      level in the cache hierarchy for which
+                      information is requested. This value must
+                      be between 0 and one less than the value
+                      returned in the cache_levels return value
+                      from PAL_CACHE_SUMMARY.
+  @param CacheType    Unsigned 64-bit integer with a value of 1
+                      for instruction cache and 2 for data or
+                      unified cache. All other values are
+                      reserved.
+  @param Reserved     Should be 0.
+
+  @retval 0           Call completed without error
+  @retval -2          Invalid argument
+  @retval -3          Call completed with error
+
+  @return R9          Detail the characteristics of a given
+                      processor controlled cache in the cache
+                      hierarchy. See PAL_CACHE_INFO_RETURN1.
+  @return R10         Detail the characteristics of a given
+                      processor controlled cache in the cache
+                      hierarchy. See PAL_CACHE_INFO_RETURN2.
+  @return R11         Reserved with 0.
+
+**/
+#define PAL_CACHE_INFO    2
+
+
+
+///
+/// Level of PAL_CACHE_INIT.
+///
+#define PAL_CACHE_INIT_ALL  0xffffffffffffffffULL
+
+///
+/// CacheType
+///
+#define PAL_CACHE_INIT_TYPE_INSTRUCTION                 0x1
+#define PAL_CACHE_INIT_TYPE_DATA                        0x2
+#define PAL_CACHE_INIT_TYPE_INSTRUCTION_AND_DATA        0x3
+
+///
+/// Restrict of PAL_CACHE_INIT.
+///
+#define PAL_CACHE_INIT_NO_RESTRICT  0
+#define PAL_CACHE_INIT_RESTRICTED   1
+
+/**
+  PAL Procedure - PAL_CACHE_INIT.
+
+  Initialize the instruction or data caches. It is required by
+  Itanium processors. The PAL procedure supports the Static Registers calling
+  convention. It could be called at physical mode.
+
+  @param Index      Index of PAL_CACHE_INIT within the list of PAL
+                    procedures.
+  @param Level      Unsigned 64-bit integer containing the level of
+                    cache to initialize. If the cache level can be
+                    initialized independently, only that level will
+                    be initialized. Otherwise
+                    implementation-dependent side-effects will
+                    occur.
+  @param CacheType  Unsigned 64-bit integer with a value of 1 to
+                    initialize the instruction cache, 2 to
+                    initialize the data cache, or 3 to
+                    initialize both. All other values are
+                    reserved.
+  @param Restrict   Unsigned 64-bit integer with a value of 0 or
+                    1. All other values are reserved. If
+                    restrict is 1 and initializing the specified
+                    level and cache_type of the cache would
+                    cause side-effects, PAL_CACHE_INIT will
+                    return -4 instead of initializing the cache.
+
+  @retval 0         Call completed without error
+  @retval -2        Invalid argument
+  @retval -3        Call completed with error.
+  @retval -4        Call could not initialize the specified
+                    level and cache_type of the cache without
+                    side-effects and restrict was 1.
+
+**/
+#define PAL_CACHE_INIT    3
+
+
+///
+/// PAL_CACHE_PROTECTION.Method.
+///
+#define PAL_CACHE_PROTECTION_NONE_PROTECT   0
+#define PAL_CACHE_PROTECTION_ODD_PROTECT    1
+#define PAL_CACHE_PROTECTION_EVEN_PROTECT   2
+#define PAL_CACHE_PROTECTION_ECC_PROTECT    3
+
+
+
+///
+/// PAL_CACHE_PROTECTION.TagOrData.
+///
+#define PAL_CACHE_PROTECTION_PROTECT_DATA   0
+#define PAL_CACHE_PROTECTION_PROTECT_TAG    1
+#define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA   2
+#define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG   3
+
+///
+/// 32-bit protection information structures.
+///
+typedef struct {
+  UINT32  DataBits:8;
+  UINT32  TagProtLsb:6;
+  UINT32  TagProtMsb:6;
+  UINT32  ProtBits:6;
+  UINT32  Method:4;
+  UINT32  TagOrData:2;
+} PAL_CACHE_PROTECTION;
+
+/**
+  PAL Procedure - PAL_CACHE_PROT_INFO.
+
+  Return instruction or data cache protection information. It is
+  required by Itanium processors. The PAL procedure supports the Static
+  Registers calling convention. It could be called at physical
+  mode and Virtual mode.
+
+  @param Index      Index of PAL_CACHE_PROT_INFO within the list of
+                    PAL procedures.
+  @param CacheLevel Unsigned 64-bit integer specifying the level
+                    in the cache hierarchy for which information
+                    is requested. This value must be between 0
+                    and one less than the value returned in the
+                    cache_levels return value from
+                    PAL_CACHE_SUMMARY.
+  @param CacheType  Unsigned 64-bit integer with a value of 1
+                    for instruction cache and 2 for data or
+                    unified cache. All other values are
+                    reserved.
+
+  @retval 0         Call completed without error
+  @retval -2        Invalid argument
+  @retval -3        Call completed with error.
+
+  @return R9        Detail the characteristics of a given
+                    processor controlled cache in the cache
+                    hierarchy. See PAL_CACHE_PROTECTION[0..1].
+  @return R10       Detail the characteristics of a given
+                    processor controlled cache in the cache
+                    hierarchy. See PAL_CACHE_PROTECTION[2..3].
+  @return R11       Detail the characteristics of a given
+                    processor controlled cache in the cache
+                    hierarchy. See PAL_CACHE_PROTECTION[4..5].
+
+**/
+#define PAL_CACHE_PROT_INFO     38
+
+typedef struct {
+  UINT64  ThreadId : 16;    ///< The thread identifier of the logical
+                            ///< processor for which information is being
+                            ///< returned. This value will be unique on a per core basis.
+  UINT64  Reserved1: 16;
+  UINT64  CoreId: 16;       ///< The core identifier of the logical processor
+                            ///< for which information is being returned.
+                            ///< This value will be unique on a per physical
+                            ///< processor package basis.
+  UINT64  Reserved2: 16;
+} PAL_PCOC_N_CACHE_INFO1;
+
+
+typedef struct {
+  UINT64  LogicalAddress : 16;  ///< Logical address: geographical address
+                                ///< of the logical processor for which
+                                ///< information is being returned. This is
+                                ///< the same value that is returned by the
+                                ///< PAL_FIXED_ADDR procedure when it is
+                                ///< called on the logical processor.
+  UINT64  Reserved1: 16;
+  UINT64  Reserved2: 32;
+} PAL_PCOC_N_CACHE_INFO2;
+
+/**
+  PAL Procedure - PAL_CACHE_SHARED_INFO.
+
+  Returns information on which logical processors share caches.
+  It is optional. The PAL procedure supports the Static
+  Registers calling convention. It could be called at physical
+  mode and Virtual mode.
+
+  @param Index       Index of PAL_CACHE_SHARED_INFO within the list
+                     of PAL procedures.
+  @param CacheLevel  Unsigned 64-bit integer specifying the
+                     level in the cache hierarchy for which
+                     information is requested. This value must
+                     be between 0 and one less than the value
+                     returned in the cache_levels return value
+                     from PAL_CACHE_SUMMARY.
+  @param CacheType   Unsigned 64-bit integer with a value of 1
+                     for instruction cache and 2 for data or
+                     unified cache. All other values are
+                     reserved.
+  @param ProcNumber  Unsigned 64-bit integer that specifies for
+                     which logical processor information is
+                     being requested. This input argument must
+                     be zero for the first call to this
+                     procedure and can be a maximum value of
+                     one less than the number of logical
+                     processors sharing this cache, which is
+                     returned by the num_shared return value.
+
+  @retval 0          Call completed without error
+  @retval -1         Unimplemented procedure
+  @retval -2         Invalid argument
+  @retval -3         Call completed with error.
+
+  @return R9         Unsigned integer that returns the number of
+                     logical processors that share the processor
+                     cache level and type, for which information was
+                     requested.
+  @return R10        The format of PAL_PCOC_N_CACHE_INFO1.
+  @return R11        The format of PAL_PCOC_N_CACHE_INFO2.
+
+**/
+#define PAL_CACHE_SHARED_INFO   43
+
+
+/**
+  PAL Procedure - PAL_CACHE_SUMMARY.
+
+  Return a summary of the cache hierarchy. It is required by
+  Itanium processors. The PAL procedure supports the Static Registers calling
+  convention. It could be called at physical mode and Virtual
+  mode.
+
+  @param Index  Index of PAL_CACHE_SUMMARY within the list of
+                PAL procedures.
+
+  @retval 0     Call completed without error
+  @retval -2    Invalid argument
+  @retval -3    Call completed with error.
+
+  @return R9    CacheLevels   Unsigned 64-bit integer denoting the
+                              number of levels of cache
+                              implemented by the processor.
+                              Strictly, this is the number of
+                              levels for which the cache
+                              controller is integrated into the
+                              processor (the cache SRAMs may be
+                              external to the processor).
+  @return R10   UniqueCaches  Unsigned 64-bit integer denoting the
+                              number of unique caches implemented
+                              by the processor. This has a maximum
+                              of 2*cache_levels, but may be less
+                              if any of the levels in the cache
+                              hierarchy are unified caches or do
+                              not have both instruction and data
+                              caches.
+
+**/
+#define PAL_CACHE_SUMMARY   4
+
+
+//
+// Virtual Memory Attributes implemented by processor.
+//
+#define PAL_MEMORY_ATTR_WB      0
+#define PAL_MEMORY_ATTR_WC      6
+#define PAL_MEMORY_ATTR_UC      4
+#define PAL_MEMORY_ATTR_UCE     5
+#define PAL_MEMORY_ATTR_NATPAGE 7
+
+/**
+  PAL Procedure - PAL_MEM_ATTRIB.
+
+  Return a list of supported memory attributes.. It is required
+  by Itanium processors. The PAL procedure supports the Static Registers calling
+  convention. It could be called at physical mode and Virtual
+  mode.
+
+  @param Index  Index of PAL_MEM_ATTRIB within the list of PAL
+                procedures.
+
+  @retval 0     Call completed without error
+  @retval -2    Invalid argument
+  @retval -3    Call completed with error.
+
+  @return R9    Attributes  8-bit vector of memory attributes
+                            implemented by processor. See Virtual
+                            Memory Attributes above.
+
+**/
+
+#define PAL_MEM_ATTRIB      5
+
+/**
+  PAL Procedure - PAL_PREFETCH_VISIBILITY.
+
+  Used in architected sequence to transition pages from a
+  cacheable, speculative attribute to an uncacheable attribute.
+  It is required by Itanium processors. The PAL procedure supports the Static
+  Registers calling convention. It could be called at physical
+  mode and Virtual mode.
+
+  @param Index          Index of PAL_PREFETCH_VISIBILITY within the list
+                        of PAL procedures.
+  @param TransitionType Unsigned integer specifying the type
+                        of memory attribute transition that is
+                        being performed.
+
+  @retval 1             Call completed without error; this
+                        call is not necessary on remote
+                        processors.
+  @retval 0             Call completed without error
+  @retval -2            Invalid argument
+  @retval -3            Call completed with error.
+
+**/
+#define PAL_PREFETCH_VISIBILITY   41
+
+/**
+  PAL Procedure - PAL_PTCE_INFO.
+
+  Return information needed for ptc.e instruction to purge
+  entire TC. It is required by Itanium processors. The PAL procedure supports
+  the Static Registers calling convention. It could be called at
+  physical mode and Virtual mode.
+
+  @param Index  Index of PAL_PTCE_INFO within the list
+                of PAL procedures.
+
+  @retval 0     Call completed without error
+  @retval -2    Invalid argument
+  @retval -3    Call completed with error.
+
+  @return R9    Unsigned 64-bit integer denoting the beginning
+                address to be used by the first PTCE instruction
+                in the purge loop.
+  @return R10   Two unsigned 32-bit integers denoting the loop
+                counts of the outer (loop 1) and inner (loop 2)
+                purge loops. count1 (loop 1) is contained in bits
+                63:32 of the parameter, and count2 (loop 2) is
+                contained in bits 31:0 of the parameter.
+  @return R11   Two unsigned 32-bit integers denoting the loop
+                strides of the outer (loop 1) and inner (loop 2)
+                purge loops. stride1 (loop 1) is contained in bits
+                63:32 of the parameter, and stride2 (loop 2) is
+                contained in bits 31:0 of the parameter.
+
+**/
+#define PAL_PTCE_INFO     6
+
+typedef struct {
+  UINT64  NumberSets:8;             ///< Unsigned 8-bit integer denoting the number
+                                    ///< of hash sets for the specified level
+                                    ///< (1=fully associative)
+  UINT64  NumberWays:8;             ///< Unsigned 8-bit integer denoting the
+                                    ///< associativity of the specified level
+                                    ///< (1=direct).
+  UINT64  NumberEntries:16;         ///< Unsigned 16-bit integer denoting the
+                                    ///< number of entries in the specified TC.
+  UINT64  PageSizeIsOptimized:1;    ///< Flag denoting whether the
+                                    ///< specified level is optimized for
+                                    ///< the region's preferred page size
+                                    ///< (1=optimized) tc_pages indicates
+                                    ///< which page sizes are usable by
+                                    ///< this translation cache.
+  UINT64  TcIsUnified:1;            ///< Flag denoting whether the specified TC is
+                                    ///< unified (1=unified).
+  UINT64  EntriesReduction:1;       ///< Flag denoting whether installed
+                                    ///< translation registers will reduce
+                                    ///< the number of entries within the
+                                    ///< specified TC.
+} PAL_TC_INFO;
+
+/**
+  PAL Procedure - PAL_VM_INFO.
+
+  Return detailed information about virtual memory features
+  supported in the processor. It is required by Itanium processors. The PAL
+  procedure supports the Static Registers calling convention. It
+  could be called at physical mode and Virtual mode.
+
+  @param Index    Index of PAL_VM_INFO within the list
+                  of PAL procedures.
+  @param TcLevel  Unsigned 64-bit integer specifying the level
+                  in the TLB hierarchy for which information is
+                  required. This value must be between 0 and one
+                  less than the value returned in the
+                  vm_info_1.num_tc_levels return value from
+                  PAL_VM_SUMMARY.
+  @param TcType   Unsigned 64-bit integer with a value of 1 for
+                  instruction translation cache and 2 for data
+                  or unified translation cache. All other values
+                  are reserved.
+
+  @retval 0       Call completed without error
+  @retval -2      Invalid argument
+  @retval -3      Call completed with error.
+
+  @return R9      8-byte formatted value returning information
+                  about the specified TC. See PAL_TC_INFO above.
+  @return R10     64-bit vector containing a bit for each page
+                  size supported in the specified TC, where bit
+                  position n indicates a page size of 2**n.
+
+**/
+#define PAL_VM_INFO       7
+
+
+/**
+  PAL Procedure - PAL_VM_PAGE_SIZE.
+
+  Return virtual memory TC and hardware walker page sizes
+  supported in the processor. It is required by Itanium processors. The PAL
+  procedure supports the Static Registers calling convention. It
+  could be called at physical mode and Virtual mode.
+
+  @param Index  Index of PAL_VM_PAGE_SIZE within the list
+                of PAL procedures.
+
+  @retval 0     Call completed without error
+  @retval -2    Invalid argument
+  @retval -3    Call completed with error.
+
+  @return R9    64-bit vector containing a bit for each
+                architected page size that is supported for
+                TLB insertions and region registers.
+  @return R10   64-bit vector containing a bit for each
+                architected page size supported for TLB purge
+                operations.
+
+**/
+#define PAL_VM_PAGE_SIZE 34
+
+typedef struct {
+  UINT64  WalkerPresent:1;              ///< 1-bit flag indicating whether a hardware
+                                        ///< TLB walker is implemented (1 = walker
+                                        ///< present).
+  UINT64  WidthOfPhysicalAddress: 7;    ///< Unsigned 7-bit integer
+                                        ///< denoting the number of bits of
+                                        ///< physical address implemented.
+  UINT64  WidthOfKey:8;                 ///< Unsigned 8-bit integer denoting the number
+                                        ///< of bits mplemented in the PKR.key field.
+  UINT64  MaxPkrIndex:8;                ///< Unsigned 8-bit integer denoting the
+                                        ///< maximum PKR index (number of PKRs-1).
+  UINT64  HashTagId:8;                  ///< Unsigned 8-bit integer which uniquely
+                                        ///< identifies the processor hash and tag
+                                        ///< algorithm.
+  UINT64  MaxDtrIndex:8;                ///< Unsigned 8 bit integer denoting the
+                                        ///< maximum data translation register index
+                                        ///< (number of dtr entries - 1).
+  UINT64  MaxItrIndex:8;                ///< Unsigned 8 bit integer denoting the
+                                        ///< maximum instruction translation register
+                                        ///< index (number of itr entries - 1).
+  UINT64  NumberOfUniqueTc:8;           ///< Unsigned 8-bit integer denoting the
+                                        ///< number of unique TCs implemented.
+                                        ///< This is a maximum of
+                                        ///< 2*num_tc_levels.
+  UINT64  NumberOfTcLevels:8;           ///< Unsigned 8-bit integer denoting the
+                                        ///< number of TC levels.
+} PAL_VM_INFO1;
+
+typedef struct {
+  UINT64  WidthOfVirtualAddress:8;  ///< Unsigned 8-bit integer denoting
+                                    ///< is the total number of virtual
+                                    ///< address bits - 1.
+  UINT64  WidthOfRid:8;             ///< Unsigned 8-bit integer denoting the number
+                                    ///< of bits implemented in the RR.rid field.
+  UINT64  MaxPurgedTlbs:16;         ///< Unsigned 16 bit integer denoting the
+                                    ///< maximum number of concurrent outstanding
+                                    ///< TLB purges allowed by the processor. A
+                                    ///< value of 0 indicates one outstanding
+                                    ///< purge allowed. A value of 216-1
+                                    ///< indicates no limit on outstanding
+                                    ///< purges. All other values indicate the
+                                    ///< actual number of concurrent outstanding
+                                    ///< purges allowed.
+  UINT64  Reserved:32;
+} PAL_VM_INFO2;
+
+/**
+  PAL Procedure - PAL_VM_SUMMARY.
+
+  Return summary information about virtual memory features
+  supported in the processor. It is required by Itanium processors. The PAL
+  procedure supports the Static Registers calling convention. It
+  could be called at physical mode and Virtual mode.
+
+  @param Index  Index of PAL_VM_SUMMARY within the list
+                of PAL procedures.
+
+  @retval 0     Call completed without error
+  @retval -2    Invalid argument
+  @retval -3    Call completed with error.
+
+  @return R9    8-byte formatted value returning global virtual
+                memory information. See PAL_VM_INFO1 above.
+  @return R10   8-byte formatted value returning global virtual
+                memory information. See PAL_VM_INFO2 above.
+
+**/
+#define PAL_VM_SUMMARY  8
+
+
+//
+// Bit mask of TR_valid flag.
+//
+#define PAL_TR_ACCESS_RIGHT_IS_VALID      BIT0
+#define PAL_TR_PRIVILEGE_LEVEL_IS_VALID   BIT1
+#define PAL_TR_DIRTY_IS_VALID             BIT2
+#define PAL_TR_MEMORY_ATTR_IS_VALID       BIT3
+
+
+/**
+  PAL Procedure - PAL_VM_TR_READ.
+
+  Read contents of a translation register. It is required by
+  Itanium processors. The PAL procedure supports the Stacked Register calling
+  convention. It could be called at physical mode.
+
+  @param Index      Index of PAL_VM_TR_READ within the list
+                    of PAL procedures.
+  @param RegNumber  Unsigned 64-bit number denoting which TR to
+                    read.
+  @param TrType     Unsigned 64-bit number denoting whether to
+                    read an ITR (0) or DTR (1). All other values
+                    are reserved.
+  @param TrBuffer   64-bit pointer to the 32-byte memory buffer in
+                    which translation data is returned.
+
+  @retval 0         Call completed without error
+  @retval -2        Invalid argument
+  @retval -3        Call completed with error.
+
+  @return R9        Formatted bit vector denoting which fields are
+                    valid. See TR_valid above.
+
+**/
+#define PAL_VM_TR_READ  261
+
+
+
+
+//
+// Bit Mask of Processor Bus Fesatures .
+//
+
+/**
+
+  When 0, bus data errors are detected and single bit errors are
+  corrected. When 1, no error detection or correction is done.
+
+**/
+#define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING   BIT63
+
+
+/**
+
+  When 0, bus address errors are signalled on the bus. When 1,
+  no bus errors are signalled on the bus. If Disable Bus Address
+  Error Checking is 1, this bit is ignored.
+
+**/
+#define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING   BIT62
+
+
+
+
+/**
+
+  When 0, bus errors are detected, single bit errors are
+  corrected., and a CMCI or MCA is generated internally to the
+  processor. When 1, no bus address errors are detected or
+  corrected.
+
+**/
+#define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK   BIT61
+
+
+/**
+
+  When 0, bus protocol errors (BINIT#) are signaled by the
+  processor on the bus. When 1, bus protocol errors (BINIT#) are
+  not signaled on the bus. If Disable Bus Initialization Event
+  Checking is 1, this bit is ignored.
+
+**/
+#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING   BIT60
+
+
+/**
+
+  When 0, bus protocol errors (BINIT#) are detected and sampled
+  and an MCA is generated internally to the processor. When 1,
+  the processor will ignore bus protocol error conditions
+  (BINIT#).
+
+**/
+#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK   BIT59
+
+
+
+/**
+
+  When 0, BERR# is signalled if a bus error is detected. When 1,
+  bus errors are not signalled on the bus.
+
+**/
+#define PAL_BUS_DISABLE_ERROR_SIGNALLING   BIT58
+
+
+
+
+/**
+
+  When 0, BERR# is signalled when internal processor requestor
+  initiated bus errors are detected. When 1, internal requester
+  bus errors are not signalled on the bus.
+
+**/
+#define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING   BIT57
+
+
+/**
+
+  When 0, the processor takes an MCA if BERR# is asserted. When
+  1, the processor ignores the BERR# signal.
+
+**/
+#define PAL_BUS_DISABLE_ERROR_CHECK   BIT56
+
+
+/**
+
+  When 0, the processor asserts BINIT# if it detects a parity
+  error on the signals which identify the transactions to which
+  this is a response. When 1, the processor ignores parity on
+  these signals.
+
+**/
+#define PAL_BUS_DISABLE_RSP_ERROR_CHECK   BIT55
+
+
+/**
+
+  When 0, the in-order transaction queue is limited only by the
+  number of hardware entries. When 1, the processor's in-order
+  transactions queue is limited to one entry.
+
+**/
+#define PAL_BUS_DISABLE_TRANSACTION_QUEUE   BIT54
+
+/**
+
+  Enable a bus cache line replacement transaction when a cache
+  line in the exclusive state is replaced from the highest level
+  processor cache and is not present in the lower level processor
+  caches. When 0, no bus cache line replacement transaction will
+  be seen on the bus. When 1, bus cache line replacement
+  transactions will be seen on the bus when the above condition is
+  detected.
+
+**/
+#define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT   BIT53
+
+
+/**
+
+  Enable a bus cache line replacement transaction when a cache
+  line in the shared or exclusive state is replaced from the
+  highest level processor cache and is not present in the lower
+  level processor caches.
+  When 0, no bus cache line replacement transaction will be seen
+  on the bus. When 1, bus cache line replacement transactions
+  will be seen on the bus when the above condition is detected.
+
+**/
+#define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT   BIT52
+
+
+
+/**
+
+  When 0, the data bus is configured at the 2x data transfer
+  rate.When 1, the data bus is configured at the 1x data
+  transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the
+  processor executes locked transactions atomically. When 1, the
+  processor masks the bus lock signal and executes locked
+  transactions as a non-atomic series of transactions.
+
+**/
+#define PAL_BUS_ENABLE_HALF_TRANSFER   BIT30
+
+/**
+
+  When 0, the processor will deassert bus request when finished
+  with each transaction. When 1, the processor will continue to
+  assert bus request after it has finished, if it was the last
+  agent to own the bus and if there are no other pending
+  requests.
+
+**/
+#define PAL_BUS_REQUEST_BUS_PARKING   BIT29
+
+
+/**
+  PAL Procedure - PAL_BUS_GET_FEATURES.
+
+  Return configurable processor bus interface features and their
+  current settings. It is required by Itanium processors. The PAL procedure
+  supports the Stacked Register calling convention. It could be
+  called at physical mode.
+
+  @param Index  Index of PAL_BUS_GET_FEATURES within the list
+                of PAL procedures.
+
+  @retval 0     Call completed without error
+  @retval -2    Invalid argument
+  @retval -3    Call completed with error.
+
+  @return R9    64-bit vector of features implemented.
+                (1=implemented, 0=not implemented)
+  @return R10   64-bit vector of current feature settings.
+  @return R11   64-bit vector of features controllable by
+                software. (1=controllable, 0= not controllable)
+
+**/
+#define PAL_BUS_GET_FEATURES 9
+
+/**
+  PAL Procedure - PAL_BUS_SET_FEATURES.
+
+  Enable or disable configurable features in processor bus
+  interface. It is required by Itanium processors. The PAL procedure
+  supports the Static Registers calling convention. It could be
+  called at physical mode.
+
+  @param Index          Index of PAL_BUS_SET_FEATURES within the list
+                        of PAL procedures.
+  @param FeatureSelect  64-bit vector denoting desired state of
+                        each feature (1=select, 0=non-select).
+
+  @retval 0             Call completed without error
+  @retval -2            Invalid argument
+  @retval -3            Call completed with error.
+
+**/
+#define PAL_BUS_SET_FEATURES 10
+
+
+/**
+  PAL Procedure - PAL_DEBUG_INFO.
+
+  Return the number of instruction and data breakpoint
+  registers. It is required by Itanium processors. The
+  PAL procedure supports the Static Registers calling
+  convention. It could be called at physical mode and virtual
+  mode.
+
+  @param Index  Index of PAL_DEBUG_INFO within the list of PAL
+                procedures.
+
+  @retval 0     Call completed without error
+  @retval -2    Invalid argument
+  @retval -3    Call completed with error.
+
+  @return R9    Unsigned 64-bit integer denoting the number of
+                pairs of instruction debug registers implemented
+                by the processor.
+  @return R10   Unsigned 64-bit integer denoting the number of
+                pairs of data debug registers implemented by the
+                processor.
+
+**/
+#define PAL_DEBUG_INFO  11
+
+/**
+  PAL Procedure - PAL_FIXED_ADDR.
+
+  Return the fixed component of a processor's directed address.
+  It is required by Itanium processors. The PAL
+  procedure supports the Static Registers calling convention. It
+  could be called at physical mode and virtual mode.
+
+  @param Index  Index of PAL_FIXED_ADDR within the list of PAL
+                procedures.
+
+  @retval 0     Call completed without error
+  @retval -2    Invalid argument
+  @retval -3    Call completed with error.
+
+  @return R9    Fixed geographical address of this processor.
+
+**/
+#define PAL_FIXED_ADDR 12
+
+/**
+  PAL Procedure - PAL_FREQ_BASE.
+
+  Return the frequency of the output clock for use by the
+  platform, if generated by the processor. It is optinal. The
+  PAL procedure supports the Static Registers calling
+  convention. It could be called at physical mode and virtual
+  mode.
+
+  @param Index  Index of PAL_FREQ_BASE within the list of PAL
+                procedures.
+
+  @retval 0     Call completed without error
+  @retval -1    Unimplemented procedure
+  @retval -2    Invalid argument
+  @retval -3    Call completed with error.
+
+  @return R9    Base frequency of the platform if generated by the
+                processor chip.
+
+**/
+#define PAL_FREQ_BASE 13
+
+
+/**
+  PAL Procedure - PAL_FREQ_RATIOS.
+
+  Return ratio of processor, bus, and interval time counter to
+  processor input clock or output clock for platform use, if
+  generated by the processor. It is required by Itanium processors. The PAL
+  procedure supports the Static Registers calling convention. It
+  could be called at physical mode and virtual mode.
+
+  @param Index  Index of PAL_FREQ_RATIOS within the list of PAL
+                procedures.
+
+  @retval 0     Call completed without error
+  @retval -2    Invalid argument
+  @retval -3    Call completed with error.
+
+  @return R9    Ratio of the processor frequency to the input
+                clock of the processor, if the platform clock is
+                generated externally or to the output clock to the
+                platform, if the platform clock is generated by
+                the processor.
+  @return R10   Ratio of the bus frequency to the input clock of
+                the processor, if the platform clock is generated
+                externally or to the output clock to the platform,
+                if the platform clock is generated by the
+                processor.
+  @return R11   Ratio of the interval timer counter rate to input
+                clock of the processor, if the platform clock is
+                generated externally or to the output clock to the
+                platform, if the platform clock is generated by
+                the processor.
+
+**/
+#define PAL_FREQ_RATIOS 14
+
+typedef struct {
+  UINT64  NumberOfLogicalProcessors:16;     ///< Total number of logical
+                                            ///< processors on this physical
+                                            ///< processor package that are
+                                            ///< enabled.
+  UINT64  ThreadsPerCore:8;                 ///< Number of threads per core.
+  UINT64  Reserved1:8;
+  UINT64  CoresPerProcessor:8;              ///< Total number of cores on this
+                                            ///< physical processor package.
+  UINT64  Reserved2:8;
+  UINT64  PhysicalProcessorPackageId:8;     ///< Physical processor package
+                                            ///< identifier which was
+                                            ///< assigned at reset by the
+                                            ///< platform or bus
+                                            ///< controller. This value may
+                                            ///< or may not be unique
+                                            ///< across the entire platform
+                                            ///< since it depends on the
+                                            ///< platform vendor's policy.
+  UINT64  Reserved3:8;
+} PAL_LOGICAL_PROCESSPR_OVERVIEW;
+
+typedef struct {
+   UINT64 ThreadId:16;      ///< The thread identifier of the logical
+                            ///< processor for which information is being
+                            ///< returned. This value will be unique on a per
+                            ///< core basis.
+   UINT64 Reserved1:16;
+   UINT64 CoreId:16;        ///< The core identifier of the logical processor
+                            ///< for which information is being returned.
+                            ///< This value will be unique on a per physical
+                            ///< processor package basis.
+   UINT64 Reserved2:16;
+} PAL_LOGICAL_PROCESSORN_INFO1;
+
+typedef struct {
+   UINT64 LogicalAddress:16;    ///< Geographical address of the logical
+                                ///< processor for which information is being
+                                ///< returned. This is the same value that is
+                                ///< returned by the PAL_FIXED_ADDR procedure
+                                ///< when it is called on the logical processor.
+   UINT64 Reserved:48;
+} PAL_LOGICAL_PROCESSORN_INFO2;
+
+/**
+  PAL Procedure - PAL_LOGICAL_TO_PHYSICAL.
+
+  Return information on which logical processors map to a
+  physical processor die. It is optinal. The PAL procedure
+  supports the Static Registers calling convention. It could be
+  called at physical mode and virtual mode.
+
+  @param Index            Index of PAL_LOGICAL_TO_PHYSICAL within the list of PAL
+                          procedures.
+  @param ProcessorNumber  Signed 64-bit integer that specifies
+                          for which logical processor
+                          information is being requested. When
+                          this input argument is -1, information
+                          is returned about the logical
+                          processor on which the procedure call
+                          is made. This input argument must be
+                          in the range of 1 up to one less than
+                          the number of logical processors
+                          returned by num_log in the
+                          log_overview return value.
+
+  @retval 0               Call completed without error
+  @retval -1              Unimplemented procedure
+  @retval -2              Invalid argument
+  @retval -3              Call completed with error.
+
+  @return R9              The format of PAL_LOGICAL_PROCESSPR_OVERVIEW.
+  @return R10             The format of PAL_LOGICAL_PROCESSORN_INFO1.
+  @return R11             The format of PAL_LOGICAL_PROCESSORN_INFO2.
+
+**/
+#define PAL_LOGICAL_TO_PHYSICAL 42
+
+typedef struct {
+  UINT64  NumberOfPmcPairs:8;               ///< Unsigned 8-bit number defining the
+                                            ///< number of generic PMC/PMD pairs.
+  UINT64  WidthOfCounter:8;                 ///< Unsigned 8-bit number in the range
+                                            ///< 0:60 defining the number of
+                                            ///< implemented counter bits.
+  UINT64  TypeOfCycleCounting:8;            ///< Unsigned 8-bit number defining the
+                                            ///< event type for counting processor cycles.
+  UINT64  TypeOfRetiredInstructionBundle:8; ///< Retired Unsigned 8-bit
+                                            ///< number defining the
+                                            ///< event type for retired
+                                            ///< instruction bundles.
+  UINT64  Reserved:32;
+} PAL_PERFORMANCE_INFO;
+
+/**
+  PAL Procedure - PAL_PERF_MON_INFO.
+
+  Return the number and type of performance monitors. It is
+  required by Itanium processors. The PAL procedure supports the Static
+  Registers calling convention. It could be called at physical
+  mode and virtual mode.
+
+  @param Index              Index of PAL_PERF_MON_INFO within the list of
+                            PAL procedures.
+  @param PerformanceBuffer  An address to an 8-byte aligned
+                            128-byte memory buffer.
+
+  @retval 0                 Call completed without error
+  @retval -2                Invalid argument
+  @retval -3                Call completed with error.
+
+  @return R9                Information about the performance monitors
+                            implemented. See PAL_PERFORMANCE_INFO;
+
+**/
+#define PAL_PERF_MON_INFO 15
+
+#define PAL_PLATFORM_ADDR_INTERRUPT_BLOCK_TOKEN                       0x0
+#define PAL_PLATFORM_ADDR_IO_BLOCK_TOKEN                              0x1
+
+/**
+  PAL Procedure - PAL_PLATFORM_ADDR.
+
+  Specify processor interrupt block address and I/O port space
+  address. It is required by Itanium processors. The PAL procedure supports the
+  Static Registers calling convention. It could be called at
+  physical mode and virtual mode.
+
+  @param Index    Index of PAL_PLATFORM_ADDR within the list of
+                  PAL procedures.
+  @param Type     Unsigned 64-bit integer specifying the type of
+                  block. 0 indicates that the processor interrupt
+                  block pointer should be initialized. 1 indicates
+                  that the processor I/O block pointer should be
+                  initialized.
+  @param Address  Unsigned 64-bit integer specifying the address
+                  to which the processor I/O block or interrupt
+                  block shall be set. The address must specify
+                  an implemented physical address on the
+                  processor model, bit 63 is ignored.
+
+  @retval 0       Call completed without error
+  @retval -1      Unimplemented procedure.
+  @retval -2      Invalid argument
+  @retval -3      Call completed with error.
+
+**/
+#define PAL_PLATFORM_ADDR 16
+
+typedef struct {
+  UINT64  Reserved1:36;
+  UINT64  FaultInUndefinedIns:1;                ///< Bit36, No Unimplemented
+                                                ///< instruction address reported as
+                                                ///< fault. Denotes how the processor
+                                                ///< reports the detection of
+                                                ///< unimplemented instruction
+                                                ///< addresses. When 1, the processor
+                                                ///< reports an Unimplemented
+                                                ///< Instruction Address fault on the
+                                                ///< unimplemented address; when 0, it
+                                                ///< reports an Unimplemented
+                                                ///< Instruction Address trap on the
+                                                ///< previous instruction in program
+                                                ///< order. This feature may only be
+                                                ///< interrogated by
+                                                ///< PAL_PROC_GET_FEATURES. It may not
+                                                ///< be enabled or disabled by
+                                                ///< PAL_PROC_SET_FEATURES. The
+                                                ///< corresponding argument is ignored.
+                                                
+  UINT64  NoPresentPmi:1;                       ///< Bit37, No INIT, PMI, and LINT pins
+                                                ///< present. Denotes the absence of INIT,
+                                                ///< PMI, LINT0 and LINT1 pins on the
+                                                ///< processor. When 1, the pins are absent.
+                                                ///< When 0, the pins are present. This
+                                                ///< feature may only be interrogated by
+                                                ///< PAL_PROC_GET_FEATURES. It may not be
+                                                ///< enabled or disabled by
+                                                ///< PAL_PROC_SET_FEATURES. The corresponding
+                                                ///< argument is ignored.
+                                                
+  UINT64  NoSimpleImpInUndefinedIns:1;          ///< Bit38, No Simple
+                                                ///< implementation of
+                                                ///< unimplemented instruction
+                                                ///< addresses. Denotes how an
+                                                ///< unimplemented instruction
+                                                ///< address is recorded in IIP
+                                                ///< on an Unimplemented
+                                                ///< Instruction Address trap or
+                                                ///< fault. When 1, the full
+                                                ///< unimplemented address is
+                                                ///< recorded in IIP; when 0, the
+                                                ///< address is sign extended
+                                                ///< (virtual addresses) or zero
+                                                ///< extended (physical
+                                                ///< addresses). This feature may
+                                                ///< only be interrogated by
+                                                ///< PAL_PROC_GET_FEATURES. It
+                                                ///< may not be enabled or
+                                                ///< disabled by
+                                                ///< PAL_PROC_SET_FEATURES. The
+                                                ///< corresponding argument is
+                                                ///< ignored.
+
+  UINT64  NoVariablePState:1;                   ///< Bit39, No Variable P-state
+                                                ///< performance: A value of 1, indicates
+                                                ///< that a processor implements
+                                                ///< techniques to optimize performance
+                                                ///< for the given P-state power budget
+                                                ///< by dynamically varying the
+                                                ///< frequency, such that maximum
+                                                ///< performance is achieved for the
+                                                ///< power budget. A value of 0,
+                                                ///< indicates that P-states have no
+                                                ///< frequency variation or very small
+                                                ///< frequency variations for their given
+                                                ///< power budget. This feature may only
+                                                ///< be interrogated by
+                                                ///< PAL_PROC_GET_FEATURES. it may not be
+                                                ///< enabled or disabled by
+                                                ///< PAL_PROC_SET_FEATURES. The
+                                                ///< corresponding argument is ignored.
+
+  UINT64  NoVM:1;                               ///< Bit40, No Virtual Machine features implemented.
+                                                ///< Denotes whether PSR.vm is implemented. This
+                                                ///< feature may only be interrogated by
+                                                ///< PAL_PROC_GET_FEATURES. It may not be enabled or
+                                                ///< disabled by PAL_PROC_SET_FEATURES. The
+                                                ///< corresponding argument is ignored.
+
+  UINT64  NoXipXpsrXfs:1;                       ///< Bit41, No XIP, XPSR, and XFS
+                                                ///< implemented. Denotes whether XIP, XPSR,
+                                                ///< and XFS are implemented for machine
+                                                ///< check recovery. This feature may only be
+                                                ///< interrogated by PAL_PROC_GET_FEATURES.
+                                                ///< It may not be enabled or disabled by
+                                                ///< PAL_PROC_SET_FEATURES. The corresponding
+                                                ///< argument is ignored.
+
+  UINT64  NoXr1ThroughXr3:1;                    ///< Bit42, No XR1 through XR3 implemented.
+                                                ///<   Denotes whether XR1 XR3 are
+                                                ///<   implemented for machine check
+                                                ///<   recovery. This feature may only be
+                                                ///<   interrogated by PAL_PROC_GET_FEATURES.
+                                                ///<   It may not be enabled or disabled by
+                                                ///<   PAL_PROC_SET_FEATURES. The
+                                                ///<   corresponding argument is ignored.
+
+  UINT64  DisableDynamicPrediction:1;           ///< Bit43, Disable Dynamic
+                                                ///< Predicate Prediction. When
+                                                ///< 0, the processor may predict
+                                                ///< predicate results and
+                                                ///< execute speculatively, but
+                                                ///< may not commit results until
+                                                ///< the actual predicates are
+                                                ///< known. When 1, the processor
+                                                ///< shall not execute predicated
+                                                ///< instructions until the
+                                                ///< actual predicates are known.
+
+  UINT64  DisableSpontaneousDeferral:1;         ///< Bit44, Disable Spontaneous
+                                                ///<   Deferral. When 1, the
+                                                ///<   processor may optionally
+                                                ///<   defer speculative loads
+                                                ///<   that do not encounter any
+                                                ///<   exception conditions, but
+                                                ///<   that trigger other
+                                                ///<   implementation-dependent
+                                                ///<   conditions (e.g., cache
+                                                ///<   miss). When 0, spontaneous
+                                                ///<   deferral is disabled.
+
+  UINT64  DisableDynamicDataCachePrefetch:1;    ///< Bit45, Disable Dynamic
+                                                ///<   Data Cache Prefetch.
+                                                ///<   When 0, the processor
+                                                ///<   may prefetch into the
+                                                ///<   caches any data which
+                                                ///<   has not been accessed
+                                                ///<   by instruction
+                                                ///<   execution, but which
+                                                ///<   is likely to be
+                                                ///<   accessed. When 1, no
+                                                ///<   data may be fetched
+                                                ///<   until it is needed for
+                                                ///<   instruction execution
+                                                ///<   or is fetched by an
+                                                ///<   lfetch instruction.
+
+  UINT64  DisableDynamicInsCachePrefetch:1;     ///< Bit46, Disable
+                                                ///< DynamicInstruction Cache
+                                                ///< Prefetch. When 0, the
+                                                ///< processor may prefetch
+                                                ///< into the caches any
+                                                ///< instruction which has
+                                                ///< not been executed, but
+                                                ///< whose execution is
+                                                ///< likely. When 1,
+                                                ///< instructions may not be
+                                                ///< fetched until needed or
+                                                ///< hinted for execution.
+                                                ///< (Prefetch for a hinted
+                                                ///< branch is allowed even
+                                                ///< when dynamic instruction
+                                                ///< cache prefetch is
+                                                ///< disabled.)
+
+  UINT64  DisableBranchPrediction:1;            ///< Bit47, Disable Dynamic branch
+                                                ///<   prediction. When 0, the
+                                                ///<   processor may predict branch
+                                                ///<   targets and speculatively
+                                                ///<   execute, but may not commit
+                                                ///<   results. When 1, the processor
+                                                ///<   must wait until branch targets
+                                                ///<   are known to execute.
+  UINT64  Reserved2:4;
+  UINT64  DisablePState:1;                      ///< Bit52, Disable P-states. When 1, the PAL
+                                                ///< P-state procedures (PAL_PSTATE_INFO,
+                                                ///< PAL_SET_PSTATE, PAL_GET_PSTATE) will
+                                                ///< return with a status of -1
+                                                ///< (Unimplemented procedure).
+
+  UINT64  EnableMcaOnDataPoisoning:1;           ///< Bit53, Enable MCA signaling
+                                                ///< on data-poisoning event
+                                                ///< detection. When 0, a CMCI
+                                                ///< will be signaled on error
+                                                ///< detection. When 1, an MCA
+                                                ///< will be signaled on error
+                                                ///< detection. If this feature
+                                                ///< is not supported, then the
+                                                ///< corresponding argument is
+                                                ///< ignored when calling
+                                                ///< PAL_PROC_SET_FEATURES. Note
+                                                ///< that the functionality of
+                                                ///< this bit is independent of
+                                                ///< the setting in bit 60
+                                                ///< (Enable CMCI promotion), and
+                                                ///< that the bit 60 setting does
+                                                ///< not affect CMCI signaling
+                                                ///< for data-poisoning related
+                                                ///< events. Volume 2: Processor
+                                                ///< Abstraction Layer 2:431
+                                                ///< PAL_PROC_GET_FEATURES
+
+  UINT64  EnableVmsw:1;                         ///< Bit54, Enable the use of the vmsw
+                                                ///<   instruction. When 0, the vmsw instruction
+                                                ///<   causes a Virtualization fault when
+                                                ///<   executed at the most privileged level.
+                                                ///<   When 1, this bit will enable normal
+                                                ///<   operation of the vmsw instruction.
+
+  UINT64  EnableEnvNotification:1;              ///< Bit55, Enable external
+                                                ///< notification when the processor
+                                                ///< detects hardware errors caused
+                                                ///< by environmental factors that
+                                                ///< could cause loss of
+                                                ///< deterministic behavior of the
+                                                ///< processor. When 1, this bit will
+                                                ///< enable external notification,
+                                                ///< when 0 external notification is
+                                                ///< not provided. The type of
+                                                ///< external notification of these
+                                                ///< errors is processor-dependent. A
+                                                ///< loss of processor deterministic
+                                                ///< behavior is considered to have
+                                                ///< occurred if these
+                                                ///< environmentally induced errors
+                                                ///< cause the processor to deviate
+                                                ///< from its normal execution and
+                                                ///< eventually causes different
+                                                ///< behavior which can be observed
+                                                ///<  at the processor bus pins.
+                                                ///< Processor errors that do not
+                                                ///< have this effects (i.e.,
+                                                ///< software induced machine checks)
+                                                ///< may or may not be promoted
+                                                ///< depending on the processor
+                                                ///< implementation.
+
+  UINT64  DisableBinitWithTimeout:1;            ///< Bit56, Disable a BINIT on
+                                                ///<   internal processor time-out.
+                                                ///<   When 0, the processor may
+                                                ///<   generate a BINIT on an
+                                                ///<   internal processor time-out.
+                                                ///<   When 1, the processor will not
+                                                ///<   generate a BINIT on an
+                                                ///<   internal processor time-out.
+                                                ///<   The event is silently ignored.
+
+  UINT64  DisableDPM:1;                         ///< Bit57, Disable Dynamic Power Management
+                                                ///<   (DPM). When 0, the hardware may reduce
+                                                ///<   power consumption by removing the clock
+                                                ///<   input from idle functional units. When 1,
+                                                ///<   all functional units will receive clock
+                                                ///<   input, even when idle.
+
+  UINT64  DisableCoherency:1;                   ///< Bit58, Disable Coherency. When 0,
+                                                ///< the processor uses normal coherency
+                                                ///< requests and responses. When 1, the
+                                                ///< processor answers all requests as if
+                                                ///< the line were not present.
+
+  UINT64  DisableCache:1;                       ///< Bit59, Disable Cache. When 0, the
+                                                ///< processor performs cast outs on
+                                                ///< cacheable pages and issues and responds
+                                                ///< to coherency requests normally. When 1,
+                                                ///< the processor performs a memory access
+                                                ///< for each reference regardless of cache
+                                                ///< contents and issues no coherence
+                                                ///< requests and responds as if the line
+                                                ///< were not present. Cache contents cannot
+                                                ///< be relied upon when the cache is
+                                                ///< disabled. WARNING: Semaphore
+                                                ///< instructions may not be atomic or may
+                                                ///< cause Unsupported Data Reference faults
+                                                ///< if caches are disabled.
+
+  UINT64  EnableCmciPromotion:1;                ///< Bit60, Enable CMCI promotion When
+                                                ///<   1, Corrected Machine Check
+                                                ///<   Interrupts (CMCI) are promoted to
+                                                ///<   MCAs. They are also further
+                                                ///<   promoted to BERR if bit 39, Enable
+                                                ///<   MCA promotion, is also set and
+                                                ///<   they are promoted to BINIT if bit
+                                                ///<   38, Enable MCA to BINIT promotion,
+                                                ///<   is also set. This bit has no
+                                                ///<   effect if MCA signalling is
+                                                ///<   disabled (see
+                                                ///<   PAL_BUS_GET/SET_FEATURES)
+
+  UINT64  EnableMcaToBinitPromotion:1;          ///< Bit61, Enable MCA to BINIT
+                                                ///< promotion. When 1, machine
+                                                ///< check aborts (MCAs) are
+                                                ///< promoted to the Bus
+                                                ///< Initialization signal, and
+                                                ///< the BINIT pin is assert on
+                                                ///< each occurrence of an MCA.
+                                                ///< Setting this bit has no
+                                                ///< effect if BINIT signalling
+                                                ///< is disabled. (See
+                                                ///< PAL_BUS_GET/SET_FEATURES)
+
+  UINT64  EnableMcaPromotion:1;                 ///< Bit62, Enable MCA promotion. When
+                                                ///<   1, machine check aborts (MCAs) are
+                                                ///<   promoted to the Bus Error signal,
+                                                ///<   and the BERR pin is assert on each
+                                                ///<   occurrence of an MCA. Setting this
+                                                ///<   bit has no effect if BERR
+                                                ///<   signalling is disabled. (See
+                                                ///<   PAL_BUS_GET/SET_FEATURES)
+                                                
+  UINT64  EnableBerrPromotion:1;                ///< Bit63. Enable BERR promotion. When
+                                                ///<   1, the Bus Error (BERR) signal is
+                                                ///<   promoted to the Bus Initialization
+                                                ///<   (BINIT) signal, and the BINIT pin
+                                                ///<   is asserted on the occurrence of
+                                                ///<   each Bus Error. Setting this bit
+                                                ///<   has no effect if BINIT signalling
+                                                ///<   is disabled. (See
+                                                ///<   PAL_BUS_GET/SET_FEATURES)
+} PAL_PROCESSOR_FEATURES;
+
+/**
+  PAL Procedure - PAL_PROC_GET_FEATURES.
+
+  Return configurable processor features and their current
+  setting. It is required by Itanium processors. The PAL procedure supports the
+  Static Registers calling convention. It could be called at
+  physical mode and virtual mode.
+
+  @param Index      Index of PAL_PROC_GET_FEATURES within the list of
+                    PAL procedures.
+  @param Reserved   Reserved parameter.
+  @param FeatureSet Feature set information is being requested
+                    for.
+
+  @retval 1         Call completed without error; The
+                    feature_set passed is not supported but a
+                    feature_set of a larger value is supported.
+  @retval 0         Call completed without error
+  @retval -2        Invalid argument
+  @retval -3        Call completed with error.
+  @retval -8        feature_set passed is beyond the maximum
+                    feature_set supported
+
+  @return R9        64-bit vector of features implemented. See
+                    PAL_PROCESSOR_FEATURES.
+  @return R10       64-bit vector of current feature settings. See
+                    PAL_PROCESSOR_FEATURES.
+  @return R11       64-bit vector of features controllable by
+                    software.
+
+**/
+#define PAL_PROC_GET_FEATURES 17
+
+
+/**
+  PAL Procedure - PAL_PROC_SET_FEATURES.
+
+  Enable or disable configurable processor features. It is
+  required by Itanium processors. The PAL procedure supports the Static
+  Registers calling convention. It could be called at physical
+  mode.
+
+  @param Index          Index of PAL_PROC_SET_FEATURES within the list of
+                        PAL procedures.
+  @param FeatureSelect  64-bit vector denoting desired state of
+                        each feature (1=select, 0=non-select).
+  @param FeatureSet     Feature set to apply changes to. See
+                        PAL_PROC_GET_FEATURES for more information
+                        on feature sets.
+
+  @retval 1             Call completed without error; The
+                        feature_set passed is not supported but a
+                        feature_set of a larger value is supported
+  @retval 0             Call completed without error
+  @retval -2            Invalid argument
+  @retval -3            Call completed with error.
+  @retval -8            feature_set passed is beyond the maximum
+                        feature_set supported
+
+**/
+#define PAL_PROC_SET_FEATURES 18
+
+
+//
+// Value of PAL_REGISTER_INFO.InfoRequest.
+//
+#define PAL_APPLICATION_REGISTER_IMPLEMENTED  0
+#define PAL_APPLICATION_REGISTER_READABLE     1
+#define PAL_CONTROL_REGISTER_IMPLEMENTED      2
+#define PAL_CONTROL_REGISTER_READABLE         3
+
+
+/**
+  PAL Procedure - PAL_REGISTER_INFO.
+
+  Return AR and CR register information. It is required by Itanium processors.
+  The PAL procedure supports the Static Registers calling
+  convention. It could be called at physical mode and virtual
+  mode.
+
+  @param Index        Index of PAL_REGISTER_INFO within the list of
+                      PAL procedures.
+  @param InfoRequest  Unsigned 64-bit integer denoting what
+                      register information is requested. See
+                      PAL_REGISTER_INFO.InfoRequest above.
+
+  @retval 0           Call completed without error
+  @retval -2          Invalid argument
+  @retval -3          Call completed with error.
+
+  @return R9          64-bit vector denoting information for registers
+                      0-63. Bit 0 is register 0, bit 63 is register 63.
+  @return R10         64-bit vector denoting information for registers
+                      64-127. Bit 0 is register 64, bit 63 is register
+                      127.
+
+**/
+#define PAL_REGISTER_INFO 39
+
+/**
+  PAL Procedure - PAL_RSE_INFO.
+
+  Return RSE information. It is required by Itanium processors. The PAL
+  procedure supports the Static Registers calling convention. It
+  could be called at physical mode and virtual mode.
+
+  @param Index        Index of PAL_RSE_INFO within the list of
+                      PAL procedures.
+  @param InfoRequest  Unsigned 64-bit integer denoting what
+                      register information is requested. See
+                      PAL_REGISTER_INFO.InfoRequest above.
+
+  @retval 0           Call completed without error
+  @retval -2          Invalid argument
+  @retval -3          Call completed with error.
+
+  @return R9          Number of physical stacked general registers.
+  @return R10         RSE hints supported by processor.
+
+**/
+#define PAL_RSE_INFO 19
+
+typedef struct {
+  UINT64  VersionOfPalB:16;     ///< Is a 16-bit binary coded decimal (BCD)
+                                ///< number that provides identification
+                                ///< information about the PAL_B firmware.
+  UINT64  Reserved1:8;
+  UINT64  PalVendor:8;          ///< Is an unsigned 8-bit integer indicating the
+                                ///< vendor of the PAL code.
+  UINT64  VersionOfPalA:16;     ///< Is a 16-bit binary coded decimal (BCD)
+                                ///< number that provides identification
+                                ///< information about the PAL_A firmware. In
+                                ///< the split PAL_A model, this return value
+                                ///< is the version number of the
+                                ///< processor-specific PAL_A. The generic
+                                ///< PAL_A version is not returned by this
+                                ///< procedure in the split PAL_A model.
+  UINT64  Reserved2:16;
+} PAL_VERSION_INFO;
+
+/**
+  PAL Procedure - PAL_VERSION.
+
+  Return version of PAL code. It is required by Itanium processors. The PAL
+  procedure supports the Static Registers calling convention. It
+  could be called at physical mode and virtual mode.
+
+  @param Index        Index of PAL_VERSION within the list of
+                      PAL procedures.
+  @param InfoRequest  Unsigned 64-bit integer denoting what
+                      register information is requested. See
+                      PAL_REGISTER_INFO.InfoRequest above.
+
+  @retval 0           Call completed without error
+  @retval -2          Invalid argument
+  @retval -3          Call completed with error.
+
+  @return R9          8-byte formatted value returning the minimum PAL
+                      version needed for proper operation of the
+                      processor. See PAL_VERSION_INFO above.
+  @return R10         8-byte formatted value returning the current PAL
+                      version running on the processor. See
+                      PAL_VERSION_INFO above.
+
+**/
+#define PAL_VERSION 20
+
+
+
+//
+// Vectors of PAL_MC_CLEAR_LOG.pending
+//
+#define PAL_MC_PENDING    BIT0
+#define PAL_INIT_PENDING  BIT1
+
+/**
+  PAL Procedure - PAL_MC_CLEAR_LOG.
+
+  Clear all error information from processor error logging
+  registers. It is required by Itanium processors. The PAL procedure supports
+  the Static Registers calling convention. It could be called at
+  physical mode and virtual mode.
+
+  @param Index  Index of PAL_MC_CLEAR_LOG within the list of
+                PAL procedures.
+
+  @retval 0     Call completed without error
+  @retval -2    Invalid argument
+  @retval -3    Call completed with error.
+
+  @return R9    64-bit vector denoting whether an event is
+                pending. See PAL_MC_CLEAR_LOG.pending above.
+
+**/
+#define PAL_MC_CLEAR_LOG 21
+
+/**
+  PAL Procedure - PAL_MC_DRAIN.
+
+  Ensure that all operations that could cause an MCA have
+  completed. It is required by Itanium processors. The PAL procedure supports
+  the Static Registers calling convention. It could be called at
+  physical mode and virtual mode.
+
+  @param Index  Index of PAL_MC_DRAIN within the list of PAL
+                procedures.
+
+  @retval 0     Call completed without error
+  @retval -2    Invalid argument
+  @retval -3    Call completed with error.
+
+**/
+#define PAL_MC_DRAIN 22
+
+
+/**
+  PAL Procedure - PAL_MC_DYNAMIC_STATE.
+
+  Return Processor Dynamic State for logging by SAL. It is
+  optional. The PAL procedure supports the Static Registers
+  calling convention. It could be called at physical mode.
+
+  @param Index  Index of PAL_MC_DYNAMIC_STATE within the list of PAL
+                procedures.
+  @param Offset Offset of the next 8 bytes of Dynamic Processor
+                State to return. (multiple of 8).
+
+  @retval 0     Call completed without error
+  @retval -1    Unimplemented procedure.
+  @retval -2    Invalid argument
+  @retval -3    Call completed with error.
+
+  @return R9    Unsigned 64-bit integer denoting bytes of Dynamic
+                Processor State returned.
+  @return R10   Next 8 bytes of Dynamic Processor State.
+
+**/
+#define PAL_MC_DYNAMIC_STATE 24
+
+
+
+//
+// Values of PAL_MC_ERROR_INFO.InfoIndex.
+//
+#define PAL_PROCESSOR_ERROR_MAP       0
+#define PAL_PROCESSOR_STATE_PARAM     1
+#define PAL_STRUCTURE_SPECIFIC_ERROR  2
+
+typedef struct {
+ UINT64 CoreId:4;                   ///< Bit3:0,  Processor core ID (default is 0 for
+                                    ///< processors with a single core)
+
+ UINT64 ThreadId:4;                 ///< Bit7:4, Logical thread ID (default is 0 for
+                                    ///< processors that execute a single thread)
+
+ UINT64 InfoOfInsCache:4;           ///< Bit11:8, Error information is
+                                    ///< available for 1st, 2nd, 3rd, and 4th
+                                    ///< level instruction caches.
+
+ UINT64 InfoOfDataCache:4;          ///< Bit15:12, Error information is
+                                    ///<   available for 1st, 2nd, 3rd, and 4th
+                                    ///<   level data/unified caches.
+
+ UINT64 InfoOfInsTlb:4;             ///< Bit19:16 Error information is available
+                                    ///< for 1st, 2nd, 3rd, and 4th level
+                                    ///< instruction TLB.
+
+ UINT64 InfoOfDataTlb:4;            ///< Bit23:20, Error information is available
+                                    ///< for 1st, 2nd, 3rd, and 4th level
+                                    ///< data/unified TLB
+
+ UINT64 InfoOfProcessorBus:4;       ///< Bit27:24 Error information is
+                                    ///<   available for the 1st, 2nd, 3rd,
+                                    ///<   and 4th level processor bus
+                                    ///<   hierarchy.
+ UINT64 InfoOfRegisterFile:4;       ///< Bit31:28 Error information is
+                                    ///<   available on register file
+                                    ///<   structures.
+ UINT64 InfoOfMicroArch:4;          ///< Bit47:32, Error information is
+                                    ///<   available on micro-architectural
+                                    ///<   structures.
+ UINT64 Reserved:16;
+} PAL_MC_ERROR_INFO_LEVEL_INDEX;
+
+//
+// Value of PAL_MC_ERROR_INFO.ErrorTypeIndex
+//
+#define PAL_ERR_INFO_BY_LEVEL_INDEX               0
+#define PAL_ERR_INFO_TARGET_ADDRESS               1
+#define PAL_ERR_INFO_REQUESTER_IDENTIFIER         2
+#define PAL_ERR_INFO_REPONSER_INDENTIFIER         3
+#define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER  4
+
+typedef struct {
+  UINT64  Operation:4;                  ///< Bit3:0, Type of cache operation that caused
+                                        ///< the machine check: 0 - unknown or internal
+                                        ///< error 1 - load 2 - store 3 - instruction
+                                        ///< fetch or instruction prefetch 4 - data
+                                        ///< prefetch (both hardware and software) 5 -
+                                        ///< snoop (coherency check) 6 - cast out
+                                        ///< (explicit or implicit write-back of a cache
+                                        ///< line) 7 - move in (cache line fill)
+
+  UINT64  FailedCacheLevel:2;           ///< Bit5:4 Level of cache where the
+                                        ///< error occurred. A value of 0
+                                        ///< indicates the first level of cache.
+  UINT64  Reserved1:2;
+  UINT64  FailedInDataPart:1;           ///< Bit8, Failure located in the data part of the cache line.
+  UINT64  FailedInTagPart:1;            ///< Bit9, Failure located in the tag part of the cache line.
+  UINT64  FailedInDataCache:1;          ///< Bit10, Failure located in the data cache
+
+  UINT64  FailedInInsCache:1;           ///< Bit11, Failure located in the
+                                        ///< instruction cache.
+                                        
+  UINT64  Mesi:3;                       ///< Bit14:12,  0 - cache line is invalid. 1 - cache
+                                        ///< line is held shared. 2 - cache line is held
+                                        ///< exclusive. 3 - cache line is modified. All other
+                                        ///< values are reserved.
+                                        
+  UINT64  MesiIsValid:1;                ///< Bit15, The mesi field in the cache_check
+                                        ///< parameter is valid.
+                                        
+  UINT64  FailedWay:5;                  ///< Bit20:16, Failure located in the way of
+                                        ///< the cache indicated by this value.
+
+  UINT64  WayIndexIsValid:1;            ///< Bit21, The way and index field in the
+                                        ///< cache_check parameter is valid.
+
+  UINT64  Reserved2:1;
+  UINT64  MultipleBitsError:1;          ///< Bit23, A multiple-bit error was
+                                        ///< detected, and data was poisoned for
+                                        ///< the corresponding cache line during
+                                        ///< castout.
+  UINT64  Reserved3:8;
+  UINT64  IndexOfCacheLineError:20;     ///< Bit51:32, Index of the cache
+                                        ///< line where the error occurred.
+  UINT64  Reserved4:2;
+
+  UINT64  InstructionSet:1;             ///< Bit54, Instruction set. If this value
+                                        ///<   is set to zero, the instruction that
+                                        ///<   generated the machine check was an
+                                        ///<   Intel Itanium instruction. If this bit
+                                        ///<   is set to one, the instruction that
+                                        ///<   generated the machine check was IA-32
+                                        ///<   instruction.
+
+  UINT64  InstructionSetIsValid:1;      ///< Bit55, The is field in the
+                                        ///< cache_check parameter is valid.
+
+  UINT64  PrivilegeLevel:2;             ///< Bit57:56, Privilege level. The
+                                        ///<   privilege level of the instruction
+                                        ///<   bundle responsible for generating the
+                                        ///<   machine check.
+
+  UINT64  PrivilegeLevelIsValide:1;     ///< Bit58, The pl field of the
+                                        ///<   cache_check parameter is
+                                        ///<   valid.
+
+  UINT64  McCorrected:1;                ///< Bit59, Machine check corrected: This bit
+                                        ///<   is set to one to indicate that the machine
+                                        ///<   check has been corrected.
+
+  UINT64  TargetAddressIsValid:1;       ///< Bit60, Target address is valid:
+                                        ///< This bit is set to one to
+                                        ///< indicate that a valid target
+                                        ///< address has been logged.
+
+  UINT64  RequesterIdentifier:1;        ///< Bit61, Requester identifier: This
+                                        ///<   bit is set to one to indicate that
+                                        ///<   a valid requester identifier has
+                                        ///<   been logged.
+
+  UINT64  ResponserIdentifier:1;        ///< Bit62, Responder identifier: This
+                                        ///<   bit is set to one to indicate that
+                                        ///<   a valid responder identifier has
+                                        ///<   been logged.
+
+  UINT64  PreciseInsPointer:1;          ///< Bit63,  Precise instruction pointer.
+                                        ///< This bit is set to one to indicate
+                                        ///< that a valid precise instruction
+                                        ///< pointer has been logged.
+
+} PAL_CACHE_CHECK_INFO;
+
+
+typedef struct {
+  UINT64  FailedSlot:8;                 ///< Bit7:0, Slot number of the translation
+                                        ///< register where the failure occurred.
+  UINT64  FailedSlotIsValid:1;          ///< Bit8, The tr_slot field in the
+                                        ///< TLB_check parameter is valid.
+  UINT64  Reserved1 :1;
+  UINT64  TlbLevel:2;                   ///< Bit11:10,  The level of the TLB where the
+                                        ///< error occurred. A value of 0 indicates the
+                                        ///< first level of TLB
+  UINT64  Reserved2 :4;
+
+  UINT64  FailedInDataTr:1;             ///< Bit16, Error occurred in the data
+                                        ///< translation registers.
+
+  UINT64  FailedInInsTr:1;              ///< Bit17, Error occurred in the instruction
+                                        ///< translation registers
+
+  UINT64  FailedInDataTc:1;             ///< Bit18, Error occurred in data
+                                        ///< translation cache.
+
+  UINT64  FailedInInsTc:1;              ///< Bit19, Error occurred in the instruction
+                                        ///< translation cache.
+
+  UINT64  FailedOperation:4;            ///< Bit23:20, Type of cache operation that
+                                        ///<   caused the machine check: 0 - unknown
+                                        ///<   1 - TLB access due to load instruction
+                                        ///<   2 - TLB access due to store
+                                        ///<   instruction 3 - TLB access due to
+                                        ///<   instruction fetch or instruction
+                                        ///<   prefetch 4 - TLB access due to data
+                                        ///<   prefetch (both hardware and software)
+                                        ///<   5 - TLB shoot down access 6 - TLB
+                                        ///<   probe instruction (probe, tpa) 7 -
+                                        ///<   move in (VHPT fill) 8 - purge (insert
+                                        ///<   operation that purges entries or a TLB
+                                        ///<   purge instruction) All other values
+                                        ///<   are reserved.
+
+  UINT64  Reserved3:30;
+  UINT64  InstructionSet:1;             ///< Bit54, Instruction set. If this value
+                                        ///<   is set to zero, the instruction that
+                                        ///<   generated the machine check was an
+                                        ///<   Intel Itanium instruction. If this bit
+                                        ///<   is set to one, the instruction that
+                                        ///<   generated the machine check was IA-32
+                                        ///<   instruction.
+
+  UINT64  InstructionSetIsValid:1;      ///< Bit55, The is field in the
+                                        ///< TLB_check parameter is valid.
+
+  UINT64  PrivelegeLevel:2;             ///< Bit57:56, Privilege level. The
+                                        ///<   privilege level of the instruction
+                                        ///<   bundle responsible for generating the
+                                        ///<   machine check.
+
+  UINT64  PrivelegeLevelIsValid:1;      ///< Bit58,  The pl field of the
+                                        ///< TLB_check parameter is valid.
+
+  UINT64  McCorrected:1;                ///< Bit59, Machine check corrected: This bit
+                                        ///<   is set to one to indicate that the machine
+                                        ///<   check has been corrected.
+
+  UINT64  TargetAddressIsValid:1;       ///< Bit60, Target address is valid:
+                                        ///< This bit is set to one to
+                                        ///< indicate that a valid target
+                                        ///< address has been logged.
+
+  UINT64  RequesterIdentifier:1;        ///< Bit61 Requester identifier: This
+                                        ///<   bit is set to one to indicate that
+                                        ///<   a valid requester identifier has
+                                        ///<   been logged.
+
+  UINT64  ResponserIdentifier:1;        ///< Bit62, Responder identifier:  This
+                                        ///<   bit is set to one to indicate that
+                                        ///<   a valid responder identifier has
+                                        ///<   been logged.
+
+  UINT64  PreciseInsPointer:1;          ///< Bit63 Precise instruction pointer.
+                                        ///<   This bit is set to one to indicate
+                                        ///<   that a valid precise instruction
+                                        ///<   pointer has been logged.
+} PAL_TLB_CHECK_INFO;
+
+/**
+  PAL Procedure - PAL_MC_ERROR_INFO.
+
+  Return Processor Machine Check Information and Processor
+  Static State for logging by SAL. It is required by Itanium processors. The
+  PAL procedure supports the Static Registers calling
+  convention. It could be called at physical and virtual mode.
+
+  @param Index            Index of PAL_MC_ERROR_INFO within the list of PAL
+                          procedures.
+  @param InfoIndex        Unsigned 64-bit integer identifying the
+                          error information that is being requested.
+                          See PAL_MC_ERROR_INFO.InfoIndex.
+  @param LevelIndex       8-byte formatted value identifying the
+                          structure to return error information
+                          on. See PAL_MC_ERROR_INFO_LEVEL_INDEX.
+  @param ErrorTypeIndex   Unsigned 64-bit integer denoting the
+                          type of error information that is
+                          being requested for the structure
+                          identified in LevelIndex.
+
+  @retval 0               Call completed without error
+  @retval -2              Invalid argument
+  @retval -3              Call completed with error.
+  @retval -6              Argument was valid, but no error
+                          information was available
+
+  @return R9              Error information returned. The format of this
+                          value is dependant on the input values passed.
+  @return R10             If this value is zero, all the error information
+                          specified by err_type_index has been returned. If
+                          this value is one, more structure-specific error
+                          information is available and the caller needs to
+                          make this procedure call again with level_index
+                          unchanged and err_type_index, incremented.
+
+**/
+#define PAL_MC_ERROR_INFO 25
+
+/**
+  PAL Procedure - PAL_MC_EXPECTED.
+
+  Set/Reset Expected Machine Check Indicator. It is required by
+  Itanium processors. The PAL procedure supports the Static Registers calling
+  convention. It could be called at physical mode.
+
+  @param Index      Index of PAL_MC_EXPECTED within the list of PAL
+                    procedures.
+  @param Expected   Unsigned integer with a value of 0 or 1 to
+                    set or reset the hardware resource
+                    PALE_CHECK examines for expected machine
+                    checks.
+
+  @retval 0         Call completed without error
+  @retval -2        Invalid argument
+  @retval -3        Call completed with error.
+
+  @return R9        Unsigned integer denoting whether a machine check
+                    was previously expected.
+
+**/
+#define PAL_MC_EXPECTED 23
+
+/**
+  PAL Procedure - PAL_MC_REGISTER_MEM.
+
+  Register min-state save area with PAL for machine checks and
+  inits. It is required by Itanium processors. The PAL procedure supports the
+  Static Registers calling convention. It could be called at
+  physical mode.
+
+  @param Index    Index of PAL_MC_REGISTER_MEM within the list of PAL
+                  procedures.
+  @param Address  Physical address of the buffer to be
+                  registered with PAL.
+
+  @retval 0       Call completed without error
+  @retval -2      Invalid argument
+  @retval -3      Call completed with error.
+
+**/
+#define PAL_MC_REGISTER_MEM 27
+
+/**
+  PAL Procedure - PAL_MC_RESUME.
+
+  Restore minimal architected state and return to interrupted
+  process. It is required by Itanium processors. The PAL procedure supports the
+  Static Registers calling convention. It could be called at
+  physical mode.
+
+  @param Index        Index of PAL_MC_RESUME within the list of PAL
+                      procedures.
+  @param SetCmci      Unsigned 64 bit integer denoting whether to
+                      set the CMC interrupt. A value of 0 indicates
+                      not to set the interrupt, a value of 1
+                      indicated to set the interrupt, and all other
+                      values are reserved.
+  @param SavePtr      Physical address of min-state save area used
+                      to used to restore processor state.
+  @param NewContext   Unsigned 64-bit integer denoting whether
+                      the caller is returning to a new context.
+                      A value of 0 indicates the caller is
+                      returning to the interrupted context, a
+                      value of 1 indicates that the caller is
+                      returning to a new context.
+
+  @retval -2          Invalid argument
+  @retval -3          Call completed with error.
+
+**/
+#define PAL_MC_RESUME 26
+
+/**
+  PAL Procedure - PAL_HALT.
+
+  Enter the low-power HALT state or an implementation-dependent
+  low-power state. It is optinal. The PAL procedure supports the
+  Static Registers calling convention. It could be called at
+  physical mode.
+
+  @param Index        Index of PAL_HALT within the list of PAL
+                      procedures.
+  @param HaltState    Unsigned 64-bit integer denoting low power
+                      state requested.
+  @param IoDetailPtr  8-byte aligned physical address pointer to
+                      information on the type of I/O
+                      (load/store) requested.
+
+  @retval 0           Call completed without error
+  @retval -1          Unimplemented procedure
+  @retval -2          Invalid argument
+  @retval -3          Call completed with error.
+
+  @return R9          Value returned if a load instruction is requested
+                      in the io_detail_ptr
+
+**/
+#define PAL_HALT 28
+
+
+/**
+  PAL Procedure - PAL_HALT_INFO.
+
+  Return the low power capabilities of the processor. It is
+  required by Itanium processors. The PAL procedure supports the
+  Stacked Registers calling convention. It could be called at
+  physical and virtual mode.
+
+  @param Index        Index of PAL_HALT_INFO within the list of PAL
+                      procedures.
+  @param PowerBuffer  64-bit pointer to a 64-byte buffer aligned
+                      on an 8-byte boundary.
+
+  @retval 0           Call completed without error
+  @retval -2          Invalid argument
+  @retval -3          Call completed with error.
+
+**/
+#define PAL_HALT_INFO 257
+
+
+/**
+  PAL Procedure - PAL_HALT_LIGHT.
+
+  Enter the low power LIGHT HALT state. It is required by
+  Itanium processors. The PAL procedure supports the Static Registers calling
+  convention. It could be called at physical and virtual mode.
+
+  @param Index  Index of PAL_HALT_LIGHT within the list of PAL
+                procedures.
+
+  @retval 0     Call completed without error
+  @retval -2    Invalid argument
+  @retval -3    Call completed with error.
+
+**/
+#define PAL_HALT_LIGHT 29
+
+/**
+  PAL Procedure - PAL_CACHE_LINE_INIT.
+
+  Initialize tags and data of a cache line for processor
+  testing. It is required by Itanium processors. The PAL procedure supports the
+  Static Registers calling convention. It could be called at
+  physical and virtual mode.
+
+  @param Index      Index of PAL_CACHE_LINE_INIT within the list of PAL
+                    procedures.
+  @param Address    Unsigned 64-bit integer value denoting the
+                    physical address from which the physical page
+                    number is to be generated. The address must be
+                    an implemented physical address, bit 63 must
+                    be zero.
+  @param DataValue  64-bit data value which is used to
+                    initialize the cache line.
+
+  @retval 0         Call completed without error
+  @retval -2        Invalid argument
+  @retval -3        Call completed with error.
+
+**/
+#define PAL_CACHE_LINE_INIT 31
+
+/**
+  PAL Procedure - PAL_CACHE_READ.
+
+  Read tag and data of a cache line for diagnostic testing. It
+  is optional. The PAL procedure supports the
+  Satcked Registers calling convention. It could be called at
+  physical mode.
+
+  @param Index    Index of PAL_CACHE_READ within the list of PAL
+                  procedures.
+  @param LineId   8-byte formatted value describing where in the
+                  cache to read the data.
+  @param Address  64-bit 8-byte aligned physical address from
+                  which to read the data. The address must be an
+                  implemented physical address on the processor
+                  model with bit 63 set to zero.
+
+  @retval 1       The word at address was found in the
+                  cache, but the line was invalid.
+  @retval 0       Call completed without error
+  @retval -2      Invalid argument
+  @retval -3      Call completed with error.
+  @retval -5      The word at address was not found in the
+                  cache.
+  @retval -7      The operation requested is not supported
+                  for this cache_type and level.
+
+  @return R9      Right-justified value returned from the cache
+                  line.
+  @return R10     The number of bits returned in data.
+  @return R11     The status of the cache line.
+
+**/
+#define PAL_CACHE_READ 259
+
+
+/**
+  PAL Procedure - PAL_CACHE_WRITE.
+
+  Write tag and data of a cache for diagnostic testing. It is
+  optional. The PAL procedure supports the Satcked Registers
+  calling convention. It could be called at physical mode.
+
+  @param Index    Index of PAL_CACHE_WRITE within the list of PAL
+                  procedures.
+  @param LineId   8-byte formatted value describing where in the
+                  cache to write the data.
+  @param Address  64-bit 8-byte aligned physical address at
+                  which the data should be written. The address
+                  must be an implemented physical address on the
+                  processor model with bit 63 set to 0.
+  @param Data     Unsigned 64-bit integer value to write into
+                  the specified part of the cache.
+
+  @retval 0       Call completed without error
+  @retval -2      Invalid argument
+  @retval -3      Call completed with error.
+  @retval -7      The operation requested is not supported
+                  for this cache_type and level.
+
+**/
+#define PAL_CACHE_WRITE 260
+
+/**
+  PAL Procedure - PAL_TEST_INFO.
+
+  Returns alignment and size requirements needed for the memory
+  buffer passed to the PAL_TEST_PROC procedure as well as
+  information on self-test control words for the processor self
+  tests. It is required by Itanium processors. The PAL procedure supports the
+  Static Registers calling convention. It could be called at
+  physical mode.
+
+  @param Index      Index of PAL_TEST_INFO within the list of PAL
+                    procedures.
+  @param TestPhase  Unsigned integer that specifies which phase
+                    of the processor self-test information is
+                    being requested on. A value of 0 indicates
+                    the phase two of the processor self-test and
+                    a value of 1 indicates phase one of the
+                    processor self-test. All other values are
+                    reserved.
+
+  @retval 0         Call completed without error
+  @retval -2        Invalid argument
+  @retval -3        Call completed with error.
+
+  @return R9        Unsigned 64-bit integer denoting the number of
+                    bytes of main memory needed to perform the second
+                    phase of processor self-test.
+  @return R10       Unsigned 64-bit integer denoting the alignment
+                    required for the memory buffer.
+  @return R11       48-bit wide bit-field indicating if control of
+                    the processor self-tests is supported and which
+                    bits of the test_control field are defined for
+                    use.
+
+**/
+#define PAL_TEST_INFO 37
+
+typedef struct {
+  UINT64  BufferSize:56;    ///< Indicates the size in bytes of the memory
+                            ///< buffer that is passed to this procedure.
+                            ///< BufferSize must be greater than or equal in
+                            ///< size to the bytes_needed return value from
+                            ///< PAL_TEST_INFO, otherwise this procedure will
+                            ///< return with an invalid argument return
+                            ///< value.
+
+  UINT64  TestPhase:8;      ///< Defines which phase of the processor
+                            ///< self-tests are requested to be run. A value
+                            ///< of zero indicates to run phase two of the
+                            ///< processor self-tests. Phase two of the
+                            ///< processor self-tests are ones that require
+                            ///< external memory to execute correctly. A
+                            ///< value of one indicates to run phase one of
+                            ///< the processor self-tests. Phase one of the
+                            ///< processor self-tests are tests run during
+                            ///< PALE_RESET and do not depend on external
+                            ///< memory to run correctly. When the caller
+                            ///< requests to have phase one of the processor
+                            ///< self-test run via this procedure call, a
+                            ///< memory buffer may be needed to save and
+                            ///< restore state as required by the PAL calling
+                            ///< conventions. The procedure PAL_TEST_INFO
+                            ///< informs the caller about the requirements of
+                            ///< the memory buffer.
+} PAL_TEST_INFO_INFO;
+
+typedef struct {
+  UINT64  TestControl:47;       ///< This is an ordered implementation-specific
+                                ///<   control word that allows the user control
+                                ///<   over the length and runtime of the
+                                ///<   processor self-tests. This control word is
+                                ///<   ordered from the longest running tests up
+                                ///<   to the shortest running tests with bit 0
+                                ///<   controlling the longest running test. PAL
+                                ///<   may not implement all 47-bits of the
+                                ///<   test_control word. PAL communicates if a
+                                ///<   bit provides control by placing a zero in
+                                ///<   that bit. If a bit provides no control,
+                                ///<   PAL will place a one in it. PAL will have
+                                ///<   two sets of test_control bits for the two
+                                ///<   phases of the processor self-test. PAL
+                                ///<   provides information about implemented
+                                ///<   test_control bits at the hand-off from PAL
+                                ///<   to SAL for the firmware recovery check.
+                                ///<   These test_control bits provide control
+                                ///<   for phase one of processor self-test. It
+                                ///<   also provides this information via the PAL
+                                ///<   procedure call PAL_TEST_INFO for both the
+                                ///<   phase one and phase two processor tests
+                                ///<   depending on which information the caller
+                                ///<   is requesting. PAL interprets these bits
+                                ///<   as input parameters on two occasions. The
+                                ///<   first time is when SAL passes control back
+                                ///<   to PAL after the firmware recovery check.
+                                ///<   The second time is when a call to
+                                ///<   PAL_TEST_PROC is made. When PAL interprets
+                                ///<   these bits it will only interpret
+                                ///<   implemented test_control bits and will
+                                ///<   ignore the values located in the
+                                ///<   unimplemented test_control bits. PAL
+                                ///<   interprets the implemented bits such that
+                                ///<   if a bit contains a zero, this indicates
+                                ///<   to run the test. If a bit contains a one,
+                                ///<   this indicates to PAL to skip the test. If
+                                ///<   the cs bit indicates that control is not
+                                ///<    available, the test_control bits will be
+                                ///<   ignored or generate an illegal argument in
+                                ///<   procedure calls if the caller sets these
+                                ///<   bits.
+                                
+  UINT64  ControlSupport:1;     ///< This bit defines if an implementation
+                                ///<  supports control of the PAL self-tests
+                                ///<  via the self-test control word. If
+                                ///<  this bit is 0, the implementation does
+                                ///<  not support control of the processor
+                                ///<  self-tests via the self-test control
+                                ///<  word. If this bit is 1, the
+                                ///<  implementation does support control of
+                                ///<  the processor self-tests via the
+                                ///<  self-test control word. If control is
+                                ///<  not supported, GR37 will be ignored at
+                                ///<  the hand-off between SAL and PAL after
+                                ///<  the firmware recovery check and the
+                                ///<  PAL procedures related to the
+                                ///<  processor self-tests may return
+                                ///<  illegal arguments if a user tries to
+                                ///<  use the self-test control features.
+  UINT64  Reserved:16;
+} PAL_SELF_TEST_CONTROL;
+
+typedef struct {
+  UINT64  Attributes:8;         ///< Specifies the memory attributes that are
+                                ///<  allowed to be used with the memory buffer
+                                ///<  passed to this procedure. The attributes
+                                ///<  parameter is a vector where each bit
+                                ///<  represents one of the virtual memory
+                                ///<  attributes defined by the architecture.See
+                                ///<  MEMORY_AATRIBUTES. The caller is required
+                                ///<  to support the cacheable attribute for the
+                                ///<  memory buffer, otherwise an invalid
+                                ///<  argument will be returned.
+  UINT64  Reserved:8;
+  UINT64  TestControl:48;       ///< Is the self-test control word
+                                ///<  corresponding to the test_phase passed.
+                                ///<  This test_control directs the coverage and
+                                ///<  runtime of the processor self-tests
+                                ///<  specified by the test_phase input
+                                ///<  argument. Information on if this
+                                ///<  feature is implemented and the number of
+                                ///<  bits supported can be obtained by the
+                                ///<  PAL_TEST_INFO procedure call. If this
+                                ///<  feature is implemented by the processor,
+                                ///<  the caller can selectively skip parts of
+                                ///<  the processor self-test by setting
+                                ///<  test_control bits to a one. If a bit has a
+                                ///<  zero, this test will be run. The values in
+                                ///<  the unimplemented bits are ignored. If
+                                ///<  PAL_TEST_INFO indicated that the self-test
+                                ///<  control word is not implemented, this
+                                ///<  procedure will return with an invalid
+                                ///<  argument status if the caller sets any of
+                                ///<  the test_control bits. See
+                                ///<  PAL_SELF_TEST_CONTROL.
+} PAL_TEST_CONTROL;
+
+/**
+  PAL Procedure - PAL_TEST_PROC.
+
+  Perform late processor self test. It is required by Itanium processors. The
+  PAL procedure supports the Static Registers calling
+  convention. It could be called at physical mode.
+
+  @param Index        Index of PAL_TEST_PROC within the list of PAL
+                      procedures.
+  @param TestAddress  64-bit physical address of main memory
+                      area to be used by processor self-test.
+                      The memory region passed must be
+                      cacheable, bit 63 must be zero.
+  @param TestInfo     Input argument specifying the size of the
+                      memory buffer passed and the phase of the
+                      processor self-test that should be run. See
+                      PAL_TEST_INFO.
+  @param TestParam    Input argument specifying the self-test
+                      control word and the allowable memory
+                      attributes that can be used with the memory
+                      buffer. See PAL_TEST_CONTROL.
+
+  @retval 1           Call completed without error, but hardware
+                      failures occurred during self-test.
+  @retval 0           Call completed without error
+  @retval -2          Invalid argument
+  @retval -3          Call completed with error.
+
+  @return R9          Formatted 8-byte value denoting the state of the
+                      processor after self-test
+
+**/
+#define PAL_TEST_PROC 258
+
+typedef struct {
+  UINT32  NumberOfInterruptControllers;     ///< Number of interrupt
+                                            ///< controllers currently
+                                            ///< enabled on the system.
+
+  UINT32  NumberOfProcessors;               ///< Number of processors currently
+                                            ///< enabled on the system.
+} PAL_PLATFORM_INFO;
+
+/**
+  PAL Procedure - PAL_COPY_INFO.
+
+  Return information needed to relocate PAL procedures and PAL
+  PMI code to memory. It is required by Itanium processors. The PAL procedure
+  supports the Static Registers calling convention. It could be
+  called at physical mode.
+
+  @param Index              Index of PAL_COPY_INFO within the list of PAL
+                            procedures.
+  @param CopyType           Unsigned integer denoting type of procedures
+                            for which copy information is requested.
+  @param PlatformInfo       8-byte formatted value describing the
+                            number of processors and the number of
+                            interrupt controllers currently enabled
+                            on the system. See PAL_PLATFORM_INFO.
+  @param McaProcStateInfo   Unsigned integer denoting the number
+                            of bytes that SAL needs for the
+                            min-state save area for each
+                            processor.
+
+  @retval 0                 Call completed without error
+  @retval -2                Invalid argument
+  @retval -3                Call completed with error.
+
+  @return R9                Unsigned integer denoting the number of bytes of
+                            PAL information that must be copied to main
+                            memory.
+  @return R10               Unsigned integer denoting the starting alignment
+                            of the data to be copied.
+
+**/
+#define PAL_COPY_INFO 30
+
+/**
+  PAL Procedure - PAL_COPY_PAL.
+
+  Relocate PAL procedures and PAL PMI code to memory. It is
+  required by Itanium processors. The PAL procedure supports the Stacked
+  Registers calling convention. It could be called at physical
+  mode.
+
+  @param Index          Index of PAL_COPY_PAL within the list of PAL
+                        procedures.
+  @param TargetAddress  Physical address of a memory buffer to
+                        copy relocatable PAL procedures and PAL
+                        PMI code.
+  @param AllocSize      Unsigned integer denoting the size of the
+                        buffer passed by SAL for the copy operation.
+  @param CopyOption     Unsigned integer indicating whether
+                        relocatable PAL code and PAL PMI code
+                        should be copied from firmware address
+                        space to main memory.
+
+  @retval 0             Call completed without error
+  @retval -2            Invalid argument
+  @retval -3            Call completed with error.
+
+  @return R9            Unsigned integer denoting the offset of PAL_PROC
+                        in the relocatable segment copied.
+
+**/
+#define PAL_COPY_PAL 256
+
+/**
+  PAL Procedure - PAL_ENTER_IA_32_ENV.
+
+  Enter IA-32 System environment. It is optional. The PAL
+  procedure supports the Static Registers calling convention.
+  It could be called at physical mode.
+
+  Note: Since this is a special call, it does not follow the PAL
+  static register calling convention. GR28 contains the index of
+  PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other
+  input arguments including GR29-GR31 are setup by SAL to values
+  as required by the IA-32 operating system defined in Table
+  11-67. The registers that are designated as preserved, scratch,
+  input arguments and procedure return values by the static
+  procedure calling convention are not followed by this call. For
+  instance, GR5 and GR6 need not be preserved since these are
+  regarded as scratch by the IA-32 operating system. Note: In an
+  MP system, this call must be COMPLETED on the first CPU to enter
+  the IA-32 System Environment (may or may not be the BSP) prior
+  to being called on the remaining processors in the MP system.
+
+  @param Index  GR28 contains the index of the
+                PAL_ENTER_IA_32_ENV call within the list of PAL
+                procedures.
+
+
+  @retval  The status is returned in GR4.
+                  -1 - Un-implemented procedure 0 JMPE detected
+                  at privilege level
+
+                  0 - 1 SAL allocated buffer for IA-32 System
+                  Environment operation is too small
+
+                  2 - IA-32 Firmware Checksum Error
+
+                  3 -  SAL allocated buffer for IA-32 System
+                  Environment operation is not properly aligned
+
+                  4 - Error in SAL MP Info Table
+
+                  5 - Error in SAL Memory Descriptor Table
+
+                  6 - Error in SAL System Table
+
+                  7 - Inconsistent IA-32 state
+
+                  8 - IA-32 Firmware Internal Error
+
+                  9 - IA-32 Soft Reset (Note: remaining register
+                  state is undefined for this termination
+                  reason)
+
+                  10 - Machine Check Error
+
+                  11 - Error in SAL I/O Intercept Table
+
+                  12 - Processor exit due to other processor in
+                  MP system terminating the IA32 system
+                  environment. (Note: remaining register state
+                  is undefined for this termination reason.)
+
+                  13 - Itanium architecture-based state
+                  corruption by either SAL PMI handler or I/O
+                  Intercept callback function.
+
+
+**/
+#define PAL_ENTER_IA_32_ENV 33
+
+/**
+  PAL Procedure - PAL_PMI_ENTRYPOINT.
+
+  Register PMI memory entrypoints with processor. It is required
+  by Itanium processors. The PAL procedure supports the Stacked Registers
+  calling convention. It could be called at physical mode.
+
+  @param Index        Index of PAL_PMI_ENTRYPOINT within the list of
+                      PAL procedures.
+  @param SalPmiEntry  256-byte aligned physical address of SAL
+                      PMI entrypoint in memory.
+
+  @retval 0           Call completed without error
+  @retval -2          Invalid argument
+  @retval -3          Call completed with error.
+
+**/
+#define PAL_PMI_ENTRYPOINT 32
+
+
+/**
+
+  The ASCII brand identification string will be copied to the
+  address specified in the address input argument. The processor
+  brand identification string is defined to be a maximum of 128
+  characters long; 127 bytes will contain characters and the 128th
+  byte is defined to be NULL (0). A processor may return less than
+  the 127 ASCII characters as long as the string is null
+  terminated. The string length will be placed in the brand_info
+  return argument.
+
+**/
+#define PAL_BRAND_INFO_ID_REQUEST  0
+
+/**
+  PAL Procedure - PAL_BRAND_INFO.
+
+  Provides processor branding information. It is optional by
+  Itanium processors. The PAL procedure supports the Stacked Registers calling
+  convention. It could be called at physical and Virtual mode.
+
+  @param Index        Index of PAL_BRAND_INFO within the list of PAL
+                      procedures.
+  @param InfoRequest  Unsigned 64-bit integer specifying the
+                      information that is being requested. (See
+                      PAL_BRAND_INFO_ID_REQUEST)
+  @param Address      Unsigned 64-bit integer specifying the
+                      address of the 128-byte block to which the
+                      processor brand string shall be written.
+
+  @retval 0           Call completed without error
+  @retval -1          Unimplemented procedure
+  @retval -2          Invalid argument
+  @retval -3          Call completed with error.
+  @retval -6          Input argument is not implemented.
+
+  @return R9          Brand information returned. The format of this
+                      value is dependent on the input values passed.
+
+**/
+#define PAL_BRAND_INFO  274
+
+/**
+  PAL Procedure - PAL_GET_HW_POLICY.
+
+  Returns the current hardware resource sharing policy of the
+  processor. It is optional by Itanium processors. The PAL procedure supports
+  the Static Registers calling convention. It could be called at
+  physical and Virtual mode.
+
+
+  @param Index            Index of PAL_GET_HW_POLICY within the list of PAL
+                          procedures.
+  @param ProcessorNumber  Unsigned 64-bit integer that specifies
+                          for which logical processor
+                          information is being requested. This
+                          input argument must be zero for the
+                          first call to this procedure and can
+                          be a maximum value of one less than
+                          the number of logical processors
+                          impacted by the hardware resource
+                          sharing policy, which is returned by
+                          the R10 return value.
+
+  @retval 0               Call completed without error
+  @retval -1              Unimplemented procedure
+  @retval -2              Invalid argument
+  @retval -3              Call completed with error.
+  @retval -9              Call requires PAL memory buffer.
+
+  @return R9              Unsigned 64-bit integer representing the current
+                          hardware resource sharing policy.
+  @return R10             Unsigned 64-bit integer that returns the number
+                          of logical processors impacted by the policy
+                          input argument.
+  @return R11             Unsigned 64-bit integer containing the logical
+                          address of one of the logical processors
+                          impacted by policy modification.
+
+**/
+#define PAL_GET_HW_POLICY   48
+
+
+//
+// Value of PAL_SET_HW_POLICY.Policy
+//
+#define PAL_SET_HW_POLICY_PERFORMANCE               0
+#define PAL_SET_HW_POLICY_FAIRNESS                  1
+#define PAL_SET_HW_POLICY_HIGH_PRIORITY             2
+#define PAL_SET_HW_POLICY_EXCLUSIVE_HIGH_PRIORITY   3
+
+/**
+  PAL Procedure - PAL_SET_HW_POLICY.
+
+  Sets the current hardware resource sharing policy of the
+  processor. It is optional by Itanium processors. The PAL procedure supports
+  the Static Registers calling convention. It could be called at
+  physical and Virtual mode.
+
+  @param Index    Index of PAL_SET_HW_POLICY within the list of PAL
+                  procedures.
+  @param Policy   Unsigned 64-bit integer specifying the hardware
+                  resource sharing policy the caller is setting.
+                  See Value of PAL_SET_HW_POLICY.Policy above.
+
+  @retval 1       Call completed successfully but could not
+                  change the hardware policy since a
+                  competing logical processor is set in
+                  exclusive high priority.
+  @retval 0       Call completed without error
+  @retval -1      Unimplemented procedure
+  @retval -2      Invalid argument
+  @retval -3      Call completed with error.
+  @retval -9      Call requires PAL memory buffer.
+
+**/
+#define PAL_SET_HW_POLICY   49
+
+typedef struct {
+  UINT64  Mode:3;                   ///< Bit2:0, Indicates the mode of operation for this
+                                    ///<    procedure: 0 - Query mode 1 - Error inject mode
+                                    ///<    (err_inj should also be specified) 2 - Cancel
+                                    ///<    outstanding trigger. All other fields in
+                                    ///<    PAL_MC_ERROR_TYPE_INFO,
+                                    ///<    PAL_MC_ERROR_STRUCTURE_INFO and
+                                    ///<    PAL_MC_ERROR_DATA_BUFFER are ignored. All other
+                                    ///<    values are reserved.
+
+  UINT64  ErrorInjection:3;         ///< Bit5:3, indicates the mode of error
+                                    ///<  injection: 0 - Error inject only (no
+                                    ///<  error consumption) 1 - Error inject
+                                    ///<  and consume All other values are
+                                    ///<  reserved.
+
+  UINT64  ErrorSeverity:2;          ///< Bit7:6, indicates the severity desired
+                                    ///<  for error injection/query. Definitions
+                                    ///<  of the different error severity types
+                                    ///<  0 - Corrected error 1 - Recoverable
+                                    ///<  error 2 - Fatal error 3 - Reserved
+
+  UINT64  ErrorStructure:5;         ///< Bit12:8, Indicates the structure
+                                    ///<  identification for error
+                                    ///<  injection/query: 0 - Any structure
+                                    ///<  (cannot be used during query mode).
+                                    ///<  When selected, the structure type used
+                                    ///<  for error injection is determined by
+                                    ///<  PAL. 1 - Cache 2 - TLB 3 - Register
+                                    ///<  file 4 - Bus/System interconnect 5-15
+                                    ///<  - Reserved 16-31 - Processor
+                                    ///<  specific error injection
+                                    ///<  capabilities.ErrorDataBuffer is used
+                                    ///<  to specify error types. Please refer
+                                    ///<  to the processor specific
+                                    ///<  documentation for additional details.
+
+  UINT64  StructureHierarchy:3;     ///< Bit15:13, Indicates the structure
+                                    ///<  hierarchy for error
+                                    ///<  injection/query: 0 - Any level of
+                                    ///<  hierarchy (cannot be used during
+                                    ///<  query mode). When selected, the
+                                    ///<  structure hierarchy used for error
+                                    ///<  injection is determined by PAL. 1
+                                    ///<  - Error structure hierarchy
+                                    ///<  level-1 2 - Error structure
+                                    ///<  hierarchy level-2 3 - Error
+                                    ///<  structure hierarchy level-3 4 -
+                                    ///<  Error structure hierarchy level-4
+                                    ///<  All other values are reserved.
+
+  UINT64  Reserved:32;              ///< Reserved 47:16 Reserved
+
+  UINT64  ImplSpec:16;              ///< Bit63:48, Processor specific error injection capabilities.
+} PAL_MC_ERROR_TYPE_INFO;
+
+typedef struct {
+  UINT64  StructInfoIsValid:1;              ///< Bit0 When 1, indicates that the
+                                            ///< structure information fields
+                                            ///< (c_t,cl_p,cl_id) are valid and
+                                            ///< should be used for error injection.
+                                            ///< When 0, the structure information
+                                            ///< fields are ignored, and the values
+                                            ///< of these fields used for error
+                                            ///< injection are
+                                            ///< implementation-specific.
+
+  UINT64  CacheType:2;                      ///< Bit2:1  Indicates which cache should be used
+                                            ///< for error injection: 0 - Reserved 1 -
+                                            ///< Instruction cache 2 - Data or unified cache
+                                            ///< 3 - Reserved
+
+  UINT64  PortionOfCacheLine:3;             ///< Bit5:3 Indicates the portion of the
+                                            ///<   cache line where the error should
+                                            ///<   be injected: 0 - Reserved 1 - Tag
+                                            ///<   2 - Data 3 - mesi All other
+                                            ///<   values are reserved.
+
+  UINT64  Mechanism:3;                      ///< Bit8:6 Indicates which mechanism is used to
+                                            ///< identify the cache line to be used for error
+                                            ///< injection: 0 - Reserved 1 - Virtual address
+                                            ///< provided in the inj_addr field of the buffer
+                                            ///< pointed to by err_data_buffer should be used
+                                            ///< to identify the cache line for error
+                                            ///< injection. 2 - Physical address provided in
+                                            ///< the inj_addr field of the buffer pointed to
+                                            ///< by err_data_buffershould be used to identify
+                                            ///< the cache line for error injection. 3 - way
+                                            ///< and index fields provided in err_data_buffer
+                                            ///< should be used to identify the cache line
+                                            ///< for error injection. All other values are
+                                            ///< reserved.
+
+  UINT64  DataPoisonOfCacheLine:1;          ///< Bit9 When 1, indicates that a
+                                            ///< multiple bit, non-correctable
+                                            ///< error should be injected in the
+                                            ///< cache line specified by cl_id.
+                                            ///< If this injected error is not
+                                            ///< consumed, it may eventually
+                                            ///< cause a data-poisoning event
+                                            ///< resulting in a corrected error
+                                            ///< signal, when the associated
+                                            ///< cache line is cast out (implicit
+                                            ///< or explicit write-back of the
+                                            ///< cache line). The error severity
+                                            ///< specified by err_sev in
+                                            ///< err_type_info must be set to 0
+                                            ///< (corrected error) when this bit
+                                            ///< is set.
+
+  UINT64  Reserved1:22;
+
+  UINT64  TrigerInfoIsValid:1;              ///< Bit32 When 1, indicates that the
+                                            ///< trigger information fields (trigger,
+                                            ///< trigger_pl) are valid and should be
+                                            ///< used for error injection. When 0,
+                                            ///< the trigger information fields are
+                                            ///< ignored and error injection is
+                                            ///< performed immediately.
+
+  UINT64  Triger:4;                         ///< Bit36:33 Indicates the operation type to be
+                                            ///<   used as the error trigger condition. The
+                                            ///<   address corresponding to the trigger is
+                                            ///<   specified in the trigger_addr field of the
+                                            ///<   buffer pointed to by err_data_buffer: 0 -
+                                            ///<   Instruction memory access. The trigger match
+                                            ///<   conditions for this operation type are similar
+                                            ///<   to the IBR address breakpoint match conditions
+                                            ///<   1 - Data memory access. The trigger match
+                                            ///<   conditions for this operation type are similar
+                                            ///<   to the DBR address breakpoint match conditions
+                                            ///<   All other values are reserved.
+
+  UINT64  PrivilegeOfTriger:3;              ///< Bit39:37  Indicates the privilege
+                                            ///< level of the context during which
+                                            ///< the error should be injected: 0 -
+                                            ///< privilege level 0 1 - privilege
+                                            ///< level 1 2 - privilege level 2 3 -
+                                            ///< privilege level 3 All other values
+                                            ///< are reserved. If the implementation
+                                            ///< does not support privilege level
+                                            ///< qualifier for triggers (i.e. if
+                                            ///< trigger_pl is 0 in the capabilities
+                                            ///< vector), this field is ignored and
+                                            ///< triggers can be taken at any
+                                            ///< privilege level.
+
+  UINT64  Reserved2:24;
+} PAL_MC_ERROR_STRUCT_INFO;
+
+/**
+
+   Buffer Pointed to by err_data_buffer - TLB
+
+**/
+typedef struct {
+  UINT64  TrigerAddress;
+  UINT64  VirtualPageNumber:52;
+  UINT64  Reserved1:8;
+  UINT64  RegionId:24;
+  UINT64  Reserved2:40;
+} PAL_MC_ERROR_DATA_BUFFER_TLB;
+
+/**
+  PAL Procedure - PAL_MC_ERROR_INJECT.
+
+  Injects the requested processor error or returns information
+  on the supported injection capabilities for this particular
+  processor implementation. It is optional by Itanium processors. The PAL
+  procedure supports the Stacked Registers calling convention.
+  It could be called at physical and Virtual mode.
+
+  @param Index            Index of PAL_MC_ERROR_INJECT within the list of PAL
+                          procedures.
+  @param ErrorTypeInfo    Unsigned 64-bit integer specifying the
+                          first level error information which
+                          identifies the error structure and
+                          corresponding structure hierarchy, and
+                          the error severity.
+  @param ErrorStructInfo  Unsigned 64-bit integer identifying
+                          the optional structure specific
+                          information that provides the  second
+                          level details for the requested error.
+  @param ErrorDataBuffer  64-bit physical address of a buffer
+                          providing additional parameters for
+                          the requested error. The address of
+                          this buffer must be 8-byte aligned.
+
+  @retval 0               Call completed without error
+  @retval -1              Unimplemented procedure
+  @retval -2              Invalid argument
+  @retval -3              Call completed with error.
+  @retval -4              Call completed with error; the requested
+                          error could not be injected due to failure in
+                          locating the target location in the specified
+                          structure.
+  @retval -5              Argument was valid, but requested error
+                          injection capability is not supported.
+  @retval -9              Call requires PAL memory buffer.
+
+  @return R9              64-bit vector specifying the supported error
+                          injection capabilities for the input argument
+                          combination of struct_hier, err_struct and
+                          err_sev fields in ErrorTypeInfo.
+  @return R10             64-bit vector specifying the architectural
+                          resources that are used by the procedure.
+
+**/
+#define PAL_MC_ERROR_INJECT 276
+
+
+//
+// Types of PAL_GET_PSTATE.Type
+//
+#define PAL_GET_PSTATE_RECENT                 0
+#define PAL_GET_PSTATE_AVERAGE_NEW_START      1
+#define PAL_GET_PSTATE_AVERAGE                2
+#define PAL_GET_PSTATE_NOW                    3
+
+/**
+  PAL Procedure - PAL_GET_PSTATE.
+
+  Returns the performance index of the processor. It is optional
+  by Itanium processors. The PAL procedure supports the Stacked Registers
+  calling convention. It could be called at physical and Virtual
+  mode.
+
+  @param Index  Index of PAL_GET_PSTATE within the list of PAL
+                procedures.
+  @param Type   Type of performance_index value to be returned
+                by this procedure.See PAL_GET_PSTATE.Type above.
+
+  @retval 1     Call completed without error, but accuracy
+                of performance index has been impacted by a
+                thermal throttling event, or a
+                hardware-initiated event.
+  @retval 0     Call completed without error
+  @retval -1    Unimplemented procedure
+  @retval -2    Invalid argument
+  @retval -3    Call completed with error.
+  @retval -9    Call requires PAL memory buffer.
+
+  @return R9    Unsigned integer denoting the processor
+                performance for the time duration since the last
+                PAL_GET_PSTATE procedure call was made. The
+                value returned is between 0 and 100, and is
+                relative to the performance index of the highest
+                available P-state.
+
+**/
+#define PAL_GET_PSTATE      262
+
+/**
+
+  Layout of PAL_PSTATE_INFO.PStateBuffer
+
+**/
+typedef struct {
+  UINT32  PerformanceIndex:7;
+  UINT32  Reserved1:5;
+  UINT32  TypicalPowerDissipation:20;
+  UINT32  TransitionLatency1;
+  UINT32  TransitionLatency2;
+  UINT32  Reserved2;
+} PAL_PSTATE_INFO_BUFFER;
+
+
+/**
+  PAL Procedure - PAL_PSTATE_INFO.
+
+  Returns information about the P-states supported by the
+  processor. It is optional by Itanium processors. The PAL procedure supports
+  the Static Registers calling convention. It could be called
+  at physical and Virtual mode.
+
+  @param Index          Index of PAL_PSTATE_INFO within the list of PAL
+                        procedures.
+  @param PStateBuffer   64-bit pointer to a 256-byte buffer
+                        aligned on an 8-byte boundary. See
+                        PAL_PSTATE_INFO_BUFFER above.
+
+  @retval 0             Call completed without error
+  @retval -1            Unimplemented procedure
+  @retval -2            Invalid argument
+  @retval -3            Call completed with error.
+
+  @return R9            Unsigned integer denoting the number of P-states
+                        supported. The maximum value of this field is 16.
+  @return R10           Dependency domain information
+
+**/
+#define PAL_PSTATE_INFO     44
+
+
+/**
+  PAL Procedure - PAL_SET_PSTATE.
+
+  To request a processor transition to a given P-state. It is
+  optional by Itanium processors. The PAL procedure supports the Stacked
+  Registers calling convention. It could be called at physical
+  and Virtual mode.
+
+  @param Index        Index of PAL_SET_PSTATE within the list of PAL
+                      procedures.
+  @param PState       Unsigned integer denoting the processor
+                      P-state being requested.
+  @param ForcePState  Unsigned integer denoting whether the
+                      P-state change should be forced for the
+                      logical processor.
+
+  @retval 1           Call completed without error, but
+                      transition request was not accepted
+  @retval 0           Call completed without error
+  @retval -1          Unimplemented procedure
+  @retval -2          Invalid argument
+  @retval -3          Call completed with error.
+  @retval -9          Call requires PAL memory buffer.
+
+**/
+#define PAL_SET_PSTATE      263
+
+/**
+  PAL Procedure - PAL_SHUTDOWN.
+
+  Put the logical processor into a low power state which can be
+  exited only by a reset event. It is optional by Itanium processors. The PAL
+  procedure supports the Static Registers calling convention. It
+  could be called at physical mode.
+
+  @param Index            Index of PAL_SHUTDOWN within the list of PAL
+                          procedures.
+  @param NotifyPlatform   8-byte aligned physical address
+                          pointer providing details on how to
+                          optionally notify the platform that
+                          the processor is entering a shutdown
+                          state.
+
+  @retval -1              Unimplemented procedure
+  @retval -2              Invalid argument
+  @retval -3              Call completed with error.
+  @retval -9              Call requires PAL memory buffer.
+
+**/
+#define PAL_SHUTDOWN        45
+
+/**
+
+  Layout of PAL_MEMORY_BUFFER.ControlWord
+
+**/
+typedef struct {
+  UINT64  Registration:1;
+  UINT64  ProbeInterrupt:1;
+  UINT64  Reserved:62;
+} PAL_MEMORY_CONTROL_WORD;
+
+/**
+  PAL Procedure - PAL_MEMORY_BUFFER.
+
+  Provides cacheable memory to PAL for exclusive use during
+  runtime. It is optional by Itanium processors. The PAL procedure supports the
+  Static Registers calling convention. It could be called at
+  physical mode.
+
+  @param Index        Index of PAL_MEMORY_BUFFER within the list of PAL
+                      procedures.
+  @param BaseAddress  Physical address of the memory buffer
+                      allocated for PAL use.
+  @param AllocSize    Unsigned integer denoting the size of the
+                      memory buffer.
+  @param ControlWord  Formatted bit vector that provides control
+                      options for this procedure. See
+                      PAL_MEMORY_CONTROL_WORD above.
+
+  @retval 1           Call has not completed a buffer relocation
+                      due to a pending interrupt
+  @retval 0           Call completed without error
+  @retval -1          Unimplemented procedure
+  @retval -2          Invalid argument
+  @retval -3          Call completed with error.
+  @retval -9          Call requires PAL memory buffer.
+
+  @return R9          Returns the minimum size of the memory buffer
+                      required if the alloc_size input argument was
+                      not large enough.
+
+**/
+#define PAL_MEMORY_BUFFER   277
+
+
+/**
+  PAL Procedure - PAL_VP_CREATE.
+
+  Initializes a new vpd for the operation of a new virtual
+  processor in the virtual environment. It is optional by Itanium processors.
+  The PAL procedure supports the Stacked Registers calling
+  convention. It could be called at Virtual mode.
+
+  @param Index            Index of PAL_VP_CREATE within the list of PAL
+                          procedures.
+  @param Vpd              64-bit host virtual pointer to the Virtual
+                          Processor Descriptor (VPD).
+  @param HostIva          64-bit host virtual pointer to the host IVT
+                          for the virtual processor
+  @param OptionalHandler  64-bit non-zero host-virtual pointer
+                          to an optional handler for
+                          virtualization intercepts.
+
+  @retval 0               Call completed without error
+  @retval -1              Unimplemented procedure
+  @retval -2              Invalid argument
+  @retval -3              Call completed with error.
+  @retval -9              Call requires PAL memory buffer.
+
+**/
+#define PAL_VP_CREATE       265
+
+/**
+
+  Virtual Environment Information Parameter
+
+**/
+typedef struct {
+  UINT64    Reserved1:8;
+  UINT64    Opcode:1;
+  UINT64    Reserved:53;
+} PAL_VP_ENV_INFO_RETURN;
+
+/**
+  PAL Procedure - PAL_VP_ENV_INFO.
+
+  Returns the parameters needed to enter a virtual environment.
+  It is optional by Itanium processors. The PAL procedure supports the Stacked
+  Registers calling convention. It could be called at Virtual
+  mode.
+
+  @param Index            Index of PAL_VP_ENV_INFO within the list of PAL
+                          procedures.
+  @param Vpd              64-bit host virtual pointer to the Virtual
+                          Processor Descriptor (VPD).
+  @param HostIva          64-bit host virtual pointer to the host IVT
+                          for the virtual processor
+  @param OptionalHandler  64-bit non-zero host-virtual pointer
+                          to an optional handler for
+                          virtualization intercepts.
+
+  @retval 0               Call completed without error
+  @retval -1              Unimplemented procedure
+  @retval -2              Invalid argument
+  @retval -3              Call completed with error.
+  @retval -9              Call requires PAL memory buffer.
+
+  @return R9              Unsigned integer denoting the number of bytes
+                          required by the PAL virtual environment buffer
+                          during PAL_VP_INIT_ENV
+  @return R10             64-bit vector of virtual environment
+                          information. See PAL_VP_ENV_INFO_RETURN.
+
+
+**/
+#define PAL_VP_ENV_INFO       266
+
+/**
+  PAL Procedure - PAL_VP_EXIT_ENV.
+
+  Allows a logical processor to exit a virtual environment.
+  It is optional by Itanium processors. The PAL procedure supports the Stacked
+  Registers calling convention. It could be called at Virtual
+  mode.
+
+  @param Index  Index of PAL_VP_EXIT_ENV within the list of PAL
+                procedures.
+  @param Iva    Optional 64-bit host virtual pointer to the IVT
+                when this procedure is done
+
+  @retval 0     Call completed without error
+  @retval -1    Unimplemented procedure
+  @retval -2    Invalid argument
+  @retval -3    Call completed with error.
+  @retval -9    Call requires PAL memory buffer.
+
+**/
+#define PAL_VP_EXIT_ENV       267
+
+
+
+/**
+  PAL Procedure - PAL_VP_INIT_ENV.
+
+  Allows a logical processor to enter a virtual environment. It
+  is optional by Itanium processors. The PAL procedure supports the Stacked
+  Registers calling convention. It could be called at Virtual
+  mode.
+
+  @param Index          Index of PAL_VP_INIT_ENV within the list of PAL
+                        procedures.
+  @param ConfigOptions  64-bit vector of global configuration
+                        settings.
+  @param PhysicalBase   Host physical base address of a block of
+                        contiguous physical memory for the PAL
+                        virtual environment buffer 1) This
+                        memory area must be allocated by the VMM
+                        and be 4K aligned. The first logical
+                        processor to enter the environment will
+                        initialize the physical block for
+                        virtualization operations.
+  @param VirtualBase    Host virtual base address of the
+                        corresponding physical memory block for
+                        the PAL virtual environment buffer : The
+                        VMM must maintain the host virtual to host
+                        physical data and instruction translations
+                        in TRs for addresses within the allocated
+                        address space. Logical processors in this
+                        virtual environment will use this address
+                        when transitioning to virtual mode
+                        operations.
+
+  @retval 0             Call completed without error
+  @retval -1            Unimplemented procedure
+  @retval -2            Invalid argument
+  @retval -3            Call completed with error.
+  @retval -9            Call requires PAL memory buffer.
+
+  @return R9            Virtualization Service Address - VSA specifies
+                        the virtual base address of the PAL
+                        virtualization services in this virtual
+                        environment.
+
+
+**/
+#define PAL_VP_INIT_ENV       268
+
+
+/**
+  PAL Procedure - PAL_VP_REGISTER.
+
+  Register a different host IVT and/or a different optional
+  virtualization intercept handler for the virtual processor
+  specified by vpd. It is optional by Itanium processors. The PAL procedure
+  supports the Stacked Registers calling convention. It could be
+  called at Virtual mode.
+
+  @param Index            Index of PAL_VP_REGISTER within the list of PAL
+                          procedures.
+  @param Vpd              64-bit host virtual pointer to the Virtual
+                          Processor Descriptor (VPD) host_iva 64-bit host
+                          virtual pointer to the host IVT for the virtual
+                          processor
+  @param OptionalHandler  64-bit non-zero host-virtual pointer
+                          to an optional handler for
+                          virtualization intercepts.
+
+  @retval 0               Call completed without error
+  @retval -1              Unimplemented procedure
+  @retval -2              Invalid argument
+  @retval -3              Call completed with error.
+  @retval -9              Call requires PAL memory buffer.
+
+**/
+#define PAL_VP_REGISTER       269
+
+
+/**
+  PAL Procedure - PAL_VP_RESTORE.
+
+  Restores virtual processor state for the specified vpd on the
+  logical processor. It is optional by Itanium processors. The PAL procedure
+  supports the Stacked Registers calling convention. It could be
+  called at Virtual mode.
+
+  @param Index      Index of PAL_VP_RESTORE within the list of PAL
+                    procedures.
+  @param Vpd        64-bit host virtual pointer to the Virtual
+                    Processor Descriptor (VPD) host_iva 64-bit host
+                    virtual pointer to the host IVT for the virtual
+                    processor
+  @param PalVector  Vector specifies PAL procedure
+                    implementation-specific state to be
+                    restored.
+
+  @retval 0         Call completed without error
+  @retval -1        Unimplemented procedure
+  @retval -2        Invalid argument
+  @retval -3        Call completed with error.
+  @retval -9        Call requires PAL memory buffer.
+
+**/
+#define PAL_VP_RESTORE       270
+
+/**
+  PAL Procedure - PAL_VP_SAVE.
+
+  Saves virtual processor state for the specified vpd on the
+  logical processor. It is optional by Itanium processors. The PAL procedure
+  supports the Stacked Registers calling convention. It could be
+  called at Virtual mode.
+
+  @param Index      Index of PAL_VP_SAVE within the list of PAL
+                    procedures.
+  @param Vpd        64-bit host virtual pointer to the Virtual
+                    Processor Descriptor (VPD) host_iva 64-bit host
+                    virtual pointer to the host IVT for the virtual
+                    processor
+  @param PalVector  Vector specifies PAL procedure
+                    implementation-specific state to be
+                    restored.
+
+  @retval 0         Call completed without error
+  @retval -1        Unimplemented procedure
+  @retval -2        Invalid argument
+  @retval -3        Call completed with error.
+  @retval -9        Call requires PAL memory buffer.
+
+**/
+#define PAL_VP_SAVE       271
+
+
+/**
+  PAL Procedure - PAL_VP_TERMINATE.
+
+  Terminates operation for the specified virtual processor. It
+  is optional by Itanium processors. The PAL procedure supports the Stacked
+  Registers calling convention. It could be called at Virtual
+  mode.
+
+  @param Index  Index of PAL_VP_TERMINATE within the list of PAL
+                procedures.
+  @param Vpd    64-bit host virtual pointer to the Virtual
+                Processor Descriptor (VPD)
+  @param Iva    Optional 64-bit host virtual pointer to the IVT
+                when this procedure is done.
+
+  @retval 0     Call completed without error
+  @retval -1    Unimplemented procedure
+  @retval -2    Invalid argument
+  @retval -3    Call completed with error.
+  @retval -9    Call requires PAL memory buffer.
+
+**/
+#define PAL_VP_TERMINATE       272
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci.h
new file mode 100644
index 0000000000..e5954dbce7
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci.h
@@ -0,0 +1,23 @@
+/** @file
+  Support for the latest PCI standard.
+
+Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under 
+the terms and conditions of the BSD License that accompanies this distribution.  
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.                                          
+    
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.                                            
+
+**/
+
+#ifndef _PCI_H_
+#define _PCI_H_
+
+#include <IndustryStandard/Pci30.h>
+#include <IndustryStandard/PciExpress21.h>
+#include <IndustryStandard/PciExpress30.h>
+#include <IndustryStandard/PciCodeId.h>
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci22.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci22.h
new file mode 100644
index 0000000000..65ab051b46
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci22.h
@@ -0,0 +1,867 @@
+/** @file
+  Support for PCI 2.2 standard.
+
+  This file includes the definitions in the following specifications,
+    PCI Local Bus Specification, 2.2
+    PCI-to-PCI Bridge Architecture Specification, Revision 1.2
+    PC Card Standard, 8.0
+    PCI Power Management Interface Specifiction, Revision 1.2
+
+  Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+**/
+
+#ifndef _PCI22_H_
+#define _PCI22_H_
+
+#define PCI_MAX_BUS     255
+#define PCI_MAX_DEVICE  31
+#define PCI_MAX_FUNC    7
+
+#pragma pack(1)
+
+///
+/// Common header region in PCI Configuration Space
+/// Section 6.1, PCI Local Bus Specification, 2.2
+///
+typedef struct {
+  UINT16  VendorId;
+  UINT16  DeviceId;
+  UINT16  Command;
+  UINT16  Status;
+  UINT8   RevisionID;
+  UINT8   ClassCode[3];
+  UINT8   CacheLineSize;
+  UINT8   LatencyTimer;
+  UINT8   HeaderType;
+  UINT8   BIST;
+} PCI_DEVICE_INDEPENDENT_REGION;
+
+///
+/// PCI Device header region in PCI Configuration Space
+/// Section 6.1, PCI Local Bus Specification, 2.2
+///
+typedef struct {
+  UINT32  Bar[6];
+  UINT32  CISPtr;
+  UINT16  SubsystemVendorID;
+  UINT16  SubsystemID;
+  UINT32  ExpansionRomBar;
+  UINT8   CapabilityPtr;
+  UINT8   Reserved1[3];
+  UINT32  Reserved2;
+  UINT8   InterruptLine;
+  UINT8   InterruptPin;
+  UINT8   MinGnt;
+  UINT8   MaxLat;
+} PCI_DEVICE_HEADER_TYPE_REGION;
+
+///
+/// PCI Device Configuration Space
+/// Section 6.1, PCI Local Bus Specification, 2.2
+///
+typedef struct {
+  PCI_DEVICE_INDEPENDENT_REGION Hdr;
+  PCI_DEVICE_HEADER_TYPE_REGION Device;
+} PCI_TYPE00;
+
+///
+/// PCI-PCI Bridge header region in PCI Configuration Space
+/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
+///
+typedef struct {
+  UINT32  Bar[2];
+  UINT8   PrimaryBus;
+  UINT8   SecondaryBus;
+  UINT8   SubordinateBus;
+  UINT8   SecondaryLatencyTimer;
+  UINT8   IoBase;
+  UINT8   IoLimit;
+  UINT16  SecondaryStatus;
+  UINT16  MemoryBase;
+  UINT16  MemoryLimit;
+  UINT16  PrefetchableMemoryBase;
+  UINT16  PrefetchableMemoryLimit;
+  UINT32  PrefetchableBaseUpper32;
+  UINT32  PrefetchableLimitUpper32;
+  UINT16  IoBaseUpper16;
+  UINT16  IoLimitUpper16;
+  UINT8   CapabilityPtr;
+  UINT8   Reserved[3];
+  UINT32  ExpansionRomBAR;
+  UINT8   InterruptLine;
+  UINT8   InterruptPin;
+  UINT16  BridgeControl;
+} PCI_BRIDGE_CONTROL_REGISTER;
+
+///
+/// PCI-to-PCI Bridge Configuration Space
+/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
+///
+typedef struct {
+  PCI_DEVICE_INDEPENDENT_REGION Hdr;
+  PCI_BRIDGE_CONTROL_REGISTER   Bridge;
+} PCI_TYPE01;
+
+typedef union {
+  PCI_TYPE00  Device;
+  PCI_TYPE01  Bridge;
+} PCI_TYPE_GENERIC;
+
+/// 
+/// CardBus Conroller Configuration Space, 
+/// Section 4.5.1, PC Card Standard. 8.0
+///
+typedef struct {
+  UINT32  CardBusSocketReg;     ///< Cardus Socket/ExCA Base
+  UINT8   Cap_Ptr;
+  UINT8   Reserved;
+  UINT16  SecondaryStatus;      ///< Secondary Status
+  UINT8   PciBusNumber;         ///< PCI Bus Number
+  UINT8   CardBusBusNumber;     ///< CardBus Bus Number
+  UINT8   SubordinateBusNumber; ///< Subordinate Bus Number
+  UINT8   CardBusLatencyTimer;  ///< CardBus Latency Timer
+  UINT32  MemoryBase0;          ///< Memory Base Register 0
+  UINT32  MemoryLimit0;         ///< Memory Limit Register 0
+  UINT32  MemoryBase1;
+  UINT32  MemoryLimit1;
+  UINT32  IoBase0;
+  UINT32  IoLimit0;             ///< I/O Base Register 0
+  UINT32  IoBase1;              ///< I/O Limit Register 0
+  UINT32  IoLimit1;
+  UINT8   InterruptLine;        ///< Interrupt Line
+  UINT8   InterruptPin;         ///< Interrupt Pin
+  UINT16  BridgeControl;        ///< Bridge Control
+} PCI_CARDBUS_CONTROL_REGISTER;
+
+//
+// Definitions of PCI class bytes and manipulation macros.
+//
+#define PCI_CLASS_OLD                 0x00
+#define   PCI_CLASS_OLD_OTHER           0x00
+#define   PCI_CLASS_OLD_VGA             0x01
+
+#define PCI_CLASS_MASS_STORAGE        0x01
+#define   PCI_CLASS_MASS_STORAGE_SCSI   0x00
+#define   PCI_CLASS_MASS_STORAGE_IDE    0x01
+#define   PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
+#define   PCI_CLASS_MASS_STORAGE_IPI    0x03
+#define   PCI_CLASS_MASS_STORAGE_RAID   0x04
+#define   PCI_CLASS_MASS_STORAGE_OTHER  0x80
+
+#define PCI_CLASS_NETWORK             0x02
+#define   PCI_CLASS_NETWORK_ETHERNET    0x00  
+#define   PCI_CLASS_NETWORK_TOKENRING   0x01
+#define   PCI_CLASS_NETWORK_FDDI        0x02
+#define   PCI_CLASS_NETWORK_ATM         0x03
+#define   PCI_CLASS_NETWORK_ISDN        0x04
+#define   PCI_CLASS_NETWORK_OTHER       0x80
+
+#define PCI_CLASS_DISPLAY             0x03
+#define   PCI_CLASS_DISPLAY_VGA         0x00
+#define     PCI_IF_VGA_VGA                0x00
+#define     PCI_IF_VGA_8514               0x01
+#define   PCI_CLASS_DISPLAY_XGA         0x01
+#define   PCI_CLASS_DISPLAY_3D          0x02
+#define   PCI_CLASS_DISPLAY_OTHER       0x80  
+
+#define PCI_CLASS_MEDIA               0x04
+#define   PCI_CLASS_MEDIA_VIDEO         0x00
+#define   PCI_CLASS_MEDIA_AUDIO         0x01
+#define   PCI_CLASS_MEDIA_TELEPHONE     0x02
+#define   PCI_CLASS_MEDIA_OTHER         0x80
+
+#define PCI_CLASS_MEMORY_CONTROLLER   0x05
+#define   PCI_CLASS_MEMORY_RAM          0x00
+#define   PCI_CLASS_MEMORY_FLASH        0x01
+#define   PCI_CLASS_MEMORY_OTHER        0x80
+
+#define PCI_CLASS_BRIDGE              0x06
+#define   PCI_CLASS_BRIDGE_HOST         0x00
+#define   PCI_CLASS_BRIDGE_ISA          0x01
+#define   PCI_CLASS_BRIDGE_EISA         0x02
+#define   PCI_CLASS_BRIDGE_MCA          0x03
+#define   PCI_CLASS_BRIDGE_P2P          0x04
+#define     PCI_IF_BRIDGE_P2P             0x00
+#define     PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01
+#define   PCI_CLASS_BRIDGE_PCMCIA       0x05
+#define   PCI_CLASS_BRIDGE_NUBUS        0x06
+#define   PCI_CLASS_BRIDGE_CARDBUS      0x07
+#define   PCI_CLASS_BRIDGE_RACEWAY      0x08
+#define   PCI_CLASS_BRIDGE_OTHER        0x80
+#define   PCI_CLASS_BRIDGE_ISA_PDECODE  0x80
+
+#define PCI_CLASS_SCC                 0x07  ///< Simple communications controllers 
+#define   PCI_SUBCLASS_SERIAL           0x00
+#define     PCI_IF_GENERIC_XT             0x00
+#define     PCI_IF_16450                  0x01
+#define     PCI_IF_16550                  0x02
+#define     PCI_IF_16650                  0x03
+#define     PCI_IF_16750                  0x04
+#define     PCI_IF_16850                  0x05
+#define     PCI_IF_16950                  0x06
+#define   PCI_SUBCLASS_PARALLEL         0x01
+#define     PCI_IF_PARALLEL_PORT          0x00
+#define     PCI_IF_BI_DIR_PARALLEL_PORT   0x01
+#define     PCI_IF_ECP_PARALLEL_PORT      0x02
+#define     PCI_IF_1284_CONTROLLER        0x03
+#define     PCI_IF_1284_DEVICE            0xFE
+#define   PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
+#define   PCI_SUBCLASS_MODEM            0x03
+#define     PCI_IF_GENERIC_MODEM          0x00
+#define     PCI_IF_16450_MODEM            0x01
+#define     PCI_IF_16550_MODEM            0x02
+#define     PCI_IF_16650_MODEM            0x03
+#define     PCI_IF_16750_MODEM            0x04
+#define   PCI_SUBCLASS_SCC_OTHER        0x80
+
+#define PCI_CLASS_SYSTEM_PERIPHERAL   0x08
+#define   PCI_SUBCLASS_PIC              0x00
+#define     PCI_IF_8259_PIC               0x00
+#define     PCI_IF_ISA_PIC                0x01
+#define     PCI_IF_EISA_PIC               0x02
+#define     PCI_IF_APIC_CONTROLLER        0x10  ///< I/O APIC interrupt controller , 32 bye none-prefectable memory.  
+#define     PCI_IF_APIC_CONTROLLER2       0x20 
+#define   PCI_SUBCLASS_DMA              0x01
+#define     PCI_IF_8237_DMA               0x00
+#define     PCI_IF_ISA_DMA                0x01
+#define     PCI_IF_EISA_DMA               0x02
+#define   PCI_SUBCLASS_TIMER            0x02
+#define     PCI_IF_8254_TIMER             0x00
+#define     PCI_IF_ISA_TIMER              0x01
+#define     PCI_IF_EISA_TIMER             0x02
+#define   PCI_SUBCLASS_RTC              0x03
+#define     PCI_IF_GENERIC_RTC            0x00
+#define     PCI_IF_ISA_RTC                0x01
+#define   PCI_SUBCLASS_PNP_CONTROLLER   0x04    ///< HotPlug Controller
+#define   PCI_SUBCLASS_PERIPHERAL_OTHER 0x80
+
+#define PCI_CLASS_INPUT_DEVICE        0x09
+#define   PCI_SUBCLASS_KEYBOARD         0x00
+#define   PCI_SUBCLASS_PEN              0x01
+#define   PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
+#define   PCI_SUBCLASS_SCAN_CONTROLLER  0x03
+#define   PCI_SUBCLASS_GAMEPORT         0x04
+#define     PCI_IF_GAMEPORT               0x00
+#define     PCI_IF_GAMEPORT1              0x10
+#define   PCI_SUBCLASS_INPUT_OTHER      0x80
+
+#define PCI_CLASS_DOCKING_STATION     0x0A
+#define   PCI_SUBCLASS_DOCKING_GENERIC  0x00
+#define   PCI_SUBCLASS_DOCKING_OTHER    0x80
+
+#define PCI_CLASS_PROCESSOR           0x0B
+#define   PCI_SUBCLASS_PROC_386         0x00
+#define   PCI_SUBCLASS_PROC_486         0x01
+#define   PCI_SUBCLASS_PROC_PENTIUM     0x02
+#define   PCI_SUBCLASS_PROC_ALPHA       0x10
+#define   PCI_SUBCLASS_PROC_POWERPC     0x20
+#define   PCI_SUBCLASS_PROC_MIPS        0x30
+#define   PCI_SUBCLASS_PROC_CO_PORC     0x40 ///< Co-Processor
+
+#define PCI_CLASS_SERIAL              0x0C
+#define   PCI_CLASS_SERIAL_FIREWIRE     0x00
+#define     PCI_IF_1394                   0x00
+#define     PCI_IF_1394_OPEN_HCI          0x10
+#define   PCI_CLASS_SERIAL_ACCESS_BUS   0x01
+#define   PCI_CLASS_SERIAL_SSA          0x02
+#define   PCI_CLASS_SERIAL_USB          0x03
+#define     PCI_IF_UHCI                   0x00
+#define     PCI_IF_OHCI                   0x10
+#define     PCI_IF_USB_OTHER              0x80
+#define     PCI_IF_USB_DEVICE             0xFE
+#define   PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
+#define   PCI_CLASS_SERIAL_SMB          0x05
+
+#define PCI_CLASS_WIRELESS            0x0D
+#define   PCI_SUBCLASS_IRDA             0x00
+#define   PCI_SUBCLASS_IR               0x01
+#define   PCI_SUBCLASS_RF               0x10
+#define   PCI_SUBCLASS_WIRELESS_OTHER   0x80
+
+#define PCI_CLASS_INTELLIGENT_IO      0x0E
+
+#define PCI_CLASS_SATELLITE           0x0F
+#define   PCI_SUBCLASS_TV               0x01
+#define   PCI_SUBCLASS_AUDIO            0x02
+#define   PCI_SUBCLASS_VOICE            0x03
+#define   PCI_SUBCLASS_DATA             0x04
+
+#define PCI_SECURITY_CONTROLLER       0x10   ///< Encryption and decryption controller
+#define   PCI_SUBCLASS_NET_COMPUT       0x00
+#define   PCI_SUBCLASS_ENTERTAINMENT    0x10 
+#define   PCI_SUBCLASS_SECURITY_OTHER   0x80
+
+#define PCI_CLASS_DPIO                0x11
+#define   PCI_SUBCLASS_DPIO             0x00
+#define   PCI_SUBCLASS_DPIO_OTHER       0x80
+
+/**  
+  Macro that checks whether the Base Class code of device matched.
+
+  @param  _p      Specified device.
+  @param  c       Base Class code needs matching.
+
+  @retval TRUE    Base Class code matches the specified device.
+  @retval FALSE   Base Class code doesn't match the specified device.         
+
+**/
+#define IS_CLASS1(_p, c)              ((_p)->Hdr.ClassCode[2] == (c))
+/**  
+  Macro that checks whether the Base Class code and Sub-Class code of device matched.
+
+  @param  _p      Specified device.
+  @param  c       Base Class code needs matching.
+  @param  s       Sub-Class code needs matching.
+
+  @retval TRUE    Base Class code and Sub-Class code match the specified device.
+  @retval FALSE   Base Class code and Sub-Class code don't match the specified device.         
+
+**/
+#define IS_CLASS2(_p, c, s)           (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
+/**  
+  Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.
+
+  @param  _p      Specified device.
+  @param  c       Base Class code needs matching.
+  @param  s       Sub-Class code needs matching.
+  @param  p       Interface code needs matching.
+
+  @retval TRUE    Base Class code, Sub-Class code and Interface code match the specified device.
+  @retval FALSE   Base Class code, Sub-Class code and Interface code don't match the specified device.         
+
+**/
+#define IS_CLASS3(_p, c, s, p)        (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
+
+/**  
+  Macro that checks whether device is a display controller.
+
+  @param  _p      Specified device.
+
+  @retval TRUE    Device is a display controller.
+  @retval FALSE   Device is not a display controller.
+
+**/
+#define IS_PCI_DISPLAY(_p)            IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
+/**  
+  Macro that checks whether device is a VGA-compatible controller.
+
+  @param  _p      Specified device.
+
+  @retval TRUE    Device is a VGA-compatible controller.
+  @retval FALSE   Device is not a VGA-compatible controller.
+
+**/
+#define IS_PCI_VGA(_p)                IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)
+/**  
+  Macro that checks whether device is an 8514-compatible controller.
+
+  @param  _p      Specified device.
+
+  @retval TRUE    Device is an 8514-compatible controller.
+  @retval FALSE   Device is not an 8514-compatible controller.
+
+**/
+#define IS_PCI_8514(_p)               IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)
+/**  
+  Macro that checks whether device is built before the Class Code field was defined.
+
+  @param  _p      Specified device.
+
+  @retval TRUE    Device is an old device.
+  @retval FALSE   Device is not an old device.
+
+**/
+#define IS_PCI_OLD(_p)                IS_CLASS1 (_p, PCI_CLASS_OLD)
+/**  
+  Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.
+
+  @param  _p      Specified device.
+
+  @retval TRUE    Device is an old VGA-compatible device.
+  @retval FALSE   Device is not an old VGA-compatible device.
+
+**/
+#define IS_PCI_OLD_VGA(_p)            IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
+/**  
+  Macro that checks whether device is an IDE controller.
+
+  @param  _p      Specified device.
+
+  @retval TRUE    Device is an IDE controller.
+  @retval FALSE   Device is not an IDE controller.
+
+**/
+#define IS_PCI_IDE(_p)                IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
+/**  
+  Macro that checks whether device is a SCSI bus controller.
+
+  @param  _p      Specified device.
+
+  @retval TRUE    Device is a SCSI bus controller.
+  @retval FALSE   Device is not a SCSI bus controller.
+
+**/
+#define IS_PCI_SCSI(_p)               IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)
+/**  
+  Macro that checks whether device is a RAID controller.
+
+  @param  _p      Specified device.
+
+  @retval TRUE    Device is a RAID controller.
+  @retval FALSE   Device is not a RAID controller.
+
+**/
+#define IS_PCI_RAID(_p)               IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)
+/**  
+  Macro that checks whether device is an ISA bridge.
+
+  @param  _p      Specified device.
+
+  @retval TRUE    Device is an ISA bridge.
+  @retval FALSE   Device is not an ISA bridge.
+
+**/
+#define IS_PCI_LPC(_p)                IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)
+/**  
+  Macro that checks whether device is a PCI-to-PCI bridge.
+
+  @param  _p      Specified device.
+
+  @retval TRUE    Device is a PCI-to-PCI bridge.
+  @retval FALSE   Device is not a PCI-to-PCI bridge.
+
+**/
+#define IS_PCI_P2P(_p)                IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)
+/**  
+  Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.
+
+  @param  _p      Specified device.
+
+  @retval TRUE    Device is a Subtractive Decode PCI-to-PCI bridge.
+  @retval FALSE   Device is not a Subtractive Decode PCI-to-PCI bridge.
+
+**/
+#define IS_PCI_P2P_SUB(_p)            IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)
+/**  
+  Macro that checks whether device is a 16550-compatible serial controller.
+
+  @param  _p      Specified device.
+
+  @retval TRUE    Device is a 16550-compatible serial controller.
+  @retval FALSE   Device is not a 16550-compatible serial controller.
+
+**/
+#define IS_PCI_16550_SERIAL(_p)       IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
+/**  
+  Macro that checks whether device is a Universal Serial Bus controller.
+
+  @param  _p      Specified device.
+
+  @retval TRUE    Device is a Universal Serial Bus controller.
+  @retval FALSE   Device is not a Universal Serial Bus controller.
+
+**/
+#define IS_PCI_USB(_p)                IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
+
+//
+// the definition of Header Type 
+//
+#define HEADER_TYPE_DEVICE            0x00
+#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
+#define HEADER_TYPE_CARDBUS_BRIDGE    0x02
+#define HEADER_TYPE_MULTI_FUNCTION    0x80
+//
+// Mask of Header type
+//
+#define HEADER_LAYOUT_CODE            0x7f
+/**  
+  Macro that checks whether device is a PCI-PCI bridge.
+
+  @param  _p      Specified device.
+
+  @retval TRUE    Device is a PCI-PCI bridge.
+  @retval FALSE   Device is not a PCI-PCI bridge.
+
+**/
+#define IS_PCI_BRIDGE(_p)             (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
+/**  
+  Macro that checks whether device is a CardBus bridge.
+
+  @param  _p      Specified device.
+
+  @retval TRUE    Device is a CardBus bridge.
+  @retval FALSE   Device is not a CardBus bridge.
+
+**/
+#define IS_CARDBUS_BRIDGE(_p)         (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
+/**  
+  Macro that checks whether device is a multiple functions device.
+
+  @param  _p      Specified device.
+
+  @retval TRUE    Device is a multiple functions device.
+  @retval FALSE   Device is not a multiple functions device.
+
+**/
+#define IS_PCI_MULTI_FUNC(_p)         ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
+
+///
+/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,
+///
+#define PCI_BRIDGE_ROMBAR             0x38
+
+#define PCI_MAX_BAR                   0x0006
+#define PCI_MAX_CONFIG_OFFSET         0x0100
+
+#define PCI_VENDOR_ID_OFFSET                        0x00
+#define PCI_DEVICE_ID_OFFSET                        0x02
+#define PCI_COMMAND_OFFSET                          0x04
+#define PCI_PRIMARY_STATUS_OFFSET                   0x06
+#define PCI_REVISION_ID_OFFSET                      0x08
+#define PCI_CLASSCODE_OFFSET                        0x09
+#define PCI_CACHELINE_SIZE_OFFSET                   0x0C
+#define PCI_LATENCY_TIMER_OFFSET                    0x0D
+#define PCI_HEADER_TYPE_OFFSET                      0x0E
+#define PCI_BIST_OFFSET                             0x0F
+#define PCI_BASE_ADDRESSREG_OFFSET                  0x10
+#define PCI_CARDBUS_CIS_OFFSET                      0x28
+#define PCI_SVID_OFFSET                             0x2C ///< SubSystem Vendor id
+#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET              0x2C
+#define PCI_SID_OFFSET                              0x2E ///< SubSystem ID
+#define PCI_SUBSYSTEM_ID_OFFSET                     0x2E
+#define PCI_EXPANSION_ROM_BASE                      0x30
+#define PCI_CAPBILITY_POINTER_OFFSET                0x34
+#define PCI_INT_LINE_OFFSET                         0x3C ///< Interrupt Line Register
+#define PCI_INT_PIN_OFFSET                          0x3D ///< Interrupt Pin Register
+#define PCI_MAXGNT_OFFSET                           0x3E ///< Max Grant Register
+#define PCI_MAXLAT_OFFSET                           0x3F ///< Max Latency Register
+
+//
+// defined in PCI-to-PCI Bridge Architecture Specification
+//
+#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET      0x18   
+#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET    0x19   
+#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET  0x1a   
+#define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET   0x1b
+#define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E   
+#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E   
+
+///
+/// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
+///
+#define PCI_INT_LINE_UNKNOWN                        0xFF               
+
+///
+/// PCI Access Data Format
+///
+typedef union {
+  struct {
+    UINT32  Reg : 8;
+    UINT32  Func : 3;
+    UINT32  Dev : 5;
+    UINT32  Bus : 8;
+    UINT32  Reserved : 7;
+    UINT32  Enable : 1;
+  } Bits;
+  UINT32  Uint32;
+} PCI_CONFIG_ACCESS_CF8;
+
+#pragma pack()
+
+#define EFI_PCI_COMMAND_IO_SPACE                        BIT0   ///< 0x0001
+#define EFI_PCI_COMMAND_MEMORY_SPACE                    BIT1   ///< 0x0002
+#define EFI_PCI_COMMAND_BUS_MASTER                      BIT2   ///< 0x0004
+#define EFI_PCI_COMMAND_SPECIAL_CYCLE                   BIT3   ///< 0x0008
+#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE     BIT4   ///< 0x0010
+#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP               BIT5   ///< 0x0020
+#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND            BIT6   ///< 0x0040
+#define EFI_PCI_COMMAND_STEPPING_CONTROL                BIT7   ///< 0x0080
+#define EFI_PCI_COMMAND_SERR                            BIT8   ///< 0x0100
+#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK               BIT9   ///< 0x0200
+
+//
+// defined in PCI-to-PCI Bridge Architecture Specification
+//
+#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE    BIT0   ///< 0x0001
+#define EFI_PCI_BRIDGE_CONTROL_SERR                     BIT1   ///< 0x0002
+#define EFI_PCI_BRIDGE_CONTROL_ISA                      BIT2   ///< 0x0004
+#define EFI_PCI_BRIDGE_CONTROL_VGA                      BIT3   ///< 0x0008
+#define EFI_PCI_BRIDGE_CONTROL_VGA_16                   BIT4   ///< 0x0010
+#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT             BIT5   ///< 0x0020
+#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS      BIT6   ///< 0x0040
+#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK        BIT7   ///< 0x0080
+#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER    BIT8   ///< 0x0100
+#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER  BIT9   ///< 0x0200
+#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS             BIT10  ///< 0x0400
+#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR       BIT11  ///< 0x0800
+
+//
+// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard
+//
+#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE           BIT7   ///< 0x0080
+#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE       BIT8   ///< 0x0100
+#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE       BIT9   ///< 0x0200
+#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE     BIT10  ///< 0x0400
+
+//
+// Following are the PCI status control bit
+//
+#define EFI_PCI_STATUS_CAPABILITY                       BIT4   ///< 0x0010
+#define EFI_PCI_STATUS_66MZ_CAPABLE                     BIT5   ///< 0x0020
+#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE               BIT7   ///< 0x0080
+#define EFI_PCI_MASTER_DATA_PARITY_ERROR                BIT8   ///< 0x0100
+
+///
+/// defined in PC Card Standard
+///
+#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
+
+#pragma pack(1)
+//
+// PCI Capability List IDs and records
+//
+#define EFI_PCI_CAPABILITY_ID_PMI     0x01
+#define EFI_PCI_CAPABILITY_ID_AGP     0x02
+#define EFI_PCI_CAPABILITY_ID_VPD     0x03
+#define EFI_PCI_CAPABILITY_ID_SLOTID  0x04
+#define EFI_PCI_CAPABILITY_ID_MSI     0x05
+#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
+#define EFI_PCI_CAPABILITY_ID_SHPC    0x0C
+
+///
+/// Capabilities List Header
+/// Section 6.7, PCI Local Bus Specification, 2.2
+///
+typedef struct {
+  UINT8 CapabilityID;
+  UINT8 NextItemPtr;
+} EFI_PCI_CAPABILITY_HDR;
+
+///
+/// PMC - Power Management Capabilities
+/// Section 3.2.3, PCI Power Management Interface Specifiction, Revision 1.2
+///
+typedef union {
+  struct {
+    UINT16 Version : 3;
+    UINT16 PmeClock : 1;
+    UINT16 Reserved : 1;
+    UINT16 DeviceSpecificInitialization : 1;
+    UINT16 AuxCurrent : 3;
+    UINT16 D1Support : 1;
+    UINT16 D2Support : 1;
+    UINT16 PmeSupport : 5;
+  } Bits;
+  UINT16 Data;
+} EFI_PCI_PMC;
+
+#define EFI_PCI_PMC_D3_COLD_MASK    (BIT15)
+
+///
+/// PMCSR - Power Management Control/Status
+/// Section 3.2.4, PCI Power Management Interface Specifiction, Revision 1.2
+///
+typedef union {
+  struct {
+    UINT16 PowerState : 2;
+    UINT16 ReservedForPciExpress : 1;
+    UINT16 NoSoftReset : 1;
+    UINT16 Reserved : 4;
+    UINT16 PmeEnable : 1;
+    UINT16 DataSelect : 4;
+    UINT16 DataScale : 2;
+    UINT16 PmeStatus : 1;
+  } Bits;
+  UINT16 Data;
+} EFI_PCI_PMCSR;
+
+#define PCI_POWER_STATE_D0     0
+#define PCI_POWER_STATE_D1     1
+#define PCI_POWER_STATE_D2     2
+#define PCI_POWER_STATE_D3_HOT 3
+
+///
+/// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions
+/// Section 3.2.5, PCI Power Management Interface Specifiction, Revision 1.2
+///
+typedef union {
+  struct {
+    UINT8 Reserved : 6;
+    UINT8 B2B3 : 1;
+    UINT8 BusPowerClockControl : 1;
+  } Bits;
+  UINT8   Uint8;
+} EFI_PCI_PMCSR_BSE;
+
+///
+/// Power Management Register Block Definition
+/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2
+///
+typedef struct {
+  EFI_PCI_CAPABILITY_HDR  Hdr;
+  EFI_PCI_PMC             PMC;
+  EFI_PCI_PMCSR           PMCSR;
+  EFI_PCI_PMCSR_BSE       BridgeExtention;
+  UINT8                   Data;
+} EFI_PCI_CAPABILITY_PMI;
+
+///
+/// A.G.P Capability
+/// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0
+///
+typedef struct {
+  EFI_PCI_CAPABILITY_HDR  Hdr;
+  UINT8                   Rev;
+  UINT8                   Reserved;
+  UINT32                  Status;
+  UINT32                  Command;
+} EFI_PCI_CAPABILITY_AGP;
+
+///
+/// VPD Capability Structure
+/// Appendix I, PCI Local Bus Specification, 2.2
+///
+typedef struct {
+  EFI_PCI_CAPABILITY_HDR  Hdr;
+  UINT16                  AddrReg;
+  UINT32                  DataReg;
+} EFI_PCI_CAPABILITY_VPD;
+
+///
+/// Slot Numbering Capabilities Register
+/// Section 3.2.6, PCI-to-PCI Bridge Architeture Specification, Revision 1.2
+///
+typedef struct {
+  EFI_PCI_CAPABILITY_HDR  Hdr;
+  UINT8                   ExpnsSlotReg;
+  UINT8                   ChassisNo;
+} EFI_PCI_CAPABILITY_SLOTID;
+
+///
+/// Message Capability Structure for 32-bit Message Address
+/// Section 6.8.1, PCI Local Bus Specification, 2.2
+///
+typedef struct {
+  EFI_PCI_CAPABILITY_HDR  Hdr;
+  UINT16                  MsgCtrlReg;
+  UINT32                  MsgAddrReg;
+  UINT16                  MsgDataReg;
+} EFI_PCI_CAPABILITY_MSI32;
+
+///
+/// Message Capability Structure for 64-bit Message Address
+/// Section 6.8.1, PCI Local Bus Specification, 2.2
+///
+typedef struct {
+  EFI_PCI_CAPABILITY_HDR  Hdr;
+  UINT16                  MsgCtrlReg;
+  UINT32                  MsgAddrRegLsdw;
+  UINT32                  MsgAddrRegMsdw;
+  UINT16                  MsgDataReg;
+} EFI_PCI_CAPABILITY_MSI64;
+
+///
+/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG, 
+/// CompactPCI Hot Swap Specification PICMG 2.1, R1.0
+///
+typedef struct {
+  EFI_PCI_CAPABILITY_HDR  Hdr;
+  ///
+  /// not finished - fields need to go here
+  ///
+} EFI_PCI_CAPABILITY_HOTPLUG;
+
+#define PCI_BAR_IDX0        0x00
+#define PCI_BAR_IDX1        0x01
+#define PCI_BAR_IDX2        0x02
+#define PCI_BAR_IDX3        0x03
+#define PCI_BAR_IDX4        0x04
+#define PCI_BAR_IDX5        0x05
+
+///
+/// EFI PCI Option ROM definitions
+/// 
+#define EFI_ROOT_BRIDGE_LIST                            'eprb'  
+#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE       0x0EF1  ///< defined in UEFI Spec.
+
+#define PCI_EXPANSION_ROM_HEADER_SIGNATURE              0xaa55
+#define PCI_DATA_STRUCTURE_SIGNATURE                    SIGNATURE_32 ('P', 'C', 'I', 'R')
+#define PCI_CODE_TYPE_PCAT_IMAGE                        0x00
+#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED         0x0001  ///< defined in UEFI spec.
+
+///
+/// Standard PCI Expansion ROM Header
+/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
+///
+typedef struct {
+  UINT16  Signature;    ///< 0xaa55
+  UINT8   Reserved[0x16];
+  UINT16  PcirOffset;
+} PCI_EXPANSION_ROM_HEADER;
+
+///
+/// Legacy ROM Header Extensions
+/// Section 6.3.3.1, PCI Local Bus Specification, 2.2
+///
+typedef struct {
+  UINT16  Signature;    ///< 0xaa55
+  UINT8   Size512;
+  UINT8   InitEntryPoint[3];
+  UINT8   Reserved[0x12];
+  UINT16  PcirOffset;
+} EFI_LEGACY_EXPANSION_ROM_HEADER;
+
+///
+/// PCI Data Structure Format
+/// Section 6.3.1.2, PCI Local Bus Specification, 2.2
+///
+typedef struct {
+  UINT32  Signature;    ///< "PCIR"
+  UINT16  VendorId;
+  UINT16  DeviceId;
+  UINT16  Reserved0;
+  UINT16  Length;
+  UINT8   Revision;
+  UINT8   ClassCode[3];
+  UINT16  ImageLength;
+  UINT16  CodeRevision;
+  UINT8   CodeType;
+  UINT8   Indicator;
+  UINT16  Reserved1;
+} PCI_DATA_STRUCTURE;
+
+///
+/// EFI PCI Expansion ROM Header
+/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
+///
+typedef struct {
+  UINT16  Signature;    ///< 0xaa55
+  UINT16  InitializationSize;
+  UINT32  EfiSignature; ///< 0x0EF1
+  UINT16  EfiSubsystem;
+  UINT16  EfiMachineType;
+  UINT16  CompressionType;
+  UINT8   Reserved[8];
+  UINT16  EfiImageHeaderOffset;
+  UINT16  PcirOffset;
+} EFI_PCI_EXPANSION_ROM_HEADER;
+
+typedef union {
+  UINT8                           *Raw;
+  PCI_EXPANSION_ROM_HEADER        *Generic;
+  EFI_PCI_EXPANSION_ROM_HEADER    *Efi;
+  EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;
+} EFI_PCI_ROM_HEADER;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci23.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci23.h
new file mode 100644
index 0000000000..43f4ac99d3
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci23.h
@@ -0,0 +1,133 @@
+/** @file
+  Support for PCI 2.3 standard.
+
+  Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php.                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+**/
+
+#ifndef _PCI23_H_
+#define _PCI23_H_
+
+#include <IndustryStandard/Pci22.h>
+
+///
+/// PCI_CLASS_MASS_STORAGE, Base Class 01h.
+///
+///@{
+#define PCI_CLASS_MASS_STORAGE_ATA       0x05
+#define   PCI_IF_MASS_STORAGE_SINGLE_DMA   0x20
+#define   PCI_IF_MASS_STORAGE_CHAINED_DMA  0x30
+///@}
+
+///
+/// PCI_CLASS_NETWORK, Base Class 02h.
+///
+///@{
+#define PCI_CLASS_NETWORK_WORLDFIP              0x05
+#define PCI_CLASS_NETWORK_PICMG_MULTI_COMPUTING 0x06
+///@}
+
+///
+/// PCI_CLASS_BRIDGE, Base Class 06h.
+///
+///@{
+#define PCI_CLASS_BRIDGE_SEMI_TRANSPARENT_P2P        0x09
+#define   PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_PRIMARY   0x40
+#define   PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_SECONDARY 0x80
+#define PCI_CLASS_BRIDGE_INFINIBAND_TO_PCI           0x0A
+///@}
+
+///
+/// PCI_CLASS_SCC, Base Class 07h.
+///
+///@{
+#define PCI_SUBCLASS_GPIB          0x04
+#define PCI_SUBCLASS_SMART_CARD    0x05
+///@}
+
+///
+/// PCI_CLASS_SERIAL, Base Class 0Ch.
+///
+///@{
+#define   PCI_IF_EHCI                      0x20
+#define PCI_CLASS_SERIAL_IB              0x06
+#define PCI_CLASS_SERIAL_IPMI            0x07
+#define   PCI_IF_IPMI_SMIC                 0x00
+#define   PCI_IF_IPMI_KCS                  0x01 ///< Keyboard Controller Style
+#define   PCI_IF_IPMI_BT                   0x02 ///< Block Transfer
+#define PCI_CLASS_SERIAL_SERCOS          0x08
+#define PCI_CLASS_SERIAL_CANBUS          0x09
+///@}
+
+///
+/// PCI_CLASS_WIRELESS, Base Class 0Dh.
+///
+///@{
+#define PCI_SUBCLASS_BLUETOOTH    0x11
+#define PCI_SUBCLASS_BROADBAND    0x12
+///@}
+
+///
+/// PCI_CLASS_DPIO, Base Class 11h.
+///
+///@{
+#define PCI_SUBCLASS_PERFORMANCE_COUNTERS          0x01
+#define PCI_SUBCLASS_COMMUNICATION_SYNCHRONIZATION 0x10
+#define PCI_SUBCLASS_MANAGEMENT_CARD               0x20
+///@}
+
+///
+/// defined in PCI Express Spec.
+///
+#define PCI_EXP_MAX_CONFIG_OFFSET     0x1000
+
+///
+/// PCI Capability List IDs and records.
+///
+#define EFI_PCI_CAPABILITY_ID_PCIX    0x07
+#define EFI_PCI_CAPABILITY_ID_VENDOR  0x09
+
+#pragma pack(1)
+///
+/// PCI-X Capabilities List, 
+/// Section 7.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.
+///
+typedef struct {
+  EFI_PCI_CAPABILITY_HDR  Hdr;
+  UINT16                  CommandReg;
+  UINT32                  StatusReg;
+} EFI_PCI_CAPABILITY_PCIX;
+
+///
+/// PCI-X Bridge Capabilities List, 
+/// Section 8.6.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.
+///
+typedef struct {
+  EFI_PCI_CAPABILITY_HDR  Hdr;
+  UINT16                  SecStatusReg;
+  UINT32                  StatusReg;
+  UINT32                  SplitTransCtrlRegUp;
+  UINT32                  SplitTransCtrlRegDn;
+} EFI_PCI_CAPABILITY_PCIX_BRDG;
+
+///
+/// Vendor Specific Capability Header
+/// Table H-1: Capability IDs, PCI Local Bus Specification, 2.3
+///
+typedef struct {
+  EFI_PCI_CAPABILITY_HDR  Hdr;
+  UINT8                   Length;
+} EFI_PCI_CAPABILITY_VENDOR_HDR;
+
+#pragma pack()
+
+#define PCI_CODE_TYPE_EFI_IMAGE       0x03
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci30.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci30.h
new file mode 100644
index 0000000000..57bd5a4179
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci30.h
@@ -0,0 +1,79 @@
+/** @file
+  Support for PCI 3.0 standard.
+
+  Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+**/
+
+#ifndef __PCI30_H__
+#define __PCI30_H__
+
+
+#include <IndustryStandard/Pci23.h>
+
+///
+/// PCI_CLASS_MASS_STORAGE, Base Class 01h.
+///
+///@{
+#define PCI_CLASS_MASS_STORAGE_SATADPA   0x06
+#define   PCI_IF_MASS_STORAGE_SATA         0x00
+#define   PCI_IF_MASS_STORAGE_AHCI         0x01
+///@}
+
+///
+/// PCI_CLASS_WIRELESS, Base Class 0Dh.
+///
+///@{
+#define PCI_SUBCLASS_ETHERNET_80211A    0x20
+#define PCI_SUBCLASS_ETHERNET_80211B    0x21
+///@}
+
+/**
+  Macro that checks whether device is a SATA controller.
+
+  @param  _p      Specified device.
+
+  @retval TRUE    Device is a SATA controller.
+  @retval FALSE   Device is not a SATA controller.
+
+**/
+#define IS_PCI_SATADPA(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SATADPA)
+
+///
+/// PCI Capability List IDs and records
+///
+#define EFI_PCI_CAPABILITY_ID_PCIEXP  0x10
+
+#pragma pack(1)
+
+///
+/// PCI Data Structure Format
+/// Section 5.1.2, PCI Firmware Specification, Revision 3.0
+///
+typedef struct {
+  UINT32  Signature;    ///< "PCIR"
+  UINT16  VendorId;
+  UINT16  DeviceId;
+  UINT16  DeviceListOffset;
+  UINT16  Length;
+  UINT8   Revision;
+  UINT8   ClassCode[3];
+  UINT16  ImageLength;
+  UINT16  CodeRevision;
+  UINT8   CodeType;
+  UINT8   Indicator;
+  UINT16  MaxRuntimeImageLength;
+  UINT16  ConfigUtilityCodeHeaderOffset;
+  UINT16  DMTFCLPEntryPointOffset;
+} PCI_3_0_DATA_STRUCTURE;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PciCodeId.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PciCodeId.h
new file mode 100644
index 0000000000..31b6b8ec5d
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PciCodeId.h
@@ -0,0 +1,100 @@
+/** @file
+  The file lists the PCI class codes only defined in PCI code and ID assignment specification
+  revision 1.3.
+
+  Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+**/
+
+#ifndef __PCI_CODE_ID_H__
+#define __PCI_CODE_ID_H__
+
+
+///
+/// PCI_CLASS_MASS_STORAGE, Base Class 01h.
+///
+///@{
+#define   PCI_IF_MASS_STORAGE_SCSI_VENDOR_SPECIFIC          0x00
+#define   PCI_IF_MASS_STORAGE_SCSI_DEVICE_PQI               0x11
+#define   PCI_IF_MASS_STORAGE_SCSI_CONTROLLER_PQI           0x12
+#define   PCI_IF_MASS_STORAGE_SCSI_DEVICE_CONTROLLER_PQI    0x13
+#define   PCI_IF_MASS_STORAGE_SCSI_DEVICE_NVM_EXPRESS       0x21
+#define   PCI_IF_MASS_STORAGE_SATA_SERIAL_BUS               0x02
+#define PCI_CLASS_MASS_STORAGE_SAS                        0x07
+#define   PCI_IF_MASS_STORAGE_SAS                           0x00
+#define   PCI_IF_MASS_STORAGE_SAS_SERIAL_BUS                0x01
+#define PCI_CLASS_MASS_STORAGE_SOLID_STATE                0x08
+#define   PCI_IF_MASS_STORAGE_SOLID_STATE                   0x00
+#define   PCI_IF_MASS_STORAGE_SOLID_STATE_NVMHCI            0x01
+#define   PCI_IF_MASS_STORAGE_SOLID_STATE_ENTERPRISE_NVMHCI 0x02
+///@}
+
+///
+/// PCI_CLASS_NETWORK, Base Class 02h.
+///
+///@{
+#define PCI_CLASS_NETWORK_INFINIBAND   0x07
+///@}
+
+///
+/// PCI_CLASS_MEDIA, Base Class 04h.
+///
+///@{
+#define PCI_CLASS_MEDIA_MIXED_MODE   0x03
+///@}
+
+///
+/// PCI_CLASS_BRIDGE, Base Class 06h.
+///
+///@{
+#define PCI_CLASS_BRIDGE_ADVANCED_SWITCHING_TO_PCI      0x0B
+#define   PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_CUSTOM  0x00
+#define   PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_ASI_SIG 0x01
+///@}
+
+///
+/// PCI_CLASS_SYSTEM_PERIPHERAL, Base Class 08h.
+///
+///@{
+#define   PCI_IF_HPET                 0x03
+#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05
+#define PCI_SUBCLASS_IOMMU              0x06
+///@}
+
+///
+/// PCI_CLASS_PROCESSOR, Base Class 0Bh.
+///
+///@{
+#define PCI_SUBCLASS_PROC_OTHER 0x80
+///@}
+
+///
+/// PCI_CLASS_SERIAL, Base Class 0Ch.
+///
+///@{
+#define   PCI_IF_XHCI             0x30
+#define PCI_CLASS_SERIAL_OTHER  0x80
+///@}
+
+///
+/// PCI_CLASS_SATELLITE, Base Class 0Fh.
+///
+///@{
+#define PCI_SUBCLASS_SATELLITE_OTHER 0x80
+///@}
+
+///
+/// PCI_CLASS_PROCESSING_ACCELERATOR, Base Class 12h.
+///
+///@{
+#define PCI_CLASS_PROCESSING_ACCELERATOR  0x12
+///@}
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PciExpress21.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PciExpress21.h
new file mode 100644
index 0000000000..d1f20001e4
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PciExpress21.h
@@ -0,0 +1,668 @@
+/** @file
+  Support for the latest PCI standard.
+
+  Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>  
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+**/
+
+#ifndef _PCIEXPRESS21_H_
+#define _PCIEXPRESS21_H_
+
+#include <IndustryStandard/Pci30.h>
+
+/**
+  Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
+  ECAM (Enhanced Configuration Access Mechanism) address. The unused upper bits
+  of Bus, Device, Function and Register are stripped prior to the generation of
+  the address.
+
+  @param  Bus       PCI Bus number. Range 0..255.
+  @param  Device    PCI Device number. Range 0..31.
+  @param  Function  PCI Function number. Range 0..7.
+  @param  Register  PCI Register number. Range 0..4095.
+
+  @return The encode ECAM address.
+
+**/
+#define PCI_ECAM_ADDRESS(Bus,Device,Function,Offset) \
+  (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
+
+#pragma pack(1)
+///
+/// PCI Express Capability Structure
+///
+typedef union {
+  struct {
+    UINT16 Version : 4;
+    UINT16 DevicePortType : 4;
+    UINT16 SlotImplemented : 1;
+    UINT16 InterruptMessageNumber : 5;
+    UINT16 Undefined : 1;
+    UINT16 Reserved : 1;
+  } Bits;
+  UINT16   Uint16;
+} PCI_REG_PCIE_CAPABILITY;
+
+#define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT                    0
+#define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT             1
+#define PCIE_DEVICE_PORT_TYPE_ROOT_PORT                        4
+#define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT                    5
+#define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT                  6
+#define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE               7
+#define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE               8
+#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9
+#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR     10
+
+typedef union {
+  struct {
+    UINT32 MaxPayloadSize : 3;
+    UINT32 PhantomFunctions : 2;
+    UINT32 ExtendedTagField : 1;
+    UINT32 EndpointL0sAcceptableLatency : 3;
+    UINT32 EndpointL1AcceptableLatency : 3;
+    UINT32 Undefined : 3;
+    UINT32 RoleBasedErrorReporting : 1;
+    UINT32 Reserved : 2;
+    UINT32 CapturedSlotPowerLimitValue : 8;
+    UINT32 CapturedSlotPowerLimitScale : 2;
+    UINT32 FunctionLevelReset : 1;
+    UINT32 Reserved2 : 3;
+  } Bits;
+  UINT32   Uint32;
+} PCI_REG_PCIE_DEVICE_CAPABILITY;
+
+typedef union {
+  struct {
+    UINT16 CorrectableError : 1;
+    UINT16 NonFatalError : 1;
+    UINT16 FatalError : 1;
+    UINT16 UnsupportedRequest : 1;
+    UINT16 RelaxedOrdering : 1;
+    UINT16 MaxPayloadSize : 3;
+    UINT16 ExtendedTagField : 1;
+    UINT16 PhantomFunctions : 1;
+    UINT16 AuxPower : 1;
+    UINT16 NoSnoop : 1;
+    UINT16 MaxReadRequestSize : 3;
+    UINT16 BridgeConfigurationRetryOrFunctionLevelReset : 1;
+  } Bits;
+  UINT16   Uint16;
+} PCI_REG_PCIE_DEVICE_CONTROL;
+
+typedef union {
+  struct {
+    UINT16 CorrectableError : 1;
+    UINT16 NonFatalError : 1;
+    UINT16 FatalError : 1;
+    UINT16 UnsupportedRequest : 1;
+    UINT16 AuxPower : 1;
+    UINT16 TransactionsPending : 1;
+    UINT16 Reserved : 10;
+  } Bits;
+  UINT16   Uint16;
+} PCI_REG_PCIE_DEVICE_STATUS;
+
+typedef union {
+  struct {
+    UINT32 MaxLinkSpeed : 4;
+    UINT32 MaxLinkWidth : 6;
+    UINT32 Aspm : 2;
+    UINT32 L0sExitLatency : 3;
+    UINT32 L1ExitLatency : 3;
+    UINT32 ClockPowerManagement : 1;
+    UINT32 SurpriseDownError : 1;
+    UINT32 DataLinkLayerLinkActive : 1;
+    UINT32 LinkBandwidthNotification : 1;
+    UINT32 AspmOptionalityCompliance : 1;
+    UINT32 Reserved : 1;
+    UINT32 PortNumber : 8;
+  } Bits;
+  UINT32   Uint32;
+} PCI_REG_PCIE_LINK_CAPABILITY;
+
+#define PCIE_LINK_ASPM_L0S BIT0
+#define PCIE_LINK_ASPM_L1  BIT1
+
+typedef union {
+  struct {
+    UINT16 AspmControl : 2;
+    UINT16 Reserved : 1;
+    UINT16 ReadCompletionBoundary : 1;
+    UINT16 LinkDisable : 1;
+    UINT16 RetrainLink : 1;
+    UINT16 CommonClockConfiguration : 1;
+    UINT16 ExtendedSynch : 1;
+    UINT16 ClockPowerManagement : 1;
+    UINT16 HardwareAutonomousWidthDisable : 1;
+    UINT16 LinkBandwidthManagementInterrupt : 1;
+    UINT16 LinkAutonomousBandwidthInterrupt : 1;
+  } Bits;
+  UINT16   Uint16;
+} PCI_REG_PCIE_LINK_CONTROL;
+
+typedef union {
+  struct {
+    UINT16 CurrentLinkSpeed : 4;
+    UINT16 NegotiatedLinkWidth : 6;
+    UINT16 Undefined : 1;
+    UINT16 LinkTraining : 1;
+    UINT16 SlotClockConfiguration : 1;
+    UINT16 DataLinkLayerLinkActive : 1;
+    UINT16 LinkBandwidthManagement : 1;
+    UINT16 LinkAutonomousBandwidth : 1;
+  } Bits;
+  UINT16   Uint16;
+} PCI_REG_PCIE_LINK_STATUS;
+
+typedef union {
+  struct {
+    UINT32 AttentionButton : 1;
+    UINT32 PowerController : 1;
+    UINT32 MrlSensor : 1;
+    UINT32 AttentionIndicator : 1;
+    UINT32 PowerIndicator : 1;
+    UINT32 HotPlugSurprise : 1;
+    UINT32 HotPlugCapable : 1;
+    UINT32 SlotPowerLimitValue : 8;
+    UINT32 SlotPowerLimitScale : 2;
+    UINT32 ElectromechanicalInterlock : 1;
+    UINT32 NoCommandCompleted : 1;
+    UINT32 PhysicalSlotNumber : 13;
+  } Bits;
+  UINT32   Uint32;
+} PCI_REG_PCIE_SLOT_CAPABILITY;
+
+typedef union {
+  struct {
+    UINT16 AttentionButtonPressed : 1;
+    UINT16 PowerFaultDetected : 1;
+    UINT16 MrlSensorChanged : 1;
+    UINT16 PresenceDetectChanged : 1;
+    UINT16 CommandCompletedInterrupt : 1;
+    UINT16 HotPlugInterrupt : 1;
+    UINT16 AttentionIndicator : 2;
+    UINT16 PowerIndicator : 2;
+    UINT16 PowerController : 1;
+    UINT16 ElectromechanicalInterlock : 1;
+    UINT16 DataLinkLayerStateChanged : 1;
+    UINT16 Reserved : 3;
+  } Bits;
+  UINT16   Uint16;
+} PCI_REG_PCIE_SLOT_CONTROL;
+
+typedef union {
+  struct {
+    UINT16 AttentionButtonPressed : 1;
+    UINT16 PowerFaultDetected : 1;
+    UINT16 MrlSensorChanged : 1;
+    UINT16 PresenceDetectChanged : 1;
+    UINT16 CommandCompleted : 1;
+    UINT16 MrlSensor : 1;
+    UINT16 PresenceDetect : 1;
+    UINT16 ElectromechanicalInterlock : 1;
+    UINT16 DataLinkLayerStateChanged : 1;
+    UINT16 Reserved : 7;
+  } Bits;
+  UINT16   Uint16;
+} PCI_REG_PCIE_SLOT_STATUS;
+
+typedef union {
+  struct {
+    UINT16 SystemErrorOnCorrectableError : 1;
+    UINT16 SystemErrorOnNonFatalError : 1;
+    UINT16 SystemErrorOnFatalError : 1;
+    UINT16 PmeInterrupt : 1;
+    UINT16 CrsSoftwareVisibility : 1;
+    UINT16 Reserved : 11;
+  } Bits;
+  UINT16   Uint16;
+} PCI_REG_PCIE_ROOT_CONTROL;
+
+typedef union {
+  struct {
+    UINT16 CrsSoftwareVisibility : 1;
+    UINT16 Reserved : 15;
+  } Bits;
+  UINT16   Uint16;
+} PCI_REG_PCIE_ROOT_CAPABILITY;
+
+typedef union {
+  struct {
+    UINT32 PmeRequesterId : 16;
+    UINT32 PmeStatus : 1;
+    UINT32 PmePending : 1;
+    UINT32 Reserved : 14;
+  } Bits;
+  UINT32   Uint32;
+} PCI_REG_PCIE_ROOT_STATUS;
+
+typedef union {
+  struct {
+    UINT32 CompletionTimeoutRanges : 4;
+    UINT32 CompletionTimeoutDisable : 1;
+    UINT32 AriForwarding : 1;
+    UINT32 AtomicOpRouting : 1;
+    UINT32 AtomicOp32Completer : 1;
+    UINT32 AtomicOp64Completer : 1;
+    UINT32 Cas128Completer : 1;
+    UINT32 NoRoEnabledPrPrPassing : 1;
+    UINT32 LtrMechanism : 1;
+    UINT32 TphCompleter : 2;
+    UINT32 Reserved : 4;
+    UINT32 Obff : 2;
+    UINT32 ExtendedFmtField : 1;
+    UINT32 EndEndTlpPrefix : 1;
+    UINT32 MaxEndEndTlpPrefixes : 2;
+    UINT32 Reserved2 : 8;
+  } Bits;
+  UINT32   Uint32;
+} PCI_REG_PCIE_DEVICE_CAPABILITY2;
+
+#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
+#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE    BIT1
+
+typedef union {
+  struct {
+    UINT16 CompletionTimeoutValue : 4;
+    UINT16 CompletionTimeoutDisable : 1;
+    UINT16 AriForwarding : 1;
+    UINT16 AtomicOpRequester : 1;
+    UINT16 AtomicOpEgressBlocking : 1;
+    UINT16 IdoRequest : 1;
+    UINT16 IdoCompletion : 1;
+    UINT16 LtrMechanism : 2;
+    UINT16 Reserved : 2;
+    UINT16 Obff : 2;
+    UINT16 EndEndTlpPrefixBlocking : 1;
+  } Bits;
+  UINT16   Uint16;
+} PCI_REG_PCIE_DEVICE_CONTROL2;
+
+#define PCIE_COMPLETION_TIMEOUT_50US_50MS   0
+#define PCIE_COMPLETION_TIMEOUT_50US_100US  1
+#define PCIE_COMPLETION_TIMEOUT_1MS_10MS    2
+#define PCIE_COMPLETION_TIMEOUT_16MS_55MS   5
+#define PCIE_COMPLETION_TIMEOUT_65MS_210MS  6
+#define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9
+#define PCIE_COMPLETION_TIMEOUT_1S_3_5S     10
+#define PCIE_COMPLETION_TIMEOUT_4S_13S      13
+#define PCIE_COMPLETION_TIMEOUT_17S_64S     14
+
+#define PCIE_DEVICE_CONTROL_OBFF_DISABLED  0
+#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1
+#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2
+#define PCIE_DEVICE_CONTROL_OBFF_WAKE      3
+
+typedef union {
+  struct {
+    UINT32 Reserved : 1;
+    UINT32 LinkSpeedsVector : 7;
+    UINT32 Crosslink : 1;
+    UINT32 Reserved2 : 23;
+  } Bits;
+  UINT32   Uint32;
+} PCI_REG_PCIE_LINK_CAPABILITY2;
+
+typedef union {
+  struct {
+    UINT16 TargetLinkSpeed : 4;
+    UINT16 EnterCompliance : 1;
+    UINT16 HardwareAutonomousSpeedDisable : 1;
+    UINT16 SelectableDeemphasis : 1;
+    UINT16 TransmitMargin : 3;
+    UINT16 EnterModifiedCompliance : 1;
+    UINT16 ComplianceSos : 1;
+    UINT16 CompliancePresetDeemphasis : 4;
+  } Bits;
+  UINT16   Uint16;
+} PCI_REG_PCIE_LINK_CONTROL2;
+
+typedef union {
+  struct {
+    UINT16 CurrentDeemphasisLevel : 1;
+    UINT16 EqualizationComplete : 1;
+    UINT16 EqualizationPhase1Successful : 1;
+    UINT16 EqualizationPhase2Successful : 1;
+    UINT16 EqualizationPhase3Successful : 1;
+    UINT16 LinkEqualizationRequest : 1;
+    UINT16 Reserved : 10;
+  } Bits;
+  UINT16   Uint16;
+} PCI_REG_PCIE_LINK_STATUS2;
+
+typedef struct {
+  EFI_PCI_CAPABILITY_HDR          Hdr;
+  PCI_REG_PCIE_CAPABILITY         Capability;
+  PCI_REG_PCIE_DEVICE_CAPABILITY  DeviceCapability;
+  PCI_REG_PCIE_DEVICE_CONTROL     DeviceControl;
+  PCI_REG_PCIE_DEVICE_STATUS      DeviceStatus;
+  PCI_REG_PCIE_LINK_CAPABILITY    LinkCapability;
+  PCI_REG_PCIE_LINK_CONTROL       LinkControl;
+  PCI_REG_PCIE_LINK_STATUS        LinkStatus;
+  PCI_REG_PCIE_SLOT_CAPABILITY    SlotCapability;
+  PCI_REG_PCIE_SLOT_CONTROL       SlotControl;
+  PCI_REG_PCIE_SLOT_STATUS        SlotStatus;
+  PCI_REG_PCIE_ROOT_CONTROL       RootControl;
+  PCI_REG_PCIE_ROOT_CAPABILITY    RootCapability;
+  PCI_REG_PCIE_ROOT_STATUS        RootStatus;
+  PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;
+  PCI_REG_PCIE_DEVICE_CONTROL2    DeviceControl2;
+  UINT16                          DeviceStatus2;
+  PCI_REG_PCIE_LINK_CAPABILITY2   LinkCapability2;
+  PCI_REG_PCIE_LINK_CONTROL2      LinkControl2;
+  PCI_REG_PCIE_LINK_STATUS2       LinkStatus2;
+  UINT32                          SlotCapability2;
+  UINT16                          SlotControl2;
+  UINT16                          SlotStatus2;
+} PCI_CAPABILITY_PCIEXP;
+
+#define EFI_PCIE_CAPABILITY_BASE_OFFSET                             0x100
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY          0x10
+#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET            0x24
+#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING    0x20
+#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET                 0x28
+#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING         0x20
+
+//
+// for SR-IOV
+//
+#define EFI_PCIE_CAPABILITY_ID_ARI        0x0E
+#define EFI_PCIE_CAPABILITY_ID_ATS        0x0F
+#define EFI_PCIE_CAPABILITY_ID_SRIOV      0x10
+#define EFI_PCIE_CAPABILITY_ID_MRIOV      0x11
+
+typedef struct {
+  UINT32  CapabilityHeader;
+  UINT32  Capability;
+  UINT16  Control;
+  UINT16  Status;
+  UINT16  InitialVFs;
+  UINT16  TotalVFs;
+  UINT16  NumVFs;
+  UINT8   FunctionDependencyLink;
+  UINT8   Reserved0;
+  UINT16  FirstVFOffset;
+  UINT16  VFStride;
+  UINT16  Reserved1;
+  UINT16  VFDeviceID;
+  UINT32  SupportedPageSize;
+  UINT32  SystemPageSize;
+  UINT32  VFBar[6];
+  UINT32  VFMigrationStateArrayOffset;
+} SR_IOV_CAPABILITY_REGISTER;
+
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES               0x04
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL                    0x08
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS                     0x0A
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS                 0x0C
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS                   0x0E
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS                     0x10
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK   0x12
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF                    0x14
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE                   0x16
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID                 0x1A
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE        0x1C
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE           0x20
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0                       0x24
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1                       0x28
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2                       0x2C
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3                       0x30
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4                       0x34
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5                       0x38
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE         0x3C
+
+typedef struct {
+  UINT32 CapabilityId:16;
+  UINT32 CapabilityVersion:4;
+  UINT32 NextCapabilityOffset:12;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER;
+
+#define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID   0x0001
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2
+
+typedef union {
+  struct {
+    UINT32 Undefined : 1;
+    UINT32 Reserved : 3;
+    UINT32 DataLinkProtocolError : 1;
+    UINT32 SurpriseDownError : 1;
+    UINT32 Reserved2 : 6;
+    UINT32 PoisonedTlp : 1;
+    UINT32 FlowControlProtocolError : 1;
+    UINT32 CompletionTimeout : 1;
+    UINT32 CompleterAbort : 1;
+    UINT32 UnexpectedCompletion : 1;
+    UINT32 ReceiverOverflow : 1;
+    UINT32 MalformedTlp : 1;
+    UINT32 EcrcError : 1;
+    UINT32 UnsupportedRequestError : 1;
+    UINT32 AcsVoilation : 1;
+    UINT32 UncorrectableInternalError : 1;
+    UINT32 McBlockedTlp : 1;
+    UINT32 AtomicOpEgressBlocked : 1;
+    UINT32 TlpPrefixBlockedError : 1;
+    UINT32 Reserved3 : 6;
+  } Bits;
+  UINT32   Uint32;
+} PCI_EXPRESS_REG_UNCORRECTABLE_ERROR;
+
+typedef struct {
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER  Header;
+  PCI_EXPRESS_REG_UNCORRECTABLE_ERROR       UncorrectableErrorStatus;
+  PCI_EXPRESS_REG_UNCORRECTABLE_ERROR       UncorrectableErrorMask;
+  PCI_EXPRESS_REG_UNCORRECTABLE_ERROR       UncorrectableErrorSeverity;
+  UINT32                                    CorrectableErrorStatus;
+  UINT32                                    CorrectableErrorMask;
+  UINT32                                    AdvancedErrorCapabilitiesAndControl;
+  UINT32                                    HeaderLog[4];
+  UINT32                                    RootErrorCommand;
+  UINT32                                    RootErrorStatus;
+  UINT16                                    ErrorSourceIdentification;
+  UINT16                                    CorrectableErrorSourceIdentification;
+  UINT32                                    TlpPrefixLog[4];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID    0x0002
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_MFVC  0x0009
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1  0x1
+
+typedef struct {
+  UINT32                                    VcResourceCapability:24;
+  UINT32                                    PortArbTableOffset:8;
+  UINT32                                    VcResourceControl;
+  UINT16                                    Reserved1;
+  UINT16                                    VcResourceStatus;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC;
+
+typedef struct {
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER              Header;
+  UINT32                                                ExtendedVcCount:3;
+  UINT32                                                PortVcCapability1:29;
+  UINT32                                                PortVcCapability2:24;
+  UINT32                                                VcArbTableOffset:8;
+  UINT16                                                PortVcControl;
+  UINT16                                                PortVcStatus;
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC  Capability[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID    0x0003
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1  0x1
+
+typedef struct {
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER  Header;
+  UINT64                                    SerialNumber;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID   0x0005
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1
+
+typedef struct {
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER  Header;
+  UINT32                                    ElementSelfDescription;
+  UINT32                                    Reserved;
+  UINT32                                    LinkEntry[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID   0x0006
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1
+
+typedef struct {
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER  Header;
+  UINT32                                    RootComplexLinkCapabilities;
+  UINT16                                    RootComplexLinkControl;
+  UINT16                                    RootComplexLinkStatus;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID   0x0004
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1
+
+typedef struct {
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER  Header;
+  UINT32                                    DataSelect:8;
+  UINT32                                    Reserved:24;
+  UINT32                                    Data;
+  UINT32                                    PowerBudgetCapability:1;
+  UINT32                                    Reserved2:7;
+  UINT32                                    Reserved3:24;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID   0x000D
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1
+
+typedef struct {
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER  Header;
+  UINT16                                    AcsCapability;
+  UINT16                                    AcsControl;
+  UINT8                                     EgressControlVectorArray[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID   0x0007
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1
+
+typedef struct {
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER  Header;
+  UINT32                                    AssociationBitmap;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID    0x0008
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_VER1  0x1
+
+typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID   0x000B
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1
+
+typedef struct {
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER  Header;
+  UINT32                                    VendorSpecificHeader;
+  UINT8                                     VendorSpecific[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID   0x000A
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1
+
+typedef struct {
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER  Header;
+  UINT16                                    VendorId;
+  UINT16                                    DeviceId;
+  UINT32                                    RcrbCapabilities;
+  UINT32                                    RcrbControl;
+  UINT32                                    Reserved;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID   0x0012
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1
+
+typedef struct {
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER  Header;
+  UINT16                                    MultiCastCapability;
+  UINT16                                    MulticastControl;
+  UINT64                                    McBaseAddress;
+  UINT64                                    McReceiveAddress;
+  UINT64                                    McBlockAll;
+  UINT64                                    McBlockUntranslated;
+  UINT64                                    McOverlayBar;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID    0x0015
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_VER1  0x1
+
+typedef struct {
+  UINT32                                                 ResizableBarCapability;
+  UINT16                                                 ResizableBarControl;
+  UINT16                                                 Reserved;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY;
+
+typedef struct {
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER               Header;
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY  Capability[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR;
+
+#define GET_NUMBER_RESIZABLE_BARS(x) (((x->Capability[0].ResizableBarControl) & 0xE0) >> 5)
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID    0x000E
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1  0x1
+
+typedef struct {
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                Header;
+  UINT16                                                  AriCapability;
+  UINT16                                                  AriControl;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID    0x0016
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1  0x1
+
+typedef struct {
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                Header;
+  UINT32                                                  DpaCapability;
+  UINT32                                                  DpaLatencyIndicator;
+  UINT16                                                  DpaStatus;
+  UINT16                                                  DpaControl;
+  UINT8                                                   DpaPowerAllocationArray[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT16)(((POWER->DpaCapability)&0x0000000F))
+
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID    0x0018
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1  0x1
+
+typedef struct {
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                Header;
+  UINT16                                                  MaxSnoopLatency;
+  UINT16                                                  MaxNoSnoopLatency;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID    0x0017
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1  0x1
+
+typedef struct {
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                Header;
+  UINT32                                                  TphRequesterCapability;
+  UINT32                                                  TphRequesterControl;
+  UINT16                                                  TphStTable[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH;
+
+#define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PciExpress30.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PciExpress30.h
new file mode 100644
index 0000000000..5ab7feb8d6
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PciExpress30.h
@@ -0,0 +1,57 @@
+/** @file
+  Support for the PCI Express 3.0 standard.
+
+  This header file may not define all structures.  Please extend as required.
+
+  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+**/
+
+#ifndef _PCIEXPRESS30_H_
+#define _PCIEXPRESS30_H_
+
+#include <IndustryStandard/PciExpress21.h>
+
+#pragma pack(1)
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID    0x0019
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_VER1  0x1
+
+typedef union {
+  struct {
+    UINT32 PerformEqualization : 1;
+    UINT32 LinkEqualizationRequestInterruptEnable : 1;
+    UINT32 Reserved : 30;
+  } Bits;
+  UINT32   Uint32;
+} PCI_EXPRESS_REG_LINK_CONTROL3;
+
+typedef union {
+  struct {
+    UINT16 DownstreamPortTransmitterPreset : 4;
+    UINT16 DownstreamPortReceiverPresetHint : 3;
+    UINT16 Reserved : 1;
+    UINT16 UpstreamPortTransmitterPreset : 4;
+    UINT16 UpstreamPortReceiverPresetHint : 3;
+    UINT16 Reserved2 : 1;
+  } Bits;
+  UINT16   Uint16;
+} PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL;
+
+typedef struct {
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                Header;
+  PCI_EXPRESS_REG_LINK_CONTROL3                           LinkControl3;
+  UINT32                                                  LaneErrorStatus;
+  PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL               EqualizationControl[2];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PciExpress31.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PciExpress31.h
new file mode 100644
index 0000000000..72a3ccda81
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PciExpress31.h
@@ -0,0 +1,78 @@
+/** @file
+Support for the PCI Express 3.1 standard.
+
+This header file may not define all structures.  Please extend as required.
+
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCIEXPRESS31_H_
+#define _PCIEXPRESS31_H_
+
+#include <IndustryStandard/PciExpress30.h>
+
+#pragma pack(1)
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_ID    0x001E
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_VER1  0x1
+
+typedef union {
+  struct {
+    UINT32 PciPmL12 : 1;
+    UINT32 PciPmL11 : 1;
+    UINT32 AspmL12 : 1;
+    UINT32 AspmL11 : 1;
+    UINT32 L1PmSubstates : 1;
+    UINT32 Reserved : 3;
+    UINT32 CommonModeRestoreTime : 8;
+    UINT32 TPowerOnScale : 2;
+    UINT32 Reserved2 : 1;
+    UINT32 TPowerOnValue : 5;
+    UINT32 Reserved3 : 8;
+  } Bits;
+  UINT32   Uint32;
+} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY;
+
+typedef union {
+  struct {
+    UINT32 PciPmL12 : 1;
+    UINT32 PciPmL11 : 1;
+    UINT32 AspmL12 : 1;
+    UINT32 AspmL11 : 1;
+    UINT32 Reserved : 4;
+    UINT32 CommonModeRestoreTime : 8;
+    UINT32 LtrL12ThresholdValue : 10;
+    UINT32 Reserved2 : 3;
+    UINT32 LtrL12ThresholdScale : 3;
+  } Bits;
+  UINT32   Uint32;
+} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1;
+
+typedef union {
+  struct {
+    UINT32 TPowerOnScale : 2;
+    UINT32 Reserved : 1;
+    UINT32 TPowerOnValue : 5;
+    UINT32 Reserved2 : 24;
+  } Bits;
+  UINT32   Uint32;
+} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2;
+
+typedef struct {
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER   Header;
+  PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY Capability;
+  PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1   Control1;
+  PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2   Control2;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_L1_PM_SUBSTATES;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PeImage.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PeImage.h
new file mode 100644
index 0000000000..3af3edbd8e
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PeImage.h
@@ -0,0 +1,756 @@
+/** @file
+  EFI image format for PE32, PE32+ and TE. Please note some data structures are 
+  different for PE32 and PE32+. EFI_IMAGE_NT_HEADERS32 is for PE32 and 
+  EFI_IMAGE_NT_HEADERS64 is for PE32+. 
+
+  This file is coded to the Visual Studio, Microsoft Portable Executable and 
+  Common Object File Format Specification, Revision 8.3 - February 6, 2013.
+  This file also includes some definitions in PI Specification, Revision 1.0.
+
+Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+This program and the accompanying materials                          
+are licensed and made available under the terms and conditions of the BSD License         
+which accompanies this distribution.  The full text of the license may be found at        
+http://opensource.org/licenses/bsd-license.php.                                           
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+**/
+
+#ifndef __PE_IMAGE_H__
+#define __PE_IMAGE_H__
+
+//
+// PE32+ Subsystem type for EFI images
+//
+#define EFI_IMAGE_SUBSYSTEM_EFI_APPLICATION         10
+#define EFI_IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER 11
+#define EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER      12
+#define EFI_IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER      13 ///< defined PI Specification, 1.0
+
+
+//
+// PE32+ Machine type for EFI images
+//
+#define IMAGE_FILE_MACHINE_I386            0x014c
+#define IMAGE_FILE_MACHINE_IA64            0x0200
+#define IMAGE_FILE_MACHINE_EBC             0x0EBC
+#define IMAGE_FILE_MACHINE_X64             0x8664
+#define IMAGE_FILE_MACHINE_ARMTHUMB_MIXED  0x01c2
+#define IMAGE_FILE_MACHINE_ARM64           0xAA64
+
+//
+// EXE file formats
+//
+#define EFI_IMAGE_DOS_SIGNATURE     SIGNATURE_16('M', 'Z')
+#define EFI_IMAGE_OS2_SIGNATURE     SIGNATURE_16('N', 'E')
+#define EFI_IMAGE_OS2_SIGNATURE_LE  SIGNATURE_16('L', 'E')
+#define EFI_IMAGE_NT_SIGNATURE      SIGNATURE_32('P', 'E', '\0', '\0')
+
+///
+/// PE images can start with an optional DOS header, so if an image is run
+/// under DOS it can print an error message.
+///
+typedef struct {
+  UINT16  e_magic;    ///< Magic number.
+  UINT16  e_cblp;     ///< Bytes on last page of file.
+  UINT16  e_cp;       ///< Pages in file.
+  UINT16  e_crlc;     ///< Relocations.
+  UINT16  e_cparhdr;  ///< Size of header in paragraphs.
+  UINT16  e_minalloc; ///< Minimum extra paragraphs needed.
+  UINT16  e_maxalloc; ///< Maximum extra paragraphs needed.
+  UINT16  e_ss;       ///< Initial (relative) SS value.
+  UINT16  e_sp;       ///< Initial SP value.
+  UINT16  e_csum;     ///< Checksum.
+  UINT16  e_ip;       ///< Initial IP value.
+  UINT16  e_cs;       ///< Initial (relative) CS value.
+  UINT16  e_lfarlc;   ///< File address of relocation table.
+  UINT16  e_ovno;     ///< Overlay number.
+  UINT16  e_res[4];   ///< Reserved words.
+  UINT16  e_oemid;    ///< OEM identifier (for e_oeminfo).
+  UINT16  e_oeminfo;  ///< OEM information; e_oemid specific.
+  UINT16  e_res2[10]; ///< Reserved words.
+  UINT32  e_lfanew;   ///< File address of new exe header.
+} EFI_IMAGE_DOS_HEADER;
+
+///
+/// COFF File Header (Object and Image).
+///
+typedef struct {
+  UINT16  Machine;
+  UINT16  NumberOfSections;
+  UINT32  TimeDateStamp;
+  UINT32  PointerToSymbolTable;
+  UINT32  NumberOfSymbols;
+  UINT16  SizeOfOptionalHeader;
+  UINT16  Characteristics;
+} EFI_IMAGE_FILE_HEADER;
+
+///
+/// Size of EFI_IMAGE_FILE_HEADER.
+///
+#define EFI_IMAGE_SIZEOF_FILE_HEADER        20
+
+//
+// Characteristics
+//
+#define EFI_IMAGE_FILE_RELOCS_STRIPPED      BIT0     ///< 0x0001  Relocation info stripped from file.
+#define EFI_IMAGE_FILE_EXECUTABLE_IMAGE     BIT1     ///< 0x0002  File is executable  (i.e. no unresolved externel references).
+#define EFI_IMAGE_FILE_LINE_NUMS_STRIPPED   BIT2     ///< 0x0004  Line nunbers stripped from file.
+#define EFI_IMAGE_FILE_LOCAL_SYMS_STRIPPED  BIT3     ///< 0x0008  Local symbols stripped from file.
+#define EFI_IMAGE_FILE_BYTES_REVERSED_LO    BIT7     ///< 0x0080  Bytes of machine word are reversed.
+#define EFI_IMAGE_FILE_32BIT_MACHINE        BIT8     ///< 0x0100  32 bit word machine.
+#define EFI_IMAGE_FILE_DEBUG_STRIPPED       BIT9     ///< 0x0200  Debugging info stripped from file in .DBG file.
+#define EFI_IMAGE_FILE_SYSTEM               BIT12    ///< 0x1000  System File.
+#define EFI_IMAGE_FILE_DLL                  BIT13    ///< 0x2000  File is a DLL.
+#define EFI_IMAGE_FILE_BYTES_REVERSED_HI    BIT15    ///< 0x8000  Bytes of machine word are reversed.
+
+///
+/// Header Data Directories.
+///
+typedef struct {
+  UINT32  VirtualAddress;
+  UINT32  Size;
+} EFI_IMAGE_DATA_DIRECTORY;
+
+//
+// Directory Entries
+//
+#define EFI_IMAGE_DIRECTORY_ENTRY_EXPORT      0
+#define EFI_IMAGE_DIRECTORY_ENTRY_IMPORT      1
+#define EFI_IMAGE_DIRECTORY_ENTRY_RESOURCE    2
+#define EFI_IMAGE_DIRECTORY_ENTRY_EXCEPTION   3
+#define EFI_IMAGE_DIRECTORY_ENTRY_SECURITY    4
+#define EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC   5
+#define EFI_IMAGE_DIRECTORY_ENTRY_DEBUG       6
+#define EFI_IMAGE_DIRECTORY_ENTRY_COPYRIGHT   7
+#define EFI_IMAGE_DIRECTORY_ENTRY_GLOBALPTR   8
+#define EFI_IMAGE_DIRECTORY_ENTRY_TLS         9
+#define EFI_IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG 10
+
+#define EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES 16
+
+///
+/// @attention
+/// EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC means PE32 and 
+/// EFI_IMAGE_OPTIONAL_HEADER32 must be used. The data structures only vary
+/// after NT additional fields.
+///
+#define EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC 0x10b
+          
+///
+/// Optional Header Standard Fields for PE32.
+///
+typedef struct {
+  ///
+  /// Standard fields.
+  ///
+  UINT16                    Magic;
+  UINT8                     MajorLinkerVersion;
+  UINT8                     MinorLinkerVersion;
+  UINT32                    SizeOfCode;
+  UINT32                    SizeOfInitializedData;
+  UINT32                    SizeOfUninitializedData;
+  UINT32                    AddressOfEntryPoint;
+  UINT32                    BaseOfCode;
+  UINT32                    BaseOfData;  ///< PE32 contains this additional field, which is absent in PE32+.
+  ///
+  /// Optional Header Windows-Specific Fields.
+  ///
+  UINT32                    ImageBase;
+  UINT32                    SectionAlignment;
+  UINT32                    FileAlignment;
+  UINT16                    MajorOperatingSystemVersion;
+  UINT16                    MinorOperatingSystemVersion;
+  UINT16                    MajorImageVersion;
+  UINT16                    MinorImageVersion;
+  UINT16                    MajorSubsystemVersion;
+  UINT16                    MinorSubsystemVersion;
+  UINT32                    Win32VersionValue;
+  UINT32                    SizeOfImage;
+  UINT32                    SizeOfHeaders;
+  UINT32                    CheckSum;
+  UINT16                    Subsystem;
+  UINT16                    DllCharacteristics;
+  UINT32                    SizeOfStackReserve;
+  UINT32                    SizeOfStackCommit;
+  UINT32                    SizeOfHeapReserve;
+  UINT32                    SizeOfHeapCommit;
+  UINT32                    LoaderFlags;
+  UINT32                    NumberOfRvaAndSizes;
+  EFI_IMAGE_DATA_DIRECTORY  DataDirectory[EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES];
+} EFI_IMAGE_OPTIONAL_HEADER32;
+
+///
+/// @attention
+/// EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC means PE32+ and 
+/// EFI_IMAGE_OPTIONAL_HEADER64 must be used. The data structures only vary
+/// after NT additional fields.
+///
+#define EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC 0x20b
+
+///
+/// Optional Header Standard Fields for PE32+.
+///
+typedef struct {
+  ///
+  /// Standard fields.
+  ///
+  UINT16                    Magic;
+  UINT8                     MajorLinkerVersion;
+  UINT8                     MinorLinkerVersion;
+  UINT32                    SizeOfCode;
+  UINT32                    SizeOfInitializedData;
+  UINT32                    SizeOfUninitializedData;
+  UINT32                    AddressOfEntryPoint;
+  UINT32                    BaseOfCode;
+  ///
+  /// Optional Header Windows-Specific Fields.
+  ///
+  UINT64                    ImageBase;
+  UINT32                    SectionAlignment;
+  UINT32                    FileAlignment;
+  UINT16                    MajorOperatingSystemVersion;
+  UINT16                    MinorOperatingSystemVersion;
+  UINT16                    MajorImageVersion;
+  UINT16                    MinorImageVersion;
+  UINT16                    MajorSubsystemVersion;
+  UINT16                    MinorSubsystemVersion;
+  UINT32                    Win32VersionValue;
+  UINT32                    SizeOfImage;
+  UINT32                    SizeOfHeaders;
+  UINT32                    CheckSum;
+  UINT16                    Subsystem;
+  UINT16                    DllCharacteristics;
+  UINT64                    SizeOfStackReserve;
+  UINT64                    SizeOfStackCommit;
+  UINT64                    SizeOfHeapReserve;
+  UINT64                    SizeOfHeapCommit;
+  UINT32                    LoaderFlags;
+  UINT32                    NumberOfRvaAndSizes;
+  EFI_IMAGE_DATA_DIRECTORY  DataDirectory[EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES];
+} EFI_IMAGE_OPTIONAL_HEADER64;
+
+
+///
+/// @attention
+/// EFI_IMAGE_NT_HEADERS32 is for use ONLY by tools.
+///
+typedef struct {
+  UINT32                      Signature;
+  EFI_IMAGE_FILE_HEADER       FileHeader;
+  EFI_IMAGE_OPTIONAL_HEADER32 OptionalHeader;
+} EFI_IMAGE_NT_HEADERS32;
+
+#define EFI_IMAGE_SIZEOF_NT_OPTIONAL32_HEADER sizeof (EFI_IMAGE_NT_HEADERS32)
+
+///
+/// @attention
+/// EFI_IMAGE_HEADERS64 is for use ONLY by tools.
+///
+typedef struct {
+  UINT32                      Signature;
+  EFI_IMAGE_FILE_HEADER       FileHeader;
+  EFI_IMAGE_OPTIONAL_HEADER64 OptionalHeader;
+} EFI_IMAGE_NT_HEADERS64;
+
+#define EFI_IMAGE_SIZEOF_NT_OPTIONAL64_HEADER sizeof (EFI_IMAGE_NT_HEADERS64)
+
+//
+// Other Windows Subsystem Values
+//
+#define EFI_IMAGE_SUBSYSTEM_UNKNOWN     0
+#define EFI_IMAGE_SUBSYSTEM_NATIVE      1
+#define EFI_IMAGE_SUBSYSTEM_WINDOWS_GUI 2
+#define EFI_IMAGE_SUBSYSTEM_WINDOWS_CUI 3
+#define EFI_IMAGE_SUBSYSTEM_OS2_CUI     5
+#define EFI_IMAGE_SUBSYSTEM_POSIX_CUI   7
+
+///
+/// Length of ShortName.
+///
+#define EFI_IMAGE_SIZEOF_SHORT_NAME 8
+
+///
+/// Section Table. This table immediately follows the optional header.
+///
+typedef struct {
+  UINT8 Name[EFI_IMAGE_SIZEOF_SHORT_NAME];
+  union {
+    UINT32  PhysicalAddress;
+    UINT32  VirtualSize;
+  } Misc;
+  UINT32  VirtualAddress;
+  UINT32  SizeOfRawData;
+  UINT32  PointerToRawData;
+  UINT32  PointerToRelocations;
+  UINT32  PointerToLinenumbers;
+  UINT16  NumberOfRelocations;
+  UINT16  NumberOfLinenumbers;
+  UINT32  Characteristics;
+} EFI_IMAGE_SECTION_HEADER;
+
+///
+/// Size of EFI_IMAGE_SECTION_HEADER.
+///
+#define EFI_IMAGE_SIZEOF_SECTION_HEADER       40
+         
+//
+// Section Flags Values
+//
+#define EFI_IMAGE_SCN_TYPE_NO_PAD                  BIT3   ///< 0x00000008  ///< Reserved.
+#define EFI_IMAGE_SCN_CNT_CODE                     BIT5   ///< 0x00000020
+#define EFI_IMAGE_SCN_CNT_INITIALIZED_DATA         BIT6   ///< 0x00000040
+#define EFI_IMAGE_SCN_CNT_UNINITIALIZED_DATA       BIT7   ///< 0x00000080
+                                                   
+#define EFI_IMAGE_SCN_LNK_OTHER                    BIT8   ///< 0x00000100  ///< Reserved.
+#define EFI_IMAGE_SCN_LNK_INFO                     BIT9   ///< 0x00000200  ///< Section contains comments or some other type of information.
+#define EFI_IMAGE_SCN_LNK_REMOVE                   BIT11  ///< 0x00000800  ///< Section contents will not become part of image.
+#define EFI_IMAGE_SCN_LNK_COMDAT                   BIT12  ///< 0x00001000
+                                                   
+#define EFI_IMAGE_SCN_ALIGN_1BYTES                 BIT20  ///< 0x00100000
+#define EFI_IMAGE_SCN_ALIGN_2BYTES                 BIT21  ///< 0x00200000
+#define EFI_IMAGE_SCN_ALIGN_4BYTES          (BIT20|BIT21) ///< 0x00300000
+#define EFI_IMAGE_SCN_ALIGN_8BYTES                 BIT22  ///< 0x00400000
+#define EFI_IMAGE_SCN_ALIGN_16BYTES         (BIT20|BIT22) ///< 0x00500000
+#define EFI_IMAGE_SCN_ALIGN_32BYTES         (BIT21|BIT22) ///< 0x00600000
+#define EFI_IMAGE_SCN_ALIGN_64BYTES   (BIT20|BIT21|BIT22) ///< 0x00700000
+                                              
+#define EFI_IMAGE_SCN_MEM_DISCARDABLE              BIT25  ///< 0x02000000
+#define EFI_IMAGE_SCN_MEM_NOT_CACHED               BIT26  ///< 0x04000000
+#define EFI_IMAGE_SCN_MEM_NOT_PAGED                BIT27  ///< 0x08000000
+#define EFI_IMAGE_SCN_MEM_SHARED                   BIT28  ///< 0x10000000
+#define EFI_IMAGE_SCN_MEM_EXECUTE                  BIT29  ///< 0x20000000
+#define EFI_IMAGE_SCN_MEM_READ                     BIT30  ///< 0x40000000
+#define EFI_IMAGE_SCN_MEM_WRITE                    BIT31  ///< 0x80000000
+
+///
+/// Size of a Symbol Table Record.
+///
+#define EFI_IMAGE_SIZEOF_SYMBOL 18
+
+//
+// Symbols have a section number of the section in which they are
+// defined. Otherwise, section numbers have the following meanings:
+//
+#define EFI_IMAGE_SYM_UNDEFINED (UINT16) 0  ///< Symbol is undefined or is common.
+#define EFI_IMAGE_SYM_ABSOLUTE  (UINT16) -1 ///< Symbol is an absolute value.
+#define EFI_IMAGE_SYM_DEBUG     (UINT16) -2 ///< Symbol is a special debug item.
+
+//
+// Symbol Type (fundamental) values.
+//
+#define EFI_IMAGE_SYM_TYPE_NULL   0   ///< no type.
+#define EFI_IMAGE_SYM_TYPE_VOID   1   ///< no valid type.
+#define EFI_IMAGE_SYM_TYPE_CHAR   2   ///< type character.
+#define EFI_IMAGE_SYM_TYPE_SHORT  3   ///< type short integer.
+#define EFI_IMAGE_SYM_TYPE_INT    4
+#define EFI_IMAGE_SYM_TYPE_LONG   5
+#define EFI_IMAGE_SYM_TYPE_FLOAT  6
+#define EFI_IMAGE_SYM_TYPE_DOUBLE 7
+#define EFI_IMAGE_SYM_TYPE_STRUCT 8
+#define EFI_IMAGE_SYM_TYPE_UNION  9
+#define EFI_IMAGE_SYM_TYPE_ENUM   10  ///< enumeration.
+#define EFI_IMAGE_SYM_TYPE_MOE    11  ///< member of enumeration.
+#define EFI_IMAGE_SYM_TYPE_BYTE   12
+#define EFI_IMAGE_SYM_TYPE_WORD   13
+#define EFI_IMAGE_SYM_TYPE_UINT   14
+#define EFI_IMAGE_SYM_TYPE_DWORD  15
+
+//
+// Symbol Type (derived) values.
+//
+#define EFI_IMAGE_SYM_DTYPE_NULL      0 ///< no derived type.
+#define EFI_IMAGE_SYM_DTYPE_POINTER   1
+#define EFI_IMAGE_SYM_DTYPE_FUNCTION  2
+#define EFI_IMAGE_SYM_DTYPE_ARRAY     3
+
+//
+// Storage classes.
+//
+#define EFI_IMAGE_SYM_CLASS_END_OF_FUNCTION   ((UINT8) -1)
+#define EFI_IMAGE_SYM_CLASS_NULL              0
+#define EFI_IMAGE_SYM_CLASS_AUTOMATIC         1
+#define EFI_IMAGE_SYM_CLASS_EXTERNAL          2
+#define EFI_IMAGE_SYM_CLASS_STATIC            3
+#define EFI_IMAGE_SYM_CLASS_REGISTER          4
+#define EFI_IMAGE_SYM_CLASS_EXTERNAL_DEF      5
+#define EFI_IMAGE_SYM_CLASS_LABEL             6
+#define EFI_IMAGE_SYM_CLASS_UNDEFINED_LABEL   7
+#define EFI_IMAGE_SYM_CLASS_MEMBER_OF_STRUCT  8
+#define EFI_IMAGE_SYM_CLASS_ARGUMENT          9
+#define EFI_IMAGE_SYM_CLASS_STRUCT_TAG        10
+#define EFI_IMAGE_SYM_CLASS_MEMBER_OF_UNION   11
+#define EFI_IMAGE_SYM_CLASS_UNION_TAG         12
+#define EFI_IMAGE_SYM_CLASS_TYPE_DEFINITION   13
+#define EFI_IMAGE_SYM_CLASS_UNDEFINED_STATIC  14
+#define EFI_IMAGE_SYM_CLASS_ENUM_TAG          15
+#define EFI_IMAGE_SYM_CLASS_MEMBER_OF_ENUM    16
+#define EFI_IMAGE_SYM_CLASS_REGISTER_PARAM    17
+#define EFI_IMAGE_SYM_CLASS_BIT_FIELD         18
+#define EFI_IMAGE_SYM_CLASS_BLOCK             100
+#define EFI_IMAGE_SYM_CLASS_FUNCTION          101
+#define EFI_IMAGE_SYM_CLASS_END_OF_STRUCT     102
+#define EFI_IMAGE_SYM_CLASS_FILE              103
+#define EFI_IMAGE_SYM_CLASS_SECTION           104
+#define EFI_IMAGE_SYM_CLASS_WEAK_EXTERNAL     105
+
+//
+// type packing constants
+//
+#define EFI_IMAGE_N_BTMASK  017
+#define EFI_IMAGE_N_TMASK   060
+#define EFI_IMAGE_N_TMASK1  0300
+#define EFI_IMAGE_N_TMASK2  0360
+#define EFI_IMAGE_N_BTSHFT  4
+#define EFI_IMAGE_N_TSHIFT  2
+
+//
+// Communal selection types.
+//
+#define EFI_IMAGE_COMDAT_SELECT_NODUPLICATES    1
+#define EFI_IMAGE_COMDAT_SELECT_ANY             2
+#define EFI_IMAGE_COMDAT_SELECT_SAME_SIZE       3
+#define EFI_IMAGE_COMDAT_SELECT_EXACT_MATCH     4
+#define EFI_IMAGE_COMDAT_SELECT_ASSOCIATIVE     5
+                                       
+//
+// the following values only be referred in PeCoff, not defined in PECOFF.
+//
+#define EFI_IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY  1
+#define EFI_IMAGE_WEAK_EXTERN_SEARCH_LIBRARY    2
+#define EFI_IMAGE_WEAK_EXTERN_SEARCH_ALIAS      3
+
+///
+/// Relocation format.
+///
+typedef struct {
+  UINT32  VirtualAddress;
+  UINT32  SymbolTableIndex;
+  UINT16  Type;
+} EFI_IMAGE_RELOCATION;
+
+///
+/// Size of EFI_IMAGE_RELOCATION
+///
+#define EFI_IMAGE_SIZEOF_RELOCATION 10
+
+//
+// I386 relocation types.
+//
+#define EFI_IMAGE_REL_I386_ABSOLUTE 0x0000  ///< Reference is absolute, no relocation is necessary.
+#define EFI_IMAGE_REL_I386_DIR16    0x0001  ///< Direct 16-bit reference to the symbols virtual address.
+#define EFI_IMAGE_REL_I386_REL16    0x0002  ///< PC-relative 16-bit reference to the symbols virtual address.
+#define EFI_IMAGE_REL_I386_DIR32    0x0006  ///< Direct 32-bit reference to the symbols virtual address.
+#define EFI_IMAGE_REL_I386_DIR32NB  0x0007  ///< Direct 32-bit reference to the symbols virtual address, base not included.
+#define EFI_IMAGE_REL_I386_SEG12    0x0009  ///< Direct 16-bit reference to the segment-selector bits of a 32-bit virtual address.
+#define EFI_IMAGE_REL_I386_SECTION  0x000A
+#define EFI_IMAGE_REL_I386_SECREL   0x000B
+#define EFI_IMAGE_REL_I386_REL32    0x0014  ///< PC-relative 32-bit reference to the symbols virtual address.
+
+// 
+// x64 processor relocation types.
+// 
+#define IMAGE_REL_AMD64_ABSOLUTE  0x0000
+#define IMAGE_REL_AMD64_ADDR64    0x0001
+#define IMAGE_REL_AMD64_ADDR32    0x0002
+#define IMAGE_REL_AMD64_ADDR32NB  0x0003
+#define IMAGE_REL_AMD64_REL32     0x0004
+#define IMAGE_REL_AMD64_REL32_1   0x0005
+#define IMAGE_REL_AMD64_REL32_2   0x0006
+#define IMAGE_REL_AMD64_REL32_3   0x0007
+#define IMAGE_REL_AMD64_REL32_4   0x0008
+#define IMAGE_REL_AMD64_REL32_5   0x0009
+#define IMAGE_REL_AMD64_SECTION   0x000A
+#define IMAGE_REL_AMD64_SECREL    0x000B
+#define IMAGE_REL_AMD64_SECREL7   0x000C
+#define IMAGE_REL_AMD64_TOKEN     0x000D
+#define IMAGE_REL_AMD64_SREL32    0x000E
+#define IMAGE_REL_AMD64_PAIR      0x000F
+#define IMAGE_REL_AMD64_SSPAN32   0x0010
+
+///
+/// Based relocation format.
+///
+typedef struct {
+  UINT32  VirtualAddress;
+  UINT32  SizeOfBlock;
+} EFI_IMAGE_BASE_RELOCATION;
+
+///
+/// Size of EFI_IMAGE_BASE_RELOCATION.
+///
+#define EFI_IMAGE_SIZEOF_BASE_RELOCATION  8
+
+//
+// Based relocation types.
+//
+#define EFI_IMAGE_REL_BASED_ABSOLUTE        0
+#define EFI_IMAGE_REL_BASED_HIGH            1
+#define EFI_IMAGE_REL_BASED_LOW             2
+#define EFI_IMAGE_REL_BASED_HIGHLOW         3
+#define EFI_IMAGE_REL_BASED_HIGHADJ         4
+#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR    5
+#define EFI_IMAGE_REL_BASED_ARM_MOV32A      5
+#define EFI_IMAGE_REL_BASED_ARM_MOV32T      7
+#define EFI_IMAGE_REL_BASED_IA64_IMM64      9
+#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR16  9
+#define EFI_IMAGE_REL_BASED_DIR64           10
+
+///
+/// Line number format.
+///
+typedef struct {
+  union {
+    UINT32  SymbolTableIndex; ///< Symbol table index of function name if Linenumber is 0.
+    UINT32  VirtualAddress;   ///< Virtual address of line number.
+  } Type;
+  UINT16  Linenumber;         ///< Line number.
+} EFI_IMAGE_LINENUMBER;
+
+///
+/// Size of EFI_IMAGE_LINENUMBER.
+///
+#define EFI_IMAGE_SIZEOF_LINENUMBER 6
+
+//
+// Archive format.
+//
+#define EFI_IMAGE_ARCHIVE_START_SIZE        8
+#define EFI_IMAGE_ARCHIVE_START             "!<arch>\n"
+#define EFI_IMAGE_ARCHIVE_END               "`\n"
+#define EFI_IMAGE_ARCHIVE_PAD               "\n"
+#define EFI_IMAGE_ARCHIVE_LINKER_MEMBER     "/               "
+#define EFI_IMAGE_ARCHIVE_LONGNAMES_MEMBER  "//              "
+
+///
+/// Archive Member Headers
+///
+typedef struct {
+  UINT8 Name[16];     ///< File member name - `/' terminated.
+  UINT8 Date[12];     ///< File member date - decimal.
+  UINT8 UserID[6];    ///< File member user id - decimal.
+  UINT8 GroupID[6];   ///< File member group id - decimal.
+  UINT8 Mode[8];      ///< File member mode - octal.
+  UINT8 Size[10];     ///< File member size - decimal.
+  UINT8 EndHeader[2]; ///< String to end header. (0x60 0x0A).
+} EFI_IMAGE_ARCHIVE_MEMBER_HEADER;
+
+///
+/// Size of EFI_IMAGE_ARCHIVE_MEMBER_HEADER.
+///
+#define EFI_IMAGE_SIZEOF_ARCHIVE_MEMBER_HDR 60
+
+
+//
+// DLL Support
+//
+
+///
+/// Export Directory Table.
+///
+typedef struct {
+  UINT32  Characteristics;
+  UINT32  TimeDateStamp;
+  UINT16  MajorVersion;
+  UINT16  MinorVersion;
+  UINT32  Name;
+  UINT32  Base;
+  UINT32  NumberOfFunctions;
+  UINT32  NumberOfNames;
+  UINT32  AddressOfFunctions;
+  UINT32  AddressOfNames;
+  UINT32  AddressOfNameOrdinals;
+} EFI_IMAGE_EXPORT_DIRECTORY;
+
+///
+/// Hint/Name Table.
+///
+typedef struct {
+  UINT16  Hint;
+  UINT8   Name[1];
+} EFI_IMAGE_IMPORT_BY_NAME;
+
+///
+/// Import Address Table RVA (Thunk Table).
+///
+typedef struct {
+  union {
+    UINT32                    Function;
+    UINT32                    Ordinal;
+    EFI_IMAGE_IMPORT_BY_NAME  *AddressOfData;
+  } u1;
+} EFI_IMAGE_THUNK_DATA;
+
+#define EFI_IMAGE_ORDINAL_FLAG              BIT31    ///< Flag for PE32.
+#define EFI_IMAGE_SNAP_BY_ORDINAL(Ordinal)  ((Ordinal & EFI_IMAGE_ORDINAL_FLAG) != 0)
+#define EFI_IMAGE_ORDINAL(Ordinal)          (Ordinal & 0xffff)
+
+///
+/// Import Directory Table
+///
+typedef struct {
+  UINT32                Characteristics;
+  UINT32                TimeDateStamp;
+  UINT32                ForwarderChain;
+  UINT32                Name;
+  EFI_IMAGE_THUNK_DATA  *FirstThunk;
+} EFI_IMAGE_IMPORT_DESCRIPTOR;
+
+
+///
+/// Debug Directory Format.
+///
+typedef struct {
+  UINT32  Characteristics;
+  UINT32  TimeDateStamp;
+  UINT16  MajorVersion;
+  UINT16  MinorVersion;
+  UINT32  Type;
+  UINT32  SizeOfData;
+  UINT32  RVA;           ///< The address of the debug data when loaded, relative to the image base.
+  UINT32  FileOffset;    ///< The file pointer to the debug data.
+} EFI_IMAGE_DEBUG_DIRECTORY_ENTRY;
+
+#define EFI_IMAGE_DEBUG_TYPE_CODEVIEW 2     ///< The Visual C++ debug information.
+
+///
+/// Debug Data Structure defined in Microsoft C++.
+///
+#define CODEVIEW_SIGNATURE_NB10  SIGNATURE_32('N', 'B', '1', '0')
+typedef struct {
+  UINT32  Signature;                        ///< "NB10"
+  UINT32  Unknown;
+  UINT32  Unknown2;
+  UINT32  Unknown3;
+  //
+  // Filename of .PDB goes here
+  //
+} EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY;
+
+///
+/// Debug Data Structure defined in Microsoft C++.
+///
+#define CODEVIEW_SIGNATURE_RSDS  SIGNATURE_32('R', 'S', 'D', 'S')
+typedef struct {
+  UINT32  Signature;                        ///< "RSDS".
+  UINT32  Unknown;
+  UINT32  Unknown2;
+  UINT32  Unknown3;
+  UINT32  Unknown4;
+  UINT32  Unknown5;
+  //
+  // Filename of .PDB goes here
+  //
+} EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY;
+
+
+///
+/// Debug Data Structure defined by Apple Mach-O to Coff utility.
+///
+#define CODEVIEW_SIGNATURE_MTOC  SIGNATURE_32('M', 'T', 'O', 'C')
+typedef struct {
+  UINT32    Signature;                       ///< "MTOC".
+  GUID      MachOUuid;
+  //
+  //  Filename of .DLL (Mach-O with debug info) goes here
+  //
+} EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY;
+
+///
+/// Resource format.
+///
+typedef struct {
+  UINT32  Characteristics;
+  UINT32  TimeDateStamp;
+  UINT16  MajorVersion;
+  UINT16  MinorVersion;
+  UINT16  NumberOfNamedEntries;
+  UINT16  NumberOfIdEntries;
+  //
+  // Array of EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY entries goes here.
+  //
+} EFI_IMAGE_RESOURCE_DIRECTORY;
+
+///
+/// Resource directory entry format.
+///
+typedef struct {
+  union {
+    struct {
+      UINT32  NameOffset:31;
+      UINT32  NameIsString:1;
+    } s;
+    UINT32  Id;
+  } u1;
+  union {
+    UINT32  OffsetToData;
+    struct {
+      UINT32  OffsetToDirectory:31;
+      UINT32  DataIsDirectory:1;
+    } s;
+  } u2;
+} EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY;
+
+///
+/// Resource directory entry for string.
+///
+typedef struct {
+  UINT16  Length;
+  CHAR16  String[1];
+} EFI_IMAGE_RESOURCE_DIRECTORY_STRING;
+
+///
+/// Resource directory entry for data array.
+///
+typedef struct {
+  UINT32  OffsetToData;
+  UINT32  Size;
+  UINT32  CodePage;
+  UINT32  Reserved;
+} EFI_IMAGE_RESOURCE_DATA_ENTRY;
+
+///
+/// Header format for TE images, defined in the PI Specification, 1.0.
+///
+typedef struct {
+  UINT16                    Signature;            ///< The signature for TE format = "VZ".
+  UINT16                    Machine;              ///< From the original file header.
+  UINT8                     NumberOfSections;     ///< From the original file header.
+  UINT8                     Subsystem;            ///< From original optional header.
+  UINT16                    StrippedSize;         ///< Number of bytes we removed from the header.
+  UINT32                    AddressOfEntryPoint;  ///< Offset to entry point -- from original optional header.
+  UINT32                    BaseOfCode;           ///< From original image -- required for ITP debug.
+  UINT64                    ImageBase;            ///< From original file header.
+  EFI_IMAGE_DATA_DIRECTORY  DataDirectory[2];     ///< Only base relocation and debug directory.
+} EFI_TE_IMAGE_HEADER;
+
+
+#define EFI_TE_IMAGE_HEADER_SIGNATURE  SIGNATURE_16('V', 'Z')
+
+//
+// Data directory indexes in our TE image header
+//
+#define EFI_TE_IMAGE_DIRECTORY_ENTRY_BASERELOC  0
+#define EFI_TE_IMAGE_DIRECTORY_ENTRY_DEBUG      1
+
+
+///
+/// Union of PE32, PE32+, and TE headers.
+///
+typedef union {
+  EFI_IMAGE_NT_HEADERS32   Pe32;
+  EFI_IMAGE_NT_HEADERS64   Pe32Plus;
+  EFI_TE_IMAGE_HEADER      Te;
+} EFI_IMAGE_OPTIONAL_HEADER_UNION;
+
+typedef union {
+  EFI_IMAGE_NT_HEADERS32            *Pe32;
+  EFI_IMAGE_NT_HEADERS64            *Pe32Plus;
+  EFI_TE_IMAGE_HEADER               *Te;
+  EFI_IMAGE_OPTIONAL_HEADER_UNION   *Union;
+} EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Sal.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Sal.h
new file mode 100644
index 0000000000..cda4e28bcd
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Sal.h
@@ -0,0 +1,915 @@
+/** @file
+  Main SAL API's defined in Intel Itanium Processor Family System Abstraction
+  Layer Specification Revision 3.2 (December 2003)
+
+Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under 
+the terms and conditions of the BSD License that accompanies this distribution.  
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.                                          
+    
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+**/
+
+#ifndef __SAL_API_H__
+#define __SAL_API_H__
+
+///
+/// SAL return status type 
+///
+typedef INTN EFI_SAL_STATUS;
+
+///
+/// Call completed without error. 
+///
+#define EFI_SAL_SUCCESS               ((EFI_SAL_STATUS) 0)
+///
+/// Call completed without error, but some information was lost due to overflow. 
+///
+#define EFI_SAL_OVERFLOW              ((EFI_SAL_STATUS) 1)
+///
+/// Call completed without error; effect a warm boot of the system to complete the update.
+///
+#define EFI_SAL_WARM_BOOT_NEEDED      ((EFI_SAL_STATUS) 2)
+///
+/// More information is available for retrieval. 
+///
+#define EFI_SAL_MORE_RECORDS          ((EFI_SAL_STATUS) 3)
+///
+/// Not implemented.
+///
+#define EFI_SAL_NOT_IMPLEMENTED       ((EFI_SAL_STATUS) - 1)
+///
+/// Invalid Argument.
+///
+#define EFI_SAL_INVALID_ARGUMENT      ((EFI_SAL_STATUS) - 2)
+///
+/// Call completed without error. 
+///
+#define EFI_SAL_ERROR                 ((EFI_SAL_STATUS) - 3)
+///
+/// Virtual address not registered. 
+///
+#define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)
+///
+/// No information available. 
+///
+#define EFI_SAL_NO_INFORMATION        ((EFI_SAL_STATUS) - 5)
+///
+/// Scratch buffer required.
+///
+#define EFI_SAL_NOT_ENOUGH_SCRATCH    ((EFI_SAL_STATUS) - 9)
+
+///
+/// Return registers from SAL.
+///
+typedef struct {
+  ///
+  /// SAL return status value in r8.
+  ///
+  EFI_SAL_STATUS  Status;
+  ///
+  /// SAL returned value in r9.
+  ///
+  UINTN           r9;
+  ///
+  /// SAL returned value in r10.
+  ///
+  UINTN           r10;
+  ///
+  /// SAL returned value in r11.
+  ///
+  UINTN           r11;
+} SAL_RETURN_REGS;
+
+/**
+  Prototype of SAL procedures.
+
+  @param  FunctionId         Functional identifier.
+                             The upper 32 bits are ignored and only the lower 32 bits
+                             are used. The following functional identifiers are defined:
+                             0x01XXXXXX - Architected SAL functional group.
+                             0x02XXXXXX to 0x03XXXXXX - OEM SAL functional group. Each OEM is
+                             allowed to use the entire range in the 0x02XXXXXX to 0x03XXXXXX range.
+                             0x04XXXXXX to 0xFFFFFFFF - Reserved.
+  @param  Arg1               The first parameter of the architected/OEM specific SAL functions.
+  @param  Arg2               The second parameter of the architected/OEM specific SAL functions.
+  @param  Arg3               The third parameter passed to the ESAL function based.
+  @param  Arg4               The fourth parameter passed to the ESAL function based.
+  @param  Arg5               The fifth parameter passed to the ESAL function based.
+  @param  Arg6               The sixth parameter passed to the ESAL function.
+  @param  Arg7               The seventh parameter passed to the ESAL function based.
+
+  @return r8                 Return status: positive number indicates successful,
+                             negative number indicates failure.
+          r9                 Other return parameter in r9.
+          r10                Other return parameter in r10.
+          r11                Other return parameter in r11.
+
+**/
+typedef
+SAL_RETURN_REGS
+(EFIAPI *SAL_PROC)(
+  IN UINT64 FunctionId,
+  IN UINT64 Arg1,
+  IN UINT64 Arg2,
+  IN UINT64 Arg3,
+  IN UINT64 Arg4,
+  IN UINT64 Arg5,
+  IN UINT64 Arg6,
+  IN UINT64 Arg7
+  );
+
+//
+// SAL Procedure FunctionId definition
+//
+
+///
+/// Register software code locations with SAL.
+///
+#define EFI_SAL_SET_VECTORS             0x01000000
+///
+/// Return Machine State information obtained by SAL.
+///
+#define EFI_SAL_GET_STATE_INFO          0x01000001
+///
+/// Obtain size of Machine State information.
+///
+#define EFI_SAL_GET_STATE_INFO_SIZE     0x01000002
+///
+/// Clear Machine State information.
+///
+#define EFI_SAL_CLEAR_STATE_INFO        0x01000003
+///
+/// Cause the processor to go into a spin loop within SAL.
+///
+#define EFI_SAL_MC_RENDEZ               0x01000004
+///
+/// Register the machine check interface layer with SAL.
+///
+#define EFI_SAL_MC_SET_PARAMS           0x01000005
+///
+/// Register the physical addresses of locations needed by SAL.
+///
+#define EFI_SAL_REGISTER_PHYSICAL_ADDR  0x01000006
+///
+/// Flush the instruction or data caches.
+///
+#define EFI_SAL_CACHE_FLUSH             0x01000008
+///
+/// Initialize the instruction and data caches.
+///
+#define EFI_SAL_CACHE_INIT              0x01000009
+///
+/// Read from the PCI configuration space.
+///
+#define EFI_SAL_PCI_CONFIG_READ         0x01000010
+///
+/// Write to the PCI configuration space.
+///
+#define EFI_SAL_PCI_CONFIG_WRITE        0x01000011
+///
+/// Return the base frequency of the platform.
+///
+#define EFI_SAL_FREQ_BASE               0x01000012
+///
+/// Returns information on the physical processor mapping within the platform.
+///
+#define EFI_SAL_PHYSICAL_ID_INFO        0x01000013
+///
+/// Update the contents of firmware blocks.
+///
+#define EFI_SAL_UPDATE_PAL              0x01000020
+
+#define EFI_SAL_FUNCTION_ID_MASK        0x0000ffff
+#define EFI_SAL_MAX_SAL_FUNCTION_ID     0x00000021
+
+//
+// SAL Procedure parameter definitions
+// Not much point in using typedefs or enums because all params
+// are UINT64 and the entry point is common
+//
+
+//
+// Parameter of EFI_SAL_SET_VECTORS
+//
+// Vector type
+//
+#define EFI_SAL_SET_MCA_VECTOR          0x0
+#define EFI_SAL_SET_INIT_VECTOR         0x1
+#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR  0x2
+///
+/// The format of a length_cs_n argument.
+///
+typedef struct {
+  UINT64  Length : 32;
+  UINT64  ChecksumValid : 1;
+  UINT64  Reserved1 : 7;
+  UINT64  ByteChecksum : 8;
+  UINT64  Reserved2 : 16;
+} SAL_SET_VECTORS_CS_N;
+
+//
+// Parameter of EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE, and EFI_SAL_CLEAR_STATE_INFO
+// 
+// Type of information
+//
+#define EFI_SAL_MCA_STATE_INFO  0x0
+#define EFI_SAL_INIT_STATE_INFO 0x1
+#define EFI_SAL_CMC_STATE_INFO  0x2
+#define EFI_SAL_CP_STATE_INFO   0x3
+
+//
+// Parameter of EFI_SAL_MC_SET_PARAMS
+//
+// Unsigned 64-bit integer value for the parameter type of the machine check interface
+//
+#define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1
+#define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2
+#define EFI_SAL_MC_SET_CPE_PARAM    0x3
+//
+// Unsigned 64-bit integer value indicating whether interrupt vector or
+// memory address is specified
+//
+#define EFI_SAL_MC_SET_INTR_PARAM   0x1
+#define EFI_SAL_MC_SET_MEM_PARAM    0x2
+
+//
+// Parameter of EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR
+//
+// The encoded value of the entity whose physical address is registered
+//
+#define EFI_SAL_REGISTER_PAL_ADDR 0x0
+
+//
+// Parameter of EFI_SAL_CACHE_FLUSH
+//
+// Unsigned 64-bit integer denoting type of cache flush operation
+//
+#define EFI_SAL_FLUSH_I_CACHE       0x01
+#define EFI_SAL_FLUSH_D_CACHE       0x02
+#define EFI_SAL_FLUSH_BOTH_CACHE    0x03
+#define EFI_SAL_FLUSH_MAKE_COHERENT 0x04
+
+//
+// Parameter of EFI_SAL_PCI_CONFIG_READ and EFI_SAL_PCI_CONFIG_WRITE
+//
+// PCI config size
+//
+#define EFI_SAL_PCI_CONFIG_ONE_BYTE   0x1
+#define EFI_SAL_PCI_CONFIG_TWO_BYTES  0x2
+#define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4
+//
+// The type of PCI configuration address
+//
+#define EFI_SAL_PCI_COMPATIBLE_ADDRESS         0x0
+#define EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS  0x1
+///
+/// The format of PCI Compatible Address.
+///
+typedef struct {
+  UINT64  Register : 8;
+  UINT64  Function : 3;
+  UINT64  Device : 5;
+  UINT64  Bus : 8;
+  UINT64  Segment : 8;
+  UINT64  Reserved : 32;
+} SAL_PCI_ADDRESS;
+///
+/// The format of Extended Register Address.
+///
+typedef struct {
+  UINT64  Register : 8;
+  UINT64  ExtendedRegister : 4;
+  UINT64  Function : 3;
+  UINT64  Device : 5;
+  UINT64  Bus : 8;
+  UINT64  Segment : 16;
+  UINT64  Reserved : 20;
+} SAL_PCI_EXTENDED_REGISTER_ADDRESS;
+
+//
+// Parameter of EFI_SAL_FREQ_BASE
+//
+// Unsigned 64-bit integer specifying the type of clock source
+//
+#define EFI_SAL_CPU_INPUT_FREQ_BASE     0x0
+#define EFI_SAL_PLATFORM_IT_FREQ_BASE   0x1
+#define EFI_SAL_PLATFORM_RTC_FREQ_BASE  0x2
+
+//
+// Parameter and return value of EFI_SAL_UPDATE_PAL
+//
+// Return parameter provides additional information on the
+// failure when the status field contains a value of -3,
+// returned in r9.
+//
+#define EFI_SAL_UPDATE_BAD_PAL_VERSION  ((UINT64) -1)
+#define EFI_SAL_UPDATE_PAL_AUTH_FAIL    ((UINT64) -2)
+#define EFI_SAL_UPDATE_PAL_BAD_TYPE     ((UINT64) -3)
+#define EFI_SAL_UPDATE_PAL_READONLY     ((UINT64) -4)
+#define EFI_SAL_UPDATE_PAL_WRITE_FAIL   ((UINT64) -10)
+#define EFI_SAL_UPDATE_PAL_ERASE_FAIL   ((UINT64) -11)
+#define EFI_SAL_UPDATE_PAL_READ_FAIL    ((UINT64) -12)
+#define EFI_SAL_UPDATE_PAL_CANT_FIT     ((UINT64) -13)
+///
+/// 64-byte header of update data block.
+///
+typedef struct {
+  UINT32  Size;
+  UINT32  MmddyyyyDate;
+  UINT16  Version;
+  UINT8   Type;
+  UINT8   Reserved[5];
+  UINT64  FwVendorId;
+  UINT8   Reserved2[40];
+} SAL_UPDATE_PAL_DATA_BLOCK;
+///
+/// Data structure pointed by the parameter param_buf.
+/// It is a 16-byte aligned data structure in memory with a length of 32 bytes
+/// that describes the new firmware. This information is organized in the form
+/// of a linked list with each element describing one firmware component.
+///
+typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {
+  struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;
+  struct SAL_UPDATE_PAL_DATA_BLOCK  *DataBlock;
+  UINT8                             StoreChecksum;
+  UINT8                             Reserved[15];
+} SAL_UPDATE_PAL_INFO_BLOCK;
+
+///
+/// SAL System Table Definitions.
+///
+#pragma pack(1)
+typedef struct {
+  ///
+  /// The ASCII string representation of "SST_" that confirms the presence of the table. 
+  /// 
+  UINT32  Signature;
+  ///
+  /// The length of the entire table in bytes, starting from offset zero and including the
+  /// header and all entries indicated by the EntryCount field.
+  ///
+  UINT32  Length;
+  ///
+  /// The revision number of the Itanium Processor Family System Abstraction Layer
+  /// Specification supported by the SAL implementation, in binary coded decimal (BCD) format.
+  ///
+  UINT16  SalRevision;
+  ///
+  /// The number of entries in the variable portion of the table.
+  ///
+  UINT16  EntryCount;
+  ///
+  /// A modulo checksum of the entire table and the entries following this table.
+  ///
+  UINT8   CheckSum;
+  ///
+  /// Unused, must be zero.
+  ///
+  UINT8   Reserved[7];
+  ///
+  /// Version Number of the SAL_A firmware implementation in BCD format.
+  ///
+  UINT16  SalAVersion;
+  ///
+  /// Version Number of the SAL_B firmware implementation in BCD format.
+  ///
+  UINT16  SalBVersion;
+  ///
+  /// An ASCII identification string which uniquely identifies the manufacturer
+  /// of the system hardware.
+  ///
+  UINT8   OemId[32];
+  ///
+  /// An ASCII identification string which uniquely identifies a family of
+  /// compatible products from the manufacturer.
+  ///
+  UINT8   ProductId[32];
+  ///
+  /// Unused, must be zero.
+  ///
+  UINT8   Reserved2[8];
+} SAL_SYSTEM_TABLE_HEADER;
+
+#define EFI_SAL_ST_HEADER_SIGNATURE "SST_"
+#define EFI_SAL_REVISION            0x0320
+//
+// SAL System Types
+//
+#define EFI_SAL_ST_ENTRY_POINT        0
+#define EFI_SAL_ST_MEMORY_DESCRIPTOR  1
+#define EFI_SAL_ST_PLATFORM_FEATURES  2
+#define EFI_SAL_ST_TR_USAGE           3
+#define EFI_SAL_ST_PTC                4
+#define EFI_SAL_ST_AP_WAKEUP          5
+
+//
+// SAL System Type Sizes
+//
+#define EFI_SAL_ST_ENTRY_POINT_SIZE        48
+#define EFI_SAL_ST_MEMORY_DESCRIPTOR_SIZE  32
+#define EFI_SAL_ST_PLATFORM_FEATURES_SIZE  16
+#define EFI_SAL_ST_TR_USAGE_SIZE           32
+#define EFI_SAL_ST_PTC_SIZE                16
+#define EFI_SAL_ST_AP_WAKEUP_SIZE          16
+
+///
+/// Format of Entrypoint Descriptor Entry.
+///
+typedef struct {
+  UINT8   Type;         ///< Type here should be 0.
+  UINT8   Reserved[7];
+  UINT64  PalProcEntry;
+  UINT64  SalProcEntry;
+  UINT64  SalGlobalDataPointer;
+  UINT64  Reserved2[2];
+} SAL_ST_ENTRY_POINT_DESCRIPTOR;
+
+///
+/// Format of Platform Features Descriptor Entry.
+///
+typedef struct {
+  UINT8 Type;           ///< Type here should be 2.
+  UINT8 PlatformFeatures;
+  UINT8 Reserved[14];
+} SAL_ST_PLATFORM_FEATURES;
+
+//
+// Value of Platform Feature List
+//
+#define SAL_PLAT_FEAT_BUS_LOCK      0x01
+#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02
+#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04
+
+///
+/// Format of Translation Register Descriptor Entry.
+///
+typedef struct {
+  UINT8   Type;         ///< Type here should be 3.
+  UINT8   TRType;
+  UINT8   TRNumber;
+  UINT8   Reserved[5];
+  UINT64  VirtualAddress;
+  UINT64  EncodedPageSize;
+  UINT64  Reserved1;
+} SAL_ST_TR_DECRIPTOR;
+
+//
+// Type of Translation Register
+//
+#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00
+#define EFI_SAL_ST_TR_USAGE_DATA        01
+
+///
+/// Definition of Coherence Domain Information.
+///
+typedef struct {
+  UINT64  NumberOfProcessors;
+  UINT64  LocalIDRegister;
+} SAL_COHERENCE_DOMAIN_INFO;
+           
+///
+/// Format of Purge Translation Cache Coherence Domain Entry.
+///
+typedef struct {
+  UINT8                     Type;       ///< Type here should be 4.
+  UINT8                     Reserved[3];
+  UINT32                    NumberOfDomains;
+  SAL_COHERENCE_DOMAIN_INFO *DomainInformation;
+} SAL_ST_CACHE_COHERENCE_DECRIPTOR;
+
+///
+/// Format of Application Processor Wake-Up Descriptor Entry.
+///
+typedef struct {
+  UINT8   Type;                   ///< Type here should be 5.
+  UINT8   WakeUpType;
+  UINT8   Reserved[6];
+  UINT64  ExternalInterruptVector;
+} SAL_ST_AP_WAKEUP_DECRIPTOR;
+
+///
+/// Format of Firmware Interface Table (FIT) Entry.
+///
+typedef struct {
+  UINT64  Address;
+  UINT8   Size[3];
+  UINT8   Reserved;
+  UINT16  Revision;
+  UINT8   Type : 7;
+  UINT8   CheckSumValid : 1;
+  UINT8   CheckSum;
+} EFI_SAL_FIT_ENTRY;
+//
+// FIT Types 
+//
+#define EFI_SAL_FIT_FIT_HEADER_TYPE                0x00
+#define EFI_SAL_FIT_PAL_B_TYPE                     0x01
+//
+// Type from 0x02 to 0x0D is reserved.
+//
+#define EFI_SAL_FIT_PROCESSOR_SPECIFIC_PAL_A_TYPE  0x0E
+#define EFI_SAL_FIT_PAL_A_TYPE                     0x0F
+//
+// OEM-defined type range is from 0x10 to 0x7E.
+// Here we defined the PEI_CORE type as 0x10
+//
+#define EFI_SAL_FIT_PEI_CORE_TYPE                  0x10
+#define EFI_SAL_FIT_UNUSED_TYPE                    0x7F
+
+//
+// FIT Entry
+//
+#define EFI_SAL_FIT_ENTRY_PTR   (0x100000000 - 32)  // 4GB - 24
+#define EFI_SAL_FIT_PALA_ENTRY  (0x100000000 - 48)  // 4GB - 32
+#define EFI_SAL_FIT_PALB_TYPE   01
+
+//
+// Following definitions are for Error Record Structure
+//
+
+///
+/// Format of TimeStamp field in Record Header.
+///
+typedef struct {
+  UINT8 Seconds;
+  UINT8 Minutes;
+  UINT8 Hours;
+  UINT8 Reserved;
+  UINT8 Day;
+  UINT8 Month;
+  UINT8 Year;
+  UINT8 Century;
+} SAL_TIME_STAMP;
+///
+/// Definition of Record Header.
+///
+typedef struct {
+  UINT64          RecordId;
+  UINT16          Revision;
+  UINT8           ErrorSeverity;
+  UINT8           ValidationBits;
+  UINT32          RecordLength;
+  SAL_TIME_STAMP  TimeStamp;
+  UINT8           OemPlatformId[16];
+} SAL_RECORD_HEADER;
+///
+/// Definition of Section Header.
+///
+typedef struct {
+  GUID      Guid;
+  UINT16    Revision;
+  UINT8     ErrorRecoveryInfo;
+  UINT8     Reserved;
+  UINT32    SectionLength;
+} SAL_SEC_HEADER;
+
+///
+/// GUID of Processor Machine Check Errors.
+///
+#define SAL_PROCESSOR_ERROR_RECORD_INFO \
+  { \
+    0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
+  }
+//
+// Bit masks for valid bits of MOD_ERROR_INFO
+//
+#define CHECK_INFO_VALID_BIT_MASK   0x1
+#define REQUESTOR_ID_VALID_BIT_MASK 0x2
+#define RESPONDER_ID_VALID_BIT_MASK 0x4
+#define TARGER_ID_VALID_BIT_MASK    0x8
+#define PRECISE_IP_VALID_BIT_MASK   0x10
+///
+/// Definition of MOD_ERROR_INFO_STRUCT.
+///
+typedef struct {
+  UINT64  InfoValid : 1;
+  UINT64  ReqValid : 1;
+  UINT64  RespValid : 1;
+  UINT64  TargetValid : 1;
+  UINT64  IpValid : 1;
+  UINT64  Reserved : 59;
+  UINT64  Info;
+  UINT64  Req;
+  UINT64  Resp;
+  UINT64  Target;
+  UINT64  Ip;
+} MOD_ERROR_INFO;
+///
+/// Definition of CPUID_INFO_STRUCT.
+///
+typedef struct {
+  UINT8 CpuidInfo[40];
+  UINT8 Reserved;
+} CPUID_INFO;
+
+typedef struct {
+  UINT64  FrLow;
+  UINT64  FrHigh;
+} FR_STRUCT;
+//
+// Bit masks for PSI_STATIC_STRUCT.ValidFieldBits
+//
+#define MIN_STATE_VALID_BIT_MASK  0x1
+#define BR_VALID_BIT_MASK         0x2
+#define CR_VALID_BIT_MASK         0x4
+#define AR_VALID_BIT_MASK         0x8
+#define RR_VALID_BIT_MASK         0x10
+#define FR_VALID_BIT_MASK         0x20
+///
+/// Definition of PSI_STATIC_STRUCT.
+///
+typedef struct {
+  UINT64    ValidFieldBits;
+  UINT8     MinStateInfo[1024];
+  UINT64    Br[8];
+  UINT64    Cr[128];
+  UINT64    Ar[128];
+  UINT64    Rr[8];
+  FR_STRUCT Fr[128];
+} PSI_STATIC_STRUCT;
+//
+// Bit masks for SAL_PROCESSOR_ERROR_RECORD.ValidationBits
+//
+#define PROC_ERROR_MAP_VALID_BIT_MASK       0x1
+#define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2
+#define PROC_CR_LID_VALID_BIT_MASK          0x4
+#define PROC_STATIC_STRUCT_VALID_BIT_MASK   0x8
+#define CPU_INFO_VALID_BIT_MASK             0x1000000
+///
+/// Definition of Processor Machine Check Error Record.
+///
+typedef struct {
+  SAL_SEC_HEADER    SectionHeader;
+  UINT64            ValidationBits;
+  UINT64            ProcErrorMap;
+  UINT64            ProcStateParameter;
+  UINT64            ProcCrLid;
+  MOD_ERROR_INFO    CacheError[15];
+  MOD_ERROR_INFO    TlbError[15];
+  MOD_ERROR_INFO    BusError[15];
+  MOD_ERROR_INFO    RegFileCheck[15];
+  MOD_ERROR_INFO    MsCheck[15];
+  CPUID_INFO        CpuInfo;
+  PSI_STATIC_STRUCT PsiValidData;
+} SAL_PROCESSOR_ERROR_RECORD;
+
+///
+/// GUID of Platform Memory Device Error Info.
+///
+#define SAL_MEMORY_ERROR_RECORD_INFO \
+  { \
+    0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
+  }
+//
+// Bit masks for SAL_MEMORY_ERROR_RECORD.ValidationBits
+//
+#define MEMORY_ERROR_STATUS_VALID_BIT_MASK                0x1
+#define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK            0x2
+#define MEMORY_ADDR_BIT_MASK                              0x4
+#define MEMORY_NODE_VALID_BIT_MASK                        0x8
+#define MEMORY_CARD_VALID_BIT_MASK                        0x10
+#define MEMORY_MODULE_VALID_BIT_MASK                      0x20
+#define MEMORY_BANK_VALID_BIT_MASK                        0x40
+#define MEMORY_DEVICE_VALID_BIT_MASK                      0x80
+#define MEMORY_ROW_VALID_BIT_MASK                         0x100
+#define MEMORY_COLUMN_VALID_BIT_MASK                      0x200
+#define MEMORY_BIT_POSITION_VALID_BIT_MASK                0x400
+#define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK       0x800
+#define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK       0x1000
+#define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK             0x2000
+#define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK  0x4000
+#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK             0x8000
+#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK    0x10000
+///
+/// Definition of Platform Memory Device Error Info Record.
+///
+typedef struct {
+  SAL_SEC_HEADER  SectionHeader;
+  UINT64          ValidationBits;
+  UINT64          MemErrorStatus;
+  UINT64          MemPhysicalAddress;
+  UINT64          MemPhysicalAddressMask;
+  UINT16          MemNode;
+  UINT16          MemCard;
+  UINT16          MemModule;
+  UINT16          MemBank;
+  UINT16          MemDevice;
+  UINT16          MemRow;
+  UINT16          MemColumn;
+  UINT16          MemBitPosition;
+  UINT64          ModRequestorId;
+  UINT64          ModResponderId;
+  UINT64          ModTargetId;
+  UINT64          BusSpecificData;
+  UINT8           MemPlatformOemId[16];
+} SAL_MEMORY_ERROR_RECORD;
+
+///
+/// GUID of Platform PCI Bus Error Info.
+///
+#define SAL_PCI_BUS_ERROR_RECORD_INFO \
+  { \
+    0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
+  }
+//
+// Bit masks for SAL_PCI_BUS_ERROR_RECORD.ValidationBits
+//
+#define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK     0x1
+#define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK       0x2
+#define PCI_BUS_ID_VALID_BIT_MASK               0x4
+#define PCI_BUS_ADDRESS_VALID_BIT_MASK          0x8
+#define PCI_BUS_DATA_VALID_BIT_MASK             0x10
+#define PCI_BUS_CMD_VALID_BIT_MASK              0x20
+#define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK     0x40
+#define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK     0x80
+#define PCI_BUS_TARGET_VALID_BIT_MASK           0x100
+#define PCI_BUS_OEM_ID_VALID_BIT_MASK           0x200
+#define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK  0x400
+
+///
+/// Designated PCI Bus identifier.
+///
+typedef struct {
+  UINT8 BusNumber;
+  UINT8 SegmentNumber;
+} PCI_BUS_ID;
+
+///
+/// Definition of Platform PCI Bus Error Info Record.
+///
+typedef struct {
+  SAL_SEC_HEADER  SectionHeader;
+  UINT64          ValidationBits;
+  UINT64          PciBusErrorStatus;
+  UINT16          PciBusErrorType;
+  PCI_BUS_ID      PciBusId;
+  UINT32          Reserved;
+  UINT64          PciBusAddress;
+  UINT64          PciBusData;
+  UINT64          PciBusCommand;
+  UINT64          PciBusRequestorId;
+  UINT64          PciBusResponderId;
+  UINT64          PciBusTargetId;
+  UINT8           PciBusOemId[16];
+} SAL_PCI_BUS_ERROR_RECORD;
+
+///
+/// GUID of Platform PCI Component Error Info.
+///
+#define SAL_PCI_COMP_ERROR_RECORD_INFO \
+  { \
+    0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
+  }
+//
+// Bit masks for SAL_PCI_COMPONENT_ERROR_RECORD.ValidationBits
+//
+#define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK    0x1
+#define PCI_COMP_INFO_VALID_BIT_MASK            0x2
+#define PCI_COMP_MEM_NUM_VALID_BIT_MASK         0x4
+#define PCI_COMP_IO_NUM_VALID_BIT_MASK          0x8
+#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK   0x10
+#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20
+///
+/// Format of PCI Component Information to identify the device.
+///
+typedef struct {
+  UINT16  VendorId;
+  UINT16  DeviceId;
+  UINT8   ClassCode[3];
+  UINT8   FunctionNumber;
+  UINT8   DeviceNumber;
+  UINT8   BusNumber;
+  UINT8   SegmentNumber;
+  UINT8   Reserved[5];
+} PCI_COMP_INFO;
+///
+/// Definition of Platform PCI Component Error Info.
+///
+typedef struct {
+  SAL_SEC_HEADER  SectionHeader;
+  UINT64          ValidationBits;
+  UINT64          PciComponentErrorStatus;
+  PCI_COMP_INFO   PciComponentInfo;
+  UINT32          PciComponentMemNum;
+  UINT32          PciComponentIoNum;
+  UINT8           PciBusOemId[16];
+} SAL_PCI_COMPONENT_ERROR_RECORD;
+
+///
+/// Platform SEL Device Error Info.
+///
+#define SAL_SEL_DEVICE_ERROR_RECORD_INFO \
+  { \
+    0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
+  }
+//
+// Bit masks for SAL_SEL_DEVICE_ERROR_RECORD.ValidationBits
+//
+#define SEL_RECORD_ID_VALID_BIT_MASK      0x1;
+#define SEL_RECORD_TYPE_VALID_BIT_MASK    0x2;
+#define SEL_GENERATOR_ID_VALID_BIT_MASK   0x4;
+#define SEL_EVM_REV_VALID_BIT_MASK        0x8;
+#define SEL_SENSOR_TYPE_VALID_BIT_MASK    0x10;
+#define SEL_SENSOR_NUM_VALID_BIT_MASK     0x20;
+#define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;
+#define SEL_EVENT_DATA1_VALID_BIT_MASK    0x80;
+#define SEL_EVENT_DATA2_VALID_BIT_MASK    0x100;
+#define SEL_EVENT_DATA3_VALID_BIT_MASK    0x200;
+///
+/// Definition of Platform SEL Device Error Info Record.
+///
+typedef struct {
+  SAL_SEC_HEADER  SectionHeader;
+  UINT64          ValidationBits;
+  UINT16          SelRecordId;
+  UINT8           SelRecordType;
+  UINT32          TimeStamp;
+  UINT16          GeneratorId;
+  UINT8           EvmRevision;
+  UINT8           SensorType;
+  UINT8           SensorNum;
+  UINT8           EventDirType;
+  UINT8           Data1;
+  UINT8           Data2;
+  UINT8           Data3;
+} SAL_SEL_DEVICE_ERROR_RECORD;
+
+///
+/// GUID of Platform SMBIOS Device Error Info.
+///
+#define SAL_SMBIOS_ERROR_RECORD_INFO \
+  { \
+    0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
+  }
+//
+// Bit masks for SAL_SMBIOS_DEVICE_ERROR_RECORD.ValidationBits
+//
+#define SMBIOS_EVENT_TYPE_VALID_BIT_MASK  0x1
+#define SMBIOS_LENGTH_VALID_BIT_MASK      0x2
+#define SMBIOS_TIME_STAMP_VALID_BIT_MASK  0x4
+#define SMBIOS_DATA_VALID_BIT_MASK        0x8
+///
+/// Definition of Platform SMBIOS Device Error Info Record.
+///
+typedef struct {
+  SAL_SEC_HEADER  SectionHeader;
+  UINT64          ValidationBits;
+  UINT8           SmbiosEventType;
+  UINT8           SmbiosLength;
+  UINT8           SmbiosBcdTimeStamp[6];
+} SAL_SMBIOS_DEVICE_ERROR_RECORD;
+
+///
+/// GUID of Platform Specific Error Info.
+///
+#define SAL_PLATFORM_ERROR_RECORD_INFO \
+  { \
+    0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
+  }
+//
+// Bit masks for SAL_PLATFORM_SPECIFIC_ERROR_RECORD.ValidationBits
+//
+#define PLATFORM_ERROR_STATUS_VALID_BIT_MASK    0x1
+#define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK    0x2
+#define PLATFORM_RESPONDER_ID_VALID_BIT_MASK    0x4
+#define PLATFORM_TARGET_VALID_BIT_MASK          0x8
+#define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK   0x10
+#define PLATFORM_OEM_ID_VALID_BIT_MASK          0x20
+#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40
+#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80
+///
+/// Definition of Platform Specific Error Info Record.
+///
+typedef struct {
+  SAL_SEC_HEADER  SectionHeader;
+  UINT64          ValidationBits;
+  UINT64          PlatformErrorStatus;
+  UINT64          PlatformRequestorId;
+  UINT64          PlatformResponderId;
+  UINT64          PlatformTargetId;
+  UINT64          PlatformBusSpecificData;
+  UINT8           OemComponentId[16];
+} SAL_PLATFORM_SPECIFIC_ERROR_RECORD;
+
+///
+/// Union of all the possible SAL Error Record Types.
+///
+typedef union {
+  SAL_RECORD_HEADER                   *RecordHeader;
+  SAL_PROCESSOR_ERROR_RECORD          *SalProcessorRecord;
+  SAL_PCI_BUS_ERROR_RECORD            *SalPciBusRecord;
+  SAL_PCI_COMPONENT_ERROR_RECORD      *SalPciComponentRecord;
+  SAL_SEL_DEVICE_ERROR_RECORD         *ImpiRecord;
+  SAL_SMBIOS_DEVICE_ERROR_RECORD      *SmbiosRecord;
+  SAL_PLATFORM_SPECIFIC_ERROR_RECORD  *PlatformRecord;
+  SAL_MEMORY_ERROR_RECORD             *MemoryRecord;
+  UINT8                               *Raw;
+} SAL_ERROR_RECORDS_POINTERS;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Scsi.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Scsi.h
new file mode 100644
index 0000000000..6de1cfd978
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Scsi.h
@@ -0,0 +1,412 @@
+/** @file
+  Support for SCSI-2 standard
+
+  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+**/
+
+#ifndef __SCSI_H__
+#define __SCSI_H__
+
+//
+// SCSI command OP Code
+//
+//
+// Commands for all device types
+//
+#define EFI_SCSI_OP_CHANGE_DEFINITION 0x40
+#define EFI_SCSI_OP_COMPARE           0x39
+#define EFI_SCSI_OP_COPY              0x18
+#define EFI_SCSI_OP_COPY_VERIFY       0x3a
+#define EFI_SCSI_OP_INQUIRY           0x12
+#define EFI_SCSI_OP_LOG_SELECT        0x4c
+#define EFI_SCSI_OP_LOG_SENSE         0x4d
+#define EFI_SCSI_OP_MODE_SEL6         0x15
+#define EFI_SCSI_OP_MODE_SEL10        0x55
+#define EFI_SCSI_OP_MODE_SEN6         0x1a
+#define EFI_SCSI_OP_MODE_SEN10        0x5a
+#define EFI_SCSI_OP_READ_BUFFER       0x3c
+#define EFI_SCSI_OP_RECEIVE_DIAG      0x1c
+#define EFI_SCSI_OP_REQUEST_SENSE     0x03
+#define EFI_SCSI_OP_SEND_DIAG         0x1d
+#define EFI_SCSI_OP_TEST_UNIT_READY   0x00
+#define EFI_SCSI_OP_WRITE_BUFF        0x3b
+
+//
+// Additional commands for Direct Access Devices
+//
+#define EFI_SCSI_OP_FORMAT          0x04
+#define EFI_SCSI_OP_LOCK_UN_CACHE   0x36
+#define EFI_SCSI_OP_PREFETCH        0x34
+#define EFI_SCSI_OP_MEDIA_REMOVAL   0x1e
+#define EFI_SCSI_OP_READ6           0x08
+#define EFI_SCSI_OP_READ10          0x28
+#define EFI_SCSI_OP_READ16          0x88
+#define EFI_SCSI_OP_READ_CAPACITY   0x25
+#define EFI_SCSI_OP_READ_CAPACITY16 0x9e
+#define EFI_SCSI_OP_READ_DEFECT     0x37
+#define EFI_SCSI_OP_READ_LONG       0x3e
+#define EFI_SCSI_OP_REASSIGN_BLK    0x07
+#define EFI_SCSI_OP_RELEASE         0x17
+#define EFI_SCSI_OP_REZERO          0x01
+#define EFI_SCSI_OP_SEARCH_DATA_E   0x31
+#define EFI_SCSI_OP_SEARCH_DATA_H   0x30
+#define EFI_SCSI_OP_SEARCH_DATA_L   0x32
+#define EFI_SCSI_OP_SEEK6           0x0b
+#define EFI_SCSI_OP_SEEK10          0x2b
+#define EFI_SCSI_OP_SEND_DIAG       0x1d
+#define EFI_SCSI_OP_SET_LIMIT       0x33
+#define EFI_SCSI_OP_START_STOP_UNIT 0x1b
+#define EFI_SCSI_OP_SYNC_CACHE      0x35
+#define EFI_SCSI_OP_VERIFY          0x2f
+#define EFI_SCSI_OP_WRITE6          0x0a
+#define EFI_SCSI_OP_WRITE10         0x2a
+#define EFI_SCSI_OP_WRITE16         0x8a
+#define EFI_SCSI_OP_WRITE_VERIFY    0x2e
+#define EFI_SCSI_OP_WRITE_LONG      0x3f
+#define EFI_SCSI_OP_WRITE_SAME      0x41
+#define EFI_SCSI_OP_UNMAP           0x42
+
+//
+// Additional commands for Sequential Access Devices
+//
+#define EFI_SCSI_OP_ERASE             0x19
+#define EFI_SCSI_OP_LOAD_UNLOAD       0x1b
+#define EFI_SCSI_OP_LOCATE            0x2b
+#define EFI_SCSI_OP_READ_BLOCK_LIMIT  0x05
+#define EFI_SCSI_OP_READ_POS          0x34
+#define EFI_SCSI_OP_READ_REVERSE      0x0f
+#define EFI_SCSI_OP_RECOVER_BUF_DATA  0x14
+#define EFI_SCSI_OP_RESERVE_UNIT      0x16
+#define EFI_SCSI_OP_REWIND            0x01
+#define EFI_SCSI_OP_SPACE             0x11
+#define EFI_SCSI_OP_VERIFY_TAPE       0x13
+#define EFI_SCSI_OP_WRITE_FILEMARK    0x10
+
+//
+// Additional commands for Printer Devices
+//
+#define EFI_SCSI_OP_PRINT       0x0a
+#define EFI_SCSI_OP_SLEW_PRINT  0x0b
+#define EFI_SCSI_OP_STOP_PRINT  0x1b
+#define EFI_SCSI_OP_SYNC_BUFF   0x10
+
+//
+// Additional commands for Processor Devices
+//
+#define EFI_SCSI_OP_RECEIVE 0x08
+#define EFI_SCSI_OP_SEND    0x0a
+
+//
+// Additional commands for Write-Once Devices
+//
+#define EFI_SCSI_OP_MEDIUM_SCAN     0x38
+#define EFI_SCSI_OP_SEARCH_DAT_E10  0x31
+#define EFI_SCSI_OP_SEARCH_DAT_E12  0xb1
+#define EFI_SCSI_OP_SEARCH_DAT_H10  0x30
+#define EFI_SCSI_OP_SEARCH_DAT_H12  0xb0
+#define EFI_SCSI_OP_SEARCH_DAT_L10  0x32
+#define EFI_SCSI_OP_SEARCH_DAT_L12  0xb2
+#define EFI_SCSI_OP_SET_LIMIT10     0x33
+#define EFI_SCSI_OP_SET_LIMIT12     0xb3
+#define EFI_SCSI_OP_VERIFY10        0x2f
+#define EFI_SCSI_OP_VERIFY12        0xaf
+#define EFI_SCSI_OP_WRITE12         0xaa
+#define EFI_SCSI_OP_WRITE_VERIFY10  0x2e
+#define EFI_SCSI_OP_WRITE_VERIFY12  0xae
+
+//
+// Additional commands for CD-ROM Devices
+//
+#define EFI_SCSI_OP_PLAY_AUD_10       0x45
+#define EFI_SCSI_OP_PLAY_AUD_12       0xa5
+#define EFI_SCSI_OP_PLAY_AUD_MSF      0x47
+#define EFI_SCSI_OP_PLAY_AUD_TKIN     0x48
+#define EFI_SCSI_OP_PLAY_TK_REL10     0x49
+#define EFI_SCSI_OP_PLAY_TK_REL12     0xa9
+#define EFI_SCSI_OP_READ_CD_CAPACITY  0x25
+#define EFI_SCSI_OP_READ_HEADER       0x44
+#define EFI_SCSI_OP_READ_SUB_CHANNEL  0x42
+#define EFI_SCSI_OP_READ_TOC          0x43
+
+//
+// Additional commands for Scanner Devices
+//
+#define EFI_SCSI_OP_GET_DATABUFF_STAT 0x34
+#define EFI_SCSI_OP_GET_WINDOW        0x25
+#define EFI_SCSI_OP_OBJECT_POS        0x31
+#define EFI_SCSI_OP_SCAN              0x1b
+#define EFI_SCSI_OP_SET_WINDOW        0x24
+
+//
+// Additional commands for Optical Memory Devices
+//
+#define EFI_SCSI_OP_UPDATE_BLOCK  0x3d
+
+//
+// Additional commands for Medium Changer Devices
+//
+#define EFI_SCSI_OP_EXCHANGE_MEDIUM   0xa6
+#define EFI_SCSI_OP_INIT_ELEMENT_STAT 0x07
+#define EFI_SCSI_OP_POS_TO_ELEMENT    0x2b
+#define EFI_SCSI_OP_REQUEST_VE_ADDR   0xb5
+#define EFI_SCSI_OP_SEND_VOL_TAG      0xb6
+
+//
+// Additional commands for Communition Devices
+//
+#define EFI_SCSI_OP_GET_MESSAGE6    0x08
+#define EFI_SCSI_OP_GET_MESSAGE10   0x28
+#define EFI_SCSI_OP_GET_MESSAGE12   0xa8
+#define EFI_SCSI_OP_SEND_MESSAGE6   0x0a
+#define EFI_SCSI_OP_SEND_MESSAGE10  0x2a
+#define EFI_SCSI_OP_SEND_MESSAGE12  0xaa
+
+//
+// SCSI Data Transfer Direction
+//
+#define EFI_SCSI_DATA_IN  0
+#define EFI_SCSI_DATA_OUT 1
+
+//
+// Peripheral Device Type Definitions
+//
+#define EFI_SCSI_TYPE_DISK          0x00  ///< Direct-access device (e.g. magnetic disk)
+#define EFI_SCSI_TYPE_TAPE          0x01  ///< Sequential-access device (e.g. magnetic tape)
+#define EFI_SCSI_TYPE_PRINTER       0x02  ///< Printer device
+#define EFI_SCSI_TYPE_PROCESSOR     0x03  ///< Processor device
+#define EFI_SCSI_TYPE_WORM          0x04  ///< Write-once device (e.g. some optical disks)
+#define EFI_SCSI_TYPE_CDROM         0x05  ///< CD-ROM device
+#define EFI_SCSI_TYPE_SCANNER       0x06  ///< Scanner device
+#define EFI_SCSI_TYPE_OPTICAL       0x07  ///< Optical memory device (e.g. some optical disks)
+#define EFI_SCSI_TYPE_MEDIUMCHANGER 0x08  ///< Medium changer device (e.g. jukeboxes)
+#define EFI_SCSI_TYPE_COMMUNICATION 0x09  ///< Communications device
+#define EFI_SCSI_TYPE_ASCIT8_1      0x0A  ///< Defined by ASC IT8 (Graphic arts pre-press devices)
+#define EFI_SCSI_TYPE_ASCIT8_2      0x0B  ///< Defined by ASC IT8 (Graphic arts pre-press devices)
+//
+// 0Ch - 1Eh are reserved
+//
+#define EFI_SCSI_TYPE_UNKNOWN       0x1F  ///< Unknown or no device type
+
+//
+// Page Codes for INQUIRY command
+//
+#define EFI_SCSI_PAGE_CODE_SUPPORTED_VPD    0x00
+#define EFI_SCSI_PAGE_CODE_BLOCK_LIMITS_VPD 0xB0
+
+#pragma pack(1)
+///
+/// Standard INQUIRY data format
+///
+typedef struct {
+  UINT8 Peripheral_Type : 5;
+  UINT8 Peripheral_Qualifier : 3;
+  UINT8 DeviceType_Modifier : 7;
+  UINT8 Rmb : 1;
+  UINT8 Version;
+  UINT8 Response_Data_Format;
+  UINT8 Addnl_Length;
+  UINT8 Reserved_5_95[95 - 5 + 1];
+} EFI_SCSI_INQUIRY_DATA;
+
+///
+/// Supported VPD Pages VPD page
+///
+typedef struct {
+  UINT8 Peripheral_Type : 5;
+  UINT8 Peripheral_Qualifier : 3;
+  UINT8 PageCode;
+  UINT8 PageLength2;
+  UINT8 PageLength1;
+  UINT8 SupportedVpdPageList[0x100];
+} EFI_SCSI_SUPPORTED_VPD_PAGES_VPD_PAGE;
+
+///
+/// Block Limits VPD page
+///
+typedef struct {
+  UINT8 Peripheral_Type : 5;
+  UINT8 Peripheral_Qualifier : 3;
+  UINT8 PageCode;
+  UINT8 PageLength2;
+  UINT8 PageLength1;
+  UINT8 WriteSameNonZero : 1;
+  UINT8 Reserved_4 : 7;
+  UINT8 MaximumCompareAndWriteLength;
+  UINT8 OptimalTransferLengthGranularity2;
+  UINT8 OptimalTransferLengthGranularity1;
+  UINT8 MaximumTransferLength4;
+  UINT8 MaximumTransferLength3;
+  UINT8 MaximumTransferLength2;
+  UINT8 MaximumTransferLength1;
+  UINT8 OptimalTransferLength4;
+  UINT8 OptimalTransferLength3;
+  UINT8 OptimalTransferLength2;
+  UINT8 OptimalTransferLength1;
+  UINT8 MaximumPrefetchXdreadXdwriteTransferLength4;
+  UINT8 MaximumPrefetchXdreadXdwriteTransferLength3;
+  UINT8 MaximumPrefetchXdreadXdwriteTransferLength2;
+  UINT8 MaximumPrefetchXdreadXdwriteTransferLength1;
+  UINT8 MaximumUnmapLbaCount4;
+  UINT8 MaximumUnmapLbaCount3;
+  UINT8 MaximumUnmapLbaCount2;
+  UINT8 MaximumUnmapLbaCount1;
+  UINT8 MaximumUnmapBlockDescriptorCount4;
+  UINT8 MaximumUnmapBlockDescriptorCount3;
+  UINT8 MaximumUnmapBlockDescriptorCount2;
+  UINT8 MaximumUnmapBlockDescriptorCount1;
+  UINT8 OptimalUnmapGranularity4;
+  UINT8 OptimalUnmapGranularity3;
+  UINT8 OptimalUnmapGranularity2;
+  UINT8 OptimalUnmapGranularity1;
+  UINT8 UnmapGranularityAlignment4 : 7;
+  UINT8 UnmapGranularityAlignmentValid : 1;
+  UINT8 UnmapGranularityAlignment3;
+  UINT8 UnmapGranularityAlignment2;
+  UINT8 UnmapGranularityAlignment1;
+  UINT8 MaximumWriteSameLength4;
+  UINT8 MaximumWriteSameLength3;
+  UINT8 MaximumWriteSameLength2;
+  UINT8 MaximumWriteSameLength1;
+  UINT8 MaximumAtomicTransferLength4;
+  UINT8 MaximumAtomicTransferLength3;
+  UINT8 MaximumAtomicTransferLength2;
+  UINT8 MaximumAtomicTransferLength1;
+  UINT8 AtomicAlignment4;
+  UINT8 AtomicAlignment3;
+  UINT8 AtomicAlignment2;
+  UINT8 AtomicAlignment1;
+  UINT8 AtomicTransferLengthGranularity4;
+  UINT8 AtomicTransferLengthGranularity3;
+  UINT8 AtomicTransferLengthGranularity2;
+  UINT8 AtomicTransferLengthGranularity1;
+  UINT8 MaximumAtomicTransferLengthWithAtomicBoundary4;
+  UINT8 MaximumAtomicTransferLengthWithAtomicBoundary3;
+  UINT8 MaximumAtomicTransferLengthWithAtomicBoundary2;
+  UINT8 MaximumAtomicTransferLengthWithAtomicBoundary1;
+  UINT8 MaximumAtomicBoundarySize4;
+  UINT8 MaximumAtomicBoundarySize3;
+  UINT8 MaximumAtomicBoundarySize2;
+  UINT8 MaximumAtomicBoundarySize1;
+} EFI_SCSI_BLOCK_LIMITS_VPD_PAGE;
+
+///
+/// Error codes 70h and 71h sense data format
+///
+typedef struct {
+  UINT8 Error_Code : 7;
+  UINT8 Valid : 1;
+  UINT8 Segment_Number;
+  UINT8 Sense_Key : 4;
+  UINT8 Reserved_21 : 1;
+  UINT8 Ili : 1;
+  UINT8 Reserved_22 : 2;
+  UINT8 Information_3_6[4];
+  UINT8 Addnl_Sense_Length;           ///< Additional sense length (n-7)
+  UINT8 Vendor_Specific_8_11[4];
+  UINT8 Addnl_Sense_Code;             ///< Additional sense code
+  UINT8 Addnl_Sense_Code_Qualifier;   ///< Additional sense code qualifier
+  UINT8 Field_Replaceable_Unit_Code;  ///< Field replaceable unit code
+  UINT8 Reserved_15_17[3];
+} EFI_SCSI_SENSE_DATA;
+
+///
+/// SCSI Disk READ CAPACITY Data
+///
+typedef struct {
+  UINT8 LastLba3;
+  UINT8 LastLba2;
+  UINT8 LastLba1;
+  UINT8 LastLba0;
+  UINT8 BlockSize3;
+  UINT8 BlockSize2;
+  UINT8 BlockSize1;
+  UINT8 BlockSize0;
+} EFI_SCSI_DISK_CAPACITY_DATA;
+
+typedef struct {
+  UINT8 LastLba7;
+  UINT8 LastLba6;
+  UINT8 LastLba5;
+  UINT8 LastLba4;
+  UINT8 LastLba3;
+  UINT8 LastLba2;
+  UINT8 LastLba1;
+  UINT8 LastLba0;
+  UINT8 BlockSize3;
+  UINT8 BlockSize2;
+  UINT8 BlockSize1;
+  UINT8 BlockSize0;
+  UINT8 Protection;
+  UINT8 LogicPerPhysical;
+  UINT8 LowestAlignLogic2;  
+  UINT8 LowestAlignLogic1;    
+  UINT8 Reserved[16];  
+} EFI_SCSI_DISK_CAPACITY_DATA16;
+
+typedef struct {
+  UINT16 DataLen;
+  UINT16 BlkDespDataLen;
+  UINT8  Reserved[4];
+} EFI_SCSI_DISK_UNMAP_PARAM_LIST_HEADER;
+
+typedef struct {
+  UINT64 Lba;
+  UINT32 BlockNum;
+  UINT8  Reserved[4];
+} EFI_SCSI_DISK_UNMAP_BLOCK_DESP;
+
+
+#pragma pack()
+
+//
+// Sense Key
+//
+#define EFI_SCSI_SK_NO_SENSE          (0x0)
+#define EFI_SCSI_SK_RECOVERY_ERROR    (0x1)
+#define EFI_SCSI_SK_NOT_READY         (0x2)
+#define EFI_SCSI_SK_MEDIUM_ERROR      (0x3)
+#define EFI_SCSI_SK_HARDWARE_ERROR    (0x4)
+#define EFI_SCSI_SK_ILLEGAL_REQUEST   (0x5)
+#define EFI_SCSI_SK_UNIT_ATTENTION    (0x6)
+#define EFI_SCSI_SK_DATA_PROTECT      (0x7)
+#define EFI_SCSI_SK_BLANK_CHECK       (0x8)
+#define EFI_SCSI_SK_VENDOR_SPECIFIC   (0x9)
+#define EFI_SCSI_SK_RESERVED_A        (0xA)
+#define EFI_SCSI_SK_ABORT             (0xB)
+#define EFI_SCSI_SK_RESERVED_C        (0xC)
+#define EFI_SCSI_SK_OVERFLOW          (0xD)
+#define EFI_SCSI_SK_MISCOMPARE        (0xE)
+#define EFI_SCSI_SK_RESERVED_F        (0xF)
+
+//
+// Additional Sense Codes and Sense Code Qualifiers.
+// Only some frequently used additional sense codes and qualifiers are
+// defined here. Please refer to SCSI standard for full value definition.
+//
+#define EFI_SCSI_ASC_NOT_READY                    (0x04)
+#define EFI_SCSI_ASCQ_IN_PROGRESS                 (0x01)
+
+#define EFI_SCSI_ASC_MEDIA_ERR1                   (0x10)
+#define EFI_SCSI_ASC_MEDIA_ERR2                   (0x11)
+#define EFI_SCSI_ASC_MEDIA_ERR3                   (0x14)
+#define EFI_SCSI_ASC_MEDIA_ERR4                   (0x30)
+#define EFI_SCSI_ASC_MEDIA_UPSIDE_DOWN            (0x06)
+#define EFI_SCSI_ASC_INVALID_CMD                  (0x20)
+#define EFI_SCSI_ASC_LBA_OUT_OF_RANGE             (0x21)
+#define EFI_SCSI_ASC_INVALID_FIELD                (0x24)
+#define EFI_SCSI_ASC_WRITE_PROTECTED              (0x27)
+#define EFI_SCSI_ASC_MEDIA_CHANGE                 (0x28)
+#define EFI_SCSI_ASC_RESET                        (0x29)   ///< Power On Reset or Bus Reset occurred
+#define EFI_SCSI_ASC_ILLEGAL_FIELD                (0x26)
+#define EFI_SCSI_ASC_NO_MEDIA                     (0x3A)
+#define EFI_SCSI_ASC_ILLEGAL_MODE_FOR_THIS_TRACK  (0x64)
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Sd.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Sd.h
new file mode 100644
index 0000000000..693dfcf6dc
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Sd.h
@@ -0,0 +1,181 @@
+/** @file
+  Header file for SD memory card support.
+
+  This header file contains some definitions defined in SD Physical Layer Simplified
+  Specification Version 4.10 spec.
+
+  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SD_H__
+#define __SD_H__
+
+//
+// SD command index
+//
+#define  SD_GO_IDLE_STATE           0
+#define  SD_ALL_SEND_CID            2
+#define  SD_SET_RELATIVE_ADDR       3
+#define  SD_SET_DSR                 4
+#define  SDIO_SEND_OP_COND          5
+#define  SD_SWITCH_FUNC             6
+#define  SD_SELECT_DESELECT_CARD    7
+#define  SD_SEND_IF_COND            8
+#define  SD_SEND_CSD                9
+#define  SD_SEND_CID                10
+#define  SD_VOLTAGE_SWITCH          11
+#define  SD_STOP_TRANSMISSION       12
+#define  SD_SEND_STATUS             13
+#define  SD_GO_INACTIVE_STATE       15
+#define  SD_SET_BLOCKLEN            16
+#define  SD_READ_SINGLE_BLOCK       17
+#define  SD_READ_MULTIPLE_BLOCK     18
+#define  SD_SEND_TUNING_BLOCK       19
+#define  SD_SPEED_CLASS_CONTROL     20
+#define  SD_SET_BLOCK_COUNT         23
+#define  SD_WRITE_SINGLE_BLOCK      24
+#define  SD_WRITE_MULTIPLE_BLOCK    25
+#define  SD_PROGRAM_CSD             27
+#define  SD_SET_WRITE_PROT          28
+#define  SD_CLR_WRITE_PROT          29
+#define  SD_SEND_WRITE_PROT         30
+#define  SD_ERASE_WR_BLK_START      32
+#define  SD_ERASE_WR_BLK_END        33
+#define  SD_ERASE                   38
+#define  SD_LOCK_UNLOCK             42
+#define  SD_READ_EXTR_SINGLE        48
+#define  SD_WRITE_EXTR_SINGLE       49
+#define  SDIO_RW_DIRECT             52
+#define  SDIO_RW_EXTENDED           53
+#define  SD_APP_CMD                 55
+#define  SD_GEN_CMD                 56
+#define  SD_READ_EXTR_MULTI         58
+#define  SD_WRITE_EXTR_MULTI        59
+
+#define  SD_SET_BUS_WIDTH           6           // ACMD6
+#define  SD_STATUS                  13          // ACMD13
+#define  SD_SEND_NUM_WR_BLOCKS      22          // ACMD22
+#define  SD_SET_WR_BLK_ERASE_COUNT  23          // ACMD23
+#define  SD_SEND_OP_COND            41          // ACMD41
+#define  SD_SET_CLR_CARD_DETECT     42          // ACMD42
+#define  SD_SEND_SCR                51          // ACMD51
+
+#pragma pack(1)
+typedef struct {
+  UINT8   NotUsed:1;                            // Not used [0:0]
+  UINT8   Crc:7;                                // CRC [7:1]
+  UINT16  ManufacturingDate:12;                 // Manufacturing date [19:8]
+  UINT16  Reserved:4;                           // Reserved [23:20]
+  UINT8   ProductSerialNumber[4];               // Product serial number [55:24]
+  UINT8   ProductRevision;                      // Product revision [63:56]
+  UINT8   ProductName[5];                       // Product name [103:64]
+  UINT8   OemId[2];                             // OEM/Application ID [119:104]
+  UINT8   ManufacturerId;                       // Manufacturer ID [127:120]
+} SD_CID;
+
+typedef struct {
+  UINT32  NotUsed:1;                            // Not used [0:0]
+  UINT32  Crc:7;                                // CRC [7:1]
+  UINT32  Reserved:2;                           // Reserved [9:8]
+  UINT32  FileFormat:2;                         // File format [11:10]
+  UINT32  TmpWriteProtect:1;                    // Temporary write protection [12:12]
+  UINT32  PermWriteProtect:1;                   // Permanent write protection [13:13]
+  UINT32  Copy:1;                               // Copy flag (OTP) [14:14]
+  UINT32  FileFormatGrp:1;                      // File format group [15:15]
+  UINT32  Reserved1:5;                          // Reserved [20:16]
+  UINT32  WriteBlPartial:1;                     // Partial blocks for write allowed [21:21]
+  UINT32  WriteBlLen:4;                         // Max. write data block length [25:22]
+  UINT32  R2WFactor:3;                          // Write speed factor [28:26]
+  UINT32  Reserved2:2;                          // Manufacturer default ECC [30:29]
+  UINT32  WpGrpEnable:1;                        // Write protect group enable [31:31]
+
+  UINT32  WpGrpSize:7;                          // Write protect group size [38:32]
+  UINT32  SectorSize:7;                         // Erase sector size [45:39]
+  UINT32  EraseBlkEn:1;                         // Erase single block enable [46:46]
+  UINT32  CSizeMul:3;                           // device size multiplier [49:47]
+  UINT32  VddWCurrMax:3;                        // max. write current @VDD max [52:50]
+  UINT32  VddWCurrMin:3;                        // max. write current @VDD min [55:53]
+  UINT32  VddRCurrMax:3;                        // max. read current @VDD max [58:56]
+  UINT32  VddRCurrMin:3;                        // max. read current @VDD min [61:59]
+  UINT32  CSizeLow:2;                           // Device size low 2 bits [63:62]
+
+  UINT32  CSizeHigh:10;                         // Device size high 10 bits [73:64]
+  UINT32  Reserved4:2;                          // Reserved [75:74]
+  UINT32  DsrImp:1;                             // DSR implemented [76:76]
+  UINT32  ReadBlkMisalign:1;                    // Read block misalignment [77:77]
+  UINT32  WriteBlkMisalign:1;                   // Write block misalignment [78:78]
+  UINT32  ReadBlPartial:1;                      // Partial blocks for read allowed [79:79]
+  UINT32  ReadBlLen:4;                          // Max. read data block length [83:80]
+  UINT32  Ccc:12;                               // Card command classes [95:84]
+
+  UINT32  TranSpeed:8;                          // Max. data transfer rate [103:96]
+  UINT32  Nsac:8;                               // Data read access-time in CLK cycles (NSAC*100) [111:104]
+  UINT32  Taac:8;                               // Data read access-time [119:112]
+  UINT32  Reserved5:6;                          // Reserved [125:120]
+  UINT32  CsdStructure:2;                       // CSD structure [127:126]
+} SD_CSD;
+
+typedef struct {
+  UINT32  NotUsed:1;                            // Not used [0:0]
+  UINT32  Crc:7;                                // CRC [7:1]
+  UINT32  Reserved:2;                           // Reserved [9:8]
+  UINT32  FileFormat:2;                         // File format [11:10]
+  UINT32  TmpWriteProtect:1;                    // Temporary write protection [12:12]
+  UINT32  PermWriteProtect:1;                   // Permanent write protection [13:13]
+  UINT32  Copy:1;                               // Copy flag (OTP) [14:14]
+  UINT32  FileFormatGrp:1;                      // File format group [15:15]
+  UINT32  Reserved1:5;                          // Reserved [20:16]
+  UINT32  WriteBlPartial:1;                     // Partial blocks for write allowed [21:21]
+  UINT32  WriteBlLen:4;                         // Max. write data block length [25:22]
+  UINT32  R2WFactor:3;                          // Write speed factor [28:26]
+  UINT32  Reserved2:2;                          // Manufacturer default ECC [30:29]
+  UINT32  WpGrpEnable:1;                        // Write protect group enable [31:31]
+
+  UINT32  WpGrpSize:7;                          // Write protect group size [38:32]
+  UINT32  SectorSize:7;                         // Erase sector size [45:39]
+  UINT32  EraseBlkEn:1;                         // Erase single block enable [46:46]
+  UINT32  Reserved3:1;                          // Reserved [47:47]
+  UINT32  CSizeLow:16;                          // Device size low 16 bits [63:48]
+
+  UINT32  CSizeHigh:6;                          // Device size high 6 bits [69:64]
+  UINT32  Reserved4:6;                          // Reserved [75:70]
+  UINT32  DsrImp:1;                             // DSR implemented [76:76]
+  UINT32  ReadBlkMisalign:1;                    // Read block misalignment [77:77]
+  UINT32  WriteBlkMisalign:1;                   // Write block misalignment [78:78]
+  UINT32  ReadBlPartial:1;                      // Partial blocks for read allowed [79:79]
+  UINT32  ReadBlLen:4;                          // Max. read data block length [83:80]
+  UINT32  Ccc:12;                               // Card command classes [95:84]
+
+  UINT32  TranSpeed:8;                          // Max. data transfer rate [103:96]
+  UINT32  Nsac:8;                               // Data read access-time in CLK cycles (NSAC*100) [111:104]
+  UINT32  Taac:8;                               // Data read access-time [119:112]
+  UINT32  Reserved5:6;                          // Reserved [125:120]
+  UINT32  CsdStructure:2;                       // CSD structure [127:126]
+} SD_CSD2;
+
+typedef struct {
+  UINT32  Reserved;                             // Reserved [31:0]
+
+  UINT32  CmdSupport:4;                         // Command Support bits [35:32]
+  UINT32  Reserved1:6;                          // Reserved [41:36]
+  UINT32  SdSpec4:1;                            // Spec. Version 4.00 or higher [42:42]
+  UINT32  ExSecurity:4;                         // Extended Security Support [46:43]
+  UINT32  SdSpec3:1;                            // Spec. Version 3.00 or higher [47:47]
+  UINT32  SdBusWidths:4;                        // DAT Bus widths supported [51:48]
+  UINT32  SdSecurity:3;                         // CPRM security support [54:52]
+  UINT32  DataStatAfterErase:1;                 // Data status after erases [55]
+  UINT32  SdSpec:4;                             // SD Memory Card Spec. Version [59:56]
+  UINT32  ScrStructure:4;                       // SCR Structure [63:60]
+} SD_SCR;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SdramSpd.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SdramSpd.h
new file mode 100644
index 0000000000..0a4d8943c0
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SdramSpd.h
@@ -0,0 +1,74 @@
+/** @file
+  This file contains definitions for the SPD fields on an SDRAM.
+
+  Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#ifndef _SDRAM_SPD_H_
+#define _SDRAM_SPD_H_
+
+#include <IndustryStandard/SdramSpdDdr3.h>
+#include <IndustryStandard/SdramSpdDdr4.h>
+#include <IndustryStandard/SdramSpdLpDdr.h>
+
+//
+// SDRAM SPD field definitions
+//
+#define SPD_MEMORY_TYPE                 2
+#define SPD_SDRAM_ROW_ADDR              3
+#define SPD_SDRAM_COL_ADDR              4
+#define SPD_SDRAM_MODULE_ROWS           5
+#define SPD_SDRAM_MODULE_DATA_WIDTH_LSB 6
+#define SPD_SDRAM_MODULE_DATA_WIDTH_MSB 7
+#define SPD_SDRAM_ECC_SUPPORT           11
+#define SPD_SDRAM_REFRESH               12
+#define SPD_SDRAM_WIDTH                 13
+#define SPD_SDRAM_ERROR_WIDTH           14
+#define SPD_SDRAM_BURST_LENGTH          16
+#define SPD_SDRAM_NO_OF_BANKS           17
+#define SPD_SDRAM_CAS_LATENCY           18
+#define SPD_SDRAM_MODULE_ATTR           21
+
+#define SPD_SDRAM_TCLK1_PULSE           9   ///< cycle time for highest cas latency
+#define SPD_SDRAM_TAC1_PULSE            10  ///< access time for highest cas latency
+#define SPD_SDRAM_TCLK2_PULSE           23  ///< cycle time for 2nd highest cas latency
+#define SPD_SDRAM_TAC2_PULSE            24  ///< access time for 2nd highest cas latency
+#define SPD_SDRAM_TCLK3_PULSE           25  ///< cycle time for 3rd highest cas latency
+#define SPD_SDRAM_TAC3_PULSE            26  ///< access time for 3rd highest cas latency
+#define SPD_SDRAM_MIN_PRECHARGE         27
+#define SPD_SDRAM_ACTIVE_MIN            28
+#define SPD_SDRAM_RAS_CAS               29
+#define SPD_SDRAM_RAS_PULSE             30
+#define SPD_SDRAM_DENSITY               31
+
+//
+// Memory Type Definitions
+//
+#define SPD_VAL_SDR_TYPE  4       ///< SDR SDRAM memory
+#define SPD_VAL_DDR_TYPE  7       ///< DDR SDRAM memory
+#define SPD_VAL_DDR2_TYPE 8       ///< DDR2 SDRAM memory
+#define SPD_VAL_DDR3_TYPE 11      ///< DDR3 SDRAM memory
+#define SPD_VAL_DDR4_TYPE 12      ///< DDR4 SDRAM memory
+#define SPD_VAL_LPDDR3_TYPE 15    ///< LPDDR3 SDRAM memory
+#define SPD_VAL_LPDDR4_TYPE 16    ///< LPDDR4 SDRAM memory
+
+//
+// ECC Type Definitions
+//
+#define SPD_ECC_TYPE_NONE   0x00  ///< No error checking
+#define SPD_ECC_TYPE_PARITY 0x01  ///< No error checking
+#define SPD_ECC_TYPE_ECC    0x02  ///< Error checking only
+//
+// Module Attributes (Bit positions)
+//
+#define SPD_BUFFERED    0x01
+#define SPD_REGISTERED  0x02
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SdramSpdDdr3.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SdramSpdDdr3.h
new file mode 100644
index 0000000000..4bcf706616
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SdramSpdDdr3.h
@@ -0,0 +1,769 @@
+/** @file
+  This file contains definitions for SPD DDR3.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Revision Reference:
+    - Serial Presence Detect (SPD) for DDR3 SDRAM Modules Document Release 6
+      http://www.jedec.org/sites/default/files/docs/4_01_02_11R21A.pdf
+**/
+
+#ifndef _SDRAM_SPD_DDR3_H_
+#define _SDRAM_SPD_DDR3_H_
+
+#pragma pack (push, 1)
+
+typedef union {
+  struct {
+    UINT8  BytesUsed                           :  4; ///< Bits 3:0
+    UINT8  BytesTotal                          :  3; ///< Bits 6:4
+    UINT8  CrcCoverage                         :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD3_DEVICE_DESCRIPTION_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Minor                               :  4; ///< Bits 3:0
+    UINT8  Major                               :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD3_REVISION_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Type                                :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD3_DRAM_DEVICE_TYPE_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  ModuleType                          :  4; ///< Bits 3:0
+    UINT8  Reserved                            :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD3_MODULE_TYPE_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Density                             :  4; ///< Bits 3:0
+    UINT8  BankAddress                         :  3; ///< Bits 6:4
+    UINT8  Reserved                            :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD3_SDRAM_DENSITY_BANKS_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  ColumnAddress                       :  3; ///< Bits 2:0
+    UINT8  RowAddress                          :  3; ///< Bits 5:3
+    UINT8  Reserved                            :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD3_SDRAM_ADDRESSING_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  OperationAt1_50                     :  1; ///< Bits 0:0
+    UINT8  OperationAt1_35                     :  1; ///< Bits 1:1
+    UINT8  OperationAt1_25                     :  1; ///< Bits 2:2
+    UINT8  Reserved                            :  5; ///< Bits 7:3
+  } Bits;
+  UINT8  Data;
+} SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  SdramDeviceWidth                    :  3; ///< Bits 2:0
+    UINT8  RankCount                           :  3; ///< Bits 5:3
+    UINT8  Reserved                            :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD3_MODULE_ORGANIZATION_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  PrimaryBusWidth                     :  3; ///< Bits 2:0
+    UINT8  BusWidthExtension                   :  2; ///< Bits 4:3
+    UINT8  Reserved                            :  3; ///< Bits 7:5
+  } Bits;
+  UINT8  Data;
+} SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Divisor                             :  4; ///< Bits 3:0
+    UINT8  Dividend                            :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD3_FINE_TIMEBASE_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Dividend                            :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Divisor                             :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT;
+
+typedef struct {
+  SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT Dividend; ///< Medium Timebase (MTB) Dividend
+  SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT  Divisor;  ///< Medium Timebase (MTB) Divisor
+} SPD3_MEDIUM_TIMEBASE;
+
+typedef union {
+  struct {
+    UINT8  tCKmin                              :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD3_TCK_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT16 Cl4                                 :  1; ///< Bits 0:0
+    UINT16 Cl5                                 :  1; ///< Bits 1:1
+    UINT16 Cl6                                 :  1; ///< Bits 2:2
+    UINT16 Cl7                                 :  1; ///< Bits 3:3
+    UINT16 Cl8                                 :  1; ///< Bits 4:4
+    UINT16 Cl9                                 :  1; ///< Bits 5:5
+    UINT16 Cl10                                :  1; ///< Bits 6:6
+    UINT16 Cl11                                :  1; ///< Bits 7:7
+    UINT16 Cl12                                :  1; ///< Bits 8:8
+    UINT16 Cl13                                :  1; ///< Bits 9:9
+    UINT16 Cl14                                :  1; ///< Bits 10:10
+    UINT16 Cl15                                :  1; ///< Bits 11:11
+    UINT16 Cl16                                :  1; ///< Bits 12:12
+    UINT16 Cl17                                :  1; ///< Bits 13:13
+    UINT16 Cl18                                :  1; ///< Bits 14:14
+    UINT16 Reserved                            :  1; ///< Bits 15:15
+  } Bits;
+  UINT16 Data;
+  UINT8  Data8[2];
+} SPD3_CAS_LATENCIES_SUPPORTED_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tAAmin                              :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD3_TAA_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tWRmin                              :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD3_TWR_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tRCDmin                             :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD3_TRCD_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tRRDmin                             :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD3_TRRD_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tRPmin                              :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD3_TRP_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tRASminUpper                        :  4; ///< Bits 3:0
+    UINT8  tRCminUpper                         :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD3_TRAS_TRC_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tRASmin                             :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD3_TRAS_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tRCmin                              :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD3_TRC_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT16 tRFCmin                             :  16; ///< Bits 15:0
+  } Bits;
+  UINT16 Data;
+  UINT8  Data8[2];
+} SPD3_TRFC_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tWTRmin                             :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD3_TWTR_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tRTPmin                             :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD3_TRTP_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tFAWminUpper                        :  4; ///< Bits 3:0
+    UINT8  Reserved                            :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD3_TFAW_MIN_MTB_UPPER_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tFAWmin                             :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD3_TFAW_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Rzq6                                :  1; ///< Bits 0:0
+    UINT8  Rzq7                                :  1; ///< Bits 1:1
+    UINT8  Reserved                            :  5; ///< Bits 6:2
+    UINT8  DllOff                              :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  ExtendedTemperatureRange            :  1; ///< Bits 0:0
+    UINT8  ExtendedTemperatureRefreshRate      :  1; ///< Bits 1:1
+    UINT8  AutoSelfRefresh                     :  1; ///< Bits 2:2
+    UINT8  OnDieThermalSensor                  :  1; ///< Bits 3:3
+    UINT8  Reserved                            :  3; ///< Bits 6:4
+    UINT8  PartialArraySelfRefresh             :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD3_SDRAM_THERMAL_REFRESH_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  ThermalSensorAccuracy               :  7; ///< Bits 6:0
+    UINT8  ThermalSensorPresence               :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD3_MODULE_THERMAL_SENSOR_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  SignalLoading                       :  2; ///< Bits 1:0
+    UINT8  Reserved                            :  2; ///< Bits 3:2
+    UINT8  DieCount                            :  3; ///< Bits 6:4
+    UINT8  SdramDeviceType                     :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD3_SDRAM_DEVICE_TYPE_STRUCT;
+
+typedef union {
+  struct {
+    INT8  tCKminFine                           :  8; ///< Bits 7:0
+  } Bits;
+  INT8  Data;
+} SPD3_TCK_MIN_FTB_STRUCT;
+
+typedef union {
+  struct {
+    INT8  tAAminFine                           :  8; ///< Bits 7:0
+  } Bits;
+  INT8  Data;
+} SPD3_TAA_MIN_FTB_STRUCT;
+
+typedef union {
+  struct {
+    INT8  tRCDminFine                          :  8; ///< Bits 7:0
+  } Bits;
+  INT8  Data;
+} SPD3_TRCD_MIN_FTB_STRUCT;
+
+typedef union {
+  struct {
+    INT8  tRPminFine                           :  8; ///< Bits 7:0
+  } Bits;
+  INT8  Data;
+} SPD3_TRP_MIN_FTB_STRUCT;
+
+typedef union {
+  struct {
+    INT8  tRCminFine                           :  8; ///< Bits 7:0
+  } Bits;
+  INT8  Data;
+} SPD3_TRC_MIN_FTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  MaximumActivateCount                :  4; ///< Bits 3:0
+    UINT8  MaximumActivateWindow               :  2; ///< Bits 5:4
+    UINT8  VendorSpecific                      :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Height                              :  5; ///< Bits 4:0
+    UINT8  RawCardExtension                    :  3; ///< Bits 7:5
+  } Bits;
+  UINT8  Data;
+} SPD3_UNBUF_MODULE_NOMINAL_HEIGHT;
+
+typedef union {
+  struct {
+    UINT8  FrontThickness                      :  4; ///< Bits 3:0
+    UINT8  BackThickness                       :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD3_UNBUF_MODULE_NOMINAL_THICKNESS;
+
+typedef union {
+  struct {
+    UINT8  Card                                :  5; ///< Bits 4:0
+    UINT8  Revision                            :  2; ///< Bits 6:5
+    UINT8  Extension                           :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD3_UNBUF_REFERENCE_RAW_CARD;
+
+typedef union {
+  struct {
+    UINT8  MappingRank1                        :  1; ///< Bits 0:0
+    UINT8  Reserved                            :  7; ///< Bits 7:1
+  } Bits;
+  UINT8  Data;
+} SPD3_UNBUF_ADDRESS_MAPPING;
+
+typedef union {
+  struct {
+    UINT8  Height                              :  5; ///< Bits 4:0
+    UINT8  Reserved                            :  3; ///< Bits 7:5
+  } Bits;
+  UINT8  Data;
+} SPD3_RDIMM_MODULE_NOMINAL_HEIGHT;
+
+typedef union {
+  struct {
+    UINT8  FrontThickness                      :  4; ///< Bits 3:0
+    UINT8  BackThickness                       :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD3_RDIMM_MODULE_NOMINAL_THICKNESS;
+
+typedef union {
+  struct {
+    UINT8  Card                                :  5; ///< Bits 4:0
+    UINT8  Revision                            :  2; ///< Bits 6:5
+    UINT8  Extension                           :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD3_RDIMM_REFERENCE_RAW_CARD;
+
+typedef union {
+  struct {
+    UINT8  RegisterCount                       :  2; ///< Bits 1:0
+    UINT8  DramRowCount                        :  2; ///< Bits 3:2
+    UINT8  RegisterType                        :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD3_RDIMM_MODULE_ATTRIBUTES;
+
+typedef union {
+  struct {
+    UINT8  HeatSpreaderThermalCharacteristics  :  7; ///< Bits 6:0
+    UINT8  HeatSpreaderSolution                :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION;
+
+typedef union {
+  struct {
+    UINT16 ContinuationCount                   :  7; ///< Bits 6:0
+    UINT16 ContinuationParity                  :  1; ///< Bits 7:7
+    UINT16 LastNonZeroByte                     :  8; ///< Bits 15:8
+  } Bits;
+  UINT16 Data;
+  UINT8  Data8[2];
+} SPD3_MANUFACTURER_ID_CODE;
+
+typedef union {
+  struct {
+    UINT8  RegisterRevisionNumber;             ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD3_RDIMM_REGISTER_REVISION_NUMBER;
+
+typedef union {
+  struct {
+    UINT8 Bit0                                :  1; ///< Bits 0:0
+    UINT8 Bit1                                :  1; ///< Bits 1:1
+    UINT8 Bit2                                :  1; ///< Bits 2:2
+    UINT8 Reserved                            :  5; ///< Bits 7:3
+  } Bits;
+  UINT8  Data;
+} SPD3_RDIMM_REGISTER_TYPE;
+
+typedef union {
+  struct {
+    UINT8 Reserved                            :  4; ///< Bits 0:3
+    UINT8 CommandAddressAOutputs              :  2; ///< Bits 5:4
+    UINT8 CommandAddressBOutputs              :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS;
+
+typedef union {
+  struct {
+    UINT8 ControlSignalsAOutputs              :  2; ///< Bits 0:1
+    UINT8 ControlSignalsBOutputs              :  2; ///< Bits 3:2
+    UINT8 Y1Y3ClockOutputs                    :  2; ///< Bits 5:4
+    UINT8 Y0Y2ClockOutputs                    :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK;
+
+typedef union {
+  struct {
+    UINT8 Reserved0                           :  4; ///< Bits 0:3
+    UINT8 Reserved1                           :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD3_RDIMM_REGISTER_CONTROL_RESERVED;
+
+typedef union {
+  struct {
+    UINT8  Height                             :  5; ///< Bits 4:0
+    UINT8  Reserved                           :  3; ///< Bits 7:5
+  } Bits;
+  UINT8  Data;
+} SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT;
+
+typedef union {
+  struct {
+    UINT8  FrontThickness                     :  4; ///< Bits 3:0
+    UINT8  BackThickness                      :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS;
+
+typedef union {
+  struct {
+    UINT8  Card                               :  5; ///< Bits 4:0
+    UINT8  Revision                           :  2; ///< Bits 6:5
+    UINT8  Extension                          :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD3_LRDIMM_REFERENCE_RAW_CARD;
+
+typedef union {
+  struct {
+    UINT8  RegisterCount                      :  2; ///< Bits 1:0
+    UINT8  DramRowCount                       :  2; ///< Bits 3:2
+    UINT8  RegisterType                       :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD3_LRDIMM_MODULE_ATTRIBUTES;
+
+typedef union {
+  struct {
+    UINT8 AddressCommandPrelaunch             :  1; ///< Bits 0:0
+    UINT8 Rank1Rank5Swap                      :  1; ///< Bits 1:1
+    UINT8 Reserved0                           :  1; ///< Bits 2:2
+    UINT8 Reserved1                           :  1; ///< Bits 3:3
+    UINT8 AddressCommandOutputs               :  2; ///< Bits 5:4
+    UINT8 QxCS_nOutputs                       :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH;
+
+typedef union {
+  struct {
+    UINT8 QxOdtOutputs                        :  2; ///< Bits 1:0
+    UINT8 QxCkeOutputs                        :  2; ///< Bits 3:2
+    UINT8 Y1Y3ClockOutputs                    :  2; ///< Bits 5:4
+    UINT8 Y0Y2ClockOutputs                    :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD3_LRDIMM_TIMING_DRIVE_STRENGTH;
+
+typedef union {
+  struct {
+    UINT8 YExtendedDelay                      :  2; ///< Bits 1:0
+    UINT8 QxCS_n                              :  2; ///< Bits 3:2
+    UINT8 QxOdt                               :  2; ///< Bits 5:4
+    UINT8 QxCke                               :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD3_LRDIMM_EXTENDED_DELAY;
+
+typedef union {
+  struct {
+    UINT8 DelayY                              :  3; ///< Bits 2:0
+    UINT8 Reserved                            :  1; ///< Bits 3:3
+    UINT8 QxCS_n                              :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA;
+
+typedef union {
+  struct {
+    UINT8 QxCS_n                              :  4; ///< Bits 3:0
+    UINT8 QxOdt                               :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE;
+
+typedef union {
+  struct {
+    UINT8 RC8MdqOdtStrength                   :  3; ///< Bits 2:0
+    UINT8 RC8Reserved                         :  1; ///< Bits 3:3
+    UINT8 RC9MdqOdtStrength                   :  3; ///< Bits 6:4
+    UINT8 RC9Reserved                         :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH;
+
+typedef union {
+  struct {
+    UINT8 RC10DA3ValueR0                      :  1; ///< Bits 0:0
+    UINT8 RC10DA4ValueR0                      :  1; ///< Bits 1:1
+    UINT8 RC10DA3ValueR1                      :  1; ///< Bits 2:2
+    UINT8 RC10DA4ValueR1                      :  1; ///< Bits 3:3
+    UINT8 RC11DA3ValueR0                      :  1; ///< Bits 4:4
+    UINT8 RC11DA4ValueR0                      :  1; ///< Bits 5:5
+    UINT8 RC11DA3ValueR1                      :  1; ///< Bits 6:6
+    UINT8 RC11DA4ValueR1                      :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL;
+
+typedef union {
+  struct {
+    UINT8 Driver_Impedance                    :  2; ///< Bits 1:0
+    UINT8 Rtt_Nom                             :  3; ///< Bits 4:2
+    UINT8 Reserved                            :  1; ///< Bits 5:5
+    UINT8 Rtt_WR                              :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD3_LRDIMM_MR_1_2;
+
+typedef union {
+  struct {
+    UINT8 MinimumDelayTime                    :  7; ///< Bits 0:6
+    UINT8 Reserved                            :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD3_LRDIMM_MODULE_DELAY_TIME;
+
+typedef struct {
+  UINT8  Year;                                 ///< Year represented in BCD (00h = 2000)
+  UINT8  Week;                                 ///< Year represented in BCD (47h = week 47)
+} SPD3_MANUFACTURING_DATE;
+
+typedef union {
+  UINT32 Data;
+  UINT16 SerialNumber16[2];
+  UINT8  SerialNumber8[4];
+} SPD3_MANUFACTURER_SERIAL_NUMBER;
+
+typedef struct {
+  UINT8 Location;                              ///< Module Manufacturing Location
+} SPD3_MANUFACTURING_LOCATION;
+
+typedef struct {
+  SPD3_MANUFACTURER_ID_CODE            IdCode;                   ///< Module Manufacturer ID Code
+  SPD3_MANUFACTURING_LOCATION          Location;                 ///< Module Manufacturing Location
+  SPD3_MANUFACTURING_DATE              Date;                     ///< Module Manufacturing Year, in BCD (range: 2000-2255)
+  SPD3_MANUFACTURER_SERIAL_NUMBER      SerialNumber;             ///< Module Serial Number
+} SPD3_UNIQUE_MODULE_ID;
+
+typedef union {
+  UINT16 Crc[1];
+  UINT8  Data8[2];
+} SPD3_CYCLIC_REDUNDANCY_CODE;
+
+typedef struct {
+  SPD3_DEVICE_DESCRIPTION_STRUCT       Description;              ///< 0   Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
+  SPD3_REVISION_STRUCT                 Revision;                 ///< 1   SPD Revision
+  SPD3_DRAM_DEVICE_TYPE_STRUCT         DramDeviceType;           ///< 2   DRAM Device Type
+  SPD3_MODULE_TYPE_STRUCT              ModuleType;               ///< 3   Module Type
+  SPD3_SDRAM_DENSITY_BANKS_STRUCT      SdramDensityAndBanks;     ///< 4   SDRAM Density and Banks
+  SPD3_SDRAM_ADDRESSING_STRUCT         SdramAddressing;          ///< 5   SDRAM Addressing
+  SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT   ModuleNominalVoltage;     ///< 6   Module Nominal Voltage, VDD
+  SPD3_MODULE_ORGANIZATION_STRUCT      ModuleOrganization;       ///< 7   Module Organization
+  SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT  ModuleMemoryBusWidth;     ///< 8   Module Memory Bus Width
+  SPD3_FINE_TIMEBASE_STRUCT            FineTimebase;             ///< 9   Fine Timebase (FTB) Dividend / Divisor
+  SPD3_MEDIUM_TIMEBASE                 MediumTimebase;           ///< 10-11 Medium Timebase (MTB) Dividend
+  SPD3_TCK_MIN_MTB_STRUCT              tCKmin;                   ///< 12  SDRAM Minimum Cycle Time (tCKmin)
+  UINT8                                Reserved0;                ///< 13  Reserved
+  SPD3_CAS_LATENCIES_SUPPORTED_STRUCT  CasLatencies;             ///< 14-15 CAS Latencies Supported
+  SPD3_TAA_MIN_MTB_STRUCT              tAAmin;                   ///< 16  Minimum CAS Latency Time (tAAmin)
+  SPD3_TWR_MIN_MTB_STRUCT              tWRmin;                   ///< 17  Minimum Write Recovery Time (tWRmin)
+  SPD3_TRCD_MIN_MTB_STRUCT             tRCDmin;                  ///< 18  Minimum RAS# to CAS# Delay Time (tRCDmin)
+  SPD3_TRRD_MIN_MTB_STRUCT             tRRDmin;                  ///< 19  Minimum Row Active to Row Active Delay Time (tRRDmin)
+  SPD3_TRP_MIN_MTB_STRUCT              tRPmin;                   ///< 20  Minimum Row Precharge Delay Time (tRPmin)
+  SPD3_TRAS_TRC_MIN_MTB_STRUCT         tRASMintRCMinUpper;       ///< 21  Upper Nibbles for tRAS and tRC
+  SPD3_TRAS_MIN_MTB_STRUCT             tRASmin;                  ///< 22  Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
+  SPD3_TRC_MIN_MTB_STRUCT              tRCmin;                   ///< 23  Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
+  SPD3_TRFC_MIN_MTB_STRUCT             tRFCmin;                  ///< 24-25  Minimum Refresh Recovery Delay Time (tRFCmin)
+  SPD3_TWTR_MIN_MTB_STRUCT             tWTRmin;                  ///< 26  Minimum Internal Write to Read Command Delay Time (tWTRmin)
+  SPD3_TRTP_MIN_MTB_STRUCT             tRTPmin;                  ///< 27  Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+  SPD3_TFAW_MIN_MTB_UPPER_STRUCT       tFAWMinUpper;             ///< 28  Upper Nibble for tFAW
+  SPD3_TFAW_MIN_MTB_STRUCT             tFAWmin;                  ///< 29  Minimum Four Activate Window Delay Time (tFAWmin)
+  SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT  SdramOptionalFeatures;    ///< 30  SDRAM Optional Features
+  SPD3_SDRAM_THERMAL_REFRESH_STRUCT    ThermalAndRefreshOptions; ///< 31  SDRAM Thermal And Refresh Options
+  SPD3_MODULE_THERMAL_SENSOR_STRUCT    ModuleThermalSensor;      ///< 32  Module Thermal Sensor
+  SPD3_SDRAM_DEVICE_TYPE_STRUCT        SdramDeviceType;          ///< 33  SDRAM Device Type
+  SPD3_TCK_MIN_FTB_STRUCT              tCKminFine;               ///< 34  Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+  SPD3_TAA_MIN_FTB_STRUCT              tAAminFine;               ///< 35  Fine Offset for Minimum CAS Latency Time (tAAmin)
+  SPD3_TRCD_MIN_FTB_STRUCT             tRCDminFine;              ///< 36  Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+  SPD3_TRP_MIN_FTB_STRUCT              tRPminFine;               ///< 37  Minimum Row Precharge Delay Time (tRPmin)
+  SPD3_TRC_MIN_FTB_STRUCT              tRCminFine;               ///< 38  Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
+  UINT8                                Reserved1[40 - 39 + 1];   ///< 39 - 40 Reserved
+  SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT     MacValue;                 ///< 41  SDRAM Maximum Active Count (MAC) Value
+  UINT8                                Reserved2[59 - 42 + 1];   ///< 42 - 59 Reserved
+} SPD3_BASE_SECTION;
+
+typedef struct {
+  SPD3_UNBUF_MODULE_NOMINAL_HEIGHT     ModuleNominalHeight;      ///< 60  Module Nominal Height
+  SPD3_UNBUF_MODULE_NOMINAL_THICKNESS  ModuleMaximumThickness;   ///< 61  Module Maximum Thickness
+  SPD3_UNBUF_REFERENCE_RAW_CARD        ReferenceRawCardUsed;     ///< 62  Reference Raw Card Used
+  SPD3_UNBUF_ADDRESS_MAPPING           AddressMappingEdgeConn;   ///< 63  Address Mapping from Edge Connector to DRAM
+  UINT8                                Reserved[116 - 64 + 1];   ///< 64-116 Reserved
+} SPD3_MODULE_UNBUFFERED;
+
+typedef struct {
+  SPD3_RDIMM_MODULE_NOMINAL_HEIGHT     ModuleNominalHeight;      ///< 60  Module Nominal Height
+  SPD3_RDIMM_MODULE_NOMINAL_THICKNESS  ModuleMaximumThickness;   ///< 61  Module Maximum Thickness
+  SPD3_RDIMM_REFERENCE_RAW_CARD        ReferenceRawCardUsed;     ///< 62  Reference Raw Card Used
+  SPD3_RDIMM_MODULE_ATTRIBUTES         DimmModuleAttributes;     ///< 63  DIMM Module Attributes
+  SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION       ThermalHeatSpreaderSolution; ///< 64     RDIMM Thermal Heat Spreader Solution
+  SPD3_MANUFACTURER_ID_CODE                       RegisterManufacturerIdCode;  ///< 65-66  Register Manufacturer ID Code
+  SPD3_RDIMM_REGISTER_REVISION_NUMBER             RegisterRevisionNumber;      ///< 67     Register Revision Number
+  SPD3_RDIMM_REGISTER_TYPE                        RegisterType; ///< 68  Register Type
+  SPD3_RDIMM_REGISTER_CONTROL_RESERVED            Rc1Rc0;       ///< 69  RC1 (MS Nibble) / RC0 (LS Nibble) - Reserved
+  SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS     Rc3Rc2;       ///< 70  RC3 (MS Nibble) / RC2 (LS Nibble) - Drive Strength, Command/Address
+  SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK       Rc5Rc4;       ///< 71  RC5 (MS Nibble) / RC4 (LS Nibble) - Drive Strength, Control and Clock
+  SPD3_RDIMM_REGISTER_CONTROL_RESERVED            Rc7Rc6;       ///< 72  RC7 (MS Nibble) / RC6 (LS Nibble) - Reserved for Register Vendor
+  SPD3_RDIMM_REGISTER_CONTROL_RESERVED            Rc9Rc8;       ///< 73  RC9 (MS Nibble) / RC8 (LS Nibble) - Reserved
+  SPD3_RDIMM_REGISTER_CONTROL_RESERVED            Rc11Rc10;     ///< 74  RC11 (MS Nibble) / RC10 (LS Nibble) - Reserved
+  SPD3_RDIMM_REGISTER_CONTROL_RESERVED            Rc13Rc12;     ///< 75  RC12 (MS Nibble) / RC12 (LS Nibble) - Reserved
+  SPD3_RDIMM_REGISTER_CONTROL_RESERVED            Rc15Rc14;     ///< 76  RC15 (MS Nibble) / RC14 (LS Nibble) - Reserved
+  UINT8                               Reserved[116 - 77 + 1];   ///< 77-116 Reserved
+} SPD3_MODULE_REGISTERED;
+
+typedef struct {
+  SPD3_UNBUF_MODULE_NOMINAL_HEIGHT     ModuleNominalHeight;     ///< 60  Module Nominal Height
+  SPD3_UNBUF_MODULE_NOMINAL_THICKNESS  ModuleMaximumThickness;  ///< 61  Module Maximum Thickness
+  SPD3_UNBUF_REFERENCE_RAW_CARD        ReferenceRawCardUsed;    ///< 62  Reference Raw Card Used
+  UINT8                                Reserved[116 - 63 + 1];  ///< 63-116 Reserved
+} SPD3_MODULE_CLOCKED;
+
+typedef struct {
+  SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT     ModuleNominalHeight;    ///< 60  Module Nominal Height
+  SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS  ModuleMaximumThickness; ///< 61  Module Maximum Thickness
+  SPD3_LRDIMM_REFERENCE_RAW_CARD        ReferenceRawCardUsed;   ///< 62  Reference Raw Card Used
+  SPD3_LRDIMM_MODULE_ATTRIBUTES         DimmModuleAttributes;   ///< 63  Module Attributes
+  UINT8                                         MemoryBufferRevisionNumber;       ///< 64    Memory Buffer Revision Number
+  SPD3_MANUFACTURER_ID_CODE                     ManufacturerIdCode;               ///< 65-66 Memory Buffer Manufacturer ID Code
+  SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH     TimingControlDriveStrengthCaCs;   ///< 67    F0RC3 / F0RC2 - Timing Control & Drive Strength, CA & CS
+  SPD3_LRDIMM_TIMING_DRIVE_STRENGTH             DriveStrength;                    ///< 68    F0RC5 / F0RC4 - Drive Strength, ODT & CKE and Y
+  SPD3_LRDIMM_EXTENDED_DELAY                    ExtendedDelay;                    ///< 69    F1RC11 / F1RC8 - Extended Delay for Y, CS and ODT & CKE
+  SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA    AdditiveDelayForCsCa;             ///< 70    F1RC13 / F1RC12 - Additive Delay for CS and CA
+  SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE    AdditiveDelayForOdtCke;           ///< 71    F1RC15 / F1RC14 - Additive Delay for ODT & CKE
+  SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH    MdqTerminationDriveStrengthFor800_1066; ///< 72    F1RC15 / F1RC14 - Additive Delay for ODT & CKE
+  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_0_1QxOdtControlFor800_1066;  ///< 73    F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066
+  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_2_3QxOdtControlFor800_1066;  ///< 74    F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066
+  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_4_5QxOdtControlFor800_1066;  ///< 75    F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066
+  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_6_7QxOdtControlFor800_1066;  ///< 76    F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066
+  SPD3_LRDIMM_MR_1_2                            MR_1_2RegistersFor800_1066;       ///< 77    MR1,2 Registers for 800 & 1066
+  SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH    MdqTerminationDriveStrengthFor1333_1600; ///< 78    F1RC15 / F1RC14 - Additive Delay for ODT & CKE
+  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_0_1QxOdtControlFor1333_1600; ///< 79    F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066
+  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_2_3QxOdtControlFor1333_1600; ///< 80    F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066
+  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_4_5QxOdtControlFor1333_1600; ///< 81    F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066
+  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_6_7QxOdtControlFor1333_1600; ///< 82    F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066
+  SPD3_LRDIMM_MR_1_2                            MR_1_2RegistersFor1333_1600;      ///< 83    MR1,2 Registers for 800 & 1066
+  SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH    MdqTerminationDriveStrengthFor1866_2133; ///< 84    F1RC15 / F1RC14 - Additive Delay for ODT & CKE
+  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_0_1QxOdtControlFor1866_2133; ///< 85    F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066
+  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_2_3QxOdtControlFor1866_2133; ///< 86    F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066
+  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_4_5QxOdtControlFor1866_2133; ///< 87    F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066
+  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_6_7QxOdtControlFor1866_2133; ///< 88    F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066
+  SPD3_LRDIMM_MR_1_2                            MR_1_2RegistersFor1866_2133;      ///< 89    MR1,2 Registers for 800 & 1066
+  SPD3_LRDIMM_MODULE_DELAY_TIME                 MinimumModuleDelayTimeFor1_5V;    ///< 90    Minimum Module Delay Time for 1.5 V
+  SPD3_LRDIMM_MODULE_DELAY_TIME                 MaximumModuleDelayTimeFor1_5V;    ///< 91    Maximum Module Delay Time for 1.5 V
+  SPD3_LRDIMM_MODULE_DELAY_TIME                 MinimumModuleDelayTimeFor1_35V;   ///< 92    Minimum Module Delay Time for 1.35 V
+  SPD3_LRDIMM_MODULE_DELAY_TIME                 MaximumModuleDelayTimeFor1_35V;   ///< 93    Maximum Module Delay Time for 1.35 V
+  SPD3_LRDIMM_MODULE_DELAY_TIME                 MinimumModuleDelayTimeFor1_25V;   ///< 94    Minimum Module Delay Time for 1.25 V
+  SPD3_LRDIMM_MODULE_DELAY_TIME                 MaximumModuleDelayTimeFor1_25V;   ///< 95    Maximum Module Delay Time for 1.25 V
+  UINT8                                         Reserved[101 - 96 + 1];           ///< 96-101  Reserved
+  UINT8                                         PersonalityByte[116 - 102 + 1];   ///< 102-116 Memory Buffer Personality Bytes
+} SPD3_MODULE_LOADREDUCED;
+
+typedef union {
+  SPD3_MODULE_UNBUFFERED              Unbuffered;               ///< 128-255 Unbuffered Memory Module Types
+  SPD3_MODULE_REGISTERED              Registered;               ///< 128-255 Registered Memory Module Types
+  SPD3_MODULE_CLOCKED                 Clocked;                  ///< 128-255 Registered Memory Module Types
+  SPD3_MODULE_LOADREDUCED             LoadReduced;              ///< 128-255 Load Reduced Memory Module Types
+} SPD3_MODULE_SPECIFIC;
+
+typedef struct {
+  UINT8                          ModulePartNumber[145 - 128 + 1];        ///< 128-145 Module Part Number
+} SPD3_MODULE_PART_NUMBER;
+
+typedef struct {
+  UINT8                          ModuleRevisionCode[147 - 146 + 1];      ///< 146-147 Module Revision Code
+} SPD3_MODULE_REVISION_CODE;
+
+typedef struct {
+  UINT8                          ManufacturerSpecificData[175 - 150 + 1];///< 150-175 Manufacturer's Specific Data
+} SPD3_MANUFACTURER_SPECIFIC;
+
+///
+/// DDR3 Serial Presence Detect structure
+///
+typedef struct {
+  SPD3_BASE_SECTION           General;                                ///< 0-59    General Section
+  SPD3_MODULE_SPECIFIC        Module;                                 ///< 60-116  Module-Specific Section
+  SPD3_UNIQUE_MODULE_ID       ModuleId;                               ///< 117-125 Unique Module ID
+  SPD3_CYCLIC_REDUNDANCY_CODE Crc;                                    ///< 126-127 Cyclical Redundancy Code (CRC)
+  SPD3_MODULE_PART_NUMBER     ModulePartNumber;                       ///< 128-145 Module Part Number
+  SPD3_MODULE_REVISION_CODE   ModuleRevisionCode;                     ///< 146-147 Module Revision Code
+  SPD3_MANUFACTURER_ID_CODE   DramIdCode;                             ///< 148-149 Dram Manufacturer ID Code
+  SPD3_MANUFACTURER_SPECIFIC  ManufacturerSpecificData;               ///< 150-175 Manufacturer's Specific Data
+  UINT8                       Reserved[255 - 176 + 1];                ///< 176-255 Open for Customer Use
+} SPD_DDR3;
+
+#pragma pack (pop)
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SdramSpdDdr4.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SdramSpdDdr4.h
new file mode 100644
index 0000000000..d6bc76f6cf
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SdramSpdDdr4.h
@@ -0,0 +1,958 @@
+/** @file
+  This file contains definitions for SPD DDR4.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Revision Reference:
+    - Serial Presence Detect (SPD) for DDR4 SDRAM Modules Document Release 4
+      http://www.jedec.org/standards-documents/docs/spd412l-4
+**/
+
+#ifndef _SDRAM_SPD_DDR4_H_
+#define _SDRAM_SPD_DDR4_H_
+
+#pragma pack (push, 1)
+
+typedef union {
+  struct {
+    UINT8  BytesUsed                           :  4; ///< Bits 3:0
+    UINT8  BytesTotal                          :  3; ///< Bits 6:4
+    UINT8  CrcCoverage                         :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD4_DEVICE_DESCRIPTION_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Minor                               :  4; ///< Bits 3:0
+    UINT8  Major                               :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD4_REVISION_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Type                                :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD4_DRAM_DEVICE_TYPE_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  ModuleType                          :  4; ///< Bits 3:0
+    UINT8  HybridMedia                         :  3; ///< Bits 6:4
+    UINT8  Hybrid                              :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD4_MODULE_TYPE_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Density                             :  4; ///< Bits 3:0
+    UINT8  BankAddress                         :  2; ///< Bits 5:4
+    UINT8  BankGroup                           :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD4_SDRAM_DENSITY_BANKS_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  ColumnAddress                       :  3; ///< Bits 2:0
+    UINT8  RowAddress                          :  3; ///< Bits 5:3
+    UINT8  Reserved                            :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD4_SDRAM_ADDRESSING_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  SignalLoading                       :  2; ///< Bits 1:0
+    UINT8  Reserved                            :  2; ///< Bits 3:2
+    UINT8  DieCount                            :  3; ///< Bits 6:4
+    UINT8  SdramPackageType                    :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  MaximumActivateCount                :  4; ///< Bits 3:0
+    UINT8  MaximumActivateWindow               :  2; ///< Bits 5:4
+    UINT8  Reserved                            :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Reserved                            :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD4_SDRAM_THERMAL_REFRESH_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Reserved                            :  5; ///< Bits 4:0
+    UINT8  SoftPPR                             :  1; ///< Bits 5:5
+    UINT8  PostPackageRepair                   :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  SignalLoading                       :  2; ///< Bits 1:0
+    UINT8  DRAMDensityRatio                    :  2; ///< Bits 3:2
+    UINT8  DieCount                            :  3; ///< Bits 6:4
+    UINT8  SdramPackageType                    :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  OperationAt1_20                     :  1; ///< Bits 0:0
+    UINT8  EndurantAt1_20                      :  1; ///< Bits 1:1
+    UINT8  Reserved                            :  6; ///< Bits 7:2
+  } Bits;
+  UINT8  Data;
+} SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  SdramDeviceWidth                    :  3; ///< Bits 2:0
+    UINT8  RankCount                           :  3; ///< Bits 5:3
+    UINT8  RankMix                             :  1; ///< Bits 6:6
+    UINT8  Reserved                            :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD4_MODULE_ORGANIZATION_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  PrimaryBusWidth                     :  3; ///< Bits 2:0
+    UINT8  BusWidthExtension                   :  2; ///< Bits 4:3
+    UINT8  Reserved                            :  3; ///< Bits 7:5
+  } Bits;
+  UINT8  Data;
+} SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Reserved                            :  7; ///< Bits 6:0
+    UINT8  ThermalSensorPresence               :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD4_MODULE_THERMAL_SENSOR_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  ExtendedBaseModuleType              :  4; ///< Bits 3:0
+    UINT8  Reserved                            :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD4_EXTENDED_MODULE_TYPE_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Fine                                :  2; ///< Bits 1:0
+    UINT8  Medium                              :  2; ///< Bits 3:2
+    UINT8  Reserved                            :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD4_TIMEBASE_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tCKmin                              :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD4_TCK_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tCKmax                              :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD4_TCK_MAX_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT32 Cl7                                 :  1; ///< Bits 0:0
+    UINT32 Cl8                                 :  1; ///< Bits 1:1
+    UINT32 Cl9                                 :  1; ///< Bits 2:2
+    UINT32 Cl10                                :  1; ///< Bits 3:3
+    UINT32 Cl11                                :  1; ///< Bits 4:4
+    UINT32 Cl12                                :  1; ///< Bits 5:5
+    UINT32 Cl13                                :  1; ///< Bits 6:6
+    UINT32 Cl14                                :  1; ///< Bits 7:7
+    UINT32 Cl15                                :  1; ///< Bits 8:8
+    UINT32 Cl16                                :  1; ///< Bits 9:9
+    UINT32 Cl17                                :  1; ///< Bits 10:10
+    UINT32 Cl18                                :  1; ///< Bits 11:11
+    UINT32 Cl19                                :  1; ///< Bits 12:12
+    UINT32 Cl20                                :  1; ///< Bits 13:13
+    UINT32 Cl21                                :  1; ///< Bits 14:14
+    UINT32 Cl22                                :  1; ///< Bits 15:15
+    UINT32 Cl23                                :  1; ///< Bits 16:16
+    UINT32 Cl24                                :  1; ///< Bits 17:17
+    UINT32 Cl25                                :  1; ///< Bits 18:18
+    UINT32 Cl26                                :  1; ///< Bits 19:19
+    UINT32 Cl27                                :  1; ///< Bits 20:20
+    UINT32 Cl28                                :  1; ///< Bits 21:21
+    UINT32 Cl29                                :  1; ///< Bits 22:22
+    UINT32 Cl30                                :  1; ///< Bits 23:23
+    UINT32 Cl31                                :  1; ///< Bits 24:24
+    UINT32 Cl32                                :  1; ///< Bits 25:25
+    UINT32 Cl33                                :  1; ///< Bits 26:26
+    UINT32 Cl34                                :  1; ///< Bits 27:27
+    UINT32 Cl35                                :  1; ///< Bits 28:28
+    UINT32 Cl36                                :  1; ///< Bits 29:29
+    UINT32 Reserved                            :  1; ///< Bits 30:30
+    UINT32 ClRange                             :  1; ///< Bits 31:31
+  } Bits;
+  struct {
+    UINT32 Cl23                                :  1; ///< Bits 0:0
+    UINT32 Cl24                                :  1; ///< Bits 1:1
+    UINT32 Cl25                                :  1; ///< Bits 2:2
+    UINT32 Cl26                                :  1; ///< Bits 3:3
+    UINT32 Cl27                                :  1; ///< Bits 4:4
+    UINT32 Cl28                                :  1; ///< Bits 5:5
+    UINT32 Cl29                                :  1; ///< Bits 6:6
+    UINT32 Cl30                                :  1; ///< Bits 7:7
+    UINT32 Cl31                                :  1; ///< Bits 8:8
+    UINT32 Cl32                                :  1; ///< Bits 9:9
+    UINT32 Cl33                                :  1; ///< Bits 10:10
+    UINT32 Cl34                                :  1; ///< Bits 11:11
+    UINT32 Cl35                                :  1; ///< Bits 12:12
+    UINT32 Cl36                                :  1; ///< Bits 13:13
+    UINT32 Cl37                                :  1; ///< Bits 14:14
+    UINT32 Cl38                                :  1; ///< Bits 15:15
+    UINT32 Cl39                                :  1; ///< Bits 16:16
+    UINT32 Cl40                                :  1; ///< Bits 17:17
+    UINT32 Cl41                                :  1; ///< Bits 18:18
+    UINT32 Cl42                                :  1; ///< Bits 19:19
+    UINT32 Cl43                                :  1; ///< Bits 20:20
+    UINT32 Cl44                                :  1; ///< Bits 21:21
+    UINT32 Cl45                                :  1; ///< Bits 22:22
+    UINT32 Cl46                                :  1; ///< Bits 23:23
+    UINT32 Cl47                                :  1; ///< Bits 24:24
+    UINT32 Cl48                                :  1; ///< Bits 25:25
+    UINT32 Cl49                                :  1; ///< Bits 26:26
+    UINT32 Cl50                                :  1; ///< Bits 27:27
+    UINT32 Cl51                                :  1; ///< Bits 28:28
+    UINT32 Cl52                                :  1; ///< Bits 29:29
+    UINT32 Reserved                            :  1; ///< Bits 30:30
+    UINT32 ClRange                             :  1; ///< Bits 31:31
+  } HighRangeBits;
+  UINT32 Data;
+  UINT16 Data16[2];
+  UINT8  Data8[4];
+} SPD4_CAS_LATENCIES_SUPPORTED_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tAAmin                              :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD4_TAA_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tRCDmin                             :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD4_TRCD_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tRPmin                              :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD4_TRP_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tRASminUpper                        :  4; ///< Bits 3:0
+    UINT8  tRCminUpper                         :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD4_TRAS_TRC_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tRASmin                             :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD4_TRAS_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tRCmin                              :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD4_TRC_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT16 tRFCmin                             :  16; ///< Bits 15:0
+  } Bits;
+  UINT16 Data;
+  UINT8  Data8[2];
+} SPD4_TRFC_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tFAWminUpper                        :  4; ///< Bits 3:0
+    UINT8  Reserved                            :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD4_TFAW_MIN_MTB_UPPER_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tFAWmin                             :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD4_TFAW_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tRRDmin                             :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD4_TRRD_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tCCDmin                             :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD4_TCCD_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tWRminMostSignificantNibble         :  4; ///< Bits 3:0
+    UINT8  Reserved                            :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD4_TWR_UPPER_NIBBLE_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tWRmin                              :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD4_TWR_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tWTR_SminMostSignificantNibble      :  4; ///< Bits 3:0
+    UINT8  tWTR_LminMostSignificantNibble      :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD4_TWTR_UPPER_NIBBLE_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tWTRmin                             :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD4_TWTR_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  BitOrderatSDRAM                     :  5; ///< Bits 4:0
+    UINT8  WiredtoUpperLowerNibble             :  1; ///< Bits 5:5
+    UINT8  PackageRankMap                      :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT;
+
+typedef union {
+  struct {
+    INT8  tCCDminFine                          :  8; ///< Bits 7:0
+  } Bits;
+  INT8  Data;
+} SPD4_TCCD_MIN_FTB_STRUCT;
+
+typedef union {
+  struct {
+    INT8  tRRDminFine                          :  8; ///< Bits 7:0
+  } Bits;
+  INT8  Data;
+} SPD4_TRRD_MIN_FTB_STRUCT;
+
+typedef union {
+  struct {
+    INT8  tRCminFine                           :  8; ///< Bits 7:0
+  } Bits;
+  INT8  Data;
+} SPD4_TRC_MIN_FTB_STRUCT;
+
+typedef union {
+  struct {
+    INT8  tRPminFine                           :  8; ///< Bits 7:0
+  } Bits;
+  INT8  Data;
+} SPD4_TRP_MIN_FTB_STRUCT;
+
+typedef union {
+  struct {
+    INT8  tRCDminFine                          :  8; ///< Bits 7:0
+  } Bits;
+  INT8  Data;
+} SPD4_TRCD_MIN_FTB_STRUCT;
+
+typedef union {
+  struct {
+    INT8  tAAminFine                           :  8; ///< Bits 7:0
+  } Bits;
+  INT8  Data;
+} SPD4_TAA_MIN_FTB_STRUCT;
+
+typedef union {
+  struct {
+    INT8  tCKmaxFine                           :  8; ///< Bits 7:0
+  } Bits;
+  INT8  Data;
+} SPD4_TCK_MAX_FTB_STRUCT;
+
+typedef union {
+  struct {
+    INT8  tCKminFine                           :  8; ///< Bits 7:0
+  } Bits;
+  INT8  Data;
+} SPD4_TCK_MIN_FTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Height                              :  5; ///< Bits 4:0
+    UINT8  RawCardExtension                    :  3; ///< Bits 7:5
+  } Bits;
+  UINT8  Data;
+} SPD4_UNBUF_MODULE_NOMINAL_HEIGHT;
+
+typedef union {
+  struct {
+    UINT8  FrontThickness                      :  4; ///< Bits 3:0
+    UINT8  BackThickness                       :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD4_UNBUF_MODULE_NOMINAL_THICKNESS;
+
+typedef union {
+  struct {
+    UINT8  Card                                :  5; ///< Bits 4:0
+    UINT8  Revision                            :  2; ///< Bits 6:5
+    UINT8  Extension                           :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD4_UNBUF_REFERENCE_RAW_CARD;
+
+typedef union {
+  struct {
+    UINT8  MappingRank1                        :  1; ///< Bits 0:0
+    UINT8  Reserved                            :  7; ///< Bits 7:1
+  } Bits;
+  UINT8  Data;
+} SPD4_UNBUF_ADDRESS_MAPPING;
+
+typedef union {
+  struct {
+    UINT8  Height                              :  5; ///< Bits 4:0
+    UINT8  Reserved                            :  3; ///< Bits 7:5
+  } Bits;
+  UINT8  Data;
+} SPD4_RDIMM_MODULE_NOMINAL_HEIGHT;
+
+typedef union {
+  struct {
+    UINT8  FrontThickness                      :  4; ///< Bits 3:0
+    UINT8  BackThickness                       :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD4_RDIMM_MODULE_NOMINAL_THICKNESS;
+
+typedef union {
+  struct {
+    UINT8  Card                                :  5; ///< Bits 4:0
+    UINT8  Revision                            :  2; ///< Bits 6:5
+    UINT8  Extension                           :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD4_RDIMM_REFERENCE_RAW_CARD;
+
+typedef union {
+  struct {
+    UINT8  RegisterCount                       :  2; ///< Bits 1:0
+    UINT8  DramRowCount                        :  2; ///< Bits 3:2
+    UINT8  RegisterType                        :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD4_RDIMM_MODULE_ATTRIBUTES;
+
+typedef union {
+  struct {
+    UINT8  HeatSpreaderThermalCharacteristics  :  7; ///< Bits 6:0
+    UINT8  HeatSpreaderSolution                :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION;
+
+typedef union {
+  struct {
+    UINT16 ContinuationCount                   :  7; ///< Bits 6:0
+    UINT16 ContinuationParity                  :  1; ///< Bits 7:7
+    UINT16 LastNonZeroByte                     :  8; ///< Bits 15:8
+  } Bits;
+  UINT16 Data;
+  UINT8  Data8[2];
+} SPD4_MANUFACTURER_ID_CODE;
+
+typedef union {
+  struct {
+    UINT8  RegisterRevisionNumber;             ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD4_RDIMM_REGISTER_REVISION_NUMBER;
+
+typedef union {
+  struct {
+    UINT8 Rank1Mapping                        :  1; ///< Bits 0:0
+    UINT8 Reserved                            :  7; ///< Bits 7:1
+  } Bits;
+  UINT8  Data;
+} SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM;
+
+typedef union {
+  struct {
+    UINT8 Cke                                 :  2; ///< Bits 1:0
+    UINT8 Odt                                 :  2; ///< Bits 3:2
+    UINT8 CommandAddress                      :  2; ///< Bits 5:4
+    UINT8 ChipSelect                          :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS;
+
+typedef union {
+  struct {
+    UINT8 Y0Y2                                :  2; ///< Bits 1:0
+    UINT8 Y1Y3                                :  2; ///< Bits 3:2
+    UINT8 Reserved0                           :  2; ///< Bits 5:4
+    UINT8 RcdOutputSlewRateControl            :  1; ///< Bits 6:6
+    UINT8 Reserved1                           :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK;
+
+typedef union {
+  struct {
+    UINT8  Height                             :  5; ///< Bits 4:0
+    UINT8  Reserved                           :  3; ///< Bits 7:5
+  } Bits;
+  UINT8  Data;
+} SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT;
+
+typedef union {
+  struct {
+    UINT8  FrontThickness                     :  4; ///< Bits 3:0
+    UINT8  BackThickness                      :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS;
+
+typedef union {
+  struct {
+    UINT8  Card                               :  5; ///< Bits 4:0
+    UINT8  Revision                           :  2; ///< Bits 6:5
+    UINT8  Extension                          :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD4_LRDIMM_REFERENCE_RAW_CARD;
+
+typedef union {
+  struct {
+    UINT8  RegisterCount                      :  2; ///< Bits 1:0
+    UINT8  DramRowCount                       :  2; ///< Bits 3:2
+    UINT8  RegisterType                       :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD4_LRDIMM_MODULE_ATTRIBUTES;
+
+typedef union {
+  struct {
+    UINT8  HeatSpreaderThermalCharacteristics :  7; ///< Bits 6:0
+    UINT8  HeatSpreaderSolution               :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION;
+
+typedef union {
+  struct {
+    UINT8  RegisterRevisionNumber;                  ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD4_LRDIMM_REGISTER_REVISION_NUMBER;
+
+typedef union {
+  struct {
+    UINT8 Rank1Mapping                        :  1; ///< Bits 0:0
+    UINT8 Reserved                            :  7; ///< Bits 7:1
+  } Bits;
+  UINT8  Data;
+} SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM;
+
+typedef union {
+  struct {
+    UINT8 Cke                                 :  2; ///< Bits 1:0
+    UINT8 Odt                                 :  2; ///< Bits 3:2
+    UINT8 CommandAddress                      :  2; ///< Bits 5:4
+    UINT8 ChipSelect                          :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS;
+
+typedef union {
+  struct {
+    UINT8 Y0Y2                                :  2; ///< Bits 1:0
+    UINT8 Y1Y3                                :  2; ///< Bits 3:2
+    UINT8 Reserved0                           :  2; ///< Bits 5:4
+    UINT8 RcdOutputSlewRateControl            :  1; ///< Bits 6:6
+    UINT8 Reserved1                           :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK;
+
+typedef struct {
+  UINT8  DataBufferRevisionNumber;
+} SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER;
+
+typedef union {
+  struct {
+    UINT8  DramVrefDQForPackageRank0          :  6; ///< Bits 5:0
+    UINT8  Reserved                           :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK;
+
+typedef struct {
+  UINT8  DataBufferVrefDQforDramInterface;
+} SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE;
+
+typedef union {
+  struct {
+    UINT8  DramInterfaceMdqDriveStrength           :  4; ///< Bits 3:0
+    UINT8  DramInterfaceMdqReadTerminationStrength :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE;
+
+typedef union {
+  struct {
+    UINT8  DataRateLe1866                           :  2; ///< Bits 1:0
+    UINT8  DataRateLe2400                           :  2; ///< Bits 3:2
+    UINT8  DataRateLe3200                           :  2; ///< Bits 5:4
+    UINT8  Reserved                                 :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD4_LRDIMM_DRAM_DRIVE_STRENGTH;
+
+typedef union {
+  struct {
+    UINT8  Rtt_Nom                                  :  3; ///< Bits 2:0
+    UINT8  Rtt_WR                                   :  3; ///< Bits 5:3
+    UINT8  Reserved                                 :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE;
+
+typedef union {
+  struct {
+    UINT8  PackageRanks0_1                          :  3; ///< Bits 2:0
+    UINT8  PackageRanks2_3                          :  3; ///< Bits 5:3
+    UINT8  Reserved                                 :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE;
+
+typedef union {
+  struct {
+    UINT8  Rank0                                    :  1; ///< Bits 0:0
+    UINT8  Rank1                                    :  1; ///< Bits 1:1
+    UINT8  Rank2                                    :  1; ///< Bits 2:2
+    UINT8  Rank3                                    :  1; ///< Bits 3:3
+    UINT8  DataBuffer                               :  1; ///< Bits 4:4
+    UINT8  Reserved                                 :  3; ///< Bits 7:5
+  } Bits;
+  UINT8  Data;
+} SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE;
+
+typedef union {
+  struct {
+    UINT8  DataBufferGainAdjustment                 :  1; ///< Bits 0:0
+    UINT8  DataBufferDfe                            :  1; ///< Bits 1:1
+    UINT8  Reserved                                 :  6; ///< Bits 7:2
+  } Bits;
+  UINT8  Data;
+} SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION;
+
+typedef UINT16 SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER;
+
+typedef union {
+  struct {
+    UINT16 ContinuationCount                   :  7; ///< Bits 6:0
+    UINT16 ContinuationParity                  :  1; ///< Bits 7:7
+    UINT16 LastNonZeroByte                     :  8; ///< Bits 15:8
+  } Bits;
+  UINT16 Data;
+  UINT8  Data8[2];
+} SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE;
+
+typedef UINT16 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER;
+
+typedef UINT8 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE;
+
+typedef union {
+  struct {
+    UINT8  Card                                :  5; ///< Bits 4:0
+    UINT8  Revision                            :  2; ///< Bits 6:5
+    UINT8  Extension                           :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD4_NVDIMM_REFERENCE_RAW_CARD;
+
+typedef union {
+  struct {
+    UINT8  Reserved                            :  4; ///< Bits 3:0
+    UINT8  Extension                           :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD4_NVDIMM_MODULE_CHARACTERISTICS;
+
+typedef struct {
+  UINT8  Reserved;
+  UINT8  MediaType;
+} SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES;
+
+typedef UINT8 SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME;
+
+typedef union {
+  struct {
+    UINT16 FunctionInterface                   :  5; ///< Bits 4:0
+    UINT16 FunctionClass                       :  5; ///< Bits 9:5
+    UINT16 BlockOffset                         :  4; ///< Bits 13:10
+    UINT16 Reserved                            :  1; ///< Bits 14:14
+    UINT16 Implemented                         :  1; ///< Bits 15:15
+  } Bits;
+  UINT16 Data;
+  UINT8  Data8[2];
+} SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR;
+
+typedef struct {
+  UINT8  Year;                                 ///< Year represented in BCD (00h = 2000)
+  UINT8  Week;                                 ///< Year represented in BCD (47h = week 47)
+} SPD4_MANUFACTURING_DATE;
+
+typedef union {
+  UINT32 Data;
+  UINT16 SerialNumber16[2];
+  UINT8  SerialNumber8[4];
+} SPD4_MANUFACTURER_SERIAL_NUMBER;
+
+typedef struct {
+  UINT8 Location;                              ///< Module Manufacturing Location
+} SPD4_MANUFACTURING_LOCATION;
+
+typedef struct {
+  SPD4_MANUFACTURER_ID_CODE            IdCode;                   ///< Module Manufacturer ID Code
+  SPD4_MANUFACTURING_LOCATION          Location;                 ///< Module Manufacturing Location
+  SPD4_MANUFACTURING_DATE              Date;                     ///< Module Manufacturing Year, in BCD (range: 2000-2255)
+  SPD4_MANUFACTURER_SERIAL_NUMBER      SerialNumber;             ///< Module Serial Number
+} SPD4_UNIQUE_MODULE_ID;
+
+typedef union {
+  UINT16 Crc[1];
+  UINT8  Data8[2];
+} SPD4_CYCLIC_REDUNDANCY_CODE;
+
+typedef struct {
+  SPD4_DEVICE_DESCRIPTION_STRUCT            Description;              ///< 0       Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
+  SPD4_REVISION_STRUCT                      Revision;                 ///< 1       SPD Revision
+  SPD4_DRAM_DEVICE_TYPE_STRUCT              DramDeviceType;           ///< 2       DRAM Device Type
+  SPD4_MODULE_TYPE_STRUCT                   ModuleType;               ///< 3       Module Type
+  SPD4_SDRAM_DENSITY_BANKS_STRUCT           SdramDensityAndBanks;     ///< 4       SDRAM Density and Banks
+  SPD4_SDRAM_ADDRESSING_STRUCT              SdramAddressing;          ///< 5       SDRAM Addressing
+  SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT    PrimarySdramPackageType;  ///< 6       Primary SDRAM Package Type
+  SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT       SdramOptionalFeatures;    ///< 7       SDRAM Optional Features
+  SPD4_SDRAM_THERMAL_REFRESH_STRUCT         ThermalAndRefreshOptions; ///< 8       SDRAM Thermal and Refresh Options
+  SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures;    ///< 9       Other SDRAM Optional Features
+  SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT  SecondarySdramPackageType;///< 10      Secondary SDRAM Package Type
+  SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT        ModuleNominalVoltage;     ///< 11      Module Nominal Voltage, VDD
+  SPD4_MODULE_ORGANIZATION_STRUCT           ModuleOrganization;       ///< 12      Module Organization
+  SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT       ModuleMemoryBusWidth;     ///< 13      Module Memory Bus Width
+  SPD4_MODULE_THERMAL_SENSOR_STRUCT         ModuleThermalSensor;      ///< 14      Module Thermal Sensor
+  SPD4_EXTENDED_MODULE_TYPE_STRUCT          ExtendedModuleType;       ///< 15      Extended Module Type
+  UINT8                                     Reserved0;                ///< 16      Reserved
+  SPD4_TIMEBASE_STRUCT                      Timebase;                 ///< 17      Timebases
+  SPD4_TCK_MIN_MTB_STRUCT                   tCKmin;                   ///< 18      SDRAM Minimum Cycle Time (tCKmin)
+  SPD4_TCK_MAX_MTB_STRUCT                   tCKmax;                   ///< 19      SDRAM Maximum Cycle Time (tCKmax)
+  SPD4_CAS_LATENCIES_SUPPORTED_STRUCT       CasLatencies;             ///< 20-23   CAS Latencies Supported
+  SPD4_TAA_MIN_MTB_STRUCT                   tAAmin;                   ///< 24      Minimum CAS Latency Time (tAAmin)
+  SPD4_TRCD_MIN_MTB_STRUCT                  tRCDmin;                  ///< 25      Minimum RAS# to CAS# Delay Time (tRCDmin)
+  SPD4_TRP_MIN_MTB_STRUCT                   tRPmin;                   ///< 26      Minimum Row Precharge Delay Time (tRPmin)
+  SPD4_TRAS_TRC_MIN_MTB_STRUCT              tRASMintRCMinUpper;       ///< 27      Upper Nibbles for tRAS and tRC
+  SPD4_TRAS_MIN_MTB_STRUCT                  tRASmin;                  ///< 28      Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
+  SPD4_TRC_MIN_MTB_STRUCT                   tRCmin;                   ///< 29      Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
+  SPD4_TRFC_MIN_MTB_STRUCT                  tRFC1min;                 ///< 30-31   Minimum Refresh Recovery Delay Time (tRFC1min)
+  SPD4_TRFC_MIN_MTB_STRUCT                  tRFC2min;                 ///< 32-33   Minimum Refresh Recovery Delay Time (tRFC2min)
+  SPD4_TRFC_MIN_MTB_STRUCT                  tRFC4min;                 ///< 34-35   Minimum Refresh Recovery Delay Time (tRFC4min)
+  SPD4_TFAW_MIN_MTB_UPPER_STRUCT            tFAWMinUpper;             ///< 36      Upper Nibble for tFAW
+  SPD4_TFAW_MIN_MTB_STRUCT                  tFAWmin;                  ///< 37      Minimum Four Activate Window Delay Time (tFAWmin)
+  SPD4_TRRD_MIN_MTB_STRUCT                  tRRD_Smin;                ///< 38      Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group
+  SPD4_TRRD_MIN_MTB_STRUCT                  tRRD_Lmin;                ///< 39      Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group
+  SPD4_TCCD_MIN_MTB_STRUCT                  tCCD_Lmin;                ///< 40      Minimum CAS to CAS Delay Time (tCCD_Lmin), Same Bank Group
+  SPD4_TWR_UPPER_NIBBLE_STRUCT              tWRUpperNibble;           ///< 41      Upper Nibble for tWRmin
+  SPD4_TWR_MIN_MTB_STRUCT                   tWRmin;                   ///< 42      Minimum Write Recovery Time (tWRmin)
+  SPD4_TWTR_UPPER_NIBBLE_STRUCT             tWTRUpperNibble;          ///< 43      Upper Nibbles for tWTRmin
+  SPD4_TWTR_MIN_MTB_STRUCT                  tWTR_Smin;                ///< 44      Minimum Write to Read Time (tWTR_Smin), Different Bank Group
+  SPD4_TWTR_MIN_MTB_STRUCT                  tWTR_Lmin;                ///< 45      Minimum Write to Read Time (tWTR_Lmin), Same Bank Group
+  UINT8                                     Reserved1[59 - 46 + 1];   ///< 46-59   Reserved
+  SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT    BitMapping[77 - 60 + 1];  ///< 60-77   Connector to SDRAM Bit Mapping
+  UINT8                                     Reserved2[116 - 78 + 1];  ///< 78-116  Reserved
+  SPD4_TCCD_MIN_FTB_STRUCT                  tCCD_LminFine;            ///< 117     Fine Offset for Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group
+  SPD4_TRRD_MIN_FTB_STRUCT                  tRRD_LminFine;            ///< 118     Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), different bank group
+  SPD4_TRRD_MIN_FTB_STRUCT                  tRRD_SminFine;            ///< 119     Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), same bank group
+  SPD4_TRC_MIN_FTB_STRUCT                   tRCminFine;               ///< 120     Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
+  SPD4_TRP_MIN_FTB_STRUCT                   tRPminFine;               ///< 121     Fine Offset for Minimum Row Precharge Delay Time (tRPabmin)
+  SPD4_TRCD_MIN_FTB_STRUCT                  tRCDminFine;              ///< 122     Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+  SPD4_TAA_MIN_FTB_STRUCT                   tAAminFine;               ///< 123     Fine Offset for Minimum CAS Latency Time (tAAmin)
+  SPD4_TCK_MAX_FTB_STRUCT                   tCKmaxFine;               ///< 124     Fine Offset for SDRAM Minimum Cycle Time (tCKmax)
+  SPD4_TCK_MIN_FTB_STRUCT                   tCKminFine;               ///< 125     Fine Offset for SDRAM Maximum Cycle Time (tCKmin)
+  SPD4_CYCLIC_REDUNDANCY_CODE               Crc;                      ///< 126-127 Cyclical Redundancy Code (CRC)
+} SPD4_BASE_SECTION;
+
+typedef struct {
+  SPD4_UNBUF_MODULE_NOMINAL_HEIGHT     ModuleNominalHeight;      ///< 128     Module Nominal Height
+  SPD4_UNBUF_MODULE_NOMINAL_THICKNESS  ModuleMaximumThickness;   ///< 129     Module Maximum Thickness
+  SPD4_UNBUF_REFERENCE_RAW_CARD        ReferenceRawCardUsed;     ///< 130     Reference Raw Card Used
+  SPD4_UNBUF_ADDRESS_MAPPING           AddressMappingEdgeConn;   ///< 131     Address Mapping from Edge Connector to DRAM
+  UINT8                                Reserved[253 - 132 + 1];  ///< 132-253 Reserved
+  SPD4_CYCLIC_REDUNDANCY_CODE          Crc;                      ///< 254-255 Cyclical Redundancy Code (CRC)
+} SPD4_MODULE_UNBUFFERED;
+
+typedef struct {
+  SPD4_RDIMM_MODULE_NOMINAL_HEIGHT     ModuleNominalHeight;      ///< 128     Module Nominal Height
+  SPD4_RDIMM_MODULE_NOMINAL_THICKNESS  ModuleMaximumThickness;   ///< 129     Module Maximum Thickness
+  SPD4_RDIMM_REFERENCE_RAW_CARD        ReferenceRawCardUsed;     ///< 130     Reference Raw Card Used
+  SPD4_RDIMM_MODULE_ATTRIBUTES         DimmModuleAttributes;     ///< 131     DIMM Module Attributes
+  SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION                             DimmThermalHeatSpreaderSolution;     ///< 132     RDIMM Thermal Heat Spreader Solution
+  SPD4_MANUFACTURER_ID_CODE                                             RegisterManufacturerIdCode;          ///< 133-134 Register Manufacturer ID Code
+  SPD4_RDIMM_REGISTER_REVISION_NUMBER                                   RegisterRevisionNumber;              ///< 135     Register Revision Number
+  SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM                      AddressMappingFromRegisterToDRAM;    ///< 136     Address Mapping from Register to DRAM
+  SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress; ///< 137 Register Output Drive Strength for Control and Command Address
+  SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK                   RegisterOutputDriveStrengthForClock; ///< 138     Register Output Drive Strength for Clock
+  UINT8                                                                 Reserved[253 - 139 + 1];             ///< 253-139 Reserved
+  SPD4_CYCLIC_REDUNDANCY_CODE                                           Crc;                                 ///< 254-255 Cyclical Redundancy Code (CRC)
+} SPD4_MODULE_REGISTERED;
+
+typedef struct {
+  SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT           ModuleNominalHeight;         ///< 128     Module Nominal Height
+  SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS        ModuleMaximumThickness;      ///< 129     Module Maximum Thickness
+  SPD4_LRDIMM_REFERENCE_RAW_CARD              ReferenceRawCardUsed;        ///< 130     Reference Raw Card Used
+  SPD4_LRDIMM_MODULE_ATTRIBUTES               DimmModuleAttributes;        ///< 131     DIMM Module Attributes
+  SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION  ThermalHeatSpreaderSolution; ///< 132     RDIMM Thermal Heat Spreader Solution
+  SPD4_MANUFACTURER_ID_CODE                   RegisterManufacturerIdCode;  ///< 133-134 Register Manufacturer ID Code
+  SPD4_LRDIMM_REGISTER_REVISION_NUMBER        RegisterRevisionNumber;      ///< 135     Register Revision Number
+  SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM                           AddressMappingFromRegisterToDram;                       ///< 136 Address Mapping from Register to DRAM
+  SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS      RegisterOutputDriveStrengthForControlCommandAddress;    ///< 137 Register Output Drive Strength for Control and Command Address
+  SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK                        RegisterOutputDriveStrengthForClock;                    ///< 138 Register Output Drive Strength for Clock
+  SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER     DataBufferRevisionNumber;    ///< 139     Data Buffer Revision Number
+  SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK    DramVrefDQForPackageRank0;   ///< 140     DRAM VrefDQ for Package Rank 0
+  SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK    DramVrefDQForPackageRank1;   ///< 141     DRAM VrefDQ for Package Rank 1
+  SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK    DramVrefDQForPackageRank2;   ///< 142     DRAM VrefDQ for Package Rank 2
+  SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK    DramVrefDQForPackageRank3;   ///< 143     DRAM VrefDQ for Package Rank 3
+  SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE                   DataBufferVrefDQForDramInterface;               ///< 144     Data Buffer VrefDQ for DRAM Interface
+  SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE        DataBufferMdqDriveStrengthRttForDataRateLe1866; ///< 145     Data Buffer MDQ Drive Strength and RTT for data rate <= 1866
+  SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE        DataBufferMdqDriveStrengthRttForDataRateLe2400; ///< 146     Data Buffer MDQ Drive Strength and RTT for data rate <=2400
+  SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE        DataBufferMdqDriveStrengthRttForDataRateLe3200; ///< 147     Data Buffer MDQ Drive Strength and RTT for data rate <=3200
+  SPD4_LRDIMM_DRAM_DRIVE_STRENGTH                                     DramDriveStrength;                              ///< 148     DRAM Drive Strength
+  SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE                   DramOdtRttWrRttNomForDataRateLe1866;            ///< 149     DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 1866
+  SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE                   DramOdtRttWrRttNomForDataRateLe2400;            ///< 150     DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 2400
+  SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE                   DramOdtRttWrRttNomForDataRateLe3200;            ///< 151     DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 3200
+  SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE                         DramOdtRttParkForDataRateLe1866;                ///< 152     DRAM ODT (RTT_PARK) for data rate <= 1866
+  SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE                         DramOdtRttParkForDataRateLe2400;                ///< 153     DRAM ODT (RTT_PARK) for data rate <= 2400
+  SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE                         DramOdtRttParkForDataRateLe3200;                ///< 154     DRAM ODT (RTT_PARK) for data rate <= 3200
+  SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE             DataBufferVrefDQForDramInterfaceRange;          ///< 155     Data Buffer VrefDQ for DRAM Interface Range
+  SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION           DataBufferDqDecisionFeedbackEqualization;       ///< 156     Data Buffer DQ Decision Feedback Equalization
+  UINT8                                                               Reserved[253 - 157 + 1];                        ///< 253-132 Reserved
+  SPD4_CYCLIC_REDUNDANCY_CODE                                         Crc;                                            ///< 254-255 Cyclical Redundancy Code (CRC)
+} SPD4_MODULE_LOADREDUCED;
+
+typedef struct {
+  UINT8                                                      Reserved0[191 - 128 + 1];              ///< 128-191  Reserved
+  SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER                      ModuleProductIdentifier;               ///< 192-193  Module Product Identifier
+  SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE      SubsystemControllerManufacturerIdCode; ///< 194-195  Subsystem Controller Manufacturer's ID Code
+  SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER                SubsystemControllerIdentifier;         ///< 196-197  Subsystem Controller Identifier
+  SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE             SubsystemControllerRevisionCode;       ///< 198      Subsystem Controller Revision Code
+  SPD4_NVDIMM_REFERENCE_RAW_CARD                             ReferenceRawCardUsed;                  ///< 199      Reference Raw Card Used
+  SPD4_NVDIMM_MODULE_CHARACTERISTICS                         ModuleCharacteristics;                 ///< 200      Module Characteristics
+  SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES                      HybridModuleMediaTypes;                ///< 201-202  Hybrid Module Media Types
+  SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME MaximumNonVolatileMemoryInitializationTime; ///< 203 Maximum Non-Volatile Memory Initialization Time
+  SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR                  FunctionInterfaceDescriptors[8];       ///< 204-219  Function Interface Descriptors
+  UINT8                                                      Reserved[253 - 220 + 1];               ///< 220-253  Reserved
+  SPD4_CYCLIC_REDUNDANCY_CODE                                Crc;                                   ///< 254-255  Cyclical Redundancy Code (CRC)
+} SPD4_MODULE_NVDIMM;
+
+typedef union {
+  SPD4_MODULE_UNBUFFERED              Unbuffered;               ///< 128-255 Unbuffered Memory Module Types
+  SPD4_MODULE_REGISTERED              Registered;               ///< 128-255 Registered Memory Module Types
+  SPD4_MODULE_LOADREDUCED             LoadReduced;              ///< 128-255 Load Reduced Memory Module Types
+  SPD4_MODULE_NVDIMM                  NonVolatile;              ///< 128-255 Non-Volatile (NVDIMM-N) Hybrid Memory Parameters
+} SPD4_MODULE_SPECIFIC;
+
+typedef struct {
+  UINT8                               ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number
+} SPD4_MODULE_PART_NUMBER;
+
+typedef struct {
+  UINT8                               ManufacturerSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data
+} SPD4_MANUFACTURER_SPECIFIC;
+
+typedef UINT8                         SPD4_MODULE_REVISION_CODE;///< 349     Module Revision Code
+typedef UINT8                         SPD4_DRAM_STEPPING;       ///< 352     Dram Stepping
+
+typedef struct {
+  SPD4_UNIQUE_MODULE_ID               ModuleId;                 ///< 320-328 Unique Module ID
+  SPD4_MODULE_PART_NUMBER             ModulePartNumber;         ///< 329-348 Module Part Number
+  SPD4_MODULE_REVISION_CODE           ModuleRevisionCode;       ///< 349     Module Revision Code
+  SPD4_MANUFACTURER_ID_CODE           DramIdCode;               ///< 350-351 Dram Manufacturer ID Code
+  SPD4_DRAM_STEPPING                  DramStepping;             ///< 352     Dram Stepping
+  SPD4_MANUFACTURER_SPECIFIC          ManufacturerSpecificData; ///< 353-381 Manufacturer's Specific Data
+  UINT8                               Reserved[2];              ///< 382-383 Reserved
+} SPD4_MANUFACTURING_DATA;
+
+typedef struct {
+  UINT8                               Reserved[511 - 384 + 1];  ///< 384-511 Unbuffered Memory Module Types
+} SPD4_END_USER_SECTION;
+
+///
+/// DDR4 Serial Presence Detect structure
+///
+typedef struct {
+  SPD4_BASE_SECTION                   Base;                     ///< 0-127   Base Configuration and DRAM Parameters
+  SPD4_MODULE_SPECIFIC                Module;                   ///< 128-255 Module-Specific Section
+  UINT8                               Reserved[319 - 256 + 1];  ///< 256-319 Reserved
+  SPD4_MANUFACTURING_DATA             ManufactureInfo;          ///< 320-383 Manufacturing Information
+  SPD4_END_USER_SECTION               EndUser;                  ///< 384-511 End User Programmable
+} SPD_DDR4;
+
+#pragma pack (pop)
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SdramSpdLpDdr.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SdramSpdLpDdr.h
new file mode 100644
index 0000000000..1f2302b424
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SdramSpdLpDdr.h
@@ -0,0 +1,474 @@
+/** @file
+  This file contains definitions for SPD LPDDR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Revision Reference:
+    - Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules Document Release 2
+      http://www.jedec.org/standards-documents/docs/spd412m-2
+**/
+
+#ifndef _SDRAM_SPD_LPDDR_H_
+#define _SDRAM_SPD_LPDDR_H_
+
+#pragma pack (push, 1)
+
+typedef union {
+  struct {
+    UINT8  BytesUsed                           :  4; ///< Bits 3:0
+    UINT8  BytesTotal                          :  3; ///< Bits 6:4
+    UINT8  CrcCoverage                         :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Minor                               :  4; ///< Bits 3:0
+    UINT8  Major                               :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_REVISION_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Type                                :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  ModuleType                          :  4; ///< Bits 3:0
+    UINT8  HybridMedia                         :  3; ///< Bits 6:4
+    UINT8  Hybrid                              :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_MODULE_TYPE_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Density                             :  4; ///< Bits 3:0
+    UINT8  BankAddress                         :  2; ///< Bits 5:4
+    UINT8  BankGroup                           :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  ColumnAddress                       :  3; ///< Bits 2:0
+    UINT8  RowAddress                          :  3; ///< Bits 5:3
+    UINT8  Reserved                            :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_SDRAM_ADDRESSING_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  SignalLoading                       :  2; ///< Bits 1:0
+    UINT8  ChannelsPerDie                      :  2; ///< Bits 3:2
+    UINT8  DieCount                            :  3; ///< Bits 6:4
+    UINT8  SdramPackageType                    :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  MaximumActivateCount                :  4; ///< Bits 3:0
+    UINT8  MaximumActivateWindow               :  2; ///< Bits 5:4
+    UINT8  Reserved                            :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Reserved                            :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Reserved                            :  5; ///< Bits 4:0
+    UINT8  SoftPPR                             :  1; ///< Bits 5:5
+    UINT8  PostPackageRepair                   :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  OperationAt1_20                     :  1; ///< Bits 0:0
+    UINT8  EndurantAt1_20                      :  1; ///< Bits 1:1
+    UINT8  OperationAt1_10                     :  1; ///< Bits 2:2
+    UINT8  EndurantAt1_10                      :  1; ///< Bits 3:3
+    UINT8  OperationAtTBD2V                    :  1; ///< Bits 4:4
+    UINT8  EndurantAtTBD2V                     :  1; ///< Bits 5:5
+    UINT8  Reserved                            :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  SdramDeviceWidth                    :  3; ///< Bits 2:0
+    UINT8  RankCount                           :  3; ///< Bits 5:3
+    UINT8  Reserved                            :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_MODULE_ORGANIZATION_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  PrimaryBusWidth                     :  3; ///< Bits 2:0
+    UINT8  BusWidthExtension                   :  2; ///< Bits 4:3
+    UINT8  NumberofChannels                    :  3; ///< Bits 7:5
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Reserved                            :  7; ///< Bits 6:0
+    UINT8  ThermalSensorPresence               :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  ExtendedBaseModuleType              :  4; ///< Bits 3:0
+    UINT8  Reserved                            :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  ChipSelectLoading                   :  3; ///< Bits 2:0
+    UINT8  CommandAddressControlClockLoading   :  3; ///< Bits 5:3
+    UINT8  DataStrobeMaskLoading               :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_SIGNAL_LOADING_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  Fine                                :  2; ///< Bits 1:0
+    UINT8  Medium                              :  2; ///< Bits 3:2
+    UINT8  Reserved                            :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_TIMEBASE_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tCKmin                              :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_TCK_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tCKmax                              :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_TCK_MAX_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT32 Cl3                                 :  1;  ///< Bits 0:0
+    UINT32 Cl6                                 :  1;  ///< Bits 1:1
+    UINT32 Cl8                                 :  1;  ///< Bits 2:2
+    UINT32 Cl9                                 :  1;  ///< Bits 3:3
+    UINT32 Cl10                                :  1;  ///< Bits 4:4
+    UINT32 Cl11                                :  1;  ///< Bits 5:5
+    UINT32 Cl12                                :  1;  ///< Bits 6:6
+    UINT32 Cl14                                :  1;  ///< Bits 7:7
+    UINT32 Cl16                                :  1;  ///< Bits 8:8
+    UINT32 Reserved0                           :  1;  ///< Bits 9:9
+    UINT32 Cl20                                :  1;  ///< Bits 10:10
+    UINT32 Cl22                                :  1;  ///< Bits 11:11
+    UINT32 Cl24                                :  1;  ///< Bits 12:12
+    UINT32 Reserved1                           :  1;  ///< Bits 13:13
+    UINT32 Cl28                                :  1;  ///< Bits 14:14
+    UINT32 Reserved2                           :  1;  ///< Bits 15:15
+    UINT32 Cl32                                :  1;  ///< Bits 16:16
+    UINT32 Reserved3                           :  1;  ///< Bits 17:17
+    UINT32 Cl36                                :  1;  ///< Bits 18:18
+    UINT32 Reserved4                           :  1;  ///< Bits 19:19
+    UINT32 Cl40                                :  1;  ///< Bits 20:20
+    UINT32 Reserved5                           :  11; ///< Bits 31:21
+  } Bits;
+  UINT32 Data;
+  UINT16 Data16[2];
+  UINT8  Data8[4];
+} SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tAAmin                              :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_TAA_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  ReadLatencyMode                     :  2; ///< Bits 1:0
+    UINT8  WriteLatencySet                     :  2; ///< Bits 3:2
+    UINT8  Reserved                            :  4; ///< Bits 7:4
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_RW_LATENCY_OPTION_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tRCDmin                             :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_TRCD_MIN_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tRPab                               :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_TRP_AB_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  tRPpb                               :  8; ///< Bits 7:0
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_TRP_PB_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT16  tRFCab                             :  16; ///< Bits 15:0
+  } Bits;
+  UINT16 Data;
+  UINT8  Data8[2];
+} SPD_LPDDR_TRFC_AB_MTB_STRUCT;
+
+typedef union {
+struct {
+    UINT16  tRFCpb                             :  16; ///< Bits 15:0
+  } Bits;
+  UINT16 Data;
+  UINT8  Data8[2];
+} SPD_LPDDR_TRFC_PB_MTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT8  BitOrderatSDRAM                     :  5; ///< Bits 4:0
+    UINT8  WiredtoUpperLowerNibble             :  1; ///< Bits 5:5
+    UINT8  PackageRankMap                      :  2; ///< Bits 7:6
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT;
+
+typedef union {
+  struct {
+    INT8  tRPpbFine                            :  8; ///< Bits 7:0
+  } Bits;
+  INT8  Data;
+} SPD_LPDDR_TRP_PB_FTB_STRUCT;
+
+typedef union {
+  struct {
+    INT8  tRPabFine                            :  8; ///< Bits 7:0
+  } Bits;
+  INT8  Data;
+} SPD_LPDDR_TRP_AB_FTB_STRUCT;
+
+typedef union {
+  struct {
+    INT8  tRCDminFine                          :  8; ///< Bits 7:0
+  } Bits;
+  INT8  Data;
+} SPD_LPDDR_TRCD_MIN_FTB_STRUCT;
+
+typedef union {
+  struct {
+    INT8  tAAminFine                           :  8; ///< Bits 7:0
+  } Bits;
+  INT8  Data;
+} SPD_LPDDR_TAA_MIN_FTB_STRUCT;
+
+typedef union {
+  struct {
+    INT8  tCKmaxFine                           :  8; ///< Bits 7:0
+  } Bits;
+  INT8  Data;
+} SPD_LPDDR_TCK_MAX_FTB_STRUCT;
+
+typedef union {
+  struct {
+    INT8  tCKminFine                           :  8; ///< Bits 7:0
+  } Bits;
+  INT8  Data;
+} SPD_LPDDR_TCK_MIN_FTB_STRUCT;
+
+typedef union {
+  struct {
+    UINT16 ContinuationCount                   :  7; ///< Bits 6:0
+    UINT16 ContinuationParity                  :  1; ///< Bits 7:7
+    UINT16 LastNonZeroByte                     :  8; ///< Bits 15:8
+  } Bits;
+  UINT16 Data;
+  UINT8  Data8[2];
+} SPD_LPDDR_MANUFACTURER_ID_CODE;
+
+typedef struct {
+  UINT8 Location;                              ///< Module Manufacturing Location
+} SPD_LPDDR_MANUFACTURING_LOCATION;
+
+typedef struct {
+  UINT8  Year;                                 ///< Year represented in BCD (00h = 2000)
+  UINT8  Week;                                 ///< Year represented in BCD (47h = week 47)
+} SPD_LPDDR_MANUFACTURING_DATE;
+
+typedef union {
+  UINT32 Data;
+  UINT16 SerialNumber16[2];
+  UINT8  SerialNumber8[4];
+} SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER;
+
+typedef struct {
+  SPD_LPDDR_MANUFACTURER_ID_CODE            IdCode;                   ///< Module Manufacturer ID Code
+  SPD_LPDDR_MANUFACTURING_LOCATION          Location;                 ///< Module Manufacturing Location
+  SPD_LPDDR_MANUFACTURING_DATE              Date;                     ///< Module Manufacturing Year, in BCD (range: 2000-2255)
+  SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER      SerialNumber;             ///< Module Serial Number
+} SPD_LPDDR_UNIQUE_MODULE_ID;
+
+typedef union {
+  struct {
+    UINT8  FrontThickness                      :  4; ///< Bits 3:0
+    UINT8  BackThickness                       :  4; ///< Bits 7:4
+  } Bits;
+  UINT8 Data;
+} SPD_LPDDR_MODULE_MAXIMUM_THICKNESS;
+
+typedef union {
+  struct {
+    UINT8  Height                              :  5; ///< Bits 4:0
+    UINT8  RawCardExtension                    :  3; ///< Bits 7:5
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_MODULE_NOMINAL_HEIGHT;
+
+typedef union {
+  struct {
+    UINT8  Card                                :  5; ///< Bits 4:0
+    UINT8  Revision                            :  2; ///< Bits 6:5
+    UINT8  Extension                           :  1; ///< Bits 7:7
+  } Bits;
+  UINT8  Data;
+} SPD_LPDDR_REFERENCE_RAW_CARD;
+
+typedef union {
+  UINT16 Crc[1];
+  UINT8  Data8[2];
+} SPD_LPDDR_CYCLIC_REDUNDANCY_CODE;
+
+typedef struct {
+  SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT            Description;              ///< 0       Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
+  SPD_LPDDR_REVISION_STRUCT                      Revision;                 ///< 1       SPD Revision
+  SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT              DramDeviceType;           ///< 2       DRAM Device Type
+  SPD_LPDDR_MODULE_TYPE_STRUCT                   ModuleType;               ///< 3       Module Type
+  SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT           SdramDensityAndBanks;     ///< 4       SDRAM Density and Banks
+  SPD_LPDDR_SDRAM_ADDRESSING_STRUCT              SdramAddressing;          ///< 5       SDRAM Addressing
+  SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT            SdramPackageType;         ///< 6       SDRAM Package Type
+  SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT       SdramOptionalFeatures;    ///< 7       SDRAM Optional Features
+  SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT         ThermalAndRefreshOptions; ///< 8       SDRAM Thermal and Refresh Options
+  SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures;    ///< 9      Other SDRAM Optional Features
+  UINT8                                          Reserved0;                ///< 10      Reserved
+  SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT        ModuleNominalVoltage;     ///< 11      Module Nominal Voltage, VDD
+  SPD_LPDDR_MODULE_ORGANIZATION_STRUCT           ModuleOrganization;       ///< 12      Module Organization
+  SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT       ModuleMemoryBusWidth;     ///< 13      Module Memory Bus Width
+  SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT         ModuleThermalSensor;      ///< 14      Module Thermal Sensor
+  SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT          ExtendedModuleType;       ///< 15      Extended Module Type
+  SPD_LPDDR_SIGNAL_LOADING_STRUCT                SignalLoading;            ///< 16      Signal Loading
+  SPD_LPDDR_TIMEBASE_STRUCT                      Timebase;                 ///< 17      Timebases
+  SPD_LPDDR_TCK_MIN_MTB_STRUCT                   tCKmin;                   ///< 18      SDRAM Minimum Cycle Time (tCKmin)
+  SPD_LPDDR_TCK_MAX_MTB_STRUCT                   tCKmax;                   ///< 19      SDRAM Maximum Cycle Time (tCKmax)
+  SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT       CasLatencies;             ///< 20-23   CAS Latencies Supported
+  SPD_LPDDR_TAA_MIN_MTB_STRUCT                   tAAmin;                   ///< 24      Minimum CAS Latency Time (tAAmin)
+  SPD_LPDDR_RW_LATENCY_OPTION_STRUCT             LatencySetOptions;        ///< 25      Read and Write Latency Set Options
+  SPD_LPDDR_TRCD_MIN_MTB_STRUCT                  tRCDmin;                  ///< 26      Minimum RAS# to CAS# Delay Time (tRCDmin)
+  SPD_LPDDR_TRP_AB_MTB_STRUCT                    tRPab;                    ///< 27      Minimum Row Precharge Delay Time (tRPab), all banks
+  SPD_LPDDR_TRP_PB_MTB_STRUCT                    tRPpb;                    ///< 28      Minimum Row Precharge Delay Time (tRPpb), per bank
+  SPD_LPDDR_TRFC_AB_MTB_STRUCT                   tRFCab;                   ///< 29-30   Minimum Refresh Recovery Delay Time (tRFCab), all banks
+  SPD_LPDDR_TRFC_PB_MTB_STRUCT                   tRFCpb;                   ///< 31-32   Minimum Refresh Recovery Delay Time (tRFCpb), per bank
+  UINT8                                          Reserved1[59 - 33 + 1];   ///< 33-59   Reserved
+  SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT    BitMapping[77 - 60 + 1];  ///< 60-77   Connector to SDRAM Bit Mapping
+  UINT8                                          Reserved2[119 - 78 + 1];  ///< 78-119  Reserved
+  SPD_LPDDR_TRP_PB_FTB_STRUCT                    tRPpbFine;                ///< 120     Fine Offset for Minimum Row Precharge Delay Time (tRPpbFine), per bank
+  SPD_LPDDR_TRP_AB_FTB_STRUCT                    tRPabFine;                ///< 121     Fine Offset for Minimum Row Precharge Delay Time (tRPabFine), all ranks
+  SPD_LPDDR_TRCD_MIN_FTB_STRUCT                  tRCDminFine;              ///< 122     Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+  SPD_LPDDR_TAA_MIN_FTB_STRUCT                   tAAminFine;               ///< 123     Fine Offset for Minimum CAS Latency Time (tAAmin)
+  SPD_LPDDR_TCK_MAX_FTB_STRUCT                   tCKmaxFine;               ///< 124     Fine Offset for SDRAM Maximum Cycle Time (tCKmax)
+  SPD_LPDDR_TCK_MIN_FTB_STRUCT                   tCKminFine;               ///< 125     Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+  SPD_LPDDR_CYCLIC_REDUNDANCY_CODE               Crc;                      ///< 126-127 Cyclical Redundancy Code (CRC)
+} SPD_LPDDR_BASE_SECTION;
+
+typedef struct {
+  SPD_LPDDR_MODULE_NOMINAL_HEIGHT         ModuleNominalHeight;      ///< 128     Module Nominal Height
+  SPD_LPDDR_MODULE_MAXIMUM_THICKNESS      ModuleMaximumThickness;   ///< 129     Module Maximum Thickness
+  SPD_LPDDR_REFERENCE_RAW_CARD            ReferenceRawCardUsed;     ///< 130     Reference Raw Card Used
+  UINT8                                   Reserved[253 - 131 + 1];  ///< 131-253 Reserved
+  SPD_LPDDR_CYCLIC_REDUNDANCY_CODE        Crc;                      ///< 254-255 Cyclical Redundancy Code (CRC)
+} SPD_LPDDR_MODULE_LPDIMM;
+
+typedef struct {
+  SPD_LPDDR_MODULE_LPDIMM                 LpDimm;                   ///< 128-255 Unbuffered Memory Module Types
+} SPD_LPDDR_MODULE_SPECIFIC;
+
+typedef struct {
+  UINT8                                   ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number
+} SPD_LPDDR_MODULE_PART_NUMBER;
+
+typedef struct {
+  UINT8                                   ManufacturerSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data
+} SPD_LPDDR_MANUFACTURER_SPECIFIC;
+
+typedef UINT8                             SPD_LPDDR_MODULE_REVISION_CODE;///< 349     Module Revision Code
+typedef UINT8                             SPD_LPDDR_DRAM_STEPPING;       ///< 352     Dram Stepping
+
+typedef struct {
+  SPD_LPDDR_UNIQUE_MODULE_ID              ModuleId;                 ///< 320-328 Unique Module ID
+  SPD_LPDDR_MODULE_PART_NUMBER            ModulePartNumber;         ///< 329-348 Module Part Number
+  SPD_LPDDR_MODULE_REVISION_CODE          ModuleRevisionCode;       ///< 349     Module Revision Code
+  SPD_LPDDR_MANUFACTURER_ID_CODE          DramIdCode;               ///< 350-351 Dram Manufacturer ID Code
+  SPD_LPDDR_DRAM_STEPPING                 DramStepping;             ///< 352     Dram Stepping
+  SPD_LPDDR_MANUFACTURER_SPECIFIC         ManufacturerSpecificData; ///< 353-381 Manufacturer's Specific Data
+  UINT8                                   Reserved[383 - 382 + 1];  ///< 382-383 Reserved
+} SPD_LPDDR_MANUFACTURING_DATA;
+
+typedef struct {
+  UINT8                                   Reserved[511 - 384 + 1];  ///< 384-511 End User Programmable
+} SPD_LPDDR_END_USER_SECTION;
+
+///
+/// LPDDR Serial Presence Detect structure
+///
+typedef struct {
+  SPD_LPDDR_BASE_SECTION                  Base;                     ///< 0-127   Base Configuration and DRAM Parameters
+  SPD_LPDDR_MODULE_SPECIFIC               Module;                   ///< 128-255 Module-Specific Section
+  UINT8                                   Reserved[319 - 256 + 1];  ///< 256-319 Hybrid Memory Parameters
+  SPD_LPDDR_MANUFACTURING_DATA            ManufactureInfo;          ///< 320-383 Manufacturing Information
+  SPD_LPDDR_END_USER_SECTION              EndUser;                  ///< 384-511 End User Programmable
+} SPD_LPDDR;
+
+#pragma pack (pop)
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SerialPortConsoleRedirectionTable.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SerialPortConsoleRedirectionTable.h
new file mode 100644
index 0000000000..e3fe03e319
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SerialPortConsoleRedirectionTable.h
@@ -0,0 +1,163 @@
+/** @file
+  ACPI Serial Port Console Redirection Table as defined by Microsoft in
+  http://www.microsoft.com/whdc/system/platform/server/spcr.mspx
+    
+  Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
+  (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
+  Copyright (c) 2014 - 2016, ARM Limited. All rights reserved.<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+**/
+
+#ifndef _SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_H_
+#define _SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_H_
+
+
+#include <IndustryStandard/Acpi.h>
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// SPCR Revision (defined in spec)
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION 0x02
+
+///
+/// Serial Port Console Redirection Table Format
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  UINT8                                   InterfaceType;
+  UINT8                                   Reserved1[3];
+  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  BaseAddress;
+  UINT8                                   InterruptType;
+  UINT8                                   Irq;
+  UINT32                                  GlobalSystemInterrupt;
+  UINT8                                   BaudRate;
+  UINT8                                   Parity;
+  UINT8                                   StopBits;
+  UINT8                                   FlowControl;
+  UINT8                                   TerminalType;
+  UINT8                                   Reserved2;
+  UINT16                                  PciDeviceId;
+  UINT16                                  PciVendorId;
+  UINT8                                   PciBusNumber;
+  UINT8                                   PciDeviceNumber;
+  UINT8                                   PciFunctionNumber;
+  UINT32                                  PciFlags;
+  UINT8                                   PciSegment;
+  UINT32                                  Reserved3;
+} EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE;
+
+#pragma pack()
+
+//
+// SPCR Definitions
+//
+
+//
+// Interface Type
+//
+
+///
+/// Full 16550 interface
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550                     0
+///
+/// Full 16450 interface
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16450                     1
+
+
+//
+// The Serial Port Subtypes for ARM are documented in Table 3 of the DBG2 Specification
+//
+
+///
+/// ARM PL011 UART
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART            0x03
+
+///
+/// ARM SBSA Generic UART (2.x) supporting 32-bit only accesses [deprecated]
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_SBSA_GENERIC_UART_2X  0x0d
+
+///
+/// ARM SBSA Generic UART
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_SBSA_GENERIC_UART     0x0e
+
+//
+// Interrupt Type
+//
+
+///
+/// PC-AT-compatible dual-8259 IRQ interrupt
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_8259    0x1
+///
+/// I/O APIC interrupt (Global System Interrupt)
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_APIC    0x2
+///
+/// I/O SAPIC interrupt (Global System Interrupt)
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_SAPIC   0x4
+///
+/// ARMH GIC interrupt (Global System Interrupt)
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC     0x8
+
+//
+// Baud Rate
+//
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_9600         3
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_19200        4
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_57600        6
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200       7
+
+//
+// Parity
+//
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY       0
+
+//
+// Stop Bits
+//
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1            1
+
+//
+// Flow Control
+//
+
+///
+/// DCD required for transmit
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_FLOW_CONTROL_DCD       0x1
+///
+/// RTS/CTS hardware flow control
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_FLOW_CONTROL_RTS_CTS   0x2
+///
+///  XON/XOFF software control
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_FLOW_CONTROL_XON_XOFF  0x4
+
+//
+// Terminal Type
+//
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_VT100      0
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_VT100_PLUS 1
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_VT_UTF8    2
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI       3
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SmBios.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SmBios.h
new file mode 100644
index 0000000000..c35bad569c
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SmBios.h
@@ -0,0 +1,2517 @@
+/** @file
+  Industry Standard Definitions of SMBIOS Table Specification v3.1.1.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+(C) Copyright 2015-2017 Hewlett Packard Enterprise Development LP<BR>
+This program and the accompanying materials are licensed and made available under 
+the terms and conditions of the BSD License that accompanies this distribution.  
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.                                          
+    
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+**/
+
+#ifndef __SMBIOS_STANDARD_H__
+#define __SMBIOS_STANDARD_H__
+
+///
+/// Reference SMBIOS 2.6, chapter 3.1.2.
+/// For v2.1 and later, handle values in the range 0FF00h to 0FFFFh are reserved for
+/// use by this specification.
+///
+#define SMBIOS_HANDLE_RESERVED_BEGIN 0xFF00
+
+///
+/// Reference SMBIOS 2.7, chapter 6.1.2.
+/// The UEFI Platform Initialization Specification reserves handle number FFFEh for its
+/// EFI_SMBIOS_PROTOCOL.Add() function to mean "assign an unused handle number automatically."
+/// This number is not used for any other purpose by the SMBIOS specification.
+///
+#define SMBIOS_HANDLE_PI_RESERVED 0xFFFE
+
+///
+/// Reference SMBIOS 2.6, chapter 3.1.3.
+/// Each text string is limited to 64 significant characters due to system MIF limitations.
+/// Reference SMBIOS 2.7, chapter 6.1.3.
+/// It will have no limit on the length of each individual text string.
+///
+#define SMBIOS_STRING_MAX_LENGTH     64
+
+//
+// The length of the entire structure table (including all strings) must be reported
+// in the Structure Table Length field of the SMBIOS Structure Table Entry Point,
+// which is a WORD field limited to 65,535 bytes.
+//
+#define SMBIOS_TABLE_MAX_LENGTH 0xFFFF
+
+//
+// For SMBIOS 3.0, Structure table maximum size in Entry Point structure is DWORD field limited to 0xFFFFFFFF bytes.
+//
+#define SMBIOS_3_0_TABLE_MAX_LENGTH 0xFFFFFFFF
+
+//
+// SMBIOS type macros which is according to SMBIOS 2.7 specification.
+//
+#define SMBIOS_TYPE_BIOS_INFORMATION                     0
+#define SMBIOS_TYPE_SYSTEM_INFORMATION                   1
+#define SMBIOS_TYPE_BASEBOARD_INFORMATION                2
+#define SMBIOS_TYPE_SYSTEM_ENCLOSURE                     3
+#define SMBIOS_TYPE_PROCESSOR_INFORMATION                4
+#define SMBIOS_TYPE_MEMORY_CONTROLLER_INFORMATION        5
+#define SMBIOS_TYPE_MEMORY_MODULE_INFORMATON             6
+#define SMBIOS_TYPE_CACHE_INFORMATION                    7
+#define SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION           8
+#define SMBIOS_TYPE_SYSTEM_SLOTS                         9
+#define SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION           10
+#define SMBIOS_TYPE_OEM_STRINGS                          11
+#define SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS         12
+#define SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION            13
+#define SMBIOS_TYPE_GROUP_ASSOCIATIONS                   14
+#define SMBIOS_TYPE_SYSTEM_EVENT_LOG                     15
+#define SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY                16
+#define SMBIOS_TYPE_MEMORY_DEVICE                        17
+#define SMBIOS_TYPE_32BIT_MEMORY_ERROR_INFORMATION       18
+#define SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS          19
+#define SMBIOS_TYPE_MEMORY_DEVICE_MAPPED_ADDRESS         20
+#define SMBIOS_TYPE_BUILT_IN_POINTING_DEVICE             21
+#define SMBIOS_TYPE_PORTABLE_BATTERY                     22
+#define SMBIOS_TYPE_SYSTEM_RESET                         23
+#define SMBIOS_TYPE_HARDWARE_SECURITY                    24
+#define SMBIOS_TYPE_SYSTEM_POWER_CONTROLS                25
+#define SMBIOS_TYPE_VOLTAGE_PROBE                        26
+#define SMBIOS_TYPE_COOLING_DEVICE                       27
+#define SMBIOS_TYPE_TEMPERATURE_PROBE                    28
+#define SMBIOS_TYPE_ELECTRICAL_CURRENT_PROBE             29
+#define SMBIOS_TYPE_OUT_OF_BAND_REMOTE_ACCESS            30
+#define SMBIOS_TYPE_BOOT_INTEGRITY_SERVICE               31
+#define SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION              32
+#define SMBIOS_TYPE_64BIT_MEMORY_ERROR_INFORMATION       33
+#define SMBIOS_TYPE_MANAGEMENT_DEVICE                    34
+#define SMBIOS_TYPE_MANAGEMENT_DEVICE_COMPONENT          35
+#define SMBIOS_TYPE_MANAGEMENT_DEVICE_THRESHOLD_DATA     36
+#define SMBIOS_TYPE_MEMORY_CHANNEL                       37
+#define SMBIOS_TYPE_IPMI_DEVICE_INFORMATION              38
+#define SMBIOS_TYPE_SYSTEM_POWER_SUPPLY                  39
+#define SMBIOS_TYPE_ADDITIONAL_INFORMATION               40
+#define SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION 41
+#define SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE 42
+#define SMBIOS_TYPE_TPM_DEVICE                           43
+
+///
+/// Inactive type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.43.
+/// Upper-level software that interprets the SMBIOS structure-table should bypass an 
+/// Inactive structure just like a structure type that the software does not recognize.
+///
+#define SMBIOS_TYPE_INACTIVE         0x007E    
+
+///
+/// End-of-table type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.44.
+/// The end-of-table indicator is used in the last physical structure in a table
+///
+#define SMBIOS_TYPE_END_OF_TABLE     0x007F
+
+#define SMBIOS_OEM_BEGIN             128
+#define SMBIOS_OEM_END               255
+
+///
+/// Types 0 through 127 (7Fh) are reserved for and defined by this
+/// specification. Types 128 through 256 (80h to FFh) are available for system- and OEM-specific information.  
+///
+typedef UINT8  SMBIOS_TYPE;
+
+///
+/// Specifies the structure's handle, a unique 16-bit number in the range 0 to 0FFFEh (for version
+/// 2.0) or 0 to 0FEFFh (for version 2.1 and later). The handle can be used with the Get SMBIOS
+/// Structure function to retrieve a specific structure; the handle numbers are not required to be
+/// contiguous. For v2.1 and later, handle values in the range 0FF00h to 0FFFFh are reserved for
+/// use by this specification.
+/// If the system configuration changes, a previously assigned handle might no longer exist.
+/// However once a handle has been assigned by the BIOS, the BIOS cannot re-assign that handle
+/// number to another structure.
+///
+typedef UINT16 SMBIOS_HANDLE;
+
+///
+/// Smbios Table Entry Point Structure.
+///
+#pragma pack(1)
+typedef struct {
+  UINT8   AnchorString[4];
+  UINT8   EntryPointStructureChecksum;
+  UINT8   EntryPointLength;
+  UINT8   MajorVersion;
+  UINT8   MinorVersion;
+  UINT16  MaxStructureSize;
+  UINT8   EntryPointRevision;
+  UINT8   FormattedArea[5];
+  UINT8   IntermediateAnchorString[5];
+  UINT8   IntermediateChecksum;
+  UINT16  TableLength;
+  UINT32  TableAddress;
+  UINT16  NumberOfSmbiosStructures;
+  UINT8   SmbiosBcdRevision;
+} SMBIOS_TABLE_ENTRY_POINT;
+
+typedef struct {
+  UINT8   AnchorString[5];
+  UINT8   EntryPointStructureChecksum;
+  UINT8   EntryPointLength;
+  UINT8   MajorVersion;
+  UINT8   MinorVersion;
+  UINT8   DocRev;
+  UINT8   EntryPointRevision;
+  UINT8   Reserved;
+  UINT32  TableMaximumSize;
+  UINT64  TableAddress;
+} SMBIOS_TABLE_3_0_ENTRY_POINT;
+
+///
+/// The Smbios structure header.
+///
+typedef struct {
+  SMBIOS_TYPE    Type;
+  UINT8          Length;
+  SMBIOS_HANDLE  Handle;
+} SMBIOS_STRUCTURE;
+
+///
+/// Text strings associated with a given SMBIOS structure are returned in the dmiStrucBuffer, appended directly after
+/// the formatted portion of the structure. This method of returning string information eliminates the need for
+/// application software to deal with pointers embedded in the SMBIOS structure. Each string is terminated with a null
+/// (00h) BYTE and the set of strings is terminated with an additional null (00h) BYTE. When the formatted portion of
+/// a SMBIOS structure references a string, it does so by specifying a non-zero string number within the structure's
+/// string-set. For example, if a string field contains 02h, it references the second string following the formatted portion
+/// of the SMBIOS structure. If a string field references no string, a null (0) is placed in that string field. If the
+/// formatted portion of the structure contains string-reference fields and all the string fields are set to 0 (no string
+/// references), the formatted section of the structure is followed by two null (00h) BYTES.
+///
+typedef UINT8 SMBIOS_TABLE_STRING;
+
+///
+/// BIOS Characteristics
+/// Defines which functions the BIOS supports. PCI, PCMCIA, Flash, etc.
+///
+typedef struct {
+  UINT32  Reserved                          :2;  ///< Bits 0-1.
+  UINT32  Unknown                           :1;
+  UINT32  BiosCharacteristicsNotSupported   :1;
+  UINT32  IsaIsSupported                    :1;
+  UINT32  McaIsSupported                    :1;
+  UINT32  EisaIsSupported                   :1;
+  UINT32  PciIsSupported                    :1;
+  UINT32  PcmciaIsSupported                 :1;
+  UINT32  PlugAndPlayIsSupported            :1;
+  UINT32  ApmIsSupported                    :1;
+  UINT32  BiosIsUpgradable                  :1;
+  UINT32  BiosShadowingAllowed              :1;
+  UINT32  VlVesaIsSupported                 :1;
+  UINT32  EscdSupportIsAvailable            :1;
+  UINT32  BootFromCdIsSupported             :1;
+  UINT32  SelectableBootIsSupported         :1;
+  UINT32  RomBiosIsSocketed                 :1;
+  UINT32  BootFromPcmciaIsSupported         :1;
+  UINT32  EDDSpecificationIsSupported       :1;
+  UINT32  JapaneseNecFloppyIsSupported      :1;
+  UINT32  JapaneseToshibaFloppyIsSupported  :1;
+  UINT32  Floppy525_360IsSupported          :1;
+  UINT32  Floppy525_12IsSupported           :1;
+  UINT32  Floppy35_720IsSupported           :1;
+  UINT32  Floppy35_288IsSupported           :1;
+  UINT32  PrintScreenIsSupported            :1;
+  UINT32  Keyboard8042IsSupported           :1;
+  UINT32  SerialIsSupported                 :1;
+  UINT32  PrinterIsSupported                :1;
+  UINT32  CgaMonoIsSupported                :1;
+  UINT32  NecPc98                           :1;
+  UINT32  ReservedForVendor                 :32; ///< Bits 32-63. Bits 32-47 reserved for BIOS vendor 
+                                                 ///< and bits 48-63 reserved for System Vendor. 
+} MISC_BIOS_CHARACTERISTICS;
+
+///
+/// BIOS Characteristics Extension Byte 1.
+/// This information, available for SMBIOS version 2.1 and later, appears at offset 12h
+/// within the BIOS Information structure.
+///
+typedef struct {
+  UINT8  AcpiIsSupported                   :1;
+  UINT8  UsbLegacyIsSupported              :1;
+  UINT8  AgpIsSupported                    :1;
+  UINT8  I2OBootIsSupported                :1;
+  UINT8  Ls120BootIsSupported              :1;
+  UINT8  AtapiZipDriveBootIsSupported      :1;
+  UINT8  Boot1394IsSupported               :1;
+  UINT8  SmartBatteryIsSupported           :1;
+} MBCE_BIOS_RESERVED;
+
+///
+/// BIOS Characteristics Extension Byte 2.
+/// This information, available for SMBIOS version 2.3 and later, appears at offset 13h
+/// within the BIOS Information structure.
+///
+typedef struct {
+  UINT8  BiosBootSpecIsSupported              :1;
+  UINT8  FunctionKeyNetworkBootIsSupported    :1;
+  UINT8  TargetContentDistributionEnabled     :1;
+  UINT8  UefiSpecificationSupported           :1;
+  UINT8  VirtualMachineSupported              :1;
+  UINT8  ExtensionByte2Reserved               :3;
+} MBCE_SYSTEM_RESERVED;
+
+///
+/// BIOS Characteristics Extension Bytes.
+///
+typedef struct {
+  MBCE_BIOS_RESERVED    BiosReserved;
+  MBCE_SYSTEM_RESERVED  SystemReserved;
+} MISC_BIOS_CHARACTERISTICS_EXTENSION;
+
+///
+/// Extended BIOS ROM size.
+///
+typedef struct {
+  UINT16 Size           :14;
+  UINT16 Unit           :2;
+} EXTENDED_BIOS_ROM_SIZE;
+
+///
+/// BIOS Information (Type 0).
+///
+typedef struct {
+  SMBIOS_STRUCTURE          Hdr;
+  SMBIOS_TABLE_STRING       Vendor;
+  SMBIOS_TABLE_STRING       BiosVersion;
+  UINT16                    BiosSegment;
+  SMBIOS_TABLE_STRING       BiosReleaseDate;
+  UINT8                     BiosSize;
+  MISC_BIOS_CHARACTERISTICS BiosCharacteristics;
+  UINT8                     BIOSCharacteristicsExtensionBytes[2];
+  UINT8                     SystemBiosMajorRelease;
+  UINT8                     SystemBiosMinorRelease;
+  UINT8                     EmbeddedControllerFirmwareMajorRelease;
+  UINT8                     EmbeddedControllerFirmwareMinorRelease;
+  //
+  // Add for smbios 3.1.0
+  //
+  EXTENDED_BIOS_ROM_SIZE    ExtendedBiosSize;
+} SMBIOS_TABLE_TYPE0;
+
+///
+///  System Wake-up Type.
+///
+typedef enum {  
+  SystemWakeupTypeReserved         = 0x00,
+  SystemWakeupTypeOther            = 0x01,
+  SystemWakeupTypeUnknown          = 0x02,
+  SystemWakeupTypeApmTimer         = 0x03,
+  SystemWakeupTypeModemRing        = 0x04,
+  SystemWakeupTypeLanRemote        = 0x05,
+  SystemWakeupTypePowerSwitch      = 0x06,
+  SystemWakeupTypePciPme           = 0x07,
+  SystemWakeupTypeAcPowerRestored  = 0x08
+} MISC_SYSTEM_WAKEUP_TYPE;
+
+///
+/// System Information (Type 1).
+/// 
+/// The information in this structure defines attributes of the overall system and is 
+/// intended to be associated with the Component ID group of the system's MIF.
+/// An SMBIOS implementation is associated with a single system instance and contains 
+/// one and only one System Information (Type 1) structure.
+///
+typedef struct {
+  SMBIOS_STRUCTURE        Hdr;
+  SMBIOS_TABLE_STRING     Manufacturer;
+  SMBIOS_TABLE_STRING     ProductName;
+  SMBIOS_TABLE_STRING     Version;
+  SMBIOS_TABLE_STRING     SerialNumber;
+  GUID                    Uuid;
+  UINT8                   WakeUpType;           ///< The enumeration value from MISC_SYSTEM_WAKEUP_TYPE.
+  SMBIOS_TABLE_STRING     SKUNumber;
+  SMBIOS_TABLE_STRING     Family;
+} SMBIOS_TABLE_TYPE1;
+
+///
+///  Base Board - Feature Flags. 
+///
+typedef struct {
+  UINT8  Motherboard           :1;
+  UINT8  RequiresDaughterCard  :1;
+  UINT8  Removable             :1;
+  UINT8  Replaceable           :1;
+  UINT8  HotSwappable          :1;
+  UINT8  Reserved              :3;
+} BASE_BOARD_FEATURE_FLAGS;
+
+///
+///  Base Board - Board Type.
+///
+typedef enum {  
+  BaseBoardTypeUnknown                  = 0x1,
+  BaseBoardTypeOther                    = 0x2,
+  BaseBoardTypeServerBlade              = 0x3,
+  BaseBoardTypeConnectivitySwitch       = 0x4,
+  BaseBoardTypeSystemManagementModule   = 0x5,
+  BaseBoardTypeProcessorModule          = 0x6,
+  BaseBoardTypeIOModule                 = 0x7,
+  BaseBoardTypeMemoryModule             = 0x8,
+  BaseBoardTypeDaughterBoard            = 0x9,
+  BaseBoardTypeMotherBoard              = 0xA,
+  BaseBoardTypeProcessorMemoryModule    = 0xB,
+  BaseBoardTypeProcessorIOModule        = 0xC,
+  BaseBoardTypeInterconnectBoard        = 0xD
+} BASE_BOARD_TYPE;
+
+///
+/// Base Board (or Module) Information (Type 2).
+///
+/// The information in this structure defines attributes of a system baseboard - 
+/// for example a motherboard, planar, or server blade or other standard system module.
+///
+typedef struct {
+  SMBIOS_STRUCTURE          Hdr;
+  SMBIOS_TABLE_STRING       Manufacturer;
+  SMBIOS_TABLE_STRING       ProductName;
+  SMBIOS_TABLE_STRING       Version;
+  SMBIOS_TABLE_STRING       SerialNumber;
+  SMBIOS_TABLE_STRING       AssetTag;
+  BASE_BOARD_FEATURE_FLAGS  FeatureFlag;
+  SMBIOS_TABLE_STRING       LocationInChassis;
+  UINT16                    ChassisHandle;
+  UINT8                     BoardType;              ///< The enumeration value from BASE_BOARD_TYPE.
+  UINT8                     NumberOfContainedObjectHandles;
+  UINT16                    ContainedObjectHandles[1];
+} SMBIOS_TABLE_TYPE2;
+
+///
+/// System Enclosure or Chassis Types
+///
+typedef enum {  
+  MiscChassisTypeOther                = 0x01,
+  MiscChassisTypeUnknown              = 0x02,
+  MiscChassisTypeDeskTop              = 0x03,
+  MiscChassisTypeLowProfileDesktop    = 0x04,
+  MiscChassisTypePizzaBox             = 0x05,
+  MiscChassisTypeMiniTower            = 0x06,
+  MiscChassisTypeTower                = 0x07,
+  MiscChassisTypePortable             = 0x08,
+  MiscChassisTypeLapTop               = 0x09,
+  MiscChassisTypeNotebook             = 0x0A,
+  MiscChassisTypeHandHeld             = 0x0B,
+  MiscChassisTypeDockingStation       = 0x0C,
+  MiscChassisTypeAllInOne             = 0x0D,
+  MiscChassisTypeSubNotebook          = 0x0E,
+  MiscChassisTypeSpaceSaving          = 0x0F,
+  MiscChassisTypeLunchBox             = 0x10,
+  MiscChassisTypeMainServerChassis    = 0x11,
+  MiscChassisTypeExpansionChassis     = 0x12,
+  MiscChassisTypeSubChassis           = 0x13,
+  MiscChassisTypeBusExpansionChassis  = 0x14,
+  MiscChassisTypePeripheralChassis    = 0x15,
+  MiscChassisTypeRaidChassis          = 0x16,
+  MiscChassisTypeRackMountChassis     = 0x17,
+  MiscChassisTypeSealedCasePc         = 0x18,
+  MiscChassisMultiSystemChassis       = 0x19,
+  MiscChassisCompactPCI               = 0x1A,
+  MiscChassisAdvancedTCA              = 0x1B,
+  MiscChassisBlade                    = 0x1C,
+  MiscChassisBladeEnclosure           = 0x1D,
+  MiscChassisTablet                   = 0x1E,
+  MiscChassisConvertible              = 0x1F,
+  MiscChassisDetachable               = 0x20,
+  MiscChassisIoTGateway               = 0x21,
+  MiscChassisEmbeddedPc               = 0x22,
+  MiscChassisMiniPc                   = 0x23,
+  MiscChassisStickPc                  = 0x24
+} MISC_CHASSIS_TYPE;
+
+///
+/// System Enclosure or Chassis States .
+///
+typedef enum {  
+  ChassisStateOther           = 0x01,
+  ChassisStateUnknown         = 0x02,
+  ChassisStateSafe            = 0x03,
+  ChassisStateWarning         = 0x04,
+  ChassisStateCritical        = 0x05,
+  ChassisStateNonRecoverable  = 0x06
+} MISC_CHASSIS_STATE;
+
+///
+/// System Enclosure or Chassis Security Status.
+///
+typedef enum {  
+  ChassisSecurityStatusOther                          = 0x01,
+  ChassisSecurityStatusUnknown                        = 0x02,
+  ChassisSecurityStatusNone                           = 0x03,
+  ChassisSecurityStatusExternalInterfaceLockedOut     = 0x04,
+  ChassisSecurityStatusExternalInterfaceLockedEnabled = 0x05
+} MISC_CHASSIS_SECURITY_STATE;
+
+///
+/// Contained Element record
+///
+typedef struct {
+  UINT8                 ContainedElementType;
+  UINT8                 ContainedElementMinimum;
+  UINT8                 ContainedElementMaximum;
+} CONTAINED_ELEMENT;
+
+
+///
+/// System Enclosure or Chassis (Type 3).
+///
+/// The information in this structure defines attributes of the system's mechanical enclosure(s).  
+/// For example, if a system included a separate enclosure for its peripheral devices, 
+/// two structures would be returned: one for the main, system enclosure and the second for
+/// the peripheral device enclosure.  The additions to this structure in v2.1 of this specification
+/// support the population of the CIM_Chassis class. 
+///
+typedef struct {
+  SMBIOS_STRUCTURE            Hdr;
+  SMBIOS_TABLE_STRING         Manufacturer;
+  UINT8                       Type;
+  SMBIOS_TABLE_STRING         Version;
+  SMBIOS_TABLE_STRING         SerialNumber;
+  SMBIOS_TABLE_STRING         AssetTag;
+  UINT8                       BootupState;            ///< The enumeration value from MISC_CHASSIS_STATE.
+  UINT8                       PowerSupplyState;       ///< The enumeration value from MISC_CHASSIS_STATE.
+  UINT8                       ThermalState;           ///< The enumeration value from MISC_CHASSIS_STATE.
+  UINT8                       SecurityStatus;         ///< The enumeration value from MISC_CHASSIS_SECURITY_STATE.
+  UINT8                       OemDefined[4];
+  UINT8                       Height;
+  UINT8                       NumberofPowerCords;
+  UINT8                       ContainedElementCount;
+  UINT8                       ContainedElementRecordLength;
+  //
+  // Can have 0 to (ContainedElementCount * ContainedElementRecordLength) contained elements
+  //
+  CONTAINED_ELEMENT           ContainedElements[1];
+  //
+  // Add for smbios 2.7
+  //
+  // Since ContainedElements has a variable number of entries, must not define SKUNumber in
+  // the structure.  Need to reference it by starting at offset 0x15 and adding
+  // (ContainedElementCount * ContainedElementRecordLength) bytes.
+  //
+  // SMBIOS_TABLE_STRING         SKUNumber;
+} SMBIOS_TABLE_TYPE3;
+
+///
+/// Processor Information - Processor Type.
+///
+typedef enum {
+  ProcessorOther   = 0x01,
+  ProcessorUnknown = 0x02,
+  CentralProcessor = 0x03,
+  MathProcessor    = 0x04,
+  DspProcessor     = 0x05,
+  VideoProcessor   = 0x06
+} PROCESSOR_TYPE_DATA;
+
+///
+/// Processor Information - Processor Family.
+///
+typedef enum {
+  ProcessorFamilyOther                  = 0x01, 
+  ProcessorFamilyUnknown                = 0x02,
+  ProcessorFamily8086                   = 0x03, 
+  ProcessorFamily80286                  = 0x04,
+  ProcessorFamilyIntel386               = 0x05, 
+  ProcessorFamilyIntel486               = 0x06,
+  ProcessorFamily8087                   = 0x07,
+  ProcessorFamily80287                  = 0x08,
+  ProcessorFamily80387                  = 0x09, 
+  ProcessorFamily80487                  = 0x0A,
+  ProcessorFamilyPentium                = 0x0B, 
+  ProcessorFamilyPentiumPro             = 0x0C,
+  ProcessorFamilyPentiumII              = 0x0D,
+  ProcessorFamilyPentiumMMX             = 0x0E,
+  ProcessorFamilyCeleron                = 0x0F,
+  ProcessorFamilyPentiumIIXeon          = 0x10,
+  ProcessorFamilyPentiumIII             = 0x11, 
+  ProcessorFamilyM1                     = 0x12,
+  ProcessorFamilyM2                     = 0x13,
+  ProcessorFamilyIntelCeleronM          = 0x14,
+  ProcessorFamilyIntelPentium4Ht        = 0x15,
+  ProcessorFamilyAmdDuron               = 0x18,
+  ProcessorFamilyK5                     = 0x19, 
+  ProcessorFamilyK6                     = 0x1A,
+  ProcessorFamilyK6_2                   = 0x1B,
+  ProcessorFamilyK6_3                   = 0x1C,
+  ProcessorFamilyAmdAthlon              = 0x1D,
+  ProcessorFamilyAmd29000               = 0x1E,
+  ProcessorFamilyK6_2Plus               = 0x1F,
+  ProcessorFamilyPowerPC                = 0x20,
+  ProcessorFamilyPowerPC601             = 0x21,
+  ProcessorFamilyPowerPC603             = 0x22,
+  ProcessorFamilyPowerPC603Plus         = 0x23,
+  ProcessorFamilyPowerPC604             = 0x24,
+  ProcessorFamilyPowerPC620             = 0x25,
+  ProcessorFamilyPowerPCx704            = 0x26,
+  ProcessorFamilyPowerPC750             = 0x27,
+  ProcessorFamilyIntelCoreDuo           = 0x28,
+  ProcessorFamilyIntelCoreDuoMobile     = 0x29,
+  ProcessorFamilyIntelCoreSoloMobile    = 0x2A,
+  ProcessorFamilyIntelAtom              = 0x2B,
+  ProcessorFamilyIntelCoreM             = 0x2C,
+  ProcessorFamilyIntelCorem3            = 0x2D,
+  ProcessorFamilyIntelCorem5            = 0x2E,
+  ProcessorFamilyIntelCorem7            = 0x2F,
+  ProcessorFamilyAlpha                  = 0x30,
+  ProcessorFamilyAlpha21064             = 0x31,
+  ProcessorFamilyAlpha21066             = 0x32,
+  ProcessorFamilyAlpha21164             = 0x33,
+  ProcessorFamilyAlpha21164PC           = 0x34,
+  ProcessorFamilyAlpha21164a            = 0x35,
+  ProcessorFamilyAlpha21264             = 0x36,
+  ProcessorFamilyAlpha21364             = 0x37,
+  ProcessorFamilyAmdTurionIIUltraDualCoreMobileM    = 0x38,
+  ProcessorFamilyAmdTurionIIDualCoreMobileM         = 0x39,
+  ProcessorFamilyAmdAthlonIIDualCoreM   = 0x3A,
+  ProcessorFamilyAmdOpteron6100Series   = 0x3B,
+  ProcessorFamilyAmdOpteron4100Series   = 0x3C,
+  ProcessorFamilyAmdOpteron6200Series   = 0x3D,
+  ProcessorFamilyAmdOpteron4200Series   = 0x3E,
+  ProcessorFamilyAmdFxSeries            = 0x3F,
+  ProcessorFamilyMips                   = 0x40,
+  ProcessorFamilyMIPSR4000              = 0x41,
+  ProcessorFamilyMIPSR4200              = 0x42,
+  ProcessorFamilyMIPSR4400              = 0x43,
+  ProcessorFamilyMIPSR4600              = 0x44,
+  ProcessorFamilyMIPSR10000             = 0x45,
+  ProcessorFamilyAmdCSeries             = 0x46,
+  ProcessorFamilyAmdESeries             = 0x47,
+  ProcessorFamilyAmdASeries             = 0x48,    ///< SMBIOS spec 2.8.0 updated the name
+  ProcessorFamilyAmdGSeries             = 0x49,
+  ProcessorFamilyAmdZSeries             = 0x4A,
+  ProcessorFamilyAmdRSeries             = 0x4B,
+  ProcessorFamilyAmdOpteron4300         = 0x4C,
+  ProcessorFamilyAmdOpteron6300         = 0x4D,
+  ProcessorFamilyAmdOpteron3300         = 0x4E,
+  ProcessorFamilyAmdFireProSeries       = 0x4F,
+  ProcessorFamilySparc                  = 0x50,
+  ProcessorFamilySuperSparc             = 0x51,
+  ProcessorFamilymicroSparcII           = 0x52,
+  ProcessorFamilymicroSparcIIep         = 0x53,
+  ProcessorFamilyUltraSparc             = 0x54,
+  ProcessorFamilyUltraSparcII           = 0x55,
+  ProcessorFamilyUltraSparcIii          = 0x56,
+  ProcessorFamilyUltraSparcIII          = 0x57,
+  ProcessorFamilyUltraSparcIIIi         = 0x58,
+  ProcessorFamily68040                  = 0x60,
+  ProcessorFamily68xxx                  = 0x61,
+  ProcessorFamily68000                  = 0x62,
+  ProcessorFamily68010                  = 0x63,
+  ProcessorFamily68020                  = 0x64,
+  ProcessorFamily68030                  = 0x65,
+  ProcessorFamilyAmdAthlonX4QuadCore    = 0x66,
+  ProcessorFamilyAmdOpteronX1000Series  = 0x67,
+  ProcessorFamilyAmdOpteronX2000Series  = 0x68,
+  ProcessorFamilyAmdOpteronASeries      = 0x69,
+  ProcessorFamilyAmdOpteronX3000Series  = 0x6A,
+  ProcessorFamilyAmdZen                 = 0x6B,
+  ProcessorFamilyHobbit                 = 0x70,
+  ProcessorFamilyCrusoeTM5000           = 0x78,
+  ProcessorFamilyCrusoeTM3000           = 0x79,
+  ProcessorFamilyEfficeonTM8000         = 0x7A,
+  ProcessorFamilyWeitek                 = 0x80,
+  ProcessorFamilyItanium                = 0x82,
+  ProcessorFamilyAmdAthlon64            = 0x83,
+  ProcessorFamilyAmdOpteron             = 0x84,
+  ProcessorFamilyAmdSempron             = 0x85,
+  ProcessorFamilyAmdTurion64Mobile      = 0x86,
+  ProcessorFamilyDualCoreAmdOpteron     = 0x87,
+  ProcessorFamilyAmdAthlon64X2DualCore  = 0x88,
+  ProcessorFamilyAmdTurion64X2Mobile    = 0x89,
+  ProcessorFamilyQuadCoreAmdOpteron     = 0x8A,
+  ProcessorFamilyThirdGenerationAmdOpteron = 0x8B,
+  ProcessorFamilyAmdPhenomFxQuadCore    = 0x8C,
+  ProcessorFamilyAmdPhenomX4QuadCore    = 0x8D,
+  ProcessorFamilyAmdPhenomX2DualCore    = 0x8E,
+  ProcessorFamilyAmdAthlonX2DualCore    = 0x8F,  
+  ProcessorFamilyPARISC                 = 0x90,
+  ProcessorFamilyPaRisc8500             = 0x91,
+  ProcessorFamilyPaRisc8000             = 0x92,
+  ProcessorFamilyPaRisc7300LC           = 0x93,
+  ProcessorFamilyPaRisc7200             = 0x94,
+  ProcessorFamilyPaRisc7100LC           = 0x95,
+  ProcessorFamilyPaRisc7100             = 0x96,
+  ProcessorFamilyV30                    = 0xA0,
+  ProcessorFamilyQuadCoreIntelXeon3200Series  = 0xA1,
+  ProcessorFamilyDualCoreIntelXeon3000Series  = 0xA2,
+  ProcessorFamilyQuadCoreIntelXeon5300Series  = 0xA3,
+  ProcessorFamilyDualCoreIntelXeon5100Series  = 0xA4,
+  ProcessorFamilyDualCoreIntelXeon5000Series  = 0xA5,
+  ProcessorFamilyDualCoreIntelXeonLV          = 0xA6,
+  ProcessorFamilyDualCoreIntelXeonULV         = 0xA7,
+  ProcessorFamilyDualCoreIntelXeon7100Series  = 0xA8,
+  ProcessorFamilyQuadCoreIntelXeon5400Series  = 0xA9,
+  ProcessorFamilyQuadCoreIntelXeon            = 0xAA,
+  ProcessorFamilyDualCoreIntelXeon5200Series  = 0xAB,
+  ProcessorFamilyDualCoreIntelXeon7200Series  = 0xAC,
+  ProcessorFamilyQuadCoreIntelXeon7300Series  = 0xAD,
+  ProcessorFamilyQuadCoreIntelXeon7400Series  = 0xAE,
+  ProcessorFamilyMultiCoreIntelXeon7400Series = 0xAF,
+  ProcessorFamilyPentiumIIIXeon         = 0xB0,
+  ProcessorFamilyPentiumIIISpeedStep    = 0xB1,
+  ProcessorFamilyPentium4               = 0xB2,
+  ProcessorFamilyIntelXeon              = 0xB3,
+  ProcessorFamilyAS400                  = 0xB4,
+  ProcessorFamilyIntelXeonMP            = 0xB5,
+  ProcessorFamilyAMDAthlonXP            = 0xB6,
+  ProcessorFamilyAMDAthlonMP            = 0xB7,
+  ProcessorFamilyIntelItanium2          = 0xB8,
+  ProcessorFamilyIntelPentiumM          = 0xB9,
+  ProcessorFamilyIntelCeleronD          = 0xBA,
+  ProcessorFamilyIntelPentiumD          = 0xBB,
+  ProcessorFamilyIntelPentiumEx         = 0xBC,
+  ProcessorFamilyIntelCoreSolo          = 0xBD,  ///< SMBIOS spec 2.6 updated this value
+  ProcessorFamilyReserved               = 0xBE,
+  ProcessorFamilyIntelCore2             = 0xBF,
+  ProcessorFamilyIntelCore2Solo         = 0xC0,
+  ProcessorFamilyIntelCore2Extreme      = 0xC1,
+  ProcessorFamilyIntelCore2Quad         = 0xC2,
+  ProcessorFamilyIntelCore2ExtremeMobile = 0xC3,
+  ProcessorFamilyIntelCore2DuoMobile    = 0xC4,
+  ProcessorFamilyIntelCore2SoloMobile   = 0xC5,
+  ProcessorFamilyIntelCoreI7            = 0xC6,
+  ProcessorFamilyDualCoreIntelCeleron   = 0xC7,  
+  ProcessorFamilyIBM390                 = 0xC8,
+  ProcessorFamilyG4                     = 0xC9,
+  ProcessorFamilyG5                     = 0xCA,
+  ProcessorFamilyG6                     = 0xCB,
+  ProcessorFamilyzArchitecture          = 0xCC,
+  ProcessorFamilyIntelCoreI5            = 0xCD,
+  ProcessorFamilyIntelCoreI3            = 0xCE,
+  ProcessorFamilyViaC7M                 = 0xD2,
+  ProcessorFamilyViaC7D                 = 0xD3,
+  ProcessorFamilyViaC7                  = 0xD4,
+  ProcessorFamilyViaEden                = 0xD5,
+  ProcessorFamilyMultiCoreIntelXeon           = 0xD6,
+  ProcessorFamilyDualCoreIntelXeon3Series     = 0xD7,
+  ProcessorFamilyQuadCoreIntelXeon3Series     = 0xD8,
+  ProcessorFamilyViaNano                      = 0xD9,
+  ProcessorFamilyDualCoreIntelXeon5Series     = 0xDA,
+  ProcessorFamilyQuadCoreIntelXeon5Series     = 0xDB,
+  ProcessorFamilyDualCoreIntelXeon7Series     = 0xDD,
+  ProcessorFamilyQuadCoreIntelXeon7Series     = 0xDE,
+  ProcessorFamilyMultiCoreIntelXeon7Series    = 0xDF,
+  ProcessorFamilyMultiCoreIntelXeon3400Series = 0xE0,
+  ProcessorFamilyAmdOpteron3000Series         = 0xE4,
+  ProcessorFamilyAmdSempronII                 = 0xE5,
+  ProcessorFamilyEmbeddedAmdOpteronQuadCore   = 0xE6,
+  ProcessorFamilyAmdPhenomTripleCore          = 0xE7,
+  ProcessorFamilyAmdTurionUltraDualCoreMobile = 0xE8,
+  ProcessorFamilyAmdTurionDualCoreMobile      = 0xE9,
+  ProcessorFamilyAmdAthlonDualCore            = 0xEA,
+  ProcessorFamilyAmdSempronSI                 = 0xEB,
+  ProcessorFamilyAmdPhenomII                  = 0xEC,
+  ProcessorFamilyAmdAthlonII                  = 0xED,
+  ProcessorFamilySixCoreAmdOpteron            = 0xEE,
+  ProcessorFamilyAmdSempronM                  = 0xEF,
+  ProcessorFamilyi860                   = 0xFA,
+  ProcessorFamilyi960                   = 0xFB,
+  ProcessorFamilyIndicatorFamily2       = 0xFE,
+  ProcessorFamilyReserved1              = 0xFF
+} PROCESSOR_FAMILY_DATA;
+
+///
+/// Processor Information2 - Processor Family2.
+///
+typedef enum {
+  ProcessorFamilyARMv7                 = 0x0100,
+  ProcessorFamilyARMv8                 = 0x0101,
+  ProcessorFamilySH3                   = 0x0104,
+  ProcessorFamilySH4                   = 0x0105,
+  ProcessorFamilyARM                   = 0x0118,
+  ProcessorFamilyStrongARM             = 0x0119,
+  ProcessorFamily6x86                  = 0x012C,
+  ProcessorFamilyMediaGX               = 0x012D,
+  ProcessorFamilyMII                   = 0x012E,
+  ProcessorFamilyWinChip               = 0x0140,
+  ProcessorFamilyDSP                   = 0x015E,
+  ProcessorFamilyVideoProcessor        = 0x01F4
+} PROCESSOR_FAMILY2_DATA;
+
+///
+/// Processor Information - Voltage. 
+///
+typedef struct {
+  UINT8  ProcessorVoltageCapability5V        :1; 
+  UINT8  ProcessorVoltageCapability3_3V      :1;  
+  UINT8  ProcessorVoltageCapability2_9V      :1;  
+  UINT8  ProcessorVoltageCapabilityReserved  :1; ///< Bit 3, must be zero.
+  UINT8  ProcessorVoltageReserved            :3; ///< Bits 4-6, must be zero.
+  UINT8  ProcessorVoltageIndicateLegacy      :1;
+} PROCESSOR_VOLTAGE;
+
+///
+/// Processor Information - Processor Upgrade.
+///
+typedef enum {
+  ProcessorUpgradeOther         = 0x01,
+  ProcessorUpgradeUnknown       = 0x02,
+  ProcessorUpgradeDaughterBoard = 0x03,
+  ProcessorUpgradeZIFSocket     = 0x04,
+  ProcessorUpgradePiggyBack     = 0x05, ///< Replaceable.
+  ProcessorUpgradeNone          = 0x06,
+  ProcessorUpgradeLIFSocket     = 0x07,
+  ProcessorUpgradeSlot1         = 0x08,
+  ProcessorUpgradeSlot2         = 0x09,
+  ProcessorUpgrade370PinSocket  = 0x0A,
+  ProcessorUpgradeSlotA         = 0x0B,
+  ProcessorUpgradeSlotM         = 0x0C,
+  ProcessorUpgradeSocket423     = 0x0D,
+  ProcessorUpgradeSocketA       = 0x0E, ///< Socket 462.
+  ProcessorUpgradeSocket478     = 0x0F,
+  ProcessorUpgradeSocket754     = 0x10,
+  ProcessorUpgradeSocket940     = 0x11,
+  ProcessorUpgradeSocket939     = 0x12,
+  ProcessorUpgradeSocketmPGA604 = 0x13,
+  ProcessorUpgradeSocketLGA771  = 0x14,
+  ProcessorUpgradeSocketLGA775  = 0x15,
+  ProcessorUpgradeSocketS1      = 0x16,
+  ProcessorUpgradeAM2           = 0x17,
+  ProcessorUpgradeF1207         = 0x18,
+  ProcessorSocketLGA1366        = 0x19,
+  ProcessorUpgradeSocketG34     = 0x1A,
+  ProcessorUpgradeSocketAM3     = 0x1B,
+  ProcessorUpgradeSocketC32     = 0x1C,
+  ProcessorUpgradeSocketLGA1156 = 0x1D,
+  ProcessorUpgradeSocketLGA1567 = 0x1E,
+  ProcessorUpgradeSocketPGA988A = 0x1F,
+  ProcessorUpgradeSocketBGA1288 = 0x20,
+  ProcessorUpgradeSocketrPGA988B = 0x21,
+  ProcessorUpgradeSocketBGA1023 = 0x22,
+  ProcessorUpgradeSocketBGA1224 = 0x23,
+  ProcessorUpgradeSocketLGA1155 = 0x24,  ///< SMBIOS spec 2.8.0 updated the name
+  ProcessorUpgradeSocketLGA1356 = 0x25,
+  ProcessorUpgradeSocketLGA2011 = 0x26,
+  ProcessorUpgradeSocketFS1     = 0x27,
+  ProcessorUpgradeSocketFS2     = 0x28,
+  ProcessorUpgradeSocketFM1     = 0x29,
+  ProcessorUpgradeSocketFM2     = 0x2A,
+  ProcessorUpgradeSocketLGA2011_3 = 0x2B,
+  ProcessorUpgradeSocketLGA1356_3 = 0x2C,
+  ProcessorUpgradeSocketLGA1150   = 0x2D,
+  ProcessorUpgradeSocketBGA1168   = 0x2E,
+  ProcessorUpgradeSocketBGA1234   = 0x2F,
+  ProcessorUpgradeSocketBGA1364   = 0x30,
+  ProcessorUpgradeSocketAM4       = 0x31,
+  ProcessorUpgradeSocketLGA1151   = 0x32,
+  ProcessorUpgradeSocketBGA1356   = 0x33,
+  ProcessorUpgradeSocketBGA1440   = 0x34,
+  ProcessorUpgradeSocketBGA1515   = 0x35,
+  ProcessorUpgradeSocketLGA3647_1 = 0x36,
+  ProcessorUpgradeSocketSP3       = 0x37,
+  ProcessorUpgradeSocketSP3r2     = 0x38
+} PROCESSOR_UPGRADE;
+
+///
+/// Processor ID Field Description
+///
+typedef struct {
+  UINT32  ProcessorSteppingId:4;
+  UINT32  ProcessorModel:     4;
+  UINT32  ProcessorFamily:    4;
+  UINT32  ProcessorType:      2;
+  UINT32  ProcessorReserved1: 2;
+  UINT32  ProcessorXModel:    4;
+  UINT32  ProcessorXFamily:   8;
+  UINT32  ProcessorReserved2: 4;
+} PROCESSOR_SIGNATURE;
+
+typedef struct {
+  UINT32  ProcessorFpu       :1;
+  UINT32  ProcessorVme       :1;
+  UINT32  ProcessorDe        :1;
+  UINT32  ProcessorPse       :1;
+  UINT32  ProcessorTsc       :1;
+  UINT32  ProcessorMsr       :1;
+  UINT32  ProcessorPae       :1;
+  UINT32  ProcessorMce       :1;
+  UINT32  ProcessorCx8       :1;
+  UINT32  ProcessorApic      :1;
+  UINT32  ProcessorReserved1 :1;
+  UINT32  ProcessorSep       :1;
+  UINT32  ProcessorMtrr      :1;
+  UINT32  ProcessorPge       :1;
+  UINT32  ProcessorMca       :1;
+  UINT32  ProcessorCmov      :1;
+  UINT32  ProcessorPat       :1;
+  UINT32  ProcessorPse36     :1;
+  UINT32  ProcessorPsn       :1;
+  UINT32  ProcessorClfsh     :1;
+  UINT32  ProcessorReserved2 :1;
+  UINT32  ProcessorDs        :1;
+  UINT32  ProcessorAcpi      :1;
+  UINT32  ProcessorMmx       :1;
+  UINT32  ProcessorFxsr      :1;
+  UINT32  ProcessorSse       :1;
+  UINT32  ProcessorSse2      :1;
+  UINT32  ProcessorSs        :1;
+  UINT32  ProcessorReserved3 :1;
+  UINT32  ProcessorTm        :1;
+  UINT32  ProcessorReserved4 :2;
+} PROCESSOR_FEATURE_FLAGS;
+
+typedef struct {
+  PROCESSOR_SIGNATURE     Signature;
+  PROCESSOR_FEATURE_FLAGS FeatureFlags;
+} PROCESSOR_ID_DATA;
+
+///
+/// Processor Information (Type 4).
+///
+/// The information in this structure defines the attributes of a single processor; 
+/// a separate structure instance is provided for each system processor socket/slot. 
+/// For example, a system with an IntelDX2 processor would have a single 
+/// structure instance, while a system with an IntelSX2 processor would have a structure
+/// to describe the main CPU, and a second structure to describe the 80487 co-processor. 
+///
+typedef struct { 
+  SMBIOS_STRUCTURE      Hdr;
+  SMBIOS_TABLE_STRING   Socket;
+  UINT8                 ProcessorType;          ///< The enumeration value from PROCESSOR_TYPE_DATA.
+  UINT8                 ProcessorFamily;        ///< The enumeration value from PROCESSOR_FAMILY_DATA.
+  SMBIOS_TABLE_STRING   ProcessorManufacture;
+  PROCESSOR_ID_DATA     ProcessorId;
+  SMBIOS_TABLE_STRING   ProcessorVersion;
+  PROCESSOR_VOLTAGE     Voltage;
+  UINT16                ExternalClock;
+  UINT16                MaxSpeed;
+  UINT16                CurrentSpeed;
+  UINT8                 Status;
+  UINT8                 ProcessorUpgrade;      ///< The enumeration value from PROCESSOR_UPGRADE.
+  UINT16                L1CacheHandle;
+  UINT16                L2CacheHandle;
+  UINT16                L3CacheHandle;
+  SMBIOS_TABLE_STRING   SerialNumber;
+  SMBIOS_TABLE_STRING   AssetTag;
+  SMBIOS_TABLE_STRING   PartNumber;
+  //
+  // Add for smbios 2.5
+  //
+  UINT8                 CoreCount;
+  UINT8                 EnabledCoreCount;
+  UINT8                 ThreadCount;
+  UINT16                ProcessorCharacteristics;
+  //
+  // Add for smbios 2.6
+  //
+  UINT16                ProcessorFamily2;
+  //
+  // Add for smbios 3.0
+  //
+  UINT16                CoreCount2;
+  UINT16                EnabledCoreCount2;
+  UINT16                ThreadCount2;
+} SMBIOS_TABLE_TYPE4;
+
+///
+/// Memory Controller Error Detecting Method.
+///
+typedef enum {  
+  ErrorDetectingMethodOther   = 0x01,
+  ErrorDetectingMethodUnknown = 0x02,
+  ErrorDetectingMethodNone    = 0x03,
+  ErrorDetectingMethodParity  = 0x04,
+  ErrorDetectingMethod32Ecc   = 0x05,
+  ErrorDetectingMethod64Ecc   = 0x06,
+  ErrorDetectingMethod128Ecc  = 0x07,
+  ErrorDetectingMethodCrc     = 0x08
+} MEMORY_ERROR_DETECT_METHOD;
+
+///
+/// Memory Controller Error Correcting Capability.
+///
+typedef struct {
+  UINT8  Other                 :1;
+  UINT8  Unknown               :1;
+  UINT8  None                  :1;
+  UINT8  SingleBitErrorCorrect :1;
+  UINT8  DoubleBitErrorCorrect :1;
+  UINT8  ErrorScrubbing        :1;
+  UINT8  Reserved              :2;
+} MEMORY_ERROR_CORRECT_CAPABILITY;
+
+///
+/// Memory Controller Information - Interleave Support.
+///
+typedef enum {  
+  MemoryInterleaveOther      = 0x01,
+  MemoryInterleaveUnknown    = 0x02,
+  MemoryInterleaveOneWay     = 0x03,
+  MemoryInterleaveTwoWay     = 0x04,
+  MemoryInterleaveFourWay    = 0x05,
+  MemoryInterleaveEightWay   = 0x06,
+  MemoryInterleaveSixteenWay = 0x07
+} MEMORY_SUPPORT_INTERLEAVE_TYPE;
+
+///
+/// Memory Controller Information - Memory Speeds.
+///
+typedef struct {
+  UINT16     Other    :1;
+  UINT16     Unknown  :1;
+  UINT16     SeventyNs:1;
+  UINT16     SixtyNs  :1;
+  UINT16     FiftyNs  :1;
+  UINT16     Reserved :11;
+} MEMORY_SPEED_TYPE;
+
+///
+/// Memory Controller Information (Type 5, Obsolete).
+///
+/// The information in this structure defines the attributes of the system's memory controller(s) 
+/// and the supported attributes of any memory-modules present in the sockets controlled by 
+/// this controller. 
+/// Note: This structure, and its companion Memory Module Information (Type 6, Obsolete), 
+/// are obsolete starting with version 2.1 of this specification. The Physical Memory Array (Type 16)
+/// and Memory Device (Type 17) structures should be used instead.  BIOS providers might
+/// choose to implement both memory description types to allow existing DMI browsers
+/// to properly display the system's memory attributes.
+///
+typedef struct {
+  SMBIOS_STRUCTURE                Hdr;
+  UINT8                           ErrDetectMethod;            ///< The enumeration value from MEMORY_ERROR_DETECT_METHOD.
+  MEMORY_ERROR_CORRECT_CAPABILITY ErrCorrectCapability;
+  UINT8                           SupportInterleave;          ///< The enumeration value from MEMORY_SUPPORT_INTERLEAVE_TYPE.
+  UINT8                           CurrentInterleave;          ///< The enumeration value from MEMORY_SUPPORT_INTERLEAVE_TYPE .     
+  UINT8                           MaxMemoryModuleSize;
+  MEMORY_SPEED_TYPE               SupportSpeed;
+  UINT16                          SupportMemoryType;
+  UINT8                           MemoryModuleVoltage;
+  UINT8                           AssociatedMemorySlotNum;
+  UINT16                          MemoryModuleConfigHandles[1];
+} SMBIOS_TABLE_TYPE5;
+
+///
+/// Memory Module Information - Memory Types
+///
+typedef struct {
+  UINT16  Other       :1;
+  UINT16  Unknown     :1;
+  UINT16  Standard    :1;
+  UINT16  FastPageMode:1;
+  UINT16  Edo         :1;
+  UINT16  Parity      :1;
+  UINT16  Ecc         :1;
+  UINT16  Simm        :1;
+  UINT16  Dimm        :1;
+  UINT16  BurstEdo    :1;
+  UINT16  Sdram       :1;
+  UINT16  Reserved    :5;
+} MEMORY_CURRENT_TYPE;
+
+///
+/// Memory Module Information - Memory Size.
+///
+typedef struct {
+  UINT8   InstalledOrEnabledSize  :7; ///< Size (n), where 2**n is the size in MB.
+  UINT8   SingleOrDoubleBank      :1;
+} MEMORY_INSTALLED_ENABLED_SIZE;
+
+///
+/// Memory Module Information (Type 6, Obsolete)
+///
+/// One Memory Module Information structure is included for each memory-module socket 
+/// in the system.  The structure describes the speed, type, size, and error status
+/// of each system memory module.  The supported attributes of each module are described 
+/// by the "owning" Memory Controller Information structure.  
+/// Note:  This structure, and its companion Memory Controller Information (Type 5, Obsolete), 
+/// are obsolete starting with version 2.1 of this specification. The Physical Memory Array (Type 16)
+/// and Memory Device (Type 17) structures should be used instead.
+///
+typedef struct {
+  SMBIOS_STRUCTURE              Hdr;
+  SMBIOS_TABLE_STRING           SocketDesignation;
+  UINT8                         BankConnections;
+  UINT8                         CurrentSpeed;
+  MEMORY_CURRENT_TYPE           CurrentMemoryType;
+  MEMORY_INSTALLED_ENABLED_SIZE InstalledSize;
+  MEMORY_INSTALLED_ENABLED_SIZE EnabledSize;
+  UINT8                         ErrorStatus;
+} SMBIOS_TABLE_TYPE6;
+
+///
+/// Cache Information - SRAM Type.
+///
+typedef struct {
+  UINT16  Other         :1;
+  UINT16  Unknown       :1;
+  UINT16  NonBurst      :1;
+  UINT16  Burst         :1;
+  UINT16  PipelineBurst :1;
+  UINT16  Synchronous   :1;
+  UINT16  Asynchronous  :1;
+  UINT16  Reserved      :9;
+} CACHE_SRAM_TYPE_DATA;
+
+///
+/// Cache Information - Error Correction Type.
+///
+typedef enum {
+  CacheErrorOther     = 0x01,
+  CacheErrorUnknown   = 0x02,
+  CacheErrorNone      = 0x03,
+  CacheErrorParity    = 0x04,
+  CacheErrorSingleBit = 0x05, ///< ECC
+  CacheErrorMultiBit  = 0x06  ///< ECC
+} CACHE_ERROR_TYPE_DATA;
+
+///
+/// Cache Information - System Cache Type. 
+///
+typedef enum {
+  CacheTypeOther       = 0x01,
+  CacheTypeUnknown     = 0x02,
+  CacheTypeInstruction = 0x03,
+  CacheTypeData        = 0x04,
+  CacheTypeUnified     = 0x05
+} CACHE_TYPE_DATA;
+
+///
+/// Cache Information - Associativity. 
+///
+typedef enum {
+  CacheAssociativityOther        = 0x01,
+  CacheAssociativityUnknown      = 0x02,
+  CacheAssociativityDirectMapped = 0x03,
+  CacheAssociativity2Way         = 0x04,
+  CacheAssociativity4Way         = 0x05,
+  CacheAssociativityFully        = 0x06,
+  CacheAssociativity8Way         = 0x07,
+  CacheAssociativity16Way        = 0x08,
+  CacheAssociativity12Way        = 0x09,
+  CacheAssociativity24Way        = 0x0A,
+  CacheAssociativity32Way        = 0x0B,
+  CacheAssociativity48Way        = 0x0C,
+  CacheAssociativity64Way        = 0x0D,
+  CacheAssociativity20Way        = 0x0E
+} CACHE_ASSOCIATIVITY_DATA;
+
+///
+/// Cache Information (Type 7).
+///
+/// The information in this structure defines the attributes of CPU cache device in the system. 
+/// One structure is specified for each such device, whether the device is internal to
+/// or external to the CPU module.  Cache modules can be associated with a processor structure
+/// in one or two ways, depending on the SMBIOS version.
+///
+typedef struct {
+  SMBIOS_STRUCTURE          Hdr;
+  SMBIOS_TABLE_STRING       SocketDesignation;
+  UINT16                    CacheConfiguration;
+  UINT16                    MaximumCacheSize;
+  UINT16                    InstalledSize;
+  CACHE_SRAM_TYPE_DATA      SupportedSRAMType;
+  CACHE_SRAM_TYPE_DATA      CurrentSRAMType;
+  UINT8                     CacheSpeed;
+  UINT8                     ErrorCorrectionType;            ///< The enumeration value from CACHE_ERROR_TYPE_DATA.
+  UINT8                     SystemCacheType;                ///< The enumeration value from CACHE_TYPE_DATA.
+  UINT8                     Associativity;                  ///< The enumeration value from CACHE_ASSOCIATIVITY_DATA.
+  //
+  // Add for smbios 3.1.0
+  //
+  UINT32                    MaximumCacheSize2;
+  UINT32                    InstalledSize2;
+} SMBIOS_TABLE_TYPE7;
+
+///
+/// Port Connector Information - Connector Types. 
+///
+typedef enum {
+  PortConnectorTypeNone                   = 0x00,
+  PortConnectorTypeCentronics             = 0x01,
+  PortConnectorTypeMiniCentronics         = 0x02,
+  PortConnectorTypeProprietary            = 0x03,
+  PortConnectorTypeDB25Male               = 0x04,
+  PortConnectorTypeDB25Female             = 0x05,
+  PortConnectorTypeDB15Male               = 0x06,
+  PortConnectorTypeDB15Female             = 0x07,
+  PortConnectorTypeDB9Male                = 0x08,
+  PortConnectorTypeDB9Female              = 0x09,
+  PortConnectorTypeRJ11                   = 0x0A,
+  PortConnectorTypeRJ45                   = 0x0B,
+  PortConnectorType50PinMiniScsi          = 0x0C,
+  PortConnectorTypeMiniDin                = 0x0D,
+  PortConnectorTypeMicroDin               = 0x0E,
+  PortConnectorTypePS2                    = 0x0F,
+  PortConnectorTypeInfrared               = 0x10,
+  PortConnectorTypeHpHil                  = 0x11,
+  PortConnectorTypeUsb                    = 0x12,
+  PortConnectorTypeSsaScsi                = 0x13,
+  PortConnectorTypeCircularDin8Male       = 0x14,
+  PortConnectorTypeCircularDin8Female     = 0x15,
+  PortConnectorTypeOnboardIde             = 0x16,
+  PortConnectorTypeOnboardFloppy          = 0x17,
+  PortConnectorType9PinDualInline         = 0x18,
+  PortConnectorType25PinDualInline        = 0x19,
+  PortConnectorType50PinDualInline        = 0x1A,
+  PortConnectorType68PinDualInline        = 0x1B,
+  PortConnectorTypeOnboardSoundInput      = 0x1C,
+  PortConnectorTypeMiniCentronicsType14   = 0x1D,
+  PortConnectorTypeMiniCentronicsType26   = 0x1E,
+  PortConnectorTypeHeadPhoneMiniJack      = 0x1F,
+  PortConnectorTypeBNC                    = 0x20,
+  PortConnectorType1394                   = 0x21,
+  PortConnectorTypeSasSata                = 0x22,
+  PortConnectorTypePC98                   = 0xA0,
+  PortConnectorTypePC98Hireso             = 0xA1,
+  PortConnectorTypePCH98                  = 0xA2,
+  PortConnectorTypePC98Note               = 0xA3,
+  PortConnectorTypePC98Full               = 0xA4,
+  PortConnectorTypeOther                  = 0xFF
+} MISC_PORT_CONNECTOR_TYPE;
+
+///
+/// Port Connector Information - Port Types 
+///
+typedef enum {
+  PortTypeNone                      = 0x00,
+  PortTypeParallelXtAtCompatible    = 0x01,
+  PortTypeParallelPortPs2           = 0x02,
+  PortTypeParallelPortEcp           = 0x03,
+  PortTypeParallelPortEpp           = 0x04,
+  PortTypeParallelPortEcpEpp        = 0x05,
+  PortTypeSerialXtAtCompatible      = 0x06,
+  PortTypeSerial16450Compatible     = 0x07,
+  PortTypeSerial16550Compatible     = 0x08,
+  PortTypeSerial16550ACompatible    = 0x09,
+  PortTypeScsi                      = 0x0A,
+  PortTypeMidi                      = 0x0B,
+  PortTypeJoyStick                  = 0x0C,
+  PortTypeKeyboard                  = 0x0D,
+  PortTypeMouse                     = 0x0E,
+  PortTypeSsaScsi                   = 0x0F,
+  PortTypeUsb                       = 0x10,
+  PortTypeFireWire                  = 0x11,
+  PortTypePcmciaTypeI               = 0x12,
+  PortTypePcmciaTypeII              = 0x13,
+  PortTypePcmciaTypeIII             = 0x14,
+  PortTypeCardBus                   = 0x15,
+  PortTypeAccessBusPort             = 0x16,
+  PortTypeScsiII                    = 0x17,
+  PortTypeScsiWide                  = 0x18,
+  PortTypePC98                      = 0x19,
+  PortTypePC98Hireso                = 0x1A,
+  PortTypePCH98                     = 0x1B,
+  PortTypeVideoPort                 = 0x1C,
+  PortTypeAudioPort                 = 0x1D,
+  PortTypeModemPort                 = 0x1E,
+  PortTypeNetworkPort               = 0x1F,
+  PortTypeSata                      = 0x20,
+  PortTypeSas                       = 0x21,
+  PortType8251Compatible            = 0xA0,
+  PortType8251FifoCompatible        = 0xA1,
+  PortTypeOther                     = 0xFF
+} MISC_PORT_TYPE;
+
+///
+/// Port Connector Information (Type 8).
+///
+/// The information in this structure defines the attributes of a system port connector, 
+/// e.g. parallel, serial, keyboard, or mouse ports.  The port's type and connector information 
+/// are provided. One structure is present for each port provided by the system.
+///
+typedef struct {
+  SMBIOS_STRUCTURE          Hdr;
+  SMBIOS_TABLE_STRING       InternalReferenceDesignator;
+  UINT8                     InternalConnectorType;          ///< The enumeration value from MISC_PORT_CONNECTOR_TYPE.
+  SMBIOS_TABLE_STRING       ExternalReferenceDesignator;
+  UINT8                     ExternalConnectorType;          ///< The enumeration value from MISC_PORT_CONNECTOR_TYPE.
+  UINT8                     PortType;                       ///< The enumeration value from MISC_PORT_TYPE.
+} SMBIOS_TABLE_TYPE8;
+
+///
+/// System Slots - Slot Type
+///
+typedef enum {
+  SlotTypeOther                        = 0x01,
+  SlotTypeUnknown                      = 0x02,
+  SlotTypeIsa                          = 0x03,
+  SlotTypeMca                          = 0x04,
+  SlotTypeEisa                         = 0x05,
+  SlotTypePci                          = 0x06,
+  SlotTypePcmcia                       = 0x07,
+  SlotTypeVlVesa                       = 0x08,
+  SlotTypeProprietary                  = 0x09,
+  SlotTypeProcessorCardSlot            = 0x0A,
+  SlotTypeProprietaryMemoryCardSlot    = 0x0B,
+  SlotTypeIORiserCardSlot              = 0x0C,
+  SlotTypeNuBus                        = 0x0D,
+  SlotTypePci66MhzCapable              = 0x0E,
+  SlotTypeAgp                          = 0x0F,
+  SlotTypeApg2X                        = 0x10,
+  SlotTypeAgp4X                        = 0x11,
+  SlotTypePciX                         = 0x12,
+  SlotTypeAgp8X                        = 0x13,
+  SlotTypeM2Socket1_DP                 = 0x14,
+  SlotTypeM2Socket1_SD                 = 0x15,
+  SlotTypeM2Socket2                    = 0x16,
+  SlotTypeM2Socket3                    = 0x17,
+  SlotTypeMxmTypeI                     = 0x18,
+  SlotTypeMxmTypeII                    = 0x19,
+  SlotTypeMxmTypeIIIStandard           = 0x1A,
+  SlotTypeMxmTypeIIIHe                 = 0x1B,
+  SlotTypeMxmTypeIV                    = 0x1C,
+  SlotTypeMxm30TypeA                   = 0x1D,
+  SlotTypeMxm30TypeB                   = 0x1E,
+  SlotTypePciExpressGen2Sff_8639       = 0x1F,
+  SlotTypePciExpressGen3Sff_8639       = 0x20,
+  SlotTypePciExpressMini52pinWithBSKO  = 0x21,      ///< PCI Express Mini 52-pin (CEM spec. 2.0) with bottom-side keep-outs.
+  SlotTypePciExpressMini52pinWithoutBSKO = 0x22,    ///< PCI Express Mini 52-pin (CEM spec. 2.0) without bottom-side keep-outs.
+  SlotTypePciExpressMini76pin          = 0x23,      ///< PCI Express Mini 76-pin (CEM spec. 2.0) Corresponds to Display-Mini card.
+  SlotTypePC98C20                      = 0xA0,
+  SlotTypePC98C24                      = 0xA1,
+  SlotTypePC98E                        = 0xA2,
+  SlotTypePC98LocalBus                 = 0xA3,
+  SlotTypePC98Card                     = 0xA4,
+  SlotTypePciExpress                   = 0xA5,
+  SlotTypePciExpressX1                 = 0xA6,
+  SlotTypePciExpressX2                 = 0xA7,
+  SlotTypePciExpressX4                 = 0xA8,
+  SlotTypePciExpressX8                 = 0xA9,
+  SlotTypePciExpressX16                = 0xAA,
+  SlotTypePciExpressGen2               = 0xAB,
+  SlotTypePciExpressGen2X1             = 0xAC,
+  SlotTypePciExpressGen2X2             = 0xAD,
+  SlotTypePciExpressGen2X4             = 0xAE,
+  SlotTypePciExpressGen2X8             = 0xAF,
+  SlotTypePciExpressGen2X16            = 0xB0,
+  SlotTypePciExpressGen3               = 0xB1,
+  SlotTypePciExpressGen3X1             = 0xB2,
+  SlotTypePciExpressGen3X2             = 0xB3,
+  SlotTypePciExpressGen3X4             = 0xB4,
+  SlotTypePciExpressGen3X8             = 0xB5,
+  SlotTypePciExpressGen3X16            = 0xB6
+} MISC_SLOT_TYPE;
+
+///
+/// System Slots - Slot Data Bus Width.
+///
+typedef enum {
+  SlotDataBusWidthOther      = 0x01,
+  SlotDataBusWidthUnknown    = 0x02,
+  SlotDataBusWidth8Bit       = 0x03,
+  SlotDataBusWidth16Bit      = 0x04,
+  SlotDataBusWidth32Bit      = 0x05,
+  SlotDataBusWidth64Bit      = 0x06,
+  SlotDataBusWidth128Bit     = 0x07,
+  SlotDataBusWidth1X         = 0x08, ///< Or X1
+  SlotDataBusWidth2X         = 0x09, ///< Or X2
+  SlotDataBusWidth4X         = 0x0A, ///< Or X4
+  SlotDataBusWidth8X         = 0x0B, ///< Or X8
+  SlotDataBusWidth12X        = 0x0C, ///< Or X12
+  SlotDataBusWidth16X        = 0x0D, ///< Or X16
+  SlotDataBusWidth32X        = 0x0E  ///< Or X32
+} MISC_SLOT_DATA_BUS_WIDTH;
+
+///
+/// System Slots - Current Usage.
+///
+typedef enum {
+  SlotUsageOther     = 0x01,
+  SlotUsageUnknown   = 0x02,
+  SlotUsageAvailable = 0x03,
+  SlotUsageInUse     = 0x04
+} MISC_SLOT_USAGE;
+
+///
+/// System Slots - Slot Length. 
+///
+typedef enum {
+  SlotLengthOther   = 0x01,
+  SlotLengthUnknown = 0x02,
+  SlotLengthShort   = 0x03,
+  SlotLengthLong    = 0x04
+} MISC_SLOT_LENGTH;
+
+///
+/// System Slots - Slot Characteristics 1. 
+///
+typedef struct {
+  UINT8  CharacteristicsUnknown  :1;
+  UINT8  Provides50Volts         :1;
+  UINT8  Provides33Volts         :1;
+  UINT8  SharedSlot              :1;
+  UINT8  PcCard16Supported       :1;
+  UINT8  CardBusSupported        :1;
+  UINT8  ZoomVideoSupported      :1;
+  UINT8  ModemRingResumeSupported:1;
+} MISC_SLOT_CHARACTERISTICS1;
+///
+/// System Slots - Slot Characteristics 2.  
+///
+typedef struct {
+  UINT8  PmeSignalSupported      :1;
+  UINT8  HotPlugDevicesSupported :1;
+  UINT8  SmbusSignalSupported    :1;
+  UINT8  Reserved                :5;  ///< Set to 0.
+} MISC_SLOT_CHARACTERISTICS2;
+
+///
+/// System Slots (Type 9)
+///
+/// The information in this structure defines the attributes of a system slot. 
+/// One structure is provided for each slot in the system.
+///
+///
+typedef struct {
+  SMBIOS_STRUCTURE            Hdr;
+  SMBIOS_TABLE_STRING         SlotDesignation;
+  UINT8                       SlotType;                 ///< The enumeration value from MISC_SLOT_TYPE.
+  UINT8                       SlotDataBusWidth;         ///< The enumeration value from MISC_SLOT_DATA_BUS_WIDTH.
+  UINT8                       CurrentUsage;             ///< The enumeration value from MISC_SLOT_USAGE.
+  UINT8                       SlotLength;               ///< The enumeration value from MISC_SLOT_LENGTH.
+  UINT16                      SlotID;
+  MISC_SLOT_CHARACTERISTICS1  SlotCharacteristics1;
+  MISC_SLOT_CHARACTERISTICS2  SlotCharacteristics2;
+  //
+  // Add for smbios 2.6
+  //
+  UINT16                      SegmentGroupNum;
+  UINT8                       BusNum;
+  UINT8                       DevFuncNum;
+} SMBIOS_TABLE_TYPE9;
+
+///
+/// On Board Devices Information - Device Types. 
+///
+typedef enum {
+  OnBoardDeviceTypeOther          = 0x01,
+  OnBoardDeviceTypeUnknown        = 0x02,
+  OnBoardDeviceTypeVideo          = 0x03,
+  OnBoardDeviceTypeScsiController = 0x04,
+  OnBoardDeviceTypeEthernet       = 0x05,
+  OnBoardDeviceTypeTokenRing      = 0x06,
+  OnBoardDeviceTypeSound          = 0x07,
+  OnBoardDeviceTypePATAController = 0x08,
+  OnBoardDeviceTypeSATAController = 0x09,
+  OnBoardDeviceTypeSASController  = 0x0A
+} MISC_ONBOARD_DEVICE_TYPE;
+
+///
+/// Device Item Entry
+///
+typedef struct {
+  UINT8                     DeviceType;             ///< Bit [6:0] - enumeration type of device from MISC_ONBOARD_DEVICE_TYPE.
+                                                    ///< Bit 7     - 1 : device enabled, 0 : device disabled.
+  SMBIOS_TABLE_STRING       DescriptionString;
+} DEVICE_STRUCT;
+
+///
+/// On Board Devices Information (Type 10, obsolete).
+///
+/// Note: This structure is obsolete starting with version 2.6 specification; the Onboard Devices Extended 
+/// Information (Type 41) structure should be used instead . BIOS providers can choose to implement both 
+/// types to allow existing SMBIOS browsers to properly display the system's onboard devices information.  
+/// The information in this structure defines the attributes of devices that are onboard (soldered onto) 
+/// a system element, usually the baseboard.  In general, an entry in this table implies that the BIOS
+/// has some level of control over the enabling of the associated device for use by the system.
+///
+typedef struct {
+  SMBIOS_STRUCTURE      Hdr;
+  DEVICE_STRUCT         Device[1];
+} SMBIOS_TABLE_TYPE10;
+
+///
+/// OEM Strings (Type 11).
+/// This structure contains free form strings defined by the OEM. Examples of this are: 
+/// Part Numbers for Reference Documents for the system, contact information for the manufacturer, etc. 
+///
+typedef struct {
+  SMBIOS_STRUCTURE      Hdr;
+  UINT8                 StringCount;
+} SMBIOS_TABLE_TYPE11;
+
+///
+/// System Configuration Options (Type 12).
+///
+/// This structure contains information required to configure the base board's Jumpers and Switches. 
+///
+typedef struct {
+  SMBIOS_STRUCTURE      Hdr;
+  UINT8                 StringCount;
+} SMBIOS_TABLE_TYPE12;
+
+
+///
+/// BIOS Language Information (Type 13).
+///
+/// The information in this structure defines the installable language attributes of the BIOS.  
+/// 
+typedef struct {
+  SMBIOS_STRUCTURE      Hdr;
+  UINT8                 InstallableLanguages;
+  UINT8                 Flags;
+  UINT8                 Reserved[15];
+  SMBIOS_TABLE_STRING   CurrentLanguages;
+} SMBIOS_TABLE_TYPE13;
+
+///
+/// Group Item Entry
+///
+typedef struct {
+  UINT8                 ItemType;
+  UINT16                ItemHandle;
+} GROUP_STRUCT;
+
+///
+/// Group Associations (Type 14).
+///
+/// The Group Associations structure is provided for OEMs who want to specify 
+/// the arrangement or hierarchy of certain components (including other Group Associations) 
+/// within the system. 
+///
+typedef struct {
+  SMBIOS_STRUCTURE      Hdr;
+  SMBIOS_TABLE_STRING   GroupName;
+  GROUP_STRUCT          Group[1];
+} SMBIOS_TABLE_TYPE14;
+
+///
+/// System Event Log - Event Log Types.
+/// 
+typedef enum {
+  EventLogTypeReserved         = 0x00,
+  EventLogTypeSingleBitECC     = 0x01,
+  EventLogTypeMultiBitECC      = 0x02,
+  EventLogTypeParityMemErr     = 0x03,
+  EventLogTypeBusTimeOut       = 0x04,
+  EventLogTypeIOChannelCheck   = 0x05,
+  EventLogTypeSoftwareNMI      = 0x06,
+  EventLogTypePOSTMemResize    = 0x07,
+  EventLogTypePOSTErr          = 0x08,
+  EventLogTypePCIParityErr     = 0x09,
+  EventLogTypePCISystemErr     = 0x0A,
+  EventLogTypeCPUFailure       = 0x0B,
+  EventLogTypeEISATimeOut      = 0x0C,
+  EventLogTypeMemLogDisabled   = 0x0D,
+  EventLogTypeLoggingDisabled  = 0x0E,
+  EventLogTypeSysLimitExce     = 0x10,
+  EventLogTypeAsyncHWTimer     = 0x11,
+  EventLogTypeSysConfigInfo    = 0x12,
+  EventLogTypeHDInfo           = 0x13,
+  EventLogTypeSysReconfig      = 0x14,
+  EventLogTypeUncorrectCPUErr  = 0x15,
+  EventLogTypeAreaResetAndClr  = 0x16,
+  EventLogTypeSystemBoot       = 0x17,
+  EventLogTypeUnused           = 0x18, ///< 0x18 - 0x7F
+  EventLogTypeAvailForSys      = 0x80, ///< 0x80 - 0xFE
+  EventLogTypeEndOfLog         = 0xFF
+} EVENT_LOG_TYPE_DATA;
+
+///
+/// System Event Log - Variable Data Format Types. 
+/// 
+typedef enum {
+  EventLogVariableNone                        = 0x00,
+  EventLogVariableHandle                      = 0x01,
+  EventLogVariableMutilEvent                  = 0x02,
+  EventLogVariableMutilEventHandle            = 0x03,
+  EventLogVariablePOSTResultBitmap            = 0x04,
+  EventLogVariableSysManagementType           = 0x05,
+  EventLogVariableMutliEventSysManagmentType  = 0x06,                               
+  EventLogVariableUnused                      = 0x07,
+  EventLogVariableOEMAssigned                 = 0x80
+} EVENT_LOG_VARIABLE_DATA;
+
+///
+/// Event Log Type Descriptors
+///
+typedef struct {
+  UINT8                 LogType;                    ///< The enumeration value from EVENT_LOG_TYPE_DATA.
+  UINT8                 DataFormatType;
+} EVENT_LOG_TYPE;
+
+///
+/// System Event Log (Type 15).
+///
+/// The presence of this structure within the SMBIOS data returned for a system indicates 
+/// that the system supports an event log.  An event log is a fixed-length area within a 
+/// non-volatile storage element, starting with a fixed-length (and vendor-specific) header 
+/// record, followed by one or more variable-length log records. 
+///
+typedef struct {
+  SMBIOS_STRUCTURE      Hdr;
+  UINT16                LogAreaLength;
+  UINT16                LogHeaderStartOffset;
+  UINT16                LogDataStartOffset;
+  UINT8                 AccessMethod;
+  UINT8                 LogStatus;
+  UINT32                LogChangeToken;
+  UINT32                AccessMethodAddress;
+  UINT8                 LogHeaderFormat;
+  UINT8                 NumberOfSupportedLogTypeDescriptors;
+  UINT8                 LengthOfLogTypeDescriptor;
+  EVENT_LOG_TYPE        EventLogTypeDescriptors[1];
+} SMBIOS_TABLE_TYPE15;
+
+///
+/// Physical Memory Array - Location.
+///
+typedef enum {
+  MemoryArrayLocationOther                 = 0x01,
+  MemoryArrayLocationUnknown               = 0x02,
+  MemoryArrayLocationSystemBoard           = 0x03,
+  MemoryArrayLocationIsaAddonCard          = 0x04,
+  MemoryArrayLocationEisaAddonCard         = 0x05,
+  MemoryArrayLocationPciAddonCard          = 0x06,
+  MemoryArrayLocationMcaAddonCard          = 0x07,
+  MemoryArrayLocationPcmciaAddonCard       = 0x08,
+  MemoryArrayLocationProprietaryAddonCard  = 0x09,
+  MemoryArrayLocationNuBus                 = 0x0A,
+  MemoryArrayLocationPc98C20AddonCard      = 0xA0,
+  MemoryArrayLocationPc98C24AddonCard      = 0xA1,
+  MemoryArrayLocationPc98EAddonCard        = 0xA2,
+  MemoryArrayLocationPc98LocalBusAddonCard = 0xA3
+} MEMORY_ARRAY_LOCATION;
+
+///
+/// Physical Memory Array - Use.
+///
+typedef enum {
+  MemoryArrayUseOther                      = 0x01,
+  MemoryArrayUseUnknown                    = 0x02,
+  MemoryArrayUseSystemMemory               = 0x03,
+  MemoryArrayUseVideoMemory                = 0x04,
+  MemoryArrayUseFlashMemory                = 0x05,
+  MemoryArrayUseNonVolatileRam             = 0x06,
+  MemoryArrayUseCacheMemory                = 0x07
+} MEMORY_ARRAY_USE;
+
+///
+/// Physical Memory Array - Error Correction Types. 
+///
+typedef enum {
+  MemoryErrorCorrectionOther               = 0x01,
+  MemoryErrorCorrectionUnknown             = 0x02,
+  MemoryErrorCorrectionNone                = 0x03,
+  MemoryErrorCorrectionParity              = 0x04,
+  MemoryErrorCorrectionSingleBitEcc        = 0x05,
+  MemoryErrorCorrectionMultiBitEcc         = 0x06,
+  MemoryErrorCorrectionCrc                 = 0x07
+} MEMORY_ERROR_CORRECTION;
+
+///
+/// Physical Memory Array (Type 16).
+///
+/// This structure describes a collection of memory devices that operate 
+/// together to form a memory address space. 
+///
+typedef struct {
+  SMBIOS_STRUCTURE          Hdr;
+  UINT8                     Location;                       ///< The enumeration value from MEMORY_ARRAY_LOCATION.
+  UINT8                     Use;                            ///< The enumeration value from MEMORY_ARRAY_USE.
+  UINT8                     MemoryErrorCorrection;          ///< The enumeration value from MEMORY_ERROR_CORRECTION.
+  UINT32                    MaximumCapacity;
+  UINT16                    MemoryErrorInformationHandle;
+  UINT16                    NumberOfMemoryDevices;
+  //
+  // Add for smbios 2.7
+  //
+  UINT64                    ExtendedMaximumCapacity;
+} SMBIOS_TABLE_TYPE16;
+
+///
+/// Memory Device - Form Factor.
+///
+typedef enum {
+  MemoryFormFactorOther                    = 0x01,
+  MemoryFormFactorUnknown                  = 0x02,
+  MemoryFormFactorSimm                     = 0x03,
+  MemoryFormFactorSip                      = 0x04,
+  MemoryFormFactorChip                     = 0x05,
+  MemoryFormFactorDip                      = 0x06,
+  MemoryFormFactorZip                      = 0x07,
+  MemoryFormFactorProprietaryCard          = 0x08,
+  MemoryFormFactorDimm                     = 0x09,
+  MemoryFormFactorTsop                     = 0x0A,
+  MemoryFormFactorRowOfChips               = 0x0B,
+  MemoryFormFactorRimm                     = 0x0C,
+  MemoryFormFactorSodimm                   = 0x0D,
+  MemoryFormFactorSrimm                    = 0x0E,
+  MemoryFormFactorFbDimm                   = 0x0F
+} MEMORY_FORM_FACTOR;
+
+///
+/// Memory Device - Type
+///
+typedef enum {
+  MemoryTypeOther                          = 0x01,
+  MemoryTypeUnknown                        = 0x02,
+  MemoryTypeDram                           = 0x03,
+  MemoryTypeEdram                          = 0x04,
+  MemoryTypeVram                           = 0x05,
+  MemoryTypeSram                           = 0x06,
+  MemoryTypeRam                            = 0x07,
+  MemoryTypeRom                            = 0x08,
+  MemoryTypeFlash                          = 0x09,
+  MemoryTypeEeprom                         = 0x0A,
+  MemoryTypeFeprom                         = 0x0B,
+  MemoryTypeEprom                          = 0x0C,
+  MemoryTypeCdram                          = 0x0D,
+  MemoryType3Dram                          = 0x0E,
+  MemoryTypeSdram                          = 0x0F,
+  MemoryTypeSgram                          = 0x10,
+  MemoryTypeRdram                          = 0x11,
+  MemoryTypeDdr                            = 0x12,
+  MemoryTypeDdr2                           = 0x13,
+  MemoryTypeDdr2FbDimm                     = 0x14,
+  MemoryTypeDdr3                           = 0x18,
+  MemoryTypeFbd2                           = 0x19,
+  MemoryTypeDdr4                           = 0x1A,
+  MemoryTypeLpddr                          = 0x1B,
+  MemoryTypeLpddr2                         = 0x1C,
+  MemoryTypeLpddr3                         = 0x1D,
+  MemoryTypeLpddr4                         = 0x1E
+} MEMORY_DEVICE_TYPE;
+
+typedef struct {
+  UINT16    Reserved        :1;
+  UINT16    Other           :1;
+  UINT16    Unknown         :1;
+  UINT16    FastPaged       :1;
+  UINT16    StaticColumn    :1;
+  UINT16    PseudoStatic    :1;
+  UINT16    Rambus          :1;
+  UINT16    Synchronous     :1;
+  UINT16    Cmos            :1;
+  UINT16    Edo             :1;
+  UINT16    WindowDram      :1;
+  UINT16    CacheDram       :1;
+  UINT16    Nonvolatile     :1;
+  UINT16    Registered      :1;
+  UINT16    Unbuffered      :1;
+  UINT16    LrDimm          :1;
+} MEMORY_DEVICE_TYPE_DETAIL;
+
+///
+/// Memory Device (Type 17).
+///
+/// This structure describes a single memory device that is part of 
+/// a larger Physical Memory Array (Type 16).
+/// Note:  If a system includes memory-device sockets, the SMBIOS implementation 
+/// includes a Memory Device structure instance for each slot, whether or not the 
+/// socket is currently populated.
+///
+typedef struct {
+  SMBIOS_STRUCTURE          Hdr;
+  UINT16                    MemoryArrayHandle;
+  UINT16                    MemoryErrorInformationHandle;
+  UINT16                    TotalWidth;
+  UINT16                    DataWidth;
+  UINT16                    Size;
+  UINT8                     FormFactor;                     ///< The enumeration value from MEMORY_FORM_FACTOR.
+  UINT8                     DeviceSet;
+  SMBIOS_TABLE_STRING       DeviceLocator;
+  SMBIOS_TABLE_STRING       BankLocator;
+  UINT8                     MemoryType;                     ///< The enumeration value from MEMORY_DEVICE_TYPE.
+  MEMORY_DEVICE_TYPE_DETAIL TypeDetail;
+  UINT16                    Speed;
+  SMBIOS_TABLE_STRING       Manufacturer;
+  SMBIOS_TABLE_STRING       SerialNumber;
+  SMBIOS_TABLE_STRING       AssetTag;
+  SMBIOS_TABLE_STRING       PartNumber;
+  //
+  // Add for smbios 2.6
+  //  
+  UINT8                     Attributes;
+  //
+  // Add for smbios 2.7
+  //
+  UINT32                    ExtendedSize;
+  UINT16                    ConfiguredMemoryClockSpeed;
+  //
+  // Add for smbios 2.8.0
+  //
+  UINT16                    MinimumVoltage;
+  UINT16                    MaximumVoltage;
+  UINT16                    ConfiguredVoltage;
+} SMBIOS_TABLE_TYPE17;
+
+///
+/// 32-bit Memory Error Information - Error Type. 
+///
+typedef enum {  
+  MemoryErrorOther             = 0x01,
+  MemoryErrorUnknown           = 0x02,
+  MemoryErrorOk                = 0x03,
+  MemoryErrorBadRead           = 0x04,
+  MemoryErrorParity            = 0x05,
+  MemoryErrorSigleBit          = 0x06,
+  MemoryErrorDoubleBit         = 0x07,
+  MemoryErrorMultiBit          = 0x08,
+  MemoryErrorNibble            = 0x09,
+  MemoryErrorChecksum          = 0x0A,
+  MemoryErrorCrc               = 0x0B,
+  MemoryErrorCorrectSingleBit  = 0x0C,
+  MemoryErrorCorrected         = 0x0D,
+  MemoryErrorUnCorrectable     = 0x0E
+} MEMORY_ERROR_TYPE;
+
+///
+/// 32-bit Memory Error Information - Error Granularity. 
+///
+typedef enum {  
+  MemoryGranularityOther               = 0x01,
+  MemoryGranularityOtherUnknown        = 0x02,
+  MemoryGranularityDeviceLevel         = 0x03,
+  MemoryGranularityMemPartitionLevel   = 0x04
+} MEMORY_ERROR_GRANULARITY;
+
+///
+/// 32-bit Memory Error Information - Error Operation. 
+///
+typedef enum {  
+  MemoryErrorOperationOther            = 0x01,
+  MemoryErrorOperationUnknown          = 0x02,
+  MemoryErrorOperationRead             = 0x03,
+  MemoryErrorOperationWrite            = 0x04,
+  MemoryErrorOperationPartialWrite     = 0x05
+} MEMORY_ERROR_OPERATION;
+
+///
+/// 32-bit Memory Error Information (Type 18).
+/// 
+/// This structure identifies the specifics of an error that might be detected 
+/// within a Physical Memory Array.
+///
+typedef struct {
+  SMBIOS_STRUCTURE          Hdr;
+  UINT8                     ErrorType;                  ///< The enumeration value from MEMORY_ERROR_TYPE.
+  UINT8                     ErrorGranularity;           ///< The enumeration value from MEMORY_ERROR_GRANULARITY.
+  UINT8                     ErrorOperation;             ///< The enumeration value from MEMORY_ERROR_OPERATION.
+  UINT32                    VendorSyndrome;
+  UINT32                    MemoryArrayErrorAddress;
+  UINT32                    DeviceErrorAddress;
+  UINT32                    ErrorResolution;
+} SMBIOS_TABLE_TYPE18;
+
+///
+/// Memory Array Mapped Address (Type 19).
+///
+/// This structure provides the address mapping for a Physical Memory Array.  
+/// One structure is present for each contiguous address range described.
+///
+typedef struct {
+  SMBIOS_STRUCTURE      Hdr;
+  UINT32                StartingAddress;
+  UINT32                EndingAddress;
+  UINT16                MemoryArrayHandle;
+  UINT8                 PartitionWidth;
+  //
+  // Add for smbios 2.7
+  //
+  UINT64                ExtendedStartingAddress;
+  UINT64                ExtendedEndingAddress;
+} SMBIOS_TABLE_TYPE19;
+
+///
+/// Memory Device Mapped Address (Type 20).
+///
+/// This structure maps memory address space usually to a device-level granularity.  
+/// One structure is present for each contiguous address range described. 
+///
+typedef struct {
+  SMBIOS_STRUCTURE      Hdr;
+  UINT32                StartingAddress;
+  UINT32                EndingAddress;
+  UINT16                MemoryDeviceHandle;
+  UINT16                MemoryArrayMappedAddressHandle;
+  UINT8                 PartitionRowPosition;
+  UINT8                 InterleavePosition;
+  UINT8                 InterleavedDataDepth;
+  //
+  // Add for smbios 2.7
+  //
+  UINT64                ExtendedStartingAddress;
+  UINT64                ExtendedEndingAddress;
+} SMBIOS_TABLE_TYPE20;
+
+///
+/// Built-in Pointing Device - Type
+///
+typedef enum {
+  PointingDeviceTypeOther         = 0x01,
+  PointingDeviceTypeUnknown       = 0x02,
+  PointingDeviceTypeMouse         = 0x03,
+  PointingDeviceTypeTrackBall     = 0x04,
+  PointingDeviceTypeTrackPoint    = 0x05,
+  PointingDeviceTypeGlidePoint    = 0x06,
+  PointingDeviceTouchPad          = 0x07,
+  PointingDeviceTouchScreen       = 0x08,
+  PointingDeviceOpticalSensor     = 0x09
+} BUILTIN_POINTING_DEVICE_TYPE;
+
+///
+/// Built-in Pointing Device - Interface.
+///
+typedef enum {
+  PointingDeviceInterfaceOther              = 0x01,
+  PointingDeviceInterfaceUnknown            = 0x02,
+  PointingDeviceInterfaceSerial             = 0x03,
+  PointingDeviceInterfacePs2                = 0x04,
+  PointingDeviceInterfaceInfrared           = 0x05,
+  PointingDeviceInterfaceHpHil              = 0x06,
+  PointingDeviceInterfaceBusMouse           = 0x07,
+  PointingDeviceInterfaceADB                = 0x08,
+  PointingDeviceInterfaceBusMouseDB9        = 0xA0,
+  PointingDeviceInterfaceBusMouseMicroDin   = 0xA1,
+  PointingDeviceInterfaceUsb                = 0xA2
+} BUILTIN_POINTING_DEVICE_INTERFACE;
+
+///
+/// Built-in Pointing Device (Type 21).
+///
+/// This structure describes the attributes of the built-in pointing device for the 
+/// system. The presence of this structure does not imply that the built-in
+/// pointing device is active for the system's use! 
+///
+typedef struct {
+  SMBIOS_STRUCTURE                  Hdr;
+  UINT8                             Type;                   ///< The enumeration value from BUILTIN_POINTING_DEVICE_TYPE.
+  UINT8                             Interface;              ///< The enumeration value from BUILTIN_POINTING_DEVICE_INTERFACE.
+  UINT8                             NumberOfButtons;
+} SMBIOS_TABLE_TYPE21;
+
+///
+/// Portable Battery - Device Chemistry
+///
+typedef enum {  
+  PortableBatteryDeviceChemistryOther               = 0x01,
+  PortableBatteryDeviceChemistryUnknown             = 0x02,
+  PortableBatteryDeviceChemistryLeadAcid            = 0x03,
+  PortableBatteryDeviceChemistryNickelCadmium       = 0x04,
+  PortableBatteryDeviceChemistryNickelMetalHydride  = 0x05,
+  PortableBatteryDeviceChemistryLithiumIon          = 0x06,
+  PortableBatteryDeviceChemistryZincAir             = 0x07,
+  PortableBatteryDeviceChemistryLithiumPolymer      = 0x08
+} PORTABLE_BATTERY_DEVICE_CHEMISTRY;
+
+///
+/// Portable Battery (Type 22).
+///
+/// This structure describes the attributes of the portable battery(s) for the system.  
+/// The structure contains the static attributes for the group.  Each structure describes 
+/// a single battery pack's attributes.
+///
+typedef struct {
+  SMBIOS_STRUCTURE                  Hdr;
+  SMBIOS_TABLE_STRING               Location;
+  SMBIOS_TABLE_STRING               Manufacturer;
+  SMBIOS_TABLE_STRING               ManufactureDate;
+  SMBIOS_TABLE_STRING               SerialNumber;
+  SMBIOS_TABLE_STRING               DeviceName;
+  UINT8                             DeviceChemistry;              ///< The enumeration value from PORTABLE_BATTERY_DEVICE_CHEMISTRY.
+  UINT16                            DeviceCapacity;
+  UINT16                            DesignVoltage;
+  SMBIOS_TABLE_STRING               SBDSVersionNumber;
+  UINT8                             MaximumErrorInBatteryData;
+  UINT16                            SBDSSerialNumber;
+  UINT16                            SBDSManufactureDate;
+  SMBIOS_TABLE_STRING               SBDSDeviceChemistry;
+  UINT8                             DesignCapacityMultiplier;
+  UINT32                            OEMSpecific;
+} SMBIOS_TABLE_TYPE22;
+
+///
+/// System Reset (Type 23)
+///
+/// This structure describes whether Automatic System Reset functions enabled (Status).  
+/// If the system has a watchdog Timer and the timer is not reset (Timer Reset)
+/// before the Interval elapses, an automatic system reset will occur. The system will re-boot 
+/// according to the Boot Option. This function may repeat until the Limit is reached, at which time 
+/// the system will re-boot according to the Boot Option at Limit.  
+///
+typedef struct {
+  SMBIOS_STRUCTURE      Hdr;
+  UINT8                 Capabilities;
+  UINT16                ResetCount;
+  UINT16                ResetLimit;
+  UINT16                TimerInterval;
+  UINT16                Timeout;
+} SMBIOS_TABLE_TYPE23;
+
+///
+/// Hardware Security (Type 24).
+///
+/// This structure describes the system-wide hardware security settings. 
+///
+typedef struct {
+  SMBIOS_STRUCTURE      Hdr;
+  UINT8                 HardwareSecuritySettings;
+} SMBIOS_TABLE_TYPE24;
+
+///
+/// System Power Controls (Type 25).
+///
+/// This structure describes the attributes for controlling the main power supply to the system. 
+/// Software that interprets this structure uses the month, day, hour, minute, and second values 
+/// to determine the number of seconds until the next power-on of the system.  The presence of  
+/// this structure implies that a timed power-on facility is available for the system. 
+///
+typedef struct {
+  SMBIOS_STRUCTURE      Hdr;
+  UINT8                 NextScheduledPowerOnMonth;
+  UINT8                 NextScheduledPowerOnDayOfMonth;
+  UINT8                 NextScheduledPowerOnHour;
+  UINT8                 NextScheduledPowerOnMinute;
+  UINT8                 NextScheduledPowerOnSecond;
+} SMBIOS_TABLE_TYPE25;
+
+///
+/// Voltage Probe - Location and Status.
+///
+typedef struct {
+  UINT8 VoltageProbeSite      :5;
+  UINT8  VoltageProbeStatus   :3;
+} MISC_VOLTAGE_PROBE_LOCATION;
+
+///
+/// Voltage Probe (Type 26)
+///
+/// This describes the attributes for a voltage probe in the system.   
+/// Each structure describes a single voltage probe.
+///
+typedef struct {
+  SMBIOS_STRUCTURE              Hdr;
+  SMBIOS_TABLE_STRING           Description;
+  MISC_VOLTAGE_PROBE_LOCATION   LocationAndStatus;
+  UINT16                        MaximumValue;
+  UINT16                        MinimumValue;
+  UINT16                        Resolution;
+  UINT16                        Tolerance;
+  UINT16                        Accuracy;
+  UINT32                        OEMDefined;
+  UINT16                        NominalValue;
+} SMBIOS_TABLE_TYPE26;
+
+///
+/// Cooling Device - Device Type and Status.
+///
+typedef struct {
+  UINT8 CoolingDevice       :5;
+  UINT8 CoolingDeviceStatus :3;
+} MISC_COOLING_DEVICE_TYPE;
+
+///
+/// Cooling Device (Type 27)
+///
+/// This structure describes the attributes for a cooling device in the system.  
+/// Each structure describes a single cooling device. 
+/// 
+typedef struct {
+  SMBIOS_STRUCTURE                  Hdr;
+  UINT16                            TemperatureProbeHandle;
+  MISC_COOLING_DEVICE_TYPE          DeviceTypeAndStatus;
+  UINT8                             CoolingUnitGroup;
+  UINT32                            OEMDefined;
+  UINT16                            NominalSpeed;
+  //
+  // Add for smbios 2.7
+  //
+  SMBIOS_TABLE_STRING               Description;
+} SMBIOS_TABLE_TYPE27;
+
+///
+/// Temperature Probe - Location and Status.
+///
+typedef struct {
+  UINT8 TemperatureProbeSite   :5;
+  UINT8 TemperatureProbeStatus :3;
+} MISC_TEMPERATURE_PROBE_LOCATION;
+
+///
+/// Temperature Probe (Type 28).
+///
+/// This structure describes the attributes for a temperature probe in the system.  
+/// Each structure describes a single temperature probe. 
+///
+typedef struct {
+  SMBIOS_STRUCTURE                  Hdr;
+  SMBIOS_TABLE_STRING               Description;
+  MISC_TEMPERATURE_PROBE_LOCATION   LocationAndStatus;
+  UINT16                            MaximumValue;
+  UINT16                            MinimumValue;
+  UINT16                            Resolution;
+  UINT16                            Tolerance;
+  UINT16                            Accuracy;
+  UINT32                            OEMDefined;
+  UINT16                            NominalValue;
+} SMBIOS_TABLE_TYPE28;
+
+///
+/// Electrical Current Probe - Location and Status.
+///
+typedef struct {
+  UINT8 ElectricalCurrentProbeSite   :5;
+  UINT8 ElectricalCurrentProbeStatus :3;
+} MISC_ELECTRICAL_CURRENT_PROBE_LOCATION;
+
+///
+/// Electrical Current Probe (Type 29).
+///
+/// This structure describes the attributes for an electrical current probe in the system.
+/// Each structure describes a single electrical current probe. 
+///
+typedef struct {
+  SMBIOS_STRUCTURE                        Hdr;
+  SMBIOS_TABLE_STRING                     Description;
+  MISC_ELECTRICAL_CURRENT_PROBE_LOCATION  LocationAndStatus;
+  UINT16                                  MaximumValue;
+  UINT16                                  MinimumValue;
+  UINT16                                  Resolution;
+  UINT16                                  Tolerance;
+  UINT16                                  Accuracy;
+  UINT32                                  OEMDefined;
+  UINT16                                  NominalValue;
+} SMBIOS_TABLE_TYPE29;
+
+///
+/// Out-of-Band Remote Access (Type 30).
+///
+/// This structure describes the attributes and policy settings of a hardware facility 
+/// that may be used to gain remote access to a hardware system when the operating system 
+/// is not available due to power-down status, hardware failures, or boot failures. 
+///
+typedef struct {
+  SMBIOS_STRUCTURE      Hdr;
+  SMBIOS_TABLE_STRING   ManufacturerName;
+  UINT8                 Connections;
+} SMBIOS_TABLE_TYPE30;
+
+///
+/// Boot Integrity Services (BIS) Entry Point (Type 31).
+///
+/// Structure type 31 (decimal) is reserved for use by the Boot Integrity Services (BIS). 
+/// 
+typedef struct {
+  SMBIOS_STRUCTURE      Hdr;
+  UINT8                 Checksum;
+  UINT8                 Reserved1;
+  UINT16                Reserved2;
+  UINT32                BisEntry16;
+  UINT32                BisEntry32;
+  UINT64                Reserved3;
+  UINT32                Reserved4;
+} SMBIOS_TABLE_TYPE31;
+
+///
+/// System Boot Information - System Boot Status.
+///
+typedef enum {
+  BootInformationStatusNoError                  = 0x00,
+  BootInformationStatusNoBootableMedia          = 0x01,
+  BootInformationStatusNormalOSFailedLoading    = 0x02,
+  BootInformationStatusFirmwareDetectedFailure  = 0x03,
+  BootInformationStatusOSDetectedFailure        = 0x04,
+  BootInformationStatusUserRequestedBoot        = 0x05,
+  BootInformationStatusSystemSecurityViolation  = 0x06,
+  BootInformationStatusPreviousRequestedImage   = 0x07,
+  BootInformationStatusWatchdogTimerExpired     = 0x08,
+  BootInformationStatusStartReserved            = 0x09,
+  BootInformationStatusStartOemSpecific         = 0x80,
+  BootInformationStatusStartProductSpecific     = 0xC0
+} MISC_BOOT_INFORMATION_STATUS_DATA_TYPE;
+
+///
+/// System Boot Information (Type 32).
+///
+/// The client system firmware, e.g. BIOS, communicates the System Boot Status to the 
+/// client's Pre-boot Execution Environment (PXE) boot image or OS-present management 
+/// application via this structure. When used in the PXE environment, for example, 
+/// this code identifies the reason the PXE was initiated and can be used by boot-image 
+/// software to further automate an enterprise's PXE sessions.  For example, an enterprise  
+/// could choose to automatically download a hardware-diagnostic image to a client whose 
+/// reason code indicated either a firmware- or operating system-detected hardware failure.
+///
+typedef struct {
+  SMBIOS_STRUCTURE                        Hdr;
+  UINT8                                   Reserved[6];
+  UINT8                                   BootStatus;     ///< The enumeration value from MISC_BOOT_INFORMATION_STATUS_DATA_TYPE.
+} SMBIOS_TABLE_TYPE32;
+
+///
+/// 64-bit Memory Error Information (Type 33).
+///
+/// This structure describes an error within a Physical Memory Array, 
+/// when the error address is above 4G (0xFFFFFFFF).
+///    
+typedef struct {
+  SMBIOS_STRUCTURE          Hdr;
+  UINT8                     ErrorType;                    ///< The enumeration value from MEMORY_ERROR_TYPE.
+  UINT8                     ErrorGranularity;             ///< The enumeration value from MEMORY_ERROR_GRANULARITY.
+  UINT8                     ErrorOperation;               ///< The enumeration value from MEMORY_ERROR_OPERATION.
+  UINT32                    VendorSyndrome;
+  UINT64                    MemoryArrayErrorAddress;
+  UINT64                    DeviceErrorAddress;
+  UINT32                    ErrorResolution;
+} SMBIOS_TABLE_TYPE33;
+
+///
+/// Management Device -  Type. 
+///
+typedef enum {
+  ManagementDeviceTypeOther      = 0x01,
+  ManagementDeviceTypeUnknown    = 0x02,
+  ManagementDeviceTypeLm75       = 0x03,
+  ManagementDeviceTypeLm78       = 0x04,
+  ManagementDeviceTypeLm79       = 0x05,
+  ManagementDeviceTypeLm80       = 0x06,
+  ManagementDeviceTypeLm81       = 0x07,
+  ManagementDeviceTypeAdm9240    = 0x08,
+  ManagementDeviceTypeDs1780     = 0x09,
+  ManagementDeviceTypeMaxim1617  = 0x0A,
+  ManagementDeviceTypeGl518Sm    = 0x0B,
+  ManagementDeviceTypeW83781D    = 0x0C,
+  ManagementDeviceTypeHt82H791   = 0x0D
+} MISC_MANAGEMENT_DEVICE_TYPE;
+
+///
+/// Management Device -  Address Type. 
+///
+typedef enum {
+  ManagementDeviceAddressTypeOther   = 0x01,
+  ManagementDeviceAddressTypeUnknown = 0x02,
+  ManagementDeviceAddressTypeIOPort  = 0x03,
+  ManagementDeviceAddressTypeMemory  = 0x04,
+  ManagementDeviceAddressTypeSmbus   = 0x05
+} MISC_MANAGEMENT_DEVICE_ADDRESS_TYPE;
+
+///
+/// Management Device (Type 34).
+///
+/// The information in this structure defines the attributes of a Management Device.  
+/// A Management Device might control one or more fans or voltage, current, or temperature
+/// probes as defined by one or more Management Device Component structures.
+///
+typedef struct {
+  SMBIOS_STRUCTURE                      Hdr;
+  SMBIOS_TABLE_STRING                   Description;
+  UINT8                                 Type;                     ///< The enumeration value from MISC_MANAGEMENT_DEVICE_TYPE.
+  UINT32                                Address;
+  UINT8                                 AddressType;              ///< The enumeration value from MISC_MANAGEMENT_DEVICE_ADDRESS_TYPE.
+} SMBIOS_TABLE_TYPE34;
+
+///
+/// Management Device Component (Type 35)
+///
+/// This structure associates a cooling device or environmental probe with structures 
+/// that define the controlling hardware device and (optionally) the component's thresholds. 
+///
+typedef struct {
+  SMBIOS_STRUCTURE      Hdr;
+  SMBIOS_TABLE_STRING   Description;
+  UINT16                ManagementDeviceHandle;
+  UINT16                ComponentHandle;
+  UINT16                ThresholdHandle;
+} SMBIOS_TABLE_TYPE35;
+
+///
+/// Management Device Threshold Data (Type 36).
+///
+/// The information in this structure defines threshold information for 
+/// a component (probe or cooling-unit) contained within a Management Device.  
+///
+typedef struct {
+  SMBIOS_STRUCTURE      Hdr;
+  UINT16                LowerThresholdNonCritical;
+  UINT16                UpperThresholdNonCritical;
+  UINT16                LowerThresholdCritical;
+  UINT16                UpperThresholdCritical;
+  UINT16                LowerThresholdNonRecoverable;
+  UINT16                UpperThresholdNonRecoverable;
+} SMBIOS_TABLE_TYPE36;
+
+///
+/// Memory Channel Entry.
+///
+typedef struct {
+  UINT8                 DeviceLoad;
+  UINT16                DeviceHandle;
+} MEMORY_DEVICE;
+
+///
+/// Memory Channel - Channel Type.
+///
+typedef enum {
+  MemoryChannelTypeOther       = 0x01,
+  MemoryChannelTypeUnknown     = 0x02,
+  MemoryChannelTypeRambus      = 0x03,
+  MemoryChannelTypeSyncLink    = 0x04
+} MEMORY_CHANNEL_TYPE;
+
+///
+/// Memory Channel (Type 37)
+///
+/// The information in this structure provides the correlation between a Memory Channel
+/// and its associated Memory Devices.  Each device presents one or more loads to the channel. 
+/// The sum of all device loads cannot exceed the channel's defined maximum.
+///
+typedef struct {
+  SMBIOS_STRUCTURE      Hdr;
+  UINT8                 ChannelType;
+  UINT8                 MaximumChannelLoad;
+  UINT8                 MemoryDeviceCount;
+  MEMORY_DEVICE         MemoryDevice[1];
+} SMBIOS_TABLE_TYPE37;
+
+///
+/// IPMI Device Information - BMC Interface Type
+///
+typedef enum {
+  IPMIDeviceInfoInterfaceTypeUnknown       = 0x00,
+  IPMIDeviceInfoInterfaceTypeKCS           = 0x01, ///< The Keyboard Controller Style.
+  IPMIDeviceInfoInterfaceTypeSMIC          = 0x02, ///< The Server Management Interface Chip.
+  IPMIDeviceInfoInterfaceTypeBT            = 0x03, ///< The Block Transfer
+  IPMIDeviceInfoInterfaceTypeReserved      = 0x04
+} BMC_INTERFACE_TYPE;
+
+///
+/// IPMI Device Information (Type 38).
+///
+/// The information in this structure defines the attributes of an
+/// Intelligent Platform Management Interface (IPMI) Baseboard Management Controller (BMC).
+///
+/// The Type 42 structure can also be used to describe a physical management controller
+/// host interface and one or more protocols that share that interface. If IPMI is not
+/// shared with other protocols, either the Type 38 or Type 42 structures can be used.
+/// Providing Type 38 is recommended for backward compatibility.
+///
+typedef struct {
+  SMBIOS_STRUCTURE      Hdr;
+  UINT8                 InterfaceType;              ///< The enumeration value from BMC_INTERFACE_TYPE.
+  UINT8                 IPMISpecificationRevision;
+  UINT8                 I2CSlaveAddress;
+  UINT8                 NVStorageDeviceAddress;
+  UINT64                BaseAddress;
+  UINT8                 BaseAddressModifier_InterruptInfo;
+  UINT8                 InterruptNumber;
+} SMBIOS_TABLE_TYPE38;
+
+///
+/// System Power Supply - Power Supply Characteristics.
+///
+typedef struct {
+  UINT16                        PowerSupplyHotReplaceable:1;
+  UINT16                        PowerSupplyPresent       :1;
+  UINT16                        PowerSupplyUnplugged     :1;
+  UINT16                        InputVoltageRangeSwitch  :4;
+  UINT16                        PowerSupplyStatus        :3;
+  UINT16                        PowerSupplyType          :4;
+  UINT16                        Reserved                 :2;
+} SYS_POWER_SUPPLY_CHARACTERISTICS;
+
+///
+/// System Power Supply (Type 39).
+///
+/// This structure identifies attributes of a system power supply. One instance
+/// of this record is present for each possible power supply in a system.
+///
+typedef struct {
+  SMBIOS_STRUCTURE                  Hdr;
+  UINT8                             PowerUnitGroup;
+  SMBIOS_TABLE_STRING               Location;
+  SMBIOS_TABLE_STRING               DeviceName;
+  SMBIOS_TABLE_STRING               Manufacturer;
+  SMBIOS_TABLE_STRING               SerialNumber;
+  SMBIOS_TABLE_STRING               AssetTagNumber;
+  SMBIOS_TABLE_STRING               ModelPartNumber;
+  SMBIOS_TABLE_STRING               RevisionLevel;
+  UINT16                            MaxPowerCapacity;
+  SYS_POWER_SUPPLY_CHARACTERISTICS  PowerSupplyCharacteristics;
+  UINT16                            InputVoltageProbeHandle;
+  UINT16                            CoolingDeviceHandle;
+  UINT16                            InputCurrentProbeHandle;
+} SMBIOS_TABLE_TYPE39;
+
+///
+/// Additional Information Entry Format. 
+///
+typedef struct {                       
+  UINT8                   EntryLength; 
+  UINT16                  ReferencedHandle;
+  UINT8                   ReferencedOffset;
+  SMBIOS_TABLE_STRING     EntryString;
+  UINT8                   Value[1];
+}ADDITIONAL_INFORMATION_ENTRY;
+
+///
+/// Additional Information (Type 40).
+///
+/// This structure is intended to provide additional information for handling unspecified 
+/// enumerated values and interim field updates in another structure. 
+///
+typedef struct {
+  SMBIOS_STRUCTURE                      Hdr;
+  UINT8                                 NumberOfAdditionalInformationEntries;
+  ADDITIONAL_INFORMATION_ENTRY          AdditionalInfoEntries[1];  
+} SMBIOS_TABLE_TYPE40;
+
+///
+/// Onboard Devices Extended Information - Onboard Device Types.
+///
+typedef enum{
+  OnBoardDeviceExtendedTypeOther          = 0x01,
+  OnBoardDeviceExtendedTypeUnknown        = 0x02,
+  OnBoardDeviceExtendedTypeVideo          = 0x03,
+  OnBoardDeviceExtendedTypeScsiController = 0x04,
+  OnBoardDeviceExtendedTypeEthernet       = 0x05,
+  OnBoardDeviceExtendedTypeTokenRing      = 0x06,
+  OnBoardDeviceExtendedTypeSound          = 0x07,
+  OnBoardDeviceExtendedTypePATAController = 0x08,
+  OnBoardDeviceExtendedTypeSATAController = 0x09,
+  OnBoardDeviceExtendedTypeSASController  = 0x0A
+} ONBOARD_DEVICE_EXTENDED_INFO_TYPE;
+
+///
+/// Onboard Devices Extended Information (Type 41).
+///
+/// The information in this structure defines the attributes of devices that 
+/// are onboard (soldered onto) a system element, usually the baseboard.  
+/// In general, an entry in this table implies that the BIOS has some level of 
+/// control over the enabling of the associated device for use by the system. 
+///
+typedef struct {
+  SMBIOS_STRUCTURE                  Hdr;
+  SMBIOS_TABLE_STRING               ReferenceDesignation;
+  UINT8                             DeviceType;             ///< The enumeration value from ONBOARD_DEVICE_EXTENDED_INFO_TYPE
+  UINT8                             DeviceTypeInstance;
+  UINT16                            SegmentGroupNum;
+  UINT8                             BusNum;
+  UINT8                             DevFuncNum;
+} SMBIOS_TABLE_TYPE41;
+
+///
+/// Management Controller Host Interface - Interface Types.
+/// 00h - 3Fh: MCTP Host Interfaces
+///
+typedef enum{
+  MCHostInterfaceTypeNetworkHostInterface       = 0x40,
+  MCHostInterfaceTypeOemDefined                 = 0xF0
+} MC_HOST_INTERFACE_TYPE;
+
+///
+/// Management Controller Host Interface - Protocol Types.
+///
+typedef enum{
+  MCHostInterfaceProtocolTypeIPMI               = 0x02,
+  MCHostInterfaceProtocolTypeMCTP               = 0x03,
+  MCHostInterfaceProtocolTypeRedfishOverIP      = 0x04,
+  MCHostInterfaceProtocolTypeOemDefined         = 0xF0
+} MC_HOST_INTERFACE_PROTOCOL_TYPE;
+
+///
+/// Management Controller Host Interface (Type 42).
+///
+/// The information in this structure defines the attributes of a Management
+/// Controller Host Interface that is not discoverable by "Plug and Play" mechanisms.
+///
+/// Type 42 should be used for management controller host interfaces that use protocols
+/// other than IPMI or that use multiple protocols on a single host interface type.
+///
+/// This structure should also be provided if IPMI is shared with other protocols
+/// over the same interface hardware. If IPMI is not shared with other protocols,
+/// either the Type 38 or Type 42 structures can be used. Providing Type 38 is
+/// recommended for backward compatibility. The structures are not required to
+/// be mutually exclusive. Type 38 and Type 42 structures may be implemented
+/// simultaneously to provide backward compatibility with IPMI applications or drivers
+/// that do not yet recognize the Type 42 structure.
+///
+typedef struct {
+  SMBIOS_STRUCTURE                  Hdr;
+  UINT8                             InterfaceType;          ///< The enumeration value from MC_HOST_INTERFACE_TYPE
+  UINT8                             MCHostInterfaceData[1]; ///< This field has a minimum of four bytes
+} SMBIOS_TABLE_TYPE42;
+
+///
+/// TPM Device (Type 43).
+///
+typedef struct {
+  SMBIOS_STRUCTURE                  Hdr;
+  UINT8                             VendorID[4];
+  UINT8                             MajorSpecVersion;
+  UINT8                             MinorSpecVersion;
+  UINT32                            FirmwareVersion1;
+  UINT32                            FirmwareVersion2;
+  SMBIOS_TABLE_STRING               Description;
+  UINT64                            Characteristics;
+  UINT32                            OemDefined;
+} SMBIOS_TABLE_TYPE43;
+
+///
+/// Inactive (Type 126)
+///
+typedef struct {
+  SMBIOS_STRUCTURE   Hdr;
+} SMBIOS_TABLE_TYPE126;
+
+///
+/// End-of-Table (Type 127)
+///
+typedef struct {
+  SMBIOS_STRUCTURE   Hdr;
+} SMBIOS_TABLE_TYPE127;
+
+///
+/// Union of all the possible SMBIOS record types.
+///
+typedef union {
+  SMBIOS_STRUCTURE      *Hdr;
+  SMBIOS_TABLE_TYPE0    *Type0;
+  SMBIOS_TABLE_TYPE1    *Type1;
+  SMBIOS_TABLE_TYPE2    *Type2;
+  SMBIOS_TABLE_TYPE3    *Type3;
+  SMBIOS_TABLE_TYPE4    *Type4;
+  SMBIOS_TABLE_TYPE5    *Type5;
+  SMBIOS_TABLE_TYPE6    *Type6;
+  SMBIOS_TABLE_TYPE7    *Type7;
+  SMBIOS_TABLE_TYPE8    *Type8;
+  SMBIOS_TABLE_TYPE9    *Type9;
+  SMBIOS_TABLE_TYPE10   *Type10;
+  SMBIOS_TABLE_TYPE11   *Type11;
+  SMBIOS_TABLE_TYPE12   *Type12;
+  SMBIOS_TABLE_TYPE13   *Type13;
+  SMBIOS_TABLE_TYPE14   *Type14;
+  SMBIOS_TABLE_TYPE15   *Type15;
+  SMBIOS_TABLE_TYPE16   *Type16;
+  SMBIOS_TABLE_TYPE17   *Type17;
+  SMBIOS_TABLE_TYPE18   *Type18;
+  SMBIOS_TABLE_TYPE19   *Type19;
+  SMBIOS_TABLE_TYPE20   *Type20;
+  SMBIOS_TABLE_TYPE21   *Type21;
+  SMBIOS_TABLE_TYPE22   *Type22;
+  SMBIOS_TABLE_TYPE23   *Type23;
+  SMBIOS_TABLE_TYPE24   *Type24;
+  SMBIOS_TABLE_TYPE25   *Type25;
+  SMBIOS_TABLE_TYPE26   *Type26;
+  SMBIOS_TABLE_TYPE27   *Type27;
+  SMBIOS_TABLE_TYPE28   *Type28;
+  SMBIOS_TABLE_TYPE29   *Type29;
+  SMBIOS_TABLE_TYPE30   *Type30;
+  SMBIOS_TABLE_TYPE31   *Type31;
+  SMBIOS_TABLE_TYPE32   *Type32;
+  SMBIOS_TABLE_TYPE33   *Type33;
+  SMBIOS_TABLE_TYPE34   *Type34;
+  SMBIOS_TABLE_TYPE35   *Type35;
+  SMBIOS_TABLE_TYPE36   *Type36;
+  SMBIOS_TABLE_TYPE37   *Type37;
+  SMBIOS_TABLE_TYPE38   *Type38;
+  SMBIOS_TABLE_TYPE39   *Type39;
+  SMBIOS_TABLE_TYPE40   *Type40;
+  SMBIOS_TABLE_TYPE41   *Type41;
+  SMBIOS_TABLE_TYPE42   *Type42;
+  SMBIOS_TABLE_TYPE43   *Type43;
+  SMBIOS_TABLE_TYPE126  *Type126;
+  SMBIOS_TABLE_TYPE127  *Type127;
+  UINT8                 *Raw;
+} SMBIOS_STRUCTURE_POINTER;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SmBus.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SmBus.h
new file mode 100644
index 0000000000..be6851800c
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SmBus.h
@@ -0,0 +1,81 @@
+/** @file
+  This file declares the SMBus definitions defined in SmBus Specifciation V2.0
+  and defined in PI1.0 specification volume 5.
+
+  Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+**/
+
+#ifndef _SMBUS_H_
+#define _SMBUS_H_
+
+
+///
+/// UDID of SMBUS device.
+///
+typedef struct {
+  UINT32  VendorSpecificId;
+  UINT16  SubsystemDeviceId;
+  UINT16  SubsystemVendorId;
+  UINT16  Interface;
+  UINT16  DeviceId;
+  UINT16  VendorId;
+  UINT8   VendorRevision;
+  UINT8   DeviceCapabilities;
+} EFI_SMBUS_UDID;
+
+///
+/// Smbus Device Address
+///
+typedef struct {
+  ///
+  /// The SMBUS hardware address to which the SMBUS device is preassigned or allocated.
+  ///
+  UINTN SmbusDeviceAddress : 7;
+} EFI_SMBUS_DEVICE_ADDRESS;
+
+typedef struct {
+  ///
+  /// The SMBUS hardware address to which the SMBUS device is preassigned or
+  /// allocated. Type EFI_SMBUS_DEVICE_ADDRESS is defined in EFI_PEI_SMBUS2_PPI.Execute().
+  ///
+  EFI_SMBUS_DEVICE_ADDRESS  SmbusDeviceAddress;
+  ///
+  /// The SMBUS Unique Device Identifier (UDID) as defined in EFI_SMBUS_UDID.
+  /// Type EFI_SMBUS_UDID is defined in EFI_PEI_SMBUS2_PPI.ArpDevice().
+  ///
+  EFI_SMBUS_UDID            SmbusDeviceUdid;
+} EFI_SMBUS_DEVICE_MAP;
+
+///
+/// Smbus Operations
+///
+typedef enum _EFI_SMBUS_OPERATION {
+  EfiSmbusQuickRead,
+  EfiSmbusQuickWrite,
+  EfiSmbusReceiveByte,
+  EfiSmbusSendByte,
+  EfiSmbusReadByte,
+  EfiSmbusWriteByte,
+  EfiSmbusReadWord,
+  EfiSmbusWriteWord,
+  EfiSmbusReadBlock,
+  EfiSmbusWriteBlock,
+  EfiSmbusProcessCall,
+  EfiSmbusBWBRProcessCall
+} EFI_SMBUS_OPERATION;
+
+///
+/// EFI_SMBUS_DEVICE_COMMAND
+///
+typedef UINTN   EFI_SMBUS_DEVICE_COMMAND;
+
+#endif
+
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/TcgPhysicalPresence.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/TcgPhysicalPresence.h
new file mode 100644
index 0000000000..23d7a09c44
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/TcgPhysicalPresence.h
@@ -0,0 +1,129 @@
+/** @file
+  TCG Physical Presence definition.
+
+Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials 
+are licensed and made available under the terms and conditions of the BSD License 
+which accompanies this distribution.  The full text of the license may be found at 
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _TCG_PHYSICAL_PRESENCE_H_
+#define _TCG_PHYSICAL_PRESENCE_H_
+
+//
+// TCG PP definition for physical presence ACPI function
+//
+#define TCG_ACPI_FUNCTION_GET_PHYSICAL_PRESENCE_INTERFACE_VERSION      1
+#define TCG_ACPI_FUNCTION_SUBMIT_REQUEST_TO_BIOS                       2
+#define TCG_ACPI_FUNCTION_GET_PENDING_REQUEST_BY_OS                    3
+#define TCG_ACPI_FUNCTION_GET_PLATFORM_ACTION_TO_TRANSITION_TO_BIOS    4
+#define TCG_ACPI_FUNCTION_RETURN_REQUEST_RESPONSE_TO_OS                5
+#define TCG_ACPI_FUNCTION_SUBMIT_PREFERRED_USER_LANGUAGE               6
+#define TCG_ACPI_FUNCTION_SUBMIT_REQUEST_TO_BIOS_2                     7
+#define TCG_ACPI_FUNCTION_GET_USER_CONFIRMATION_STATUS_FOR_REQUEST     8
+
+//
+// TCG PP definition for TPM Operation Response to OS Environment
+//
+#define TCG_PP_OPERATION_RESPONSE_SUCCESS              0x0
+#define TCG_PP_OPERATION_RESPONSE_USER_ABORT           0xFFFFFFF0
+#define TCG_PP_OPERATION_RESPONSE_BIOS_FAILURE         0xFFFFFFF1
+
+//
+// TCG PP definition of return code for Return TPM Operation Response to OS Environment
+//
+#define TCG_PP_RETURN_TPM_OPERATION_RESPONSE_SUCCESS                   0
+#define TCG_PP_RETURN_TPM_OPERATION_RESPONSE_FAILURE                   1
+
+//
+// TCG PP definition of return code for Submit TPM Request to Pre-OS Environment
+// and Submit TPM Request to Pre-OS Environment 2
+//
+#define TCG_PP_SUBMIT_REQUEST_TO_PREOS_SUCCESS                                  0
+#define TCG_PP_SUBMIT_REQUEST_TO_PREOS_NOT_IMPLEMENTED                          1
+#define TCG_PP_SUBMIT_REQUEST_TO_PREOS_GENERAL_FAILURE                          2
+#define TCG_PP_SUBMIT_REQUEST_TO_PREOS_BLOCKED_BY_BIOS_SETTINGS                 3
+
+//
+// TCG PP definition of return code for Get User Confirmation Status for Operation
+//
+#define TCG_PP_GET_USER_CONFIRMATION_NOT_IMPLEMENTED                                 0
+#define TCG_PP_GET_USER_CONFIRMATION_BIOS_ONLY                                       1
+#define TCG_PP_GET_USER_CONFIRMATION_BLOCKED_BY_BIOS_CONFIGURATION                   2
+#define TCG_PP_GET_USER_CONFIRMATION_ALLOWED_AND_PPUSER_REQUIRED                     3
+#define TCG_PP_GET_USER_CONFIRMATION_ALLOWED_AND_PPUSER_NOT_REQUIRED                 4
+
+//
+// TCG PP definition of physical presence operation actions for TPM12
+//
+#define TCG_PHYSICAL_PRESENCE_NO_ACTION                               0
+#define TCG_PHYSICAL_PRESENCE_ENABLE                                  1
+#define TCG_PHYSICAL_PRESENCE_DISABLE                                 2
+#define TCG_PHYSICAL_PRESENCE_ACTIVATE                                3
+#define TCG_PHYSICAL_PRESENCE_DEACTIVATE                              4 
+#define TCG_PHYSICAL_PRESENCE_CLEAR                                   5
+#define TCG_PHYSICAL_PRESENCE_ENABLE_ACTIVATE                         6
+#define TCG_PHYSICAL_PRESENCE_DEACTIVATE_DISABLE                      7
+#define TCG_PHYSICAL_PRESENCE_SET_OWNER_INSTALL_TRUE                  8
+#define TCG_PHYSICAL_PRESENCE_SET_OWNER_INSTALL_FALSE                 9
+#define TCG_PHYSICAL_PRESENCE_ENABLE_ACTIVATE_OWNER_TRUE              10
+#define TCG_PHYSICAL_PRESENCE_DEACTIVATE_DISABLE_OWNER_FALSE          11
+#define TCG_PHYSICAL_PRESENCE_DEFERRED_PP_UNOWNERED_FIELD_UPGRADE     12
+#define TCG_PHYSICAL_PRESENCE_SET_OPERATOR_AUTH                       13
+#define TCG_PHYSICAL_PRESENCE_CLEAR_ENABLE_ACTIVATE                   14
+#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_PROVISION_FALSE              15
+#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_PROVISION_TRUE               16
+#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_CLEAR_FALSE                  17
+#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_CLEAR_TRUE                   18
+#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_MAINTENANCE_FALSE            19
+#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_MAINTENANCE_TRUE             20
+#define TCG_PHYSICAL_PRESENCE_ENABLE_ACTIVATE_CLEAR                   21
+#define TCG_PHYSICAL_PRESENCE_ENABLE_ACTIVATE_CLEAR_ENABLE_ACTIVATE   22
+
+#define TCG_PHYSICAL_PRESENCE_VENDOR_SPECIFIC_OPERATION               128
+
+//
+// TCG PP definition of physical presence operation actions for TPM2
+//
+#define TCG2_PHYSICAL_PRESENCE_NO_ACTION                                         0
+#define TCG2_PHYSICAL_PRESENCE_ENABLE                                            1
+#define TCG2_PHYSICAL_PRESENCE_DISABLE                                           2
+#define TCG2_PHYSICAL_PRESENCE_CLEAR                                             5
+#define TCG2_PHYSICAL_PRESENCE_ENABLE_CLEAR                                      14
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CLEAR_TRUE                    17
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CLEAR_FALSE                   18
+#define TCG2_PHYSICAL_PRESENCE_ENABLE_CLEAR_2                                    21
+#define TCG2_PHYSICAL_PRESENCE_ENABLE_CLEAR_3                                    22
+#define TCG2_PHYSICAL_PRESENCE_SET_PCR_BANKS                                     23
+#define TCG2_PHYSICAL_PRESENCE_CHANGE_EPS                                        24
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CHANGE_PCRS_FALSE             25
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CHANGE_PCRS_TRUE              26
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_TURN_ON_FALSE                 27
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_TURN_ON_TRUE                  28
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_TURN_OFF_FALSE                29
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_TURN_OFF_TRUE                 30
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CHANGE_EPS_FALSE              31
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CHANGE_EPS_TRUE               32
+#define TCG2_PHYSICAL_PRESENCE_LOG_ALL_DIGESTS                                   33
+#define TCG2_PHYSICAL_PRESENCE_DISABLE_ENDORSEMENT_ENABLE_STORAGE_HIERARCHY      34
+#define TCG2_PHYSICAL_PRESENCE_NO_ACTION_MAX                                     34
+
+//
+// TCG PP definition of physical presence operation actions for storage management
+//
+#define TCG2_PHYSICAL_PRESENCE_STORAGE_MANAGEMENT_BEGIN                          96
+#define TCG2_PHYSICAL_PRESENCE_ENABLE_BLOCK_SID                                  96
+#define TCG2_PHYSICAL_PRESENCE_DISABLE_BLOCK_SID                                 97
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_FUNC_TRUE    98
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_FUNC_FALSE   99
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_FUNC_TRUE   100
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_FUNC_FALSE  101
+
+#define TCG2_PHYSICAL_PRESENCE_VENDOR_SPECIFIC_OPERATION                         128
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/TcgStorageCore.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/TcgStorageCore.h
new file mode 100644
index 0000000000..79954df5ad
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/TcgStorageCore.h
@@ -0,0 +1,394 @@
+/** @file
+  TCG defined values and structures.
+
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _TCG_STORAGE_CORE_H_
+#define _TCG_STORAGE_CORE_H_
+
+#include <Base.h>
+
+#pragma pack(1)
+
+/// UID in host native byte order
+typedef UINT64 TCG_UID;
+
+#define TCG_TO_UID(b0, b1, b2, b3, b4, b5, b6, b7) (TCG_UID)( \
+  (UINT64)(b0)         | \
+  ((UINT64)(b1) << 8)  | \
+  ((UINT64)(b2) << 16) | \
+  ((UINT64)(b3) << 24) | \
+  ((UINT64)(b4) << 32) | \
+  ((UINT64)(b5) << 40) | \
+  ((UINT64)(b6) << 48) | \
+  ((UINT64)(b7) << 56))
+
+typedef struct {
+  UINT32     ReservedBE;
+  UINT16     ComIDBE;
+  UINT16     ComIDExtensionBE;
+  UINT32     OutstandingDataBE;
+  UINT32     MinTransferBE;
+  UINT32     LengthBE;
+  UINT8      Payload[0];
+} TCG_COM_PACKET;
+
+typedef struct {
+  UINT32     TperSessionNumberBE;
+  UINT32     HostSessionNumberBE;
+  UINT32     SequenceNumberBE;
+  UINT16     ReservedBE;
+  UINT16     AckTypeBE;
+  UINT32     AcknowledgementBE;
+  UINT32     LengthBE;
+  UINT8      Payload[0];
+} TCG_PACKET;
+
+#define TCG_SUBPACKET_ALIGNMENT 4 // 4-byte alignment per spec
+
+typedef struct {
+  UINT8      ReservedBE[6];
+  UINT16     KindBE;
+  UINT32     LengthBE;
+  UINT8      Payload[0];
+} TCG_SUB_PACKET;
+
+#define SUBPACKET_KIND_DATA           0x0000
+#define SUBPACKET_KIND_CREDIT_CONTROL 0x8001
+
+#define TCG_ATOM_TYPE_INTEGER 0x0
+#define TCG_ATOM_TYPE_BYTE    0x1
+typedef struct {
+  UINT8   Data : 6;
+  UINT8   Sign : 1;
+  UINT8   IsZero : 1;
+} TCG_TINY_ATOM_BITS;
+
+typedef union {
+  UINT8               Raw;
+  TCG_TINY_ATOM_BITS  TinyAtomBits;
+} TCG_SIMPLE_TOKEN_TINY_ATOM;
+
+
+typedef struct {
+  UINT8   Length : 4;
+  UINT8   SignOrCont : 1;
+  UINT8   ByteOrInt : 1;
+  UINT8   IsZero : 1;
+  UINT8   IsOne : 1;
+} TCG_SHORT_ATOM_BITS;
+
+typedef union {
+  UINT8                 RawHeader;
+  TCG_SHORT_ATOM_BITS   ShortAtomBits;
+} TCG_SIMPLE_TOKEN_SHORT_ATOM;
+
+
+#define TCG_MEDIUM_ATOM_LENGTH_HIGH_SHIFT 0x8
+#define TCG_MEDIUM_ATOM_LENGTH_HIGH_MASK  0x7
+
+typedef struct {
+  UINT8  LengthHigh : 3;
+  UINT8  SignOrCont : 1;
+  UINT8  ByteOrInt : 1;
+  UINT8  IsZero : 1;
+  UINT8  IsOne1 : 1;
+  UINT8  IsOne2 : 1;
+  UINT8  LengthLow;
+} TCG_MEDIUM_ATOM_BITS;
+
+typedef union {
+  UINT16                RawHeader;
+  TCG_MEDIUM_ATOM_BITS  MediumAtomBits;
+} TCG_SIMPLE_TOKEN_MEDIUM_ATOM;
+
+
+#define TCG_LONG_ATOM_LENGTH_HIGH_SHIFT 16
+#define TCG_LONG_ATOM_LENGTH_MID_SHIFT  8
+
+typedef  struct {
+  UINT8   SignOrCont : 1;
+  UINT8   ByteOrInt : 1;
+  UINT8   Reserved : 2;
+  UINT8   IsZero : 1;
+  UINT8   IsOne1 : 1;
+  UINT8   IsOne2 : 1;
+  UINT8   IsOne3 : 1;
+  UINT8   LengthHigh;
+  UINT8   LengthMid;
+  UINT8   LengthLow;
+} TCG_LONG_ATOM_BITS;
+
+typedef union {
+  UINT32              RawHeader;
+  TCG_LONG_ATOM_BITS  LongAtomBits;
+} TCG_SIMPLE_TOKEN_LONG_ATOM;
+
+
+// TCG Core Spec v2 - Table 04 - Token Types
+typedef enum {
+  TcgTokenTypeReserved,
+  TcgTokenTypeTinyAtom,
+  TcgTokenTypeShortAtom,
+  TcgTokenTypeMediumAtom,
+  TcgTokenTypeLongAtom,
+  TcgTokenTypeStartList,
+  TcgTokenTypeEndList,
+  TcgTokenTypeStartName,
+  TcgTokenTypeEndName,
+  TcgTokenTypeCall,
+  TcgTokenTypeEndOfData,
+  TcgTokenTypeEndOfSession,
+  TcgTokenTypeStartTransaction,
+  TcgTokenTypeEndTransaction,
+  TcgTokenTypeEmptyAtom,
+} TCG_TOKEN_TYPE;
+
+#pragma pack()
+
+#define TCG_TOKEN_SHORTATOM_MAX_BYTE_SIZE   0x0F
+#define TCG_TOKEN_MEDIUMATOM_MAX_BYTE_SIZE  0x7FF
+#define TCG_TOKEN_LONGATOM_MAX_BYTE_SIZE    0xFFFFFF
+
+#define TCG_TOKEN_TINYATOM_UNSIGNED_MAX_VALUE 0x3F
+#define TCG_TOKEN_TINYATOM_SIGNED_MAX_VALUE   0x1F
+#define TCG_TOKEN_TINYATOM_SIGNED_MIN_VALUE   -32
+
+// TOKEN TYPES
+#define TCG_TOKEN_TINYATOM          0x00
+#define TCG_TOKEN_TINYSIGNEDATOM    0x40
+#define TCG_TOKEN_SHORTATOM         0x80
+#define TCG_TOKEN_SHORTSIGNEDATOM   0x90
+#define TCG_TOKEN_SHORTBYTESATOM    0xA0
+#define TCG_TOKEN_MEDIUMATOM        0xC0
+#define TCG_TOKEN_MEDIUMSIGNEDATOM  0xC8
+#define TCG_TOKEN_MEDIUMBYTESATOM   0xD0
+#define TCG_TOKEN_LONGATOM          0xE0
+#define TCG_TOKEN_LONGSIGNEDATOM    0xE1
+#define TCG_TOKEN_LONGBYTESATOM     0xE2
+#define TCG_TOKEN_STARTLIST         0xF0
+#define TCG_TOKEN_ENDLIST           0xF1
+#define TCG_TOKEN_STARTNAME         0xF2
+#define TCG_TOKEN_ENDNAME           0xF3
+// 0xF4 - 0xF7 TCG Reserved
+#define TCG_TOKEN_CALL              0xF8
+#define TCG_TOKEN_ENDDATA           0xF9
+#define TCG_TOKEN_ENDSESSION        0xFA
+#define TCG_TOKEN_STARTTRANSACTION  0xFB
+#define TCG_TOKEN_ENDTRANSACTION    0xFC
+// 0xFD - 0xFE TCG Reserved
+#define TCG_TOKEN_EMPTY             0xFF
+
+// CELLBLOCK reserved Names
+#define TCG_CELL_BLOCK_TABLE_NAME           (UINT8)0x00
+#define TCG_CELL_BLOCK_START_ROW_NAME       (UINT8)0x01
+#define TCG_CELL_BLOCK_END_ROW_NAME         (UINT8)0x02
+#define TCG_CELL_BLOCK_START_COLUMN_NAME    (UINT8)0x03
+#define TCG_CELL_BLOCK_END_COLUMN_NAME      (UINT8)0x04
+
+// METHOD STATUS CODES
+#define TCG_METHOD_STATUS_CODE_SUCCESS                  0x00
+#define TCG_METHOD_STATUS_CODE_NOT_AUTHORIZED           0x01
+#define TCG_METHOD_STATUS_CODE_OBSOLETE                 0x02
+#define TCG_METHOD_STATUS_CODE_SP_BUSY                  0x03
+#define TCG_METHOD_STATUS_CODE_SP_FAILED                0x04
+#define TCG_METHOD_STATUS_CODE_SP_DISABLED              0x05
+#define TCG_METHOD_STATUS_CODE_SP_FROZEN                0x06
+#define TCG_METHOD_STATUS_CODE_NO_SESSIONS_AVAILABLE    0x07
+#define TCG_METHOD_STATUS_CODE_UNIQUENESS_CONFLICT      0x08
+#define TCG_METHOD_STATUS_CODE_INSUFFICIENT_SPACE       0x09
+#define TCG_METHOD_STATUS_CODE_INSUFFICIENT_ROWS        0x0A
+#define TCG_METHOD_STATUS_CODE_INVALID_PARAMETER        0x0C
+#define TCG_METHOD_STATUS_CODE_OBSOLETE2                0x0D
+#define TCG_METHOD_STATUS_CODE_OBSOLETE3                0x0E
+#define TCG_METHOD_STATUS_CODE_TPER_MALFUNCTION         0x0F
+#define TCG_METHOD_STATUS_CODE_TRANSACTION_FAILURE      0x10
+#define TCG_METHOD_STATUS_CODE_RESPONSE_OVERFLOW        0x11
+#define TCG_METHOD_STATUS_CODE_AUTHORITY_LOCKED_OUT     0x12
+#define TCG_METHOD_STATUS_CODE_FAIL                     0x3F
+
+
+// Feature Codes
+#define TCG_FEATURE_INVALID             (UINT16)0x0000
+#define TCG_FEATURE_TPER                (UINT16)0x0001
+#define TCG_FEATURE_LOCKING             (UINT16)0x0002
+#define TCG_FEATURE_GEOMETRY_REPORTING  (UINT16)0x0003
+#define TCG_FEATURE_SINGLE_USER_MODE    (UINT16)0x0201
+#define TCG_FEATURE_DATASTORE_TABLE     (UINT16)0x0202
+#define TCG_FEATURE_OPAL_SSC_V1_0_0     (UINT16)0x0200
+#define TCG_FEATURE_OPAL_SSC_V2_0_0     (UINT16)0x0203
+#define TCG_FEATURE_OPAL_SSC_LITE       (UINT16)0x0301
+#define TCG_FEATURE_PYRITE_SSC          (UINT16)0x0302
+#define TCG_FEATURE_BLOCK_SID           (UINT16)0x0402
+
+// ACE Expression values
+#define TCG_ACE_EXPRESSION_AND 0x0
+#define TCG_ACE_EXPRESSION_OR  0x1
+
+/****************************************************************************
+TRUSTED RECEIVE - supported security protocols list (SP_Specific = 0000h)
+ATA 8 Rev6a Table 68 7.57.6.2
+****************************************************************************/
+// Security Protocol IDs
+#define TCG_SECURITY_PROTOCOL_INFO                   0x00
+#define TCG_OPAL_SECURITY_PROTOCOL_1                 0x01
+#define TCG_OPAL_SECURITY_PROTOCOL_2                 0x02
+#define TCG_SECURITY_PROTOCOL_TCG3                   0x03
+#define TCG_SECURITY_PROTOCOL_TCG4                   0x04
+#define TCG_SECURITY_PROTOCOL_TCG5                   0x05
+#define TCG_SECURITY_PROTOCOL_TCG6                   0x06
+#define TCG_SECURITY_PROTOCOL_CBCS                   0x07
+#define TCG_SECURITY_PROTOCOL_TAPE_DATA              0x20
+#define TCG_SECURITY_PROTOCOL_DATA_ENCRYPT_CONFIG    0x21
+#define TCG_SECURITY_PROTOCOL_SA_CREATION_CAPS       0x40
+#define TCG_SECURITY_PROTOCOL_IKEV2_SCSI             0x41
+#define TCG_SECURITY_PROTOCOL_JEDEC_UFS              0xEC
+#define TCG_SECURITY_PROTOCOL_SDCARD_SECURITY        0xED
+#define TCG_SECURITY_PROTOCOL_IEEE_1667              0xEE
+#define TCG_SECURITY_PROTOCOL_ATA_DEVICE_SERVER_PASS 0xEF
+
+// Security Protocol Specific IDs
+#define TCG_SP_SPECIFIC_PROTOCOL_LIST               0x0000
+#define TCG_SP_SPECIFIC_PROTOCOL_LEVEL0_DISCOVERY   0x0001
+
+#define TCG_RESERVED_COMID 0x0000
+
+// Defined in TCG Storage Feature Set:Block SID Authentication spec,
+// ComId used for BlockSid command is hardcode 0x0005.
+#define TCG_BLOCKSID_COMID 0x0005
+
+#pragma pack(1)
+typedef struct {
+  UINT8   Reserved[6];
+  UINT16  ListLength_BE;  // 6 - 7
+  UINT8   List[504];      // 8...
+} TCG_SUPPORTED_SECURITY_PROTOCOLS;
+
+
+// Level 0 Discovery
+typedef struct {
+  UINT32 LengthBE;    // number of valid bytes in discovery response, not including length field
+  UINT16 VerMajorBE;
+  UINT16 VerMinorBE;
+  UINT8  Reserved[8];
+  UINT8  VendorUnique[32];
+} TCG_LEVEL0_DISCOVERY_HEADER;
+
+typedef struct _TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER {
+  UINT16 FeatureCode_BE;
+  UINT8  Reserved : 4;
+  UINT8  Version : 4;
+  UINT8  Length;     // length of feature dependent data in bytes
+} TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER;
+
+
+typedef struct {
+  TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+  UINT8                                LockingSupported : 1;
+  UINT8                                LockingEnabled : 1;   // means the locking security provider (SP) is enabled
+  UINT8                                Locked : 1;   // means at least 1 locking range is enabled
+  UINT8                                MediaEncryption : 1;
+  UINT8                                MbrEnabled : 1;
+  UINT8                                MbrDone : 1;
+  UINT8                                Reserved : 2;
+  UINT8                                Reserved515[11];
+} TCG_LOCKING_FEATURE_DESCRIPTOR;
+
+typedef struct {
+  TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+  UINT8                                SIDValueState : 1;
+  UINT8                                SIDBlockedState : 1;
+  UINT8                                Reserved4 : 6;
+  UINT8                                HardwareReset : 1;
+  UINT8                                Reserved5 : 7;
+  UINT8                                Reserved615[10];
+} TCG_BLOCK_SID_FEATURE_DESCRIPTOR;
+
+
+typedef struct {
+  TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+  UINT8                                SyncSupported : 1;
+  UINT8                                AsyncSupported : 1;
+  UINT8                                AckNakSupported : 1;
+  UINT8                                BufferMgmtSupported : 1;
+  UINT8                                StreamingSupported : 1;
+  UINT8                                Reserved4b5 : 1;
+  UINT8                                ComIdMgmtSupported : 1;
+  UINT8                                Reserved4b7 : 1;
+  UINT8                                Reserved515[11];
+} TCG_TPER_FEATURE_DESCRIPTOR;
+
+#pragma pack()
+
+// Special Purpose UIDs
+#define TCG_UID_NULL                            TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00)
+#define TCG_UID_THIS_SP                         TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01)
+#define TCG_UID_SMUID                           TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF)
+
+// Session Manager Method UIDS
+#define TCG_UID_SM_PROPERTIES                   TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01)
+#define TCG_UID_SM_START_SESSION                TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x02)
+#define TCG_UID_SM_SYNC_SESSION                 TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x03)
+#define TCG_UID_SM_START_TRUSTED_SESSION        TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x04)
+#define TCG_UID_SM_SYNC_TRUSTED_SESSION         TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x05)
+#define TCG_UID_SM_CLOSE_SESSION                TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x06)
+
+// MethodID UIDs
+#define TCG_UID_METHOD_DELETE_SP                TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x01)
+#define TCG_UID_METHOD_CREATE_TABLE             TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02)
+#define TCG_UID_METHOD_DELETE                   TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x03)
+#define TCG_UID_METHOD_CREATE_ROW               TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x04)
+#define TCG_UID_METHOD_DELETE_ROW               TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x05)
+#define TCG_UID_METHOD_NEXT                     TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x08)
+#define TCG_UID_METHOD_GET_FREE_SPACE           TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x09)
+#define TCG_UID_METHOD_GET_FREE_ROWS            TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0A)
+#define TCG_UID_METHOD_DELETE_METHOD            TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0B)
+#define TCG_UID_METHOD_GET_ACL                  TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0D)
+#define TCG_UID_METHOD_ADD_ACE                  TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0E)
+#define TCG_UID_METHOD_REMOVE_ACE               TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0F)
+#define TCG_UID_METHOD_GEN_KEY                  TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x10)
+#define TCG_UID_METHOD_GET_PACKAGE              TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x12)
+#define TCG_UID_METHOD_SET_PACKAGE              TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x13)
+#define TCG_UID_METHOD_GET                      TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x16)
+#define TCG_UID_METHOD_SET                      TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x17)
+#define TCG_UID_METHOD_AUTHENTICATE             TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x1C)
+#define TCG_UID_METHOD_ISSUE_SP                 TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x01)
+#define TCG_UID_METHOD_GET_CLOCK                TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x01)
+#define TCG_UID_METHOD_RESET_CLOCK              TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x02)
+#define TCG_UID_METHOD_SET_CLOCK_HIGH           TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x03)
+#define TCG_UID_METHOD_SET_LAG_HIGH             TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x04)
+#define TCG_UID_METHOD_SET_CLOCK_LOW            TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x05)
+#define TCG_UID_METHOD_SET_LAG_LOW              TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x06)
+#define TCG_UID_METHOD_INCREMENT_COUNTER        TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x07)
+#define TCG_UID_METHOD_RANDOM                   TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x01)
+#define TCG_UID_METHOD_SALT                     TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x02)
+#define TCG_UID_METHOD_DECRYPT_INIT             TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x03)
+#define TCG_UID_METHOD_DECRYPT                  TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x04)
+#define TCG_UID_METHOD_DECRYPT_FINALIZE         TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x05)
+#define TCG_UID_METHOD_ENCRYPT_INIT             TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x06)
+#define TCG_UID_METHOD_ENCRYPT                  TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x07)
+#define TCG_UID_METHOD_ENCRYPT_FINALIZE         TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x08)
+#define TCG_UID_METHOD_HMAC_INIT                TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x09)
+#define TCG_UID_METHOD_HMAC                     TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0A)
+#define TCG_UID_METHOD_HMAC_FINALIZE            TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0B)
+#define TCG_UID_METHOD_HASH_INIT                TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0C)
+#define TCG_UID_METHOD_HASH                     TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0D)
+#define TCG_UID_METHOD_HASH_FINALIZE            TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0E)
+#define TCG_UID_METHOD_SIGN                     TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0F)
+#define TCG_UID_METHOD_VERIFY                   TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x10)
+#define TCG_UID_METHOD_XOR                      TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x11)
+#define TCG_UID_METHOD_ADD_LOG                  TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x01)
+#define TCG_UID_METHOD_CREATE_LOG               TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x02)
+#define TCG_UID_METHOD_CLEAR_LOG                TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x03)
+#define TCG_UID_METHOD_FLUSH_LOG                TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x04)
+
+#endif // TCG_H_
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/TcgStorageOpal.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/TcgStorageOpal.h
new file mode 100644
index 0000000000..1f32b7ecca
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/TcgStorageOpal.h
@@ -0,0 +1,181 @@
+/** @file
+  Opal Specification defined values and structures.
+
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _TCG_STORAGE_OPAL_H_
+#define _TCG_STORAGE_OPAL_H_
+
+#include <IndustryStandard/TcgStorageCore.h>
+
+#define OPAL_UID_ADMIN_SP                   TCG_TO_UID(0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x01)
+#define OPAL_UID_ADMIN_SP_C_PIN_MSID        TCG_TO_UID(0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x84, 0x02)
+#define OPAL_UID_ADMIN_SP_C_PIN_SID         TCG_TO_UID(0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x01)
+#define OPAL_UID_LOCKING_SP                 TCG_TO_UID(0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x02)
+
+// ADMIN_SP
+// Authorities
+#define OPAL_ADMIN_SP_ANYBODY_AUTHORITY     TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x01)
+#define OPAL_ADMIN_SP_ADMINS_AUTHORITY      TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02)
+#define OPAL_ADMIN_SP_MAKERS_AUTHORITY      TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x03)
+#define OPAL_ADMIN_SP_SID_AUTHORITY         TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x06)
+#define OPAL_ADMIN_SP_ADMIN1_AUTHORITY      TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x02, 0x01)
+#define OPAL_ADMIN_SP_PSID_AUTHORITY        TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x01, 0xFF, 0x01)
+
+#define OPAL_ADMIN_SP_ACTIVATE_METHOD       TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x03)
+#define OPAL_ADMIN_SP_REVERT_METHOD         TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x02)
+
+
+// LOCKING SP
+// Authorities
+#define OPAL_LOCKING_SP_ANYBODY_AUTHORITY   TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x01)
+#define OPAL_LOCKING_SP_ADMINS_AUTHORITY    TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02)
+#define OPAL_LOCKING_SP_ADMIN1_AUTHORITY    TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x01, 0x00, 0x01)
+#define OPAL_LOCKING_SP_USERS_AUTHORITY     TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x03, 0x00, 0x00)
+#define OPAL_LOCKING_SP_USER1_AUTHORITY     TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x03, 0x00, 0x01)
+
+#define OPAL_LOCKING_SP_REVERTSP_METHOD     TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x11)
+
+// C_PIN Table Rows
+#define OPAL_LOCKING_SP_C_PIN_ADMIN1        TCG_TO_UID( 0x00, 0x00, 0x00, 0x0B, 0x00, 0x01, 0x00, 0x01 )
+#define OPAL_LOCKING_SP_C_PIN_USER1         TCG_TO_UID( 0x00, 0x00, 0x00, 0x0B, 0x00, 0x03, 0x00, 0x01 )
+
+// Locking Table
+#define OPAL_LOCKING_SP_LOCKING_GLOBALRANGE TCG_TO_UID( 0x00, 0x00, 0x08, 0x02, 0x00, 0x00, 0x00, 0x01 )
+#define OPAL_LOCKING_SP_LOCKING_RANGE1      TCG_TO_UID( 0x00, 0x00, 0x08, 0x02, 0x00, 0x03, 0x00, 0x01 )
+
+
+// LOCKING SP ACE Table Preconfiguration
+#define OPAL_LOCKING_SP_ACE_LOCKING_GLOBALRANGE_GET_ALL      TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xD0, 0x00 )
+#define OPAL_LOCKING_SP_ACE_LOCKING_GLOBALRANGE_SET_RDLOCKED TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xE0, 0x00 )
+#define OPAL_LOCKING_SP_ACE_LOCKING_GLOBALRANGE_SET_WRLOCKED TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xE8, 0x00 )
+
+#define OPAL_LOCKING_SP_ACE_K_AES_256_GLOBALRANGE_GENKEY TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xB8, 0x00 )
+#define OPAL_LOCKING_SP_ACE_K_AES_128_GLOBALRANGE_GENKEY TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xB0, 0x00 )
+
+
+// LOCKING SP LockingInfo Table Preconfiguration
+#define OPAL_LOCKING_SP_LOCKING_INFO TCG_TO_UID( 0x00, 0x00, 0x08, 0x01, 0x00, 0x00, 0x00, 0x01 )
+
+#define OPAL_LOCKING_SP_LOCKINGINFO_ALIGNMENTREQUIRED_COL       0x7
+#define OPAL_LOCKING_SP_LOCKINGINFO_LOGICALBLOCKSIZE_COL        0x8
+#define OPAL_LOCKING_SP_LOCKINGINFO_ALIGNMENTGRANULARITY_COL    0x9
+#define OPAL_LOCKING_SP_LOCKINGINFO_LOWESTALIGNEDLBA_COL        0xA
+
+// K_AES_256 Table Preconfiguration
+#define OPAL_LOCKING_SP_K_AES_256_GLOBALRANGE_KEY TCG_TO_UID( 0x00, 0x00, 0x08, 0x06, 0x00, 0x00, 0x00, 0x01 )
+
+// K_AES_128 Table Preconfiguration
+#define OPAL_LOCKING_SP_K_AES_128_GLOBALRANGE_KEY TCG_TO_UID( 0x00, 0x00, 0x08, 0x05, 0x00, 0x00, 0x00, 0x01 )
+
+// Minimum Properties that an Opal Compliant SD Shall support
+#define OPAL_MIN_MAX_COM_PACKET_SIZE            2048
+#define OPAL_MIN_MAX_REPONSE_COM_PACKET_SIZE    2048
+#define OPAL_MIN_MAX_PACKET_SIZE                2028
+#define OPAL_MIN_MAX_IND_TOKEN_SIZE             1992
+#define OPAL_MIN_MAX_PACKETS                    1
+#define OPAL_MIN_MAX_SUBPACKETS                 1
+#define OPAL_MIN_MAX_METHODS                    1
+#define OPAL_MIN_MAX_SESSIONS                   1
+#define OPAL_MIN_MAX_AUTHENTICATIONS            2
+#define OPAL_MIN_MAX_TRANSACTION_LIMIT          1
+
+#define OPAL_ADMIN_SP_PIN_COL  3
+#define OPAL_LOCKING_SP_C_PIN_TRYLIMIT_COL 5
+#define OPAL_RANDOM_METHOD_MAX_COUNT_SIZE 32
+
+#pragma pack(1)
+
+typedef struct _OPAL_GEOMETRY_REPORTING_FEATURE {
+  TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+  UINT8                                Reserved[8];
+  UINT32                               LogicalBlockSizeBE;
+  UINT64                               AlignmentGranularityBE;
+  UINT64                               LowestAlignedLBABE;
+} OPAL_GEOMETRY_REPORTING_FEATURE;
+
+typedef struct _OPAL_SINGLE_USER_MODE_FEATURE  {
+  TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+  UINT32                               NumLockingObjectsSupportedBE;
+  UINT8                                Any : 1;
+  UINT8                                All : 1;
+  UINT8                                Policy : 1;
+  UINT8                                Reserved : 5;
+  UINT8                                Reserved2[7];
+} OPAL_SINGLE_USER_MODE_FEATURE;
+
+typedef struct _OPAL_DATASTORE_TABLE_FEATURE {
+  TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+  UINT16                               Reserved;
+  UINT16                               MaxNumTablesBE;
+  UINT32                               MaxTotalSizeBE;
+  UINT32                               SizeAlignmentBE;
+} OPAL_DATASTORE_TABLE_FEATURE;
+
+typedef struct _OPAL_SSCV1_FEATURE_DESCRIPTOR {
+  TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+  UINT16                               BaseComdIdBE;
+  UINT16                               NumComIdsBE;
+  UINT8                                RangeCrossing : 1;
+  UINT8                                Reserved : 7;
+  UINT8                                Future[11];
+} OPAL_SSCV1_FEATURE_DESCRIPTOR;
+
+typedef struct _OPAL_SSCV2_FEATURE_DESCRIPTOR {
+  TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+  UINT16                               BaseComdIdBE;
+  UINT16                               NumComIdsBE;
+  UINT8                                Reserved;
+  UINT16                               NumLockingSpAdminAuthoritiesSupportedBE;
+  UINT16                               NumLockingSpUserAuthoritiesSupportedBE;
+  UINT8                                InitialCPINSIDPIN;
+  UINT8                                CPINSIDPINRevertBehavior;
+  UINT8                                Future[5];
+} OPAL_SSCV2_FEATURE_DESCRIPTOR;
+
+typedef struct _OPAL_SSCLITE_FEATURE_DESCRIPTOR {
+  TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+  UINT16                               BaseComdIdBE;
+  UINT16                               NumComIdsBE;
+  UINT8                                Reserved[5];
+  UINT8                                InitialCPINSIDPIN;
+  UINT8                                CPINSIDPINRevertBehavior;
+  UINT8                                Future[5];
+} OPAL_SSCLITE_FEATURE_DESCRIPTOR;
+
+typedef struct _PYRITE_SSC_FEATURE_DESCRIPTOR {
+  TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+  UINT16                               BaseComdIdBE;
+  UINT16                               NumComIdsBE;
+  UINT8                                Reserved[5];
+  UINT8                                InitialCPINSIDPIN;
+  UINT8                                CPINSIDPINRevertBehavior;
+  UINT8                                Future[5];
+} PYRITE_SSC_FEATURE_DESCRIPTOR;
+
+typedef union {
+  TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER     CommonHeader;
+  TCG_TPER_FEATURE_DESCRIPTOR              Tper;
+  TCG_LOCKING_FEATURE_DESCRIPTOR           Locking;
+  OPAL_GEOMETRY_REPORTING_FEATURE          Geometry;
+  OPAL_SINGLE_USER_MODE_FEATURE            SingleUser;
+  OPAL_DATASTORE_TABLE_FEATURE             DataStore;
+  OPAL_SSCV1_FEATURE_DESCRIPTOR            OpalSscV1;
+  OPAL_SSCV2_FEATURE_DESCRIPTOR            OpalSscV2;
+  OPAL_SSCLITE_FEATURE_DESCRIPTOR          OpalSscLite;
+  PYRITE_SSC_FEATURE_DESCRIPTOR            PyriteSsc;
+  TCG_BLOCK_SID_FEATURE_DESCRIPTOR         BlockSid;
+} OPAL_LEVEL0_FEATURE_DESCRIPTOR;
+
+#pragma pack()
+
+#endif // _OPAL_H_
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/TcpaAcpi.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/TcpaAcpi.h
new file mode 100644
index 0000000000..fde31ab8b2
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/TcpaAcpi.h
@@ -0,0 +1,58 @@
+/** @file
+  TCPA ACPI table definition.
+
+Copyright (c) 2013, Intel Corporation. All rights reserved. <BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _TCPA_ACPI_H_
+#define _TCPA_ACPI_H_
+
+#include <IndustryStandard/Acpi.h>
+
+#pragma pack (1)
+
+typedef struct _EFI_TCG_CLIENT_ACPI_TABLE {
+  EFI_ACPI_DESCRIPTION_HEADER       Header;
+  UINT16                            PlatformClass;
+  UINT32                            Laml;
+  UINT64                            Lasa;
+} EFI_TCG_CLIENT_ACPI_TABLE;
+
+typedef struct _EFI_TCG_SERVER_ACPI_TABLE {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  UINT16                                  PlatformClass;
+  UINT16                                  Reserved0;
+  UINT64                                  Laml;
+  UINT64                                  Lasa;
+  UINT16                                  SpecRev;
+  UINT8                                   DeviceFlags;
+  UINT8                                   InterruptFlags;
+  UINT8                                   Gpe;
+  UINT8                                   Reserved1[3];
+  UINT32                                  GlobalSysInt;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  BaseAddress;
+  UINT32                                  Reserved2;
+  EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE  ConfigAddress;
+  UINT8                                   PciSegNum;
+  UINT8                                   PciBusNum;
+  UINT8                                   PciDevNum;
+  UINT8                                   PciFuncNum;
+} EFI_TCG_SERVER_ACPI_TABLE;
+
+//
+// TCG Platform Type based on TCG ACPI Specification Version 1.00
+//
+#define TCG_PLATFORM_TYPE_CLIENT   0
+#define TCG_PLATFORM_TYPE_SERVER   1
+
+#pragma pack ()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tls1.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tls1.h
new file mode 100644
index 0000000000..af7eb428af
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tls1.h
@@ -0,0 +1,93 @@
+/** @file
+  Transport Layer Security  -- TLS 1.0/1.1/1.2 Standard definitions, from RFC 2246/4346/5246
+
+  This file contains common TLS 1.0/1.1/1.2 definitions from RFC 2246/4346/5246
+
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#ifndef __TLS_1_H__
+#define __TLS_1_H__
+
+#pragma pack(1)
+
+///
+/// TLS Cipher Suite, refers to A.5 of rfc-2246, rfc-4346 and rfc-5246.
+///
+#define TLS_RSA_WITH_NULL_MD5                    {0x00, 0x01}
+#define TLS_RSA_WITH_NULL_SHA                    {0x00, 0x02}
+#define TLS_RSA_WITH_RC4_128_MD5                 {0x00, 0x04}
+#define TLS_RSA_WITH_RC4_128_SHA                 {0x00, 0x05}
+#define TLS_RSA_WITH_IDEA_CBC_SHA                {0x00, 0x07}
+#define TLS_RSA_WITH_DES_CBC_SHA                 {0x00, 0x09}
+#define TLS_RSA_WITH_3DES_EDE_CBC_SHA            {0x00, 0x0A}
+#define TLS_DH_DSS_WITH_DES_CBC_SHA              {0x00, 0x0C}
+#define TLS_DH_DSS_WITH_3DES_EDE_CBC_SHA         {0x00, 0x0D}
+#define TLS_DH_RSA_WITH_DES_CBC_SHA              {0x00, 0x0F}
+#define TLS_DH_RSA_WITH_3DES_EDE_CBC_SHA         {0x00, 0x10}
+#define TLS_DHE_DSS_WITH_DES_CBC_SHA             {0x00, 0x12}
+#define TLS_DHE_DSS_WITH_3DES_EDE_CBC_SHA        {0x00, 0x13}
+#define TLS_DHE_RSA_WITH_DES_CBC_SHA             {0x00, 0x15}
+#define TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA        {0x00, 0x16}
+#define TLS_RSA_WITH_AES_128_CBC_SHA             {0x00, 0x2F}
+#define TLS_DH_DSS_WITH_AES_128_CBC_SHA          {0x00, 0x30}
+#define TLS_DH_RSA_WITH_AES_128_CBC_SHA          {0x00, 0x31}
+#define TLS_DHE_DSS_WITH_AES_128_CBC_SHA         {0x00, 0x32}
+#define TLS_DHE_RSA_WITH_AES_128_CBC_SHA         {0x00, 0x33}
+#define TLS_RSA_WITH_AES_256_CBC_SHA             {0x00, 0x35}
+#define TLS_DH_DSS_WITH_AES_256_CBC_SHA          {0x00, 0x36}
+#define TLS_DH_RSA_WITH_AES_256_CBC_SHA          {0x00, 0x37}
+#define TLS_DHE_DSS_WITH_AES_256_CBC_SHA         {0x00, 0x38}
+#define TLS_DHE_RSA_WITH_AES_256_CBC_SHA         {0x00, 0x39}
+#define TLS_RSA_WITH_NULL_SHA256                 {0x00, 0x3B}
+#define TLS_RSA_WITH_AES_128_CBC_SHA256          {0x00, 0x3C}
+#define TLS_RSA_WITH_AES_256_CBC_SHA256          {0x00, 0x3D}
+#define TLS_DH_DSS_WITH_AES_128_CBC_SHA256       {0x00, 0x3E}
+#define TLS_DH_RSA_WITH_AES_128_CBC_SHA256       {0x00, 0x3F}
+#define TLS_DHE_DSS_WITH_AES_128_CBC_SHA256      {0x00, 0x40}
+#define TLS_DHE_RSA_WITH_AES_128_CBC_SHA256      {0x00, 0x67}
+#define TLS_DH_DSS_WITH_AES_256_CBC_SHA256       {0x00, 0x68}
+#define TLS_DH_RSA_WITH_AES_256_CBC_SHA256       {0x00, 0x69}
+#define TLS_DHE_DSS_WITH_AES_256_CBC_SHA256      {0x00, 0x6A}
+#define TLS_DHE_RSA_WITH_AES_256_CBC_SHA256      {0x00, 0x6B}
+
+///
+/// TLS Version, refers to A.1 of rfc-2246, rfc-4346 and rfc-5246.
+///
+#define TLS10_PROTOCOL_VERSION_MAJOR  0x03
+#define TLS10_PROTOCOL_VERSION_MINOR  0x01
+#define TLS11_PROTOCOL_VERSION_MAJOR  0x03
+#define TLS11_PROTOCOL_VERSION_MINOR  0x02
+#define TLS12_PROTOCOL_VERSION_MAJOR  0x03
+#define TLS12_PROTOCOL_VERSION_MINOR  0x03
+
+///
+/// TLS Content Type, refers to A.1 of rfc-2246, rfc-4346 and rfc-5246.
+///
+typedef enum {
+  TlsContentTypeChangeCipherSpec = 20,
+  TlsContentTypeAlert            = 21,
+  TlsContentTypeHandshake        = 22,
+  TlsContentTypeApplicationData  = 23,
+} TLS_CONTENT_TYPE;
+
+///
+/// TLS Record Header, refers to A.1 of rfc-2246, rfc-4346 and rfc-5246.
+///
+typedef struct {
+  UINT8                   ContentType;
+  EFI_TLS_VERSION         Version;
+  UINT16                  Length;
+} TLS_RECORD_HEADER;
+
+#pragma pack()
+
+#endif
+
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tpm12.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tpm12.h
new file mode 100644
index 0000000000..0736c02a80
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tpm12.h
@@ -0,0 +1,2173 @@
+/** @file   
+  TPM Specification data structures (TCG TPM Specification Version 1.2 Revision 103)
+  See http://trustedcomputinggroup.org for latest specification updates
+
+  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+**/
+
+
+#ifndef _TPM12_H_
+#define _TPM12_H_
+
+///
+/// The start of TPM return codes
+///
+#define TPM_BASE                    0
+
+//
+// All structures MUST be packed on a byte boundary.
+//
+
+#pragma pack (1)
+
+//
+// Part 2, section 2.2.3: Helper redefinitions
+//
+///
+/// Indicates the conditions where it is required that authorization be presented
+///
+typedef UINT8                       TPM_AUTH_DATA_USAGE;
+///
+/// The information as to what the payload is in an encrypted structure
+///
+typedef UINT8                       TPM_PAYLOAD_TYPE;
+///
+/// The version info breakdown
+///
+typedef UINT8                       TPM_VERSION_BYTE;
+///
+/// The state of the dictionary attack mitigation logic
+///
+typedef UINT8                       TPM_DA_STATE;
+///
+/// The request or response authorization type
+///
+typedef UINT16                      TPM_TAG;
+///
+/// The protocol in use
+///
+typedef UINT16                      TPM_PROTOCOL_ID;
+///
+/// Indicates the start state
+///
+typedef UINT16                      TPM_STARTUP_TYPE;
+///
+/// The definition of the encryption scheme
+///
+typedef UINT16                      TPM_ENC_SCHEME;
+///
+/// The definition of the signature scheme
+///
+typedef UINT16                      TPM_SIG_SCHEME;
+///
+/// The definition of the migration scheme
+///
+typedef UINT16                      TPM_MIGRATE_SCHEME;
+///
+/// Sets the state of the physical presence mechanism
+///
+typedef UINT16                      TPM_PHYSICAL_PRESENCE;
+///
+/// Indicates the types of entity that are supported by the TPM
+///
+typedef UINT16                      TPM_ENTITY_TYPE;
+///
+/// Indicates the permitted usage of the key
+///
+typedef UINT16                      TPM_KEY_USAGE;
+///
+/// The type of asymmetric encrypted structure in use by the endorsement key
+///
+typedef UINT16                      TPM_EK_TYPE;
+///
+/// The tag for the structure
+///
+typedef UINT16                      TPM_STRUCTURE_TAG;
+///
+/// The platform specific spec to which the information relates to
+///
+typedef UINT16                      TPM_PLATFORM_SPECIFIC;
+///
+/// The command ordinal
+///
+typedef UINT32                      TPM_COMMAND_CODE;
+///
+/// Identifies a TPM capability area
+///
+typedef UINT32                      TPM_CAPABILITY_AREA;
+///
+/// Indicates information regarding a key
+///
+typedef UINT32                      TPM_KEY_FLAGS;
+///
+/// Indicates the type of algorithm
+///
+typedef UINT32                      TPM_ALGORITHM_ID;
+///
+/// The locality modifier
+///
+typedef UINT32                      TPM_MODIFIER_INDICATOR;
+///
+/// The actual number of a counter
+///
+typedef UINT32                      TPM_ACTUAL_COUNT;
+///
+/// Attributes that define what options are in use for a transport session
+///
+typedef UINT32                      TPM_TRANSPORT_ATTRIBUTES;
+///
+/// Handle to an authorization session
+///
+typedef UINT32                      TPM_AUTHHANDLE;
+///
+/// Index to a DIR register
+///
+typedef UINT32                      TPM_DIRINDEX;
+///
+/// The area where a key is held assigned by the TPM
+///
+typedef UINT32                      TPM_KEY_HANDLE;
+///
+/// Index to a PCR register
+///
+typedef UINT32                      TPM_PCRINDEX;
+///
+/// The return code from a function
+///
+typedef UINT32                      TPM_RESULT;
+///
+/// The types of resources that a TPM may have using internal resources
+///
+typedef UINT32                      TPM_RESOURCE_TYPE;
+///
+/// Allows for controlling of the key when loaded and how to handle TPM_Startup issues
+///
+typedef UINT32                      TPM_KEY_CONTROL;
+///
+/// The index into the NV storage area
+///
+typedef UINT32                      TPM_NV_INDEX;
+///
+/// The family ID. Family IDs are automatically assigned a sequence number by the TPM. 
+/// A trusted process can set the FamilyID value in an individual row to NULL, which 
+/// invalidates that row. The family ID resets to NULL on each change of TPM Owner.
+///
+typedef UINT32                      TPM_FAMILY_ID;
+///
+/// IA value used as a label for the most recent verification of this family. Set to zero when not in use.
+///
+typedef UINT32                      TPM_FAMILY_VERIFICATION;
+///
+/// How the TPM handles var
+///
+typedef UINT32                      TPM_STARTUP_EFFECTS;
+///
+/// The mode of a symmetric encryption
+///
+typedef UINT32                      TPM_SYM_MODE;
+///
+/// The family flags
+///
+typedef UINT32                      TPM_FAMILY_FLAGS;
+///
+/// The index value for the delegate NV table
+///
+typedef UINT32                      TPM_DELEGATE_INDEX;
+///
+/// The restrictions placed on delegation of CMK commands
+///
+typedef UINT32                      TPM_CMK_DELEGATE;
+///
+/// The ID value of a monotonic counter
+///
+typedef UINT32                      TPM_COUNT_ID;
+///
+/// A command to execute
+///
+typedef UINT32                      TPM_REDIT_COMMAND;
+///
+/// A transport session handle
+///
+typedef UINT32                      TPM_TRANSHANDLE;
+///
+/// A generic handle could be key, transport etc
+///
+typedef UINT32                      TPM_HANDLE;
+///
+/// What operation is happening
+///
+typedef UINT32                      TPM_FAMILY_OPERATION;
+
+//
+// Part 2, section 2.2.4: Vendor specific
+// The following defines allow for the quick specification of a
+// vendor specific item.
+//
+#define TPM_Vendor_Specific32       ((UINT32) 0x00000400)
+#define TPM_Vendor_Specific8        ((UINT8) 0x80)
+
+//
+// Part 2, section 3.1: TPM_STRUCTURE_TAG
+//
+#define TPM_TAG_CONTEXTBLOB         ((TPM_STRUCTURE_TAG) 0x0001)
+#define TPM_TAG_CONTEXT_SENSITIVE   ((TPM_STRUCTURE_TAG) 0x0002)
+#define TPM_TAG_CONTEXTPOINTER      ((TPM_STRUCTURE_TAG) 0x0003)
+#define TPM_TAG_CONTEXTLIST         ((TPM_STRUCTURE_TAG) 0x0004)
+#define TPM_TAG_SIGNINFO            ((TPM_STRUCTURE_TAG) 0x0005)
+#define TPM_TAG_PCR_INFO_LONG       ((TPM_STRUCTURE_TAG) 0x0006)
+#define TPM_TAG_PERSISTENT_FLAGS    ((TPM_STRUCTURE_TAG) 0x0007)
+#define TPM_TAG_VOLATILE_FLAGS      ((TPM_STRUCTURE_TAG) 0x0008)
+#define TPM_TAG_PERSISTENT_DATA     ((TPM_STRUCTURE_TAG) 0x0009)
+#define TPM_TAG_VOLATILE_DATA       ((TPM_STRUCTURE_TAG) 0x000A)
+#define TPM_TAG_SV_DATA             ((TPM_STRUCTURE_TAG) 0x000B)
+#define TPM_TAG_EK_BLOB             ((TPM_STRUCTURE_TAG) 0x000C)
+#define TPM_TAG_EK_BLOB_AUTH        ((TPM_STRUCTURE_TAG) 0x000D)
+#define TPM_TAG_COUNTER_VALUE       ((TPM_STRUCTURE_TAG) 0x000E)
+#define TPM_TAG_TRANSPORT_INTERNAL  ((TPM_STRUCTURE_TAG) 0x000F)
+#define TPM_TAG_TRANSPORT_LOG_IN    ((TPM_STRUCTURE_TAG) 0x0010)
+#define TPM_TAG_TRANSPORT_LOG_OUT   ((TPM_STRUCTURE_TAG) 0x0011)
+#define TPM_TAG_AUDIT_EVENT_IN      ((TPM_STRUCTURE_TAG) 0x0012)
+#define TPM_TAG_AUDIT_EVENT_OUT     ((TPM_STRUCTURE_TAG) 0x0013)
+#define TPM_TAG_CURRENT_TICKS       ((TPM_STRUCTURE_TAG) 0x0014)
+#define TPM_TAG_KEY                 ((TPM_STRUCTURE_TAG) 0x0015)
+#define TPM_TAG_STORED_DATA12       ((TPM_STRUCTURE_TAG) 0x0016)
+#define TPM_TAG_NV_ATTRIBUTES       ((TPM_STRUCTURE_TAG) 0x0017)
+#define TPM_TAG_NV_DATA_PUBLIC      ((TPM_STRUCTURE_TAG) 0x0018)
+#define TPM_TAG_NV_DATA_SENSITIVE   ((TPM_STRUCTURE_TAG) 0x0019)
+#define TPM_TAG_DELEGATIONS         ((TPM_STRUCTURE_TAG) 0x001A)
+#define TPM_TAG_DELEGATE_PUBLIC     ((TPM_STRUCTURE_TAG) 0x001B)
+#define TPM_TAG_DELEGATE_TABLE_ROW  ((TPM_STRUCTURE_TAG) 0x001C)
+#define TPM_TAG_TRANSPORT_AUTH      ((TPM_STRUCTURE_TAG) 0x001D)
+#define TPM_TAG_TRANSPORT_PUBLIC    ((TPM_STRUCTURE_TAG) 0x001E)
+#define TPM_TAG_PERMANENT_FLAGS     ((TPM_STRUCTURE_TAG) 0x001F)
+#define TPM_TAG_STCLEAR_FLAGS       ((TPM_STRUCTURE_TAG) 0x0020)
+#define TPM_TAG_STANY_FLAGS         ((TPM_STRUCTURE_TAG) 0x0021)
+#define TPM_TAG_PERMANENT_DATA      ((TPM_STRUCTURE_TAG) 0x0022)
+#define TPM_TAG_STCLEAR_DATA        ((TPM_STRUCTURE_TAG) 0x0023)
+#define TPM_TAG_STANY_DATA          ((TPM_STRUCTURE_TAG) 0x0024)
+#define TPM_TAG_FAMILY_TABLE_ENTRY  ((TPM_STRUCTURE_TAG) 0x0025)
+#define TPM_TAG_DELEGATE_SENSITIVE  ((TPM_STRUCTURE_TAG) 0x0026)
+#define TPM_TAG_DELG_KEY_BLOB       ((TPM_STRUCTURE_TAG) 0x0027)
+#define TPM_TAG_KEY12               ((TPM_STRUCTURE_TAG) 0x0028)
+#define TPM_TAG_CERTIFY_INFO2       ((TPM_STRUCTURE_TAG) 0x0029)
+#define TPM_TAG_DELEGATE_OWNER_BLOB ((TPM_STRUCTURE_TAG) 0x002A)
+#define TPM_TAG_EK_BLOB_ACTIVATE    ((TPM_STRUCTURE_TAG) 0x002B)
+#define TPM_TAG_DAA_BLOB            ((TPM_STRUCTURE_TAG) 0x002C)
+#define TPM_TAG_DAA_CONTEXT         ((TPM_STRUCTURE_TAG) 0x002D)
+#define TPM_TAG_DAA_ENFORCE         ((TPM_STRUCTURE_TAG) 0x002E)
+#define TPM_TAG_DAA_ISSUER          ((TPM_STRUCTURE_TAG) 0x002F)
+#define TPM_TAG_CAP_VERSION_INFO    ((TPM_STRUCTURE_TAG) 0x0030)
+#define TPM_TAG_DAA_SENSITIVE       ((TPM_STRUCTURE_TAG) 0x0031)
+#define TPM_TAG_DAA_TPM             ((TPM_STRUCTURE_TAG) 0x0032)
+#define TPM_TAG_CMK_MIGAUTH         ((TPM_STRUCTURE_TAG) 0x0033)
+#define TPM_TAG_CMK_SIGTICKET       ((TPM_STRUCTURE_TAG) 0x0034)
+#define TPM_TAG_CMK_MA_APPROVAL     ((TPM_STRUCTURE_TAG) 0x0035)
+#define TPM_TAG_QUOTE_INFO2         ((TPM_STRUCTURE_TAG) 0x0036)
+#define TPM_TAG_DA_INFO             ((TPM_STRUCTURE_TAG) 0x0037)
+#define TPM_TAG_DA_LIMITED          ((TPM_STRUCTURE_TAG) 0x0038)
+#define TPM_TAG_DA_ACTION_TYPE      ((TPM_STRUCTURE_TAG) 0x0039)
+
+//
+// Part 2, section 4: TPM Types
+//
+
+//
+// Part 2, section 4.1: TPM_RESOURCE_TYPE
+//
+#define TPM_RT_KEY                  ((TPM_RESOURCE_TYPE) 0x00000001) ///< The handle is a key handle and is the result of a LoadKey type operation
+#define TPM_RT_AUTH                 ((TPM_RESOURCE_TYPE) 0x00000002) ///< The handle is an authorization handle. Auth handles come from TPM_OIAP, TPM_OSAP and TPM_DSAP
+#define TPM_RT_HASH                 ((TPM_RESOURCE_TYPE) 0x00000003) ///< Reserved for hashes
+#define TPM_RT_TRANS                ((TPM_RESOURCE_TYPE) 0x00000004) ///< The handle is for a transport session. Transport handles come from TPM_EstablishTransport
+#define TPM_RT_CONTEXT              ((TPM_RESOURCE_TYPE) 0x00000005) ///< Resource wrapped and held outside the TPM using the context save/restore commands
+#define TPM_RT_COUNTER              ((TPM_RESOURCE_TYPE) 0x00000006) ///< Reserved for counters
+#define TPM_RT_DELEGATE             ((TPM_RESOURCE_TYPE) 0x00000007) ///< The handle is for a delegate row. These are the internal rows held in NV storage by the TPM
+#define TPM_RT_DAA_TPM              ((TPM_RESOURCE_TYPE) 0x00000008) ///< The value is a DAA TPM specific blob
+#define TPM_RT_DAA_V0               ((TPM_RESOURCE_TYPE) 0x00000009) ///< The value is a DAA V0 parameter
+#define TPM_RT_DAA_V1               ((TPM_RESOURCE_TYPE) 0x0000000A) ///< The value is a DAA V1 parameter
+
+//
+// Part 2, section 4.2: TPM_PAYLOAD_TYPE
+//
+#define TPM_PT_ASYM                 ((TPM_PAYLOAD_TYPE) 0x01) ///< The entity is an asymmetric key
+#define TPM_PT_BIND                 ((TPM_PAYLOAD_TYPE) 0x02) ///< The entity is bound data
+#define TPM_PT_MIGRATE              ((TPM_PAYLOAD_TYPE) 0x03) ///< The entity is a migration blob
+#define TPM_PT_MAINT                ((TPM_PAYLOAD_TYPE) 0x04) ///< The entity is a maintenance blob
+#define TPM_PT_SEAL                 ((TPM_PAYLOAD_TYPE) 0x05) ///< The entity is sealed data
+#define TPM_PT_MIGRATE_RESTRICTED   ((TPM_PAYLOAD_TYPE) 0x06) ///< The entity is a restricted-migration asymmetric key
+#define TPM_PT_MIGRATE_EXTERNAL     ((TPM_PAYLOAD_TYPE) 0x07) ///< The entity is a external migratable key
+#define TPM_PT_CMK_MIGRATE          ((TPM_PAYLOAD_TYPE) 0x08) ///< The entity is a CMK migratable blob
+#define TPM_PT_VENDOR_SPECIFIC      ((TPM_PAYLOAD_TYPE) 0x80) ///< 0x80 - 0xFF Vendor specific payloads
+
+//
+// Part 2, section 4.3: TPM_ENTITY_TYPE
+//
+#define TPM_ET_KEYHANDLE            ((UINT16) 0x0001) ///< The entity is a keyHandle or key
+#define TPM_ET_OWNER                ((UINT16) 0x0002) ///< The entity is the TPM Owner
+#define TPM_ET_DATA                 ((UINT16) 0x0003) ///< The entity is some data
+#define TPM_ET_SRK                  ((UINT16) 0x0004) ///< The entity is the SRK
+#define TPM_ET_KEY                  ((UINT16) 0x0005) ///< The entity is a key or keyHandle
+#define TPM_ET_REVOKE               ((UINT16) 0x0006) ///< The entity is the RevokeTrust value
+#define TPM_ET_DEL_OWNER_BLOB       ((UINT16) 0x0007) ///< The entity is a delegate owner blob
+#define TPM_ET_DEL_ROW              ((UINT16) 0x0008) ///< The entity is a delegate row
+#define TPM_ET_DEL_KEY_BLOB         ((UINT16) 0x0009) ///< The entity is a delegate key blob
+#define TPM_ET_COUNTER              ((UINT16) 0x000A) ///< The entity is a counter
+#define TPM_ET_NV                   ((UINT16) 0x000B) ///< The entity is a NV index
+#define TPM_ET_OPERATOR             ((UINT16) 0x000C) ///< The entity is the operator
+#define TPM_ET_RESERVED_HANDLE      ((UINT16) 0x0040) ///< Reserved. This value avoids collisions with the handle MSB setting.
+//
+// TPM_ENTITY_TYPE MSB Values: The MSB is used to indicate the ADIP encryption sheme when applicable
+//
+#define TPM_ET_XOR                  ((UINT16) 0x0000) ///< ADIP encryption scheme: XOR
+#define TPM_ET_AES128               ((UINT16) 0x0006) ///< ADIP encryption scheme: AES 128 bits
+
+//
+// Part 2, section 4.4.1: Reserved Key Handles
+//
+#define TPM_KH_SRK                  ((TPM_KEY_HANDLE) 0x40000000) ///< The handle points to the SRK
+#define TPM_KH_OWNER                ((TPM_KEY_HANDLE) 0x40000001) ///< The handle points to the TPM Owner
+#define TPM_KH_REVOKE               ((TPM_KEY_HANDLE) 0x40000002) ///< The handle points to the RevokeTrust value
+#define TPM_KH_TRANSPORT            ((TPM_KEY_HANDLE) 0x40000003) ///< The handle points to the EstablishTransport static authorization
+#define TPM_KH_OPERATOR             ((TPM_KEY_HANDLE) 0x40000004) ///< The handle points to the Operator auth
+#define TPM_KH_ADMIN                ((TPM_KEY_HANDLE) 0x40000005) ///< The handle points to the delegation administration auth
+#define TPM_KH_EK                   ((TPM_KEY_HANDLE) 0x40000006) ///< The handle points to the PUBEK, only usable with TPM_OwnerReadInternalPub
+
+//
+// Part 2, section 4.5: TPM_STARTUP_TYPE
+//
+#define TPM_ST_CLEAR                ((TPM_STARTUP_TYPE) 0x0001) ///< The TPM is starting up from a clean state
+#define TPM_ST_STATE                ((TPM_STARTUP_TYPE) 0x0002) ///< The TPM is starting up from a saved state
+#define TPM_ST_DEACTIVATED          ((TPM_STARTUP_TYPE) 0x0003) ///< The TPM is to startup and set the deactivated flag to TRUE
+
+//
+// Part 2, section 4.6: TPM_STATUP_EFFECTS
+// The table makeup is still an open issue.
+//
+
+//
+// Part 2, section 4.7: TPM_PROTOCOL_ID
+//
+#define TPM_PID_OIAP                ((TPM_PROTOCOL_ID) 0x0001) ///< The OIAP protocol.
+#define TPM_PID_OSAP                ((TPM_PROTOCOL_ID) 0x0002) ///< The OSAP protocol.
+#define TPM_PID_ADIP                ((TPM_PROTOCOL_ID) 0x0003) ///< The ADIP protocol.
+#define TPM_PID_ADCP                ((TPM_PROTOCOL_ID) 0x0004) ///< The ADCP protocol.
+#define TPM_PID_OWNER               ((TPM_PROTOCOL_ID) 0x0005) ///< The protocol for taking ownership of a TPM.
+#define TPM_PID_DSAP                ((TPM_PROTOCOL_ID) 0x0006) ///< The DSAP protocol
+#define TPM_PID_TRANSPORT           ((TPM_PROTOCOL_ID) 0x0007) ///< The transport protocol
+
+//
+// Part 2, section 4.8: TPM_ALGORITHM_ID
+//   The TPM MUST support the algorithms TPM_ALG_RSA, TPM_ALG_SHA, TPM_ALG_HMAC,
+//   TPM_ALG_MGF1
+//
+#define TPM_ALG_RSA                 ((TPM_ALGORITHM_ID) 0x00000001) ///< The RSA algorithm.
+#define TPM_ALG_DES                 ((TPM_ALGORITHM_ID) 0x00000002) ///< The DES algorithm
+#define TPM_ALG_3DES                ((TPM_ALGORITHM_ID) 0x00000003) ///< The 3DES algorithm in EDE mode
+#define TPM_ALG_SHA                 ((TPM_ALGORITHM_ID) 0x00000004) ///< The SHA1 algorithm
+#define TPM_ALG_HMAC                ((TPM_ALGORITHM_ID) 0x00000005) ///< The RFC 2104 HMAC algorithm
+#define TPM_ALG_AES128              ((TPM_ALGORITHM_ID) 0x00000006) ///< The AES algorithm, key size 128
+#define TPM_ALG_MGF1                ((TPM_ALGORITHM_ID) 0x00000007) ///< The XOR algorithm using MGF1 to create a string the size of the encrypted block
+#define TPM_ALG_AES192              ((TPM_ALGORITHM_ID) 0x00000008) ///< AES, key size 192
+#define TPM_ALG_AES256              ((TPM_ALGORITHM_ID) 0x00000009) ///< AES, key size 256
+#define TPM_ALG_XOR                 ((TPM_ALGORITHM_ID) 0x0000000A) ///< XOR using the rolling nonces
+
+//
+// Part 2, section 4.9: TPM_PHYSICAL_PRESENCE
+//
+#define TPM_PHYSICAL_PRESENCE_HW_DISABLE    ((TPM_PHYSICAL_PRESENCE) 0x0200) ///< Sets the physicalPresenceHWEnable to FALSE
+#define TPM_PHYSICAL_PRESENCE_CMD_DISABLE   ((TPM_PHYSICAL_PRESENCE) 0x0100) ///< Sets the physicalPresenceCMDEnable to FALSE
+#define TPM_PHYSICAL_PRESENCE_LIFETIME_LOCK ((TPM_PHYSICAL_PRESENCE) 0x0080) ///< Sets the physicalPresenceLifetimeLock to TRUE
+#define TPM_PHYSICAL_PRESENCE_HW_ENABLE     ((TPM_PHYSICAL_PRESENCE) 0x0040) ///< Sets the physicalPresenceHWEnable to TRUE
+#define TPM_PHYSICAL_PRESENCE_CMD_ENABLE    ((TPM_PHYSICAL_PRESENCE) 0x0020) ///< Sets the physicalPresenceCMDEnable to TRUE
+#define TPM_PHYSICAL_PRESENCE_NOTPRESENT    ((TPM_PHYSICAL_PRESENCE) 0x0010) ///< Sets PhysicalPresence = FALSE
+#define TPM_PHYSICAL_PRESENCE_PRESENT       ((TPM_PHYSICAL_PRESENCE) 0x0008) ///< Sets PhysicalPresence = TRUE
+#define TPM_PHYSICAL_PRESENCE_LOCK          ((TPM_PHYSICAL_PRESENCE) 0x0004) ///< Sets PhysicalPresenceLock = TRUE
+
+//
+// Part 2, section 4.10: TPM_MIGRATE_SCHEME
+//
+#define TPM_MS_MIGRATE                      ((TPM_MIGRATE_SCHEME) 0x0001) ///< A public key that can be used with all TPM migration commands other than 'ReWrap' mode.
+#define TPM_MS_REWRAP                       ((TPM_MIGRATE_SCHEME) 0x0002) ///< A public key that can be used for the ReWrap mode of TPM_CreateMigrationBlob.
+#define TPM_MS_MAINT                        ((TPM_MIGRATE_SCHEME) 0x0003) ///< A public key that can be used for the Maintenance commands
+#define TPM_MS_RESTRICT_MIGRATE             ((TPM_MIGRATE_SCHEME) 0x0004) ///< The key is to be migrated to a Migration Authority.
+#define TPM_MS_RESTRICT_APPROVE_DOUBLE      ((TPM_MIGRATE_SCHEME) 0x0005) ///< The key is to be migrated to an entity approved by a Migration Authority using double wrapping
+
+//
+// Part 2, section 4.11: TPM_EK_TYPE
+//
+#define TPM_EK_TYPE_ACTIVATE        ((TPM_EK_TYPE) 0x0001) ///< The blob MUST be TPM_EK_BLOB_ACTIVATE
+#define TPM_EK_TYPE_AUTH            ((TPM_EK_TYPE) 0x0002) ///< The blob MUST be TPM_EK_BLOB_AUTH
+
+//
+// Part 2, section 4.12: TPM_PLATFORM_SPECIFIC
+//
+#define TPM_PS_PC_11                ((TPM_PLATFORM_SPECIFIC) 0x0001) ///< PC Specific version 1.1
+#define TPM_PS_PC_12                ((TPM_PLATFORM_SPECIFIC) 0x0002) ///< PC Specific version 1.2
+#define TPM_PS_PDA_12               ((TPM_PLATFORM_SPECIFIC) 0x0003) ///< PDA Specific version 1.2
+#define TPM_PS_Server_12            ((TPM_PLATFORM_SPECIFIC) 0x0004) ///< Server Specific version 1.2
+#define TPM_PS_Mobile_12            ((TPM_PLATFORM_SPECIFIC) 0x0005) ///< Mobil Specific version 1.2
+
+//
+// Part 2, section 5: Basic Structures
+//
+
+///
+/// Part 2, section 5.1: TPM_STRUCT_VER
+///
+typedef struct tdTPM_STRUCT_VER {
+  UINT8                             major;
+  UINT8                             minor;
+  UINT8                             revMajor;
+  UINT8                             revMinor;
+} TPM_STRUCT_VER;
+
+///
+/// Part 2, section 5.3: TPM_VERSION
+///
+typedef struct tdTPM_VERSION {
+  TPM_VERSION_BYTE                  major;
+  TPM_VERSION_BYTE                  minor;
+  UINT8                             revMajor;
+  UINT8                             revMinor;
+} TPM_VERSION;
+
+
+#define TPM_SHA1_160_HASH_LEN       0x14
+#define TPM_SHA1BASED_NONCE_LEN     TPM_SHA1_160_HASH_LEN
+
+///
+/// Part 2, section 5.4: TPM_DIGEST
+///
+typedef struct tdTPM_DIGEST{
+  UINT8                             digest[TPM_SHA1_160_HASH_LEN];
+} TPM_DIGEST;
+
+///
+/// This SHALL be the digest of the chosen identityLabel and privacyCA for a new TPM identity
+///
+typedef TPM_DIGEST                  TPM_CHOSENID_HASH;
+///
+/// This SHALL be the hash of a list of PCR indexes and PCR values that a key or data is bound to
+///
+typedef TPM_DIGEST                  TPM_COMPOSITE_HASH;
+///
+/// This SHALL be the value of a DIR register
+///
+typedef TPM_DIGEST                  TPM_DIRVALUE;
+
+typedef TPM_DIGEST                  TPM_HMAC;
+///
+/// The value inside of the PCR
+///
+typedef TPM_DIGEST                  TPM_PCRVALUE;
+///
+/// This SHALL be the value of the current internal audit state
+///
+typedef TPM_DIGEST                  TPM_AUDITDIGEST;
+
+///
+/// Part 2, section 5.5: TPM_NONCE
+///
+typedef struct tdTPM_NONCE{
+  UINT8                             nonce[20];
+} TPM_NONCE;
+
+///
+/// This SHALL be a random value generated by a TPM immediately after the EK is installed
+/// in that TPM, whenever an EK is installed in that TPM
+///
+typedef TPM_NONCE                  TPM_DAA_TPM_SEED;
+///
+/// This SHALL be a random value
+///
+typedef TPM_NONCE                  TPM_DAA_CONTEXT_SEED;
+
+//
+// Part 2, section 5.6: TPM_AUTHDATA
+//
+///
+/// The AuthData data is the information that is saved or passed to provide proof of ownership
+/// 296 of an entity
+///
+typedef UINT8                       tdTPM_AUTHDATA[20];
+
+typedef tdTPM_AUTHDATA              TPM_AUTHDATA;
+///
+/// A secret plaintext value used in the authorization process
+///
+typedef TPM_AUTHDATA                TPM_SECRET;
+///
+/// A ciphertext (encrypted) version of AuthData data. The encryption mechanism depends on the context
+///
+typedef TPM_AUTHDATA                TPM_ENCAUTH;
+
+///
+/// Part 2, section 5.7: TPM_KEY_HANDLE_LIST
+/// Size of handle is loaded * sizeof(TPM_KEY_HANDLE)
+///
+typedef struct tdTPM_KEY_HANDLE_LIST {
+  UINT16                            loaded;
+  TPM_KEY_HANDLE                    handle[1];
+} TPM_KEY_HANDLE_LIST;
+
+//
+// Part 2, section 5.8: TPM_KEY_USAGE values
+//
+///
+/// TPM_KEY_SIGNING SHALL indicate a signing key. The [private] key SHALL be
+/// used for signing operations, only. This means that it MUST be a leaf of the
+/// Protected Storage key hierarchy.
+///
+#define TPM_KEY_SIGNING             ((UINT16) 0x0010)
+///
+/// TPM_KEY_STORAGE SHALL indicate a storage key. The key SHALL be used to wrap
+/// and unwrap other keys in the Protected Storage hierarchy
+///
+#define TPM_KEY_STORAGE             ((UINT16) 0x0011)
+///
+/// TPM_KEY_IDENTITY SHALL indicate an identity key. The key SHALL be used for
+/// operations that require a TPM identity, only.
+///
+#define TPM_KEY_IDENTITY            ((UINT16) 0x0012)
+///
+/// TPM_KEY_AUTHCHANGE SHALL indicate an ephemeral key that is in use during
+/// the ChangeAuthAsym process, only.
+///
+#define TPM_KEY_AUTHCHANGE          ((UINT16) 0x0013)
+///
+/// TPM_KEY_BIND SHALL indicate a key that can be used for TPM_Bind and
+/// TPM_Unbind operations only.
+///
+#define TPM_KEY_BIND                ((UINT16) 0x0014)
+///
+/// TPM_KEY_LEGACY SHALL indicate a key that can perform signing and binding
+/// operations. The key MAY be used for both signing and binding operations.
+/// The TPM_KEY_LEGACY key type is to allow for use by applications where both
+/// signing and encryption operations occur with the same key. The use of this
+/// key type is not recommended TPM_KEY_MIGRATE 0x0016 This SHALL indicate a
+/// key in use for TPM_MigrateKey
+///
+#define TPM_KEY_LEGACY              ((UINT16) 0x0015)
+///
+/// TPM_KEY_MIGRAGE SHALL indicate a key in use for TPM_MigrateKey
+///
+#define TPM_KEY_MIGRATE             ((UINT16) 0x0016)
+
+//
+// Part 2, section 5.8.1: Mandatory Key Usage Schemes
+//
+
+#define TPM_ES_NONE                 ((TPM_ENC_SCHEME) 0x0001)
+#define TPM_ES_RSAESPKCSv15         ((TPM_ENC_SCHEME) 0x0002)
+#define TPM_ES_RSAESOAEP_SHA1_MGF1  ((TPM_ENC_SCHEME) 0x0003)
+#define TPM_ES_SYM_CNT              ((TPM_ENC_SCHEME) 0x0004)  ///< rev94 defined
+#define TPM_ES_SYM_CTR              ((TPM_ENC_SCHEME) 0x0004)
+#define TPM_ES_SYM_OFB              ((TPM_ENC_SCHEME) 0x0005)
+
+#define TPM_SS_NONE                 ((TPM_SIG_SCHEME) 0x0001)
+#define TPM_SS_RSASSAPKCS1v15_SHA1  ((TPM_SIG_SCHEME) 0x0002)
+#define TPM_SS_RSASSAPKCS1v15_DER   ((TPM_SIG_SCHEME) 0x0003)
+#define TPM_SS_RSASSAPKCS1v15_INFO  ((TPM_SIG_SCHEME) 0x0004)
+
+//
+// Part 2, section 5.9: TPM_AUTH_DATA_USAGE values
+//
+#define TPM_AUTH_NEVER              ((TPM_AUTH_DATA_USAGE) 0x00)
+#define TPM_AUTH_ALWAYS             ((TPM_AUTH_DATA_USAGE) 0x01)
+#define TPM_AUTH_PRIV_USE_ONLY      ((TPM_AUTH_DATA_USAGE) 0x03)
+
+///
+/// Part 2, section 5.10: TPM_KEY_FLAGS
+///
+typedef enum tdTPM_KEY_FLAGS {
+  redirection                       = 0x00000001,
+  migratable                        = 0x00000002,
+  isVolatile                        = 0x00000004,
+  pcrIgnoredOnRead                  = 0x00000008,
+  migrateAuthority                  = 0x00000010
+} TPM_KEY_FLAGS_BITS;
+
+///
+/// Part 2, section 5.11: TPM_CHANGEAUTH_VALIDATE
+///
+typedef struct tdTPM_CHANGEAUTH_VALIDATE {
+  TPM_SECRET                        newAuthSecret;
+  TPM_NONCE                         n1;
+} TPM_CHANGEAUTH_VALIDATE;
+
+///
+/// Part 2, section 5.12: TPM_MIGRATIONKEYAUTH
+///   decalared after section 10 to catch declaration of TPM_PUBKEY
+///
+/// Part 2 section 10.1: TPM_KEY_PARMS
+///   [size_is(parmSize)] BYTE* parms;
+///
+typedef struct tdTPM_KEY_PARMS {
+  TPM_ALGORITHM_ID                  algorithmID;
+  TPM_ENC_SCHEME                    encScheme;
+  TPM_SIG_SCHEME                    sigScheme;
+  UINT32                            parmSize;
+  UINT8                             *parms;
+} TPM_KEY_PARMS;
+
+///
+/// Part 2, section 10.4: TPM_STORE_PUBKEY
+///
+typedef struct tdTPM_STORE_PUBKEY {
+  UINT32                            keyLength;
+  UINT8                             key[1];
+} TPM_STORE_PUBKEY;
+
+///
+/// Part 2, section 10.5: TPM_PUBKEY
+///
+typedef struct tdTPM_PUBKEY{
+  TPM_KEY_PARMS                     algorithmParms;
+  TPM_STORE_PUBKEY                  pubKey;
+} TPM_PUBKEY;
+
+///
+/// Part 2, section 5.12: TPM_MIGRATIONKEYAUTH
+///
+typedef struct tdTPM_MIGRATIONKEYAUTH{
+  TPM_PUBKEY                        migrationKey;
+  TPM_MIGRATE_SCHEME                migrationScheme;
+  TPM_DIGEST                        digest;
+} TPM_MIGRATIONKEYAUTH;
+
+///
+/// Part 2, section 5.13: TPM_COUNTER_VALUE
+///
+typedef struct tdTPM_COUNTER_VALUE{
+  TPM_STRUCTURE_TAG                 tag;
+  UINT8                             label[4];
+  TPM_ACTUAL_COUNT                  counter;
+} TPM_COUNTER_VALUE;
+
+///
+/// Part 2, section 5.14: TPM_SIGN_INFO
+///   Size of data indicated by dataLen
+///
+typedef struct tdTPM_SIGN_INFO {
+  TPM_STRUCTURE_TAG                 tag;
+  UINT8                             fixed[4];
+  TPM_NONCE                         replay;
+  UINT32                            dataLen;
+  UINT8                             *data;
+} TPM_SIGN_INFO;
+
+///
+/// Part 2, section 5.15: TPM_MSA_COMPOSITE
+///   Number of migAuthDigest indicated by MSAlist
+///
+typedef struct tdTPM_MSA_COMPOSITE {
+  UINT32                            MSAlist;
+  TPM_DIGEST                        migAuthDigest[1];
+} TPM_MSA_COMPOSITE;
+
+///
+/// Part 2, section 5.16: TPM_CMK_AUTH
+///
+typedef struct tdTPM_CMK_AUTH{
+  TPM_DIGEST                        migrationAuthorityDigest;
+  TPM_DIGEST                        destinationKeyDigest;
+  TPM_DIGEST                        sourceKeyDigest;
+} TPM_CMK_AUTH;
+
+//
+// Part 2, section 5.17: TPM_CMK_DELEGATE
+//
+#define TPM_CMK_DELEGATE_SIGNING    ((TPM_CMK_DELEGATE) BIT31)
+#define TPM_CMK_DELEGATE_STORAGE    ((TPM_CMK_DELEGATE) BIT30)
+#define TPM_CMK_DELEGATE_BIND       ((TPM_CMK_DELEGATE) BIT29)
+#define TPM_CMK_DELEGATE_LEGACY     ((TPM_CMK_DELEGATE) BIT28)
+#define TPM_CMK_DELEGATE_MIGRATE    ((TPM_CMK_DELEGATE) BIT27)
+
+///
+/// Part 2, section 5.18: TPM_SELECT_SIZE
+///
+typedef struct tdTPM_SELECT_SIZE {
+  UINT8                             major;
+  UINT8                             minor;
+  UINT16                            reqSize;
+} TPM_SELECT_SIZE;
+
+///
+/// Part 2, section 5,19: TPM_CMK_MIGAUTH
+///
+typedef struct tdTPM_CMK_MIGAUTH{
+  TPM_STRUCTURE_TAG                 tag;
+  TPM_DIGEST                        msaDigest;
+  TPM_DIGEST                        pubKeyDigest;
+} TPM_CMK_MIGAUTH;
+
+///
+/// Part 2, section 5.20: TPM_CMK_SIGTICKET
+///
+typedef struct tdTPM_CMK_SIGTICKET{
+  TPM_STRUCTURE_TAG                 tag;
+  TPM_DIGEST                        verKeyDigest;
+  TPM_DIGEST                        signedData;
+} TPM_CMK_SIGTICKET;
+
+///
+/// Part 2, section 5.21: TPM_CMK_MA_APPROVAL
+///
+typedef struct tdTPM_CMK_MA_APPROVAL{
+  TPM_STRUCTURE_TAG                 tag;
+  TPM_DIGEST                        migrationAuthorityDigest;
+} TPM_CMK_MA_APPROVAL;
+
+//
+// Part 2, section 6: Command Tags
+//
+#define TPM_TAG_RQU_COMMAND         ((TPM_STRUCTURE_TAG) 0x00C1)
+#define TPM_TAG_RQU_AUTH1_COMMAND   ((TPM_STRUCTURE_TAG) 0x00C2)
+#define TPM_TAG_RQU_AUTH2_COMMAND   ((TPM_STRUCTURE_TAG) 0x00C3)
+#define TPM_TAG_RSP_COMMAND         ((TPM_STRUCTURE_TAG) 0x00C4)
+#define TPM_TAG_RSP_AUTH1_COMMAND   ((TPM_STRUCTURE_TAG) 0x00C5)
+#define TPM_TAG_RSP_AUTH2_COMMAND   ((TPM_STRUCTURE_TAG) 0x00C6)
+
+///
+/// Part 2, section 7.1: TPM_PERMANENT_FLAGS
+///
+typedef struct tdTPM_PERMANENT_FLAGS{
+  TPM_STRUCTURE_TAG                 tag;
+  BOOLEAN                           disable;
+  BOOLEAN                           ownership;
+  BOOLEAN                           deactivated;
+  BOOLEAN                           readPubek;
+  BOOLEAN                           disableOwnerClear;
+  BOOLEAN                           allowMaintenance;
+  BOOLEAN                           physicalPresenceLifetimeLock;
+  BOOLEAN                           physicalPresenceHWEnable;
+  BOOLEAN                           physicalPresenceCMDEnable;
+  BOOLEAN                           CEKPUsed;
+  BOOLEAN                           TPMpost;
+  BOOLEAN                           TPMpostLock;
+  BOOLEAN                           FIPS;
+  BOOLEAN                           operator;
+  BOOLEAN                           enableRevokeEK;
+  BOOLEAN                           nvLocked;
+  BOOLEAN                           readSRKPub;
+  BOOLEAN                           tpmEstablished;
+  BOOLEAN                           maintenanceDone;
+  BOOLEAN                           disableFullDALogicInfo;
+} TPM_PERMANENT_FLAGS;
+
+//
+// Part 2, section 7.1.1: Flag Restrictions (of TPM_PERMANENT_FLAGS)
+//
+#define TPM_PF_DISABLE                      ((TPM_CAPABILITY_AREA) 1)
+#define TPM_PF_OWNERSHIP                    ((TPM_CAPABILITY_AREA) 2)
+#define TPM_PF_DEACTIVATED                  ((TPM_CAPABILITY_AREA) 3)
+#define TPM_PF_READPUBEK                    ((TPM_CAPABILITY_AREA) 4)
+#define TPM_PF_DISABLEOWNERCLEAR            ((TPM_CAPABILITY_AREA) 5)
+#define TPM_PF_ALLOWMAINTENANCE             ((TPM_CAPABILITY_AREA) 6)
+#define TPM_PF_PHYSICALPRESENCELIFETIMELOCK ((TPM_CAPABILITY_AREA) 7)
+#define TPM_PF_PHYSICALPRESENCEHWENABLE     ((TPM_CAPABILITY_AREA) 8)
+#define TPM_PF_PHYSICALPRESENCECMDENABLE    ((TPM_CAPABILITY_AREA) 9)
+#define TPM_PF_CEKPUSED                     ((TPM_CAPABILITY_AREA) 10)
+#define TPM_PF_TPMPOST                      ((TPM_CAPABILITY_AREA) 11)
+#define TPM_PF_TPMPOSTLOCK                  ((TPM_CAPABILITY_AREA) 12)
+#define TPM_PF_FIPS                         ((TPM_CAPABILITY_AREA) 13)
+#define TPM_PF_OPERATOR                     ((TPM_CAPABILITY_AREA) 14)
+#define TPM_PF_ENABLEREVOKEEK               ((TPM_CAPABILITY_AREA) 15)
+#define TPM_PF_NV_LOCKED                    ((TPM_CAPABILITY_AREA) 16)
+#define TPM_PF_READSRKPUB                   ((TPM_CAPABILITY_AREA) 17)
+#define TPM_PF_TPMESTABLISHED               ((TPM_CAPABILITY_AREA) 18)
+#define TPM_PF_MAINTENANCEDONE              ((TPM_CAPABILITY_AREA) 19)
+#define TPM_PF_DISABLEFULLDALOGICINFO       ((TPM_CAPABILITY_AREA) 20)
+
+///
+/// Part 2, section 7.2: TPM_STCLEAR_FLAGS
+///
+typedef struct tdTPM_STCLEAR_FLAGS{
+  TPM_STRUCTURE_TAG                 tag;
+  BOOLEAN                           deactivated;
+  BOOLEAN                           disableForceClear;
+  BOOLEAN                           physicalPresence;
+  BOOLEAN                           physicalPresenceLock;
+  BOOLEAN                           bGlobalLock;
+} TPM_STCLEAR_FLAGS;
+
+//
+// Part 2, section 7.2.1: Flag Restrictions (of TPM_STCLEAR_FLAGS)
+//
+#define TPM_SF_DEACTIVATED          ((TPM_CAPABILITY_AREA) 1)
+#define TPM_SF_DISABLEFORCECLEAR    ((TPM_CAPABILITY_AREA) 2)
+#define TPM_SF_PHYSICALPRESENCE     ((TPM_CAPABILITY_AREA) 3)
+#define TPM_SF_PHYSICALPRESENCELOCK ((TPM_CAPABILITY_AREA) 4)
+#define TPM_SF_BGLOBALLOCK          ((TPM_CAPABILITY_AREA) 5)
+
+///
+/// Part 2, section 7.3: TPM_STANY_FLAGS
+///
+typedef struct tdTPM_STANY_FLAGS{
+  TPM_STRUCTURE_TAG                 tag;
+  BOOLEAN                           postInitialise;
+  TPM_MODIFIER_INDICATOR            localityModifier;
+  BOOLEAN                           transportExclusive;
+  BOOLEAN                           TOSPresent;
+} TPM_STANY_FLAGS;
+
+//
+// Part 2, section 7.3.1: Flag Restrictions (of TPM_STANY_FLAGS)
+//
+#define TPM_AF_POSTINITIALISE       ((TPM_CAPABILITY_AREA) 1)
+#define TPM_AF_LOCALITYMODIFIER     ((TPM_CAPABILITY_AREA) 2)
+#define TPM_AF_TRANSPORTEXCLUSIVE   ((TPM_CAPABILITY_AREA) 3)
+#define TPM_AF_TOSPRESENT           ((TPM_CAPABILITY_AREA) 4)
+
+//
+// All those structures defined in section 7.4, 7.5, 7.6 are not normative and 
+// thus no definitions here
+//
+// Part 2, section 7.4: TPM_PERMANENT_DATA
+//
+#define TPM_MIN_COUNTERS            4   ///< the minimum number of counters is 4
+#define TPM_DELEGATE_KEY            TPM_KEY
+#define TPM_NUM_PCR                 16
+#define TPM_MAX_NV_WRITE_NOOWNER    64
+
+//
+// Part 2, section 7.4.1: PERMANENT_DATA Subcap for SetCapability
+//
+#define TPM_PD_REVMAJOR               ((TPM_CAPABILITY_AREA) 1)
+#define TPM_PD_REVMINOR               ((TPM_CAPABILITY_AREA) 2)
+#define TPM_PD_TPMPROOF               ((TPM_CAPABILITY_AREA) 3)
+#define TPM_PD_OWNERAUTH              ((TPM_CAPABILITY_AREA) 4)
+#define TPM_PD_OPERATORAUTH           ((TPM_CAPABILITY_AREA) 5)
+#define TPM_PD_MANUMAINTPUB           ((TPM_CAPABILITY_AREA) 6)
+#define TPM_PD_ENDORSEMENTKEY         ((TPM_CAPABILITY_AREA) 7)
+#define TPM_PD_SRK                    ((TPM_CAPABILITY_AREA) 8)
+#define TPM_PD_DELEGATEKEY            ((TPM_CAPABILITY_AREA) 9)
+#define TPM_PD_CONTEXTKEY             ((TPM_CAPABILITY_AREA) 10)
+#define TPM_PD_AUDITMONOTONICCOUNTER  ((TPM_CAPABILITY_AREA) 11)
+#define TPM_PD_MONOTONICCOUNTER       ((TPM_CAPABILITY_AREA) 12)
+#define TPM_PD_PCRATTRIB              ((TPM_CAPABILITY_AREA) 13)
+#define TPM_PD_ORDINALAUDITSTATUS     ((TPM_CAPABILITY_AREA) 14)
+#define TPM_PD_AUTHDIR                ((TPM_CAPABILITY_AREA) 15)
+#define TPM_PD_RNGSTATE               ((TPM_CAPABILITY_AREA) 16)
+#define TPM_PD_FAMILYTABLE            ((TPM_CAPABILITY_AREA) 17)
+#define TPM_DELEGATETABLE             ((TPM_CAPABILITY_AREA) 18)
+#define TPM_PD_EKRESET                ((TPM_CAPABILITY_AREA) 19)
+#define TPM_PD_MAXNVBUFSIZE           ((TPM_CAPABILITY_AREA) 20)
+#define TPM_PD_LASTFAMILYID           ((TPM_CAPABILITY_AREA) 21)
+#define TPM_PD_NOOWNERNVWRITE         ((TPM_CAPABILITY_AREA) 22)
+#define TPM_PD_RESTRICTDELEGATE       ((TPM_CAPABILITY_AREA) 23)
+#define TPM_PD_TPMDAASEED             ((TPM_CAPABILITY_AREA) 24)
+#define TPM_PD_DAAPROOF               ((TPM_CAPABILITY_AREA) 25)
+
+///
+/// Part 2, section 7.5: TPM_STCLEAR_DATA
+///   available inside TPM only
+///
+ typedef struct tdTPM_STCLEAR_DATA{
+   TPM_STRUCTURE_TAG                  tag;
+   TPM_NONCE                          contextNonceKey;
+   TPM_COUNT_ID                       countID;
+   UINT32                             ownerReference;
+   BOOLEAN                            disableResetLock;
+   TPM_PCRVALUE                       PCR[TPM_NUM_PCR];
+   UINT32                             deferredPhysicalPresence;
+ }TPM_STCLEAR_DATA;
+
+//
+// Part 2, section 7.5.1: STCLEAR_DATA Subcap for SetCapability
+//
+#define TPM_SD_CONTEXTNONCEKEY            ((TPM_CAPABILITY_AREA)0x00000001)
+#define TPM_SD_COUNTID                    ((TPM_CAPABILITY_AREA)0x00000002)
+#define TPM_SD_OWNERREFERENCE             ((TPM_CAPABILITY_AREA)0x00000003)
+#define TPM_SD_DISABLERESETLOCK           ((TPM_CAPABILITY_AREA)0x00000004)
+#define TPM_SD_PCR                        ((TPM_CAPABILITY_AREA)0x00000005)
+#define TPM_SD_DEFERREDPHYSICALPRESENCE   ((TPM_CAPABILITY_AREA)0x00000006)
+
+//
+// Part 2, section 7.6.1: STANY_DATA Subcap for SetCapability
+//
+#define TPM_AD_CONTEXTNONCESESSION        ((TPM_CAPABILITY_AREA) 1)
+#define TPM_AD_AUDITDIGEST                ((TPM_CAPABILITY_AREA) 2)
+#define TPM_AD_CURRENTTICKS               ((TPM_CAPABILITY_AREA) 3)
+#define TPM_AD_CONTEXTCOUNT               ((TPM_CAPABILITY_AREA) 4)
+#define TPM_AD_CONTEXTLIST                ((TPM_CAPABILITY_AREA) 5)
+#define TPM_AD_SESSIONS                   ((TPM_CAPABILITY_AREA) 6)
+
+//
+// Part 2, section 8: PCR Structures
+// 
+
+///
+/// Part 2, section 8.1: TPM_PCR_SELECTION
+///   Size of pcrSelect[] indicated by sizeOfSelect
+///
+typedef struct tdTPM_PCR_SELECTION {
+  UINT16                            sizeOfSelect;
+  UINT8                             pcrSelect[1];
+} TPM_PCR_SELECTION;
+
+///
+/// Part 2, section 8.2: TPM_PCR_COMPOSITE
+///   Size of pcrValue[] indicated by valueSize
+///
+typedef struct tdTPM_PCR_COMPOSITE {
+  TPM_PCR_SELECTION                 select;
+  UINT32                            valueSize;
+  TPM_PCRVALUE                      pcrValue[1];
+} TPM_PCR_COMPOSITE;
+
+///
+/// Part 2, section 8.3: TPM_PCR_INFO
+///
+typedef struct tdTPM_PCR_INFO {
+  TPM_PCR_SELECTION                 pcrSelection;
+  TPM_COMPOSITE_HASH                digestAtRelease;
+  TPM_COMPOSITE_HASH                digestAtCreation;
+} TPM_PCR_INFO;
+
+///
+/// Part 2, section 8.6: TPM_LOCALITY_SELECTION
+///
+typedef UINT8                       TPM_LOCALITY_SELECTION;
+
+#define TPM_LOC_FOUR                ((UINT8) 0x10)
+#define TPM_LOC_THREE               ((UINT8) 0x08)
+#define TPM_LOC_TWO                 ((UINT8) 0x04)
+#define TPM_LOC_ONE                 ((UINT8) 0x02)
+#define TPM_LOC_ZERO                ((UINT8) 0x01)
+
+///
+/// Part 2, section 8.4: TPM_PCR_INFO_LONG
+///
+typedef struct tdTPM_PCR_INFO_LONG {
+  TPM_STRUCTURE_TAG                 tag;
+  TPM_LOCALITY_SELECTION            localityAtCreation;
+  TPM_LOCALITY_SELECTION            localityAtRelease;
+  TPM_PCR_SELECTION                 creationPCRSelection;
+  TPM_PCR_SELECTION                 releasePCRSelection;
+  TPM_COMPOSITE_HASH                digestAtCreation;
+  TPM_COMPOSITE_HASH                digestAtRelease;
+} TPM_PCR_INFO_LONG;
+
+///
+/// Part 2, section 8.5: TPM_PCR_INFO_SHORT
+///
+typedef struct tdTPM_PCR_INFO_SHORT{
+  TPM_PCR_SELECTION                 pcrSelection;
+  TPM_LOCALITY_SELECTION            localityAtRelease;
+  TPM_COMPOSITE_HASH                digestAtRelease;
+} TPM_PCR_INFO_SHORT;
+
+///
+/// Part 2, section 8.8: TPM_PCR_ATTRIBUTES
+///
+typedef struct tdTPM_PCR_ATTRIBUTES{
+  BOOLEAN                           pcrReset;
+  TPM_LOCALITY_SELECTION            pcrExtendLocal;
+  TPM_LOCALITY_SELECTION            pcrResetLocal;
+} TPM_PCR_ATTRIBUTES;
+
+//
+// Part 2, section 9: Storage Structures
+//
+
+///
+/// Part 2, section 9.1: TPM_STORED_DATA
+///   [size_is(sealInfoSize)] BYTE* sealInfo;
+///   [size_is(encDataSize)] BYTE* encData;
+///
+typedef struct tdTPM_STORED_DATA {
+  TPM_STRUCT_VER                    ver;
+  UINT32                            sealInfoSize;
+  UINT8                             *sealInfo;
+  UINT32                            encDataSize;
+  UINT8                             *encData;
+} TPM_STORED_DATA;
+
+///
+/// Part 2, section 9.2: TPM_STORED_DATA12
+///   [size_is(sealInfoSize)] BYTE* sealInfo;
+///   [size_is(encDataSize)] BYTE* encData;
+///
+typedef struct tdTPM_STORED_DATA12 {
+  TPM_STRUCTURE_TAG                 tag;
+  TPM_ENTITY_TYPE                   et;
+  UINT32                            sealInfoSize;
+  UINT8                             *sealInfo;
+  UINT32                            encDataSize;
+  UINT8                             *encData;
+} TPM_STORED_DATA12;
+
+///
+/// Part 2, section 9.3: TPM_SEALED_DATA
+///   [size_is(dataSize)] BYTE* data;
+///
+typedef struct tdTPM_SEALED_DATA {
+  TPM_PAYLOAD_TYPE                  payload;
+  TPM_SECRET                        authData;
+  TPM_NONCE                         tpmProof;
+  TPM_DIGEST                        storedDigest;
+  UINT32                            dataSize;
+  UINT8                             *data;
+} TPM_SEALED_DATA;
+
+///
+/// Part 2, section 9.4: TPM_SYMMETRIC_KEY
+///   [size_is(size)] BYTE* data;
+///
+typedef struct tdTPM_SYMMETRIC_KEY {
+  TPM_ALGORITHM_ID                  algId;
+  TPM_ENC_SCHEME                    encScheme;
+  UINT16                            dataSize;
+  UINT8                             *data;
+} TPM_SYMMETRIC_KEY;
+
+///
+/// Part 2, section 9.5: TPM_BOUND_DATA
+///
+typedef struct tdTPM_BOUND_DATA {
+  TPM_STRUCT_VER                    ver;
+  TPM_PAYLOAD_TYPE                  payload;
+  UINT8                             payloadData[1];
+} TPM_BOUND_DATA;
+
+//
+// Part 2 section 10: TPM_KEY complex
+// 
+
+//
+// Section 10.1, 10.4, and 10.5 have been defined previously
+//
+
+///
+/// Part 2, section 10.2: TPM_KEY
+///   [size_is(encDataSize)] BYTE* encData;
+///
+typedef struct tdTPM_KEY{
+  TPM_STRUCT_VER                    ver;
+  TPM_KEY_USAGE                     keyUsage;
+  TPM_KEY_FLAGS                     keyFlags;
+  TPM_AUTH_DATA_USAGE               authDataUsage;
+  TPM_KEY_PARMS                     algorithmParms;
+  UINT32                            PCRInfoSize;
+  UINT8                             *PCRInfo;
+  TPM_STORE_PUBKEY                  pubKey;
+  UINT32                            encDataSize;
+  UINT8                             *encData;
+} TPM_KEY;
+
+///
+/// Part 2, section 10.3: TPM_KEY12
+///   [size_is(encDataSize)] BYTE* encData;
+///
+typedef struct tdTPM_KEY12{
+  TPM_STRUCTURE_TAG                 tag;
+  UINT16                            fill;
+  TPM_KEY_USAGE                     keyUsage;
+  TPM_KEY_FLAGS                     keyFlags;
+  TPM_AUTH_DATA_USAGE               authDataUsage;
+  TPM_KEY_PARMS                     algorithmParms;
+  UINT32                            PCRInfoSize;
+  UINT8                             *PCRInfo;
+  TPM_STORE_PUBKEY                  pubKey;
+  UINT32                            encDataSize;
+  UINT8                             *encData;
+} TPM_KEY12;
+
+///
+/// Part 2, section 10.7: TPM_STORE_PRIVKEY
+///   [size_is(keyLength)] BYTE* key;
+///
+typedef struct tdTPM_STORE_PRIVKEY {
+  UINT32                            keyLength;
+  UINT8                             *key;
+} TPM_STORE_PRIVKEY;
+
+///
+/// Part 2, section 10.6: TPM_STORE_ASYMKEY
+///
+typedef struct tdTPM_STORE_ASYMKEY {                // pos len total
+  TPM_PAYLOAD_TYPE                  payload;        // 0    1   1
+  TPM_SECRET                        usageAuth;      // 1    20  21
+  TPM_SECRET                        migrationAuth;  // 21   20  41
+  TPM_DIGEST                        pubDataDigest;  // 41   20  61
+  TPM_STORE_PRIVKEY                 privKey;        // 61 132-151 193-214
+} TPM_STORE_ASYMKEY;
+
+///
+/// Part 2, section 10.8: TPM_MIGRATE_ASYMKEY
+///   [size_is(partPrivKeyLen)] BYTE* partPrivKey;
+///
+typedef struct tdTPM_MIGRATE_ASYMKEY {              // pos  len  total
+  TPM_PAYLOAD_TYPE                  payload;        //   0    1       1
+  TPM_SECRET                        usageAuth;      //   1   20      21
+  TPM_DIGEST                        pubDataDigest;  //  21   20      41
+  UINT32                            partPrivKeyLen; //  41    4      45
+  UINT8                             *partPrivKey;   //  45 112-127 157-172
+} TPM_MIGRATE_ASYMKEY;
+
+///
+/// Part 2, section 10.9: TPM_KEY_CONTROL
+///
+#define TPM_KEY_CONTROL_OWNER_EVICT ((UINT32) 0x00000001)
+
+//
+// Part 2, section 11: Signed Structures
+//
+
+///
+/// Part 2, section 11.1: TPM_CERTIFY_INFO Structure
+///
+typedef struct tdTPM_CERTIFY_INFO {
+  TPM_STRUCT_VER                  version;
+  TPM_KEY_USAGE                   keyUsage;
+  TPM_KEY_FLAGS                   keyFlags;
+  TPM_AUTH_DATA_USAGE             authDataUsage;
+  TPM_KEY_PARMS                   algorithmParms;
+  TPM_DIGEST                      pubkeyDigest;
+  TPM_NONCE                       data;
+  BOOLEAN                         parentPCRStatus;
+  UINT32                          PCRInfoSize;
+  UINT8                           *PCRInfo;
+} TPM_CERTIFY_INFO;
+
+///
+/// Part 2, section 11.2: TPM_CERTIFY_INFO2 Structure
+///
+typedef struct tdTPM_CERTIFY_INFO2 {
+  TPM_STRUCTURE_TAG               tag;
+  UINT8                           fill;
+  TPM_PAYLOAD_TYPE                payloadType;
+  TPM_KEY_USAGE                   keyUsage;
+  TPM_KEY_FLAGS                   keyFlags;
+  TPM_AUTH_DATA_USAGE             authDataUsage;
+  TPM_KEY_PARMS                   algorithmParms;
+  TPM_DIGEST                      pubkeyDigest;
+  TPM_NONCE                       data;
+  BOOLEAN                         parentPCRStatus;
+  UINT32                          PCRInfoSize;
+  UINT8                           *PCRInfo;
+  UINT32                          migrationAuthoritySize;
+  UINT8                           *migrationAuthority;
+} TPM_CERTIFY_INFO2;
+
+///
+/// Part 2, section 11.3 TPM_QUOTE_INFO Structure
+///
+typedef struct tdTPM_QUOTE_INFO {
+  TPM_STRUCT_VER                  version;
+  UINT8                           fixed[4];
+  TPM_COMPOSITE_HASH              digestValue;
+  TPM_NONCE                       externalData;
+} TPM_QUOTE_INFO;
+
+///
+/// Part 2, section 11.4 TPM_QUOTE_INFO2 Structure
+///
+typedef struct tdTPM_QUOTE_INFO2 {
+  TPM_STRUCTURE_TAG               tag;
+  UINT8                           fixed[4];
+  TPM_NONCE                       externalData;
+  TPM_PCR_INFO_SHORT              infoShort;
+} TPM_QUOTE_INFO2;
+
+//
+// Part 2, section 12: Identity Structures
+//
+
+///
+/// Part 2, section 12.1 TPM_EK_BLOB
+///
+typedef struct tdTPM_EK_BLOB {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_EK_TYPE                     ekType;
+  UINT32                          blobSize;
+  UINT8                           *blob;
+} TPM_EK_BLOB;
+
+///
+/// Part 2, section 12.2 TPM_EK_BLOB_ACTIVATE
+///
+typedef struct tdTPM_EK_BLOB_ACTIVATE {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_SYMMETRIC_KEY               sessionKey;
+  TPM_DIGEST                      idDigest;
+  TPM_PCR_INFO_SHORT              pcrInfo;
+} TPM_EK_BLOB_ACTIVATE;
+
+///
+/// Part 2, section 12.3 TPM_EK_BLOB_AUTH
+///
+typedef struct tdTPM_EK_BLOB_AUTH {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_SECRET                      authValue;
+} TPM_EK_BLOB_AUTH;
+
+
+///
+/// Part 2, section 12.5 TPM_IDENTITY_CONTENTS
+///
+typedef struct tdTPM_IDENTITY_CONTENTS {
+  TPM_STRUCT_VER                  ver;
+  UINT32                          ordinal;
+  TPM_CHOSENID_HASH               labelPrivCADigest;
+  TPM_PUBKEY                      identityPubKey;
+} TPM_IDENTITY_CONTENTS;
+
+///
+/// Part 2, section 12.6 TPM_IDENTITY_REQ
+///
+typedef struct tdTPM_IDENTITY_REQ {
+  UINT32                          asymSize;
+  UINT32                          symSize;
+  TPM_KEY_PARMS                   asymAlgorithm;
+  TPM_KEY_PARMS                   symAlgorithm;
+  UINT8                           *asymBlob;
+  UINT8                           *symBlob;
+} TPM_IDENTITY_REQ;
+
+///
+/// Part 2, section 12.7 TPM_IDENTITY_PROOF
+///
+typedef struct tdTPM_IDENTITY_PROOF {
+  TPM_STRUCT_VER                  ver;
+  UINT32                          labelSize;
+  UINT32                          identityBindingSize;
+  UINT32                          endorsementSize;
+  UINT32                          platformSize;
+  UINT32                          conformanceSize;
+  TPM_PUBKEY                      identityKey;
+  UINT8                           *labelArea;
+  UINT8                           *identityBinding;
+  UINT8                           *endorsementCredential;
+  UINT8                           *platformCredential;
+  UINT8                           *conformanceCredential;
+} TPM_IDENTITY_PROOF;
+
+///
+/// Part 2, section 12.8 TPM_ASYM_CA_CONTENTS
+///
+typedef struct tdTPM_ASYM_CA_CONTENTS {
+  TPM_SYMMETRIC_KEY               sessionKey;
+  TPM_DIGEST                      idDigest;
+} TPM_ASYM_CA_CONTENTS;
+
+///
+/// Part 2, section 12.9 TPM_SYM_CA_ATTESTATION
+///
+typedef struct tdTPM_SYM_CA_ATTESTATION {
+  UINT32                          credSize;
+  TPM_KEY_PARMS                   algorithm;
+  UINT8                           *credential;
+} TPM_SYM_CA_ATTESTATION;
+
+///
+/// Part 2, section 15: Tick Structures
+///   Placed here out of order because definitions are used in section 13.
+///
+typedef struct tdTPM_CURRENT_TICKS {
+  TPM_STRUCTURE_TAG                 tag;
+  UINT64                            currentTicks;
+  UINT16                            tickRate;
+  TPM_NONCE                         tickNonce;
+} TPM_CURRENT_TICKS;
+
+///
+/// Part 2, section 13: Transport structures
+///
+
+///
+/// Part 2, section 13.1: TPM _TRANSPORT_PUBLIC
+///
+typedef struct tdTPM_TRANSPORT_PUBLIC {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_TRANSPORT_ATTRIBUTES        transAttributes;
+  TPM_ALGORITHM_ID                algId;
+  TPM_ENC_SCHEME                  encScheme;
+} TPM_TRANSPORT_PUBLIC;
+
+//
+// Part 2, section 13.1.1 TPM_TRANSPORT_ATTRIBUTES Definitions
+//
+#define TPM_TRANSPORT_ENCRYPT       ((UINT32)BIT0)
+#define TPM_TRANSPORT_LOG           ((UINT32)BIT1)
+#define TPM_TRANSPORT_EXCLUSIVE     ((UINT32)BIT2)
+
+///
+/// Part 2, section 13.2 TPM_TRANSPORT_INTERNAL
+///
+typedef struct tdTPM_TRANSPORT_INTERNAL {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_AUTHDATA                    authData;
+  TPM_TRANSPORT_PUBLIC            transPublic;
+  TPM_TRANSHANDLE                 transHandle;
+  TPM_NONCE                       transNonceEven;
+  TPM_DIGEST                      transDigest;
+} TPM_TRANSPORT_INTERNAL;
+
+///
+/// Part 2, section 13.3 TPM_TRANSPORT_LOG_IN structure
+///
+typedef struct tdTPM_TRANSPORT_LOG_IN {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_DIGEST                      parameters;
+  TPM_DIGEST                      pubKeyHash;
+} TPM_TRANSPORT_LOG_IN;
+
+///
+/// Part 2, section 13.4 TPM_TRANSPORT_LOG_OUT structure
+///
+typedef struct tdTPM_TRANSPORT_LOG_OUT {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_CURRENT_TICKS               currentTicks;
+  TPM_DIGEST                      parameters;
+  TPM_MODIFIER_INDICATOR          locality;
+} TPM_TRANSPORT_LOG_OUT;
+
+///
+/// Part 2, section 13.5 TPM_TRANSPORT_AUTH structure
+///
+typedef struct tdTPM_TRANSPORT_AUTH {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_AUTHDATA                    authData;
+} TPM_TRANSPORT_AUTH;
+
+//
+// Part 2, section 14: Audit Structures
+//
+
+///
+/// Part 2, section 14.1 TPM_AUDIT_EVENT_IN structure
+///
+typedef struct tdTPM_AUDIT_EVENT_IN {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_DIGEST                      inputParms;
+  TPM_COUNTER_VALUE               auditCount;
+} TPM_AUDIT_EVENT_IN;
+
+///
+/// Part 2, section 14.2 TPM_AUDIT_EVENT_OUT structure
+///
+typedef struct tdTPM_AUDIT_EVENT_OUT {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_COMMAND_CODE                ordinal;
+  TPM_DIGEST                      outputParms;
+  TPM_COUNTER_VALUE               auditCount;
+  TPM_RESULT                      returnCode;
+} TPM_AUDIT_EVENT_OUT;
+
+//
+// Part 2, section 16: Return Codes
+//
+
+#define TPM_VENDOR_ERROR            TPM_Vendor_Specific32
+#define TPM_NON_FATAL               0x00000800
+
+#define TPM_SUCCESS                 ((TPM_RESULT) TPM_BASE)
+#define TPM_AUTHFAIL                ((TPM_RESULT) (TPM_BASE + 1))
+#define TPM_BADINDEX                ((TPM_RESULT) (TPM_BASE + 2))
+#define TPM_BAD_PARAMETER           ((TPM_RESULT) (TPM_BASE + 3))
+#define TPM_AUDITFAILURE            ((TPM_RESULT) (TPM_BASE + 4))
+#define TPM_CLEAR_DISABLED          ((TPM_RESULT) (TPM_BASE + 5))
+#define TPM_DEACTIVATED             ((TPM_RESULT) (TPM_BASE + 6))
+#define TPM_DISABLED                ((TPM_RESULT) (TPM_BASE + 7))
+#define TPM_DISABLED_CMD            ((TPM_RESULT) (TPM_BASE + 8))
+#define TPM_FAIL                    ((TPM_RESULT) (TPM_BASE + 9))
+#define TPM_BAD_ORDINAL             ((TPM_RESULT) (TPM_BASE + 10))
+#define TPM_INSTALL_DISABLED        ((TPM_RESULT) (TPM_BASE + 11))
+#define TPM_INVALID_KEYHANDLE       ((TPM_RESULT) (TPM_BASE + 12))
+#define TPM_KEYNOTFOUND             ((TPM_RESULT) (TPM_BASE + 13))
+#define TPM_INAPPROPRIATE_ENC       ((TPM_RESULT) (TPM_BASE + 14))
+#define TPM_MIGRATEFAIL             ((TPM_RESULT) (TPM_BASE + 15))
+#define TPM_INVALID_PCR_INFO        ((TPM_RESULT) (TPM_BASE + 16))
+#define TPM_NOSPACE                 ((TPM_RESULT) (TPM_BASE + 17))
+#define TPM_NOSRK                   ((TPM_RESULT) (TPM_BASE + 18))
+#define TPM_NOTSEALED_BLOB          ((TPM_RESULT) (TPM_BASE + 19))
+#define TPM_OWNER_SET               ((TPM_RESULT) (TPM_BASE + 20))
+#define TPM_RESOURCES               ((TPM_RESULT) (TPM_BASE + 21))
+#define TPM_SHORTRANDOM             ((TPM_RESULT) (TPM_BASE + 22))
+#define TPM_SIZE                    ((TPM_RESULT) (TPM_BASE + 23))
+#define TPM_WRONGPCRVAL             ((TPM_RESULT) (TPM_BASE + 24))
+#define TPM_BAD_PARAM_SIZE          ((TPM_RESULT) (TPM_BASE + 25))
+#define TPM_SHA_THREAD              ((TPM_RESULT) (TPM_BASE + 26))
+#define TPM_SHA_ERROR               ((TPM_RESULT) (TPM_BASE + 27))
+#define TPM_FAILEDSELFTEST          ((TPM_RESULT) (TPM_BASE + 28))
+#define TPM_AUTH2FAIL               ((TPM_RESULT) (TPM_BASE + 29))
+#define TPM_BADTAG                  ((TPM_RESULT) (TPM_BASE + 30))
+#define TPM_IOERROR                 ((TPM_RESULT) (TPM_BASE + 31))
+#define TPM_ENCRYPT_ERROR           ((TPM_RESULT) (TPM_BASE + 32))
+#define TPM_DECRYPT_ERROR           ((TPM_RESULT) (TPM_BASE + 33))
+#define TPM_INVALID_AUTHHANDLE      ((TPM_RESULT) (TPM_BASE + 34))
+#define TPM_NO_ENDORSEMENT          ((TPM_RESULT) (TPM_BASE + 35))
+#define TPM_INVALID_KEYUSAGE        ((TPM_RESULT) (TPM_BASE + 36))
+#define TPM_WRONG_ENTITYTYPE        ((TPM_RESULT) (TPM_BASE + 37))
+#define TPM_INVALID_POSTINIT        ((TPM_RESULT) (TPM_BASE + 38))
+#define TPM_INAPPROPRIATE_SIG       ((TPM_RESULT) (TPM_BASE + 39))
+#define TPM_BAD_KEY_PROPERTY        ((TPM_RESULT) (TPM_BASE + 40))
+#define TPM_BAD_MIGRATION           ((TPM_RESULT) (TPM_BASE + 41))
+#define TPM_BAD_SCHEME              ((TPM_RESULT) (TPM_BASE + 42))
+#define TPM_BAD_DATASIZE            ((TPM_RESULT) (TPM_BASE + 43))
+#define TPM_BAD_MODE                ((TPM_RESULT) (TPM_BASE + 44))
+#define TPM_BAD_PRESENCE            ((TPM_RESULT) (TPM_BASE + 45))
+#define TPM_BAD_VERSION             ((TPM_RESULT) (TPM_BASE + 46))
+#define TPM_NO_WRAP_TRANSPORT       ((TPM_RESULT) (TPM_BASE + 47))
+#define TPM_AUDITFAIL_UNSUCCESSFUL  ((TPM_RESULT) (TPM_BASE + 48))
+#define TPM_AUDITFAIL_SUCCESSFUL    ((TPM_RESULT) (TPM_BASE + 49))
+#define TPM_NOTRESETABLE            ((TPM_RESULT) (TPM_BASE + 50))
+#define TPM_NOTLOCAL                ((TPM_RESULT) (TPM_BASE + 51))
+#define TPM_BAD_TYPE                ((TPM_RESULT) (TPM_BASE + 52))
+#define TPM_INVALID_RESOURCE        ((TPM_RESULT) (TPM_BASE + 53))
+#define TPM_NOTFIPS                 ((TPM_RESULT) (TPM_BASE + 54))
+#define TPM_INVALID_FAMILY          ((TPM_RESULT) (TPM_BASE + 55))
+#define TPM_NO_NV_PERMISSION        ((TPM_RESULT) (TPM_BASE + 56))
+#define TPM_REQUIRES_SIGN           ((TPM_RESULT) (TPM_BASE + 57))
+#define TPM_KEY_NOTSUPPORTED        ((TPM_RESULT) (TPM_BASE + 58))
+#define TPM_AUTH_CONFLICT           ((TPM_RESULT) (TPM_BASE + 59))
+#define TPM_AREA_LOCKED             ((TPM_RESULT) (TPM_BASE + 60))
+#define TPM_BAD_LOCALITY            ((TPM_RESULT) (TPM_BASE + 61))
+#define TPM_READ_ONLY               ((TPM_RESULT) (TPM_BASE + 62))
+#define TPM_PER_NOWRITE             ((TPM_RESULT) (TPM_BASE + 63))
+#define TPM_FAMILYCOUNT             ((TPM_RESULT) (TPM_BASE + 64))
+#define TPM_WRITE_LOCKED            ((TPM_RESULT) (TPM_BASE + 65))
+#define TPM_BAD_ATTRIBUTES          ((TPM_RESULT) (TPM_BASE + 66))
+#define TPM_INVALID_STRUCTURE       ((TPM_RESULT) (TPM_BASE + 67))
+#define TPM_KEY_OWNER_CONTROL       ((TPM_RESULT) (TPM_BASE + 68))
+#define TPM_BAD_COUNTER             ((TPM_RESULT) (TPM_BASE + 69))
+#define TPM_NOT_FULLWRITE           ((TPM_RESULT) (TPM_BASE + 70))
+#define TPM_CONTEXT_GAP             ((TPM_RESULT) (TPM_BASE + 71))
+#define TPM_MAXNVWRITES             ((TPM_RESULT) (TPM_BASE + 72))
+#define TPM_NOOPERATOR              ((TPM_RESULT) (TPM_BASE + 73))
+#define TPM_RESOURCEMISSING         ((TPM_RESULT) (TPM_BASE + 74))
+#define TPM_DELEGATE_LOCK           ((TPM_RESULT) (TPM_BASE + 75))
+#define TPM_DELEGATE_FAMILY         ((TPM_RESULT) (TPM_BASE + 76))
+#define TPM_DELEGATE_ADMIN          ((TPM_RESULT) (TPM_BASE + 77))
+#define TPM_TRANSPORT_NOTEXCLUSIVE  ((TPM_RESULT) (TPM_BASE + 78))
+#define TPM_OWNER_CONTROL           ((TPM_RESULT) (TPM_BASE + 79))
+#define TPM_DAA_RESOURCES           ((TPM_RESULT) (TPM_BASE + 80))
+#define TPM_DAA_INPUT_DATA0         ((TPM_RESULT) (TPM_BASE + 81))
+#define TPM_DAA_INPUT_DATA1         ((TPM_RESULT) (TPM_BASE + 82))
+#define TPM_DAA_ISSUER_SETTINGS     ((TPM_RESULT) (TPM_BASE + 83))
+#define TPM_DAA_TPM_SETTINGS        ((TPM_RESULT) (TPM_BASE + 84))
+#define TPM_DAA_STAGE               ((TPM_RESULT) (TPM_BASE + 85))
+#define TPM_DAA_ISSUER_VALIDITY     ((TPM_RESULT) (TPM_BASE + 86))
+#define TPM_DAA_WRONG_W             ((TPM_RESULT) (TPM_BASE + 87))
+#define TPM_BAD_HANDLE              ((TPM_RESULT) (TPM_BASE + 88))
+#define TPM_BAD_DELEGATE            ((TPM_RESULT) (TPM_BASE + 89))
+#define TPM_BADCONTEXT              ((TPM_RESULT) (TPM_BASE + 90))
+#define TPM_TOOMANYCONTEXTS         ((TPM_RESULT) (TPM_BASE + 91))
+#define TPM_MA_TICKET_SIGNATURE     ((TPM_RESULT) (TPM_BASE + 92))
+#define TPM_MA_DESTINATION          ((TPM_RESULT) (TPM_BASE + 93))
+#define TPM_MA_SOURCE               ((TPM_RESULT) (TPM_BASE + 94))
+#define TPM_MA_AUTHORITY            ((TPM_RESULT) (TPM_BASE + 95))
+#define TPM_PERMANENTEK             ((TPM_RESULT) (TPM_BASE + 97))
+#define TPM_BAD_SIGNATURE           ((TPM_RESULT) (TPM_BASE + 98))
+#define TPM_NOCONTEXTSPACE          ((TPM_RESULT) (TPM_BASE + 99))
+
+#define TPM_RETRY                   ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL))
+#define TPM_NEEDS_SELFTEST          ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 1))
+#define TPM_DOING_SELFTEST          ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 2))
+#define TPM_DEFEND_LOCK_RUNNING     ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 3))
+
+//
+// Part 2, section 17: Ordinals
+//
+// Ordinals are 32 bit values. The upper byte contains values that serve as
+// flag indicators, the next byte contains values indicating what committee
+// designated the ordinal, and the final two bytes contain the Command
+// Ordinal Index.
+//      3                   2                   1
+//    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+//   +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+//   |P|C|V| Reserved| Purview |     Command Ordinal Index           |
+//   +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+//
+//  Where:
+//
+//    * P is Protected/Unprotected command. When 0 the command is a Protected
+//      command, when 1 the command is an Unprotected command.
+//
+//    * C is Non-Connection/Connection related command. When 0 this command
+//      passes through to either the protected (TPM) or unprotected (TSS)
+//      components.
+//
+//    * V is TPM/Vendor command. When 0 the command is TPM defined, when 1 the
+//      command is vendor defined.
+//
+//    * All reserved area bits are set to 0.
+//
+
+#define TPM_ORD_ActivateIdentity                  ((TPM_COMMAND_CODE) 0x0000007A)
+#define TPM_ORD_AuthorizeMigrationKey             ((TPM_COMMAND_CODE) 0x0000002B)
+#define TPM_ORD_CertifyKey                        ((TPM_COMMAND_CODE) 0x00000032)
+#define TPM_ORD_CertifyKey2                       ((TPM_COMMAND_CODE) 0x00000033)
+#define TPM_ORD_CertifySelfTest                   ((TPM_COMMAND_CODE) 0x00000052)
+#define TPM_ORD_ChangeAuth                        ((TPM_COMMAND_CODE) 0x0000000C)
+#define TPM_ORD_ChangeAuthAsymFinish              ((TPM_COMMAND_CODE) 0x0000000F)
+#define TPM_ORD_ChangeAuthAsymStart               ((TPM_COMMAND_CODE) 0x0000000E)
+#define TPM_ORD_ChangeAuthOwner                   ((TPM_COMMAND_CODE) 0x00000010)
+#define TPM_ORD_CMK_ApproveMA                     ((TPM_COMMAND_CODE) 0x0000001D)
+#define TPM_ORD_CMK_ConvertMigration              ((TPM_COMMAND_CODE) 0x00000024)
+#define TPM_ORD_CMK_CreateBlob                    ((TPM_COMMAND_CODE) 0x0000001B)
+#define TPM_ORD_CMK_CreateKey                     ((TPM_COMMAND_CODE) 0x00000013)
+#define TPM_ORD_CMK_CreateTicket                  ((TPM_COMMAND_CODE) 0x00000012)
+#define TPM_ORD_CMK_SetRestrictions               ((TPM_COMMAND_CODE) 0x0000001C)
+#define TPM_ORD_ContinueSelfTest                  ((TPM_COMMAND_CODE) 0x00000053)
+#define TPM_ORD_ConvertMigrationBlob              ((TPM_COMMAND_CODE) 0x0000002A)
+#define TPM_ORD_CreateCounter                     ((TPM_COMMAND_CODE) 0x000000DC)
+#define TPM_ORD_CreateEndorsementKeyPair          ((TPM_COMMAND_CODE) 0x00000078)
+#define TPM_ORD_CreateMaintenanceArchive          ((TPM_COMMAND_CODE) 0x0000002C)
+#define TPM_ORD_CreateMigrationBlob               ((TPM_COMMAND_CODE) 0x00000028)
+#define TPM_ORD_CreateRevocableEK                 ((TPM_COMMAND_CODE) 0x0000007F)
+#define TPM_ORD_CreateWrapKey                     ((TPM_COMMAND_CODE) 0x0000001F)
+#define TPM_ORD_DAA_JOIN                          ((TPM_COMMAND_CODE) 0x00000029)
+#define TPM_ORD_DAA_SIGN                          ((TPM_COMMAND_CODE) 0x00000031)
+#define TPM_ORD_Delegate_CreateKeyDelegation      ((TPM_COMMAND_CODE) 0x000000D4)
+#define TPM_ORD_Delegate_CreateOwnerDelegation    ((TPM_COMMAND_CODE) 0x000000D5)
+#define TPM_ORD_Delegate_LoadOwnerDelegation      ((TPM_COMMAND_CODE) 0x000000D8)
+#define TPM_ORD_Delegate_Manage                   ((TPM_COMMAND_CODE) 0x000000D2)
+#define TPM_ORD_Delegate_ReadTable                ((TPM_COMMAND_CODE) 0x000000DB)
+#define TPM_ORD_Delegate_UpdateVerification       ((TPM_COMMAND_CODE) 0x000000D1)
+#define TPM_ORD_Delegate_VerifyDelegation         ((TPM_COMMAND_CODE) 0x000000D6)
+#define TPM_ORD_DirRead                           ((TPM_COMMAND_CODE) 0x0000001A)
+#define TPM_ORD_DirWriteAuth                      ((TPM_COMMAND_CODE) 0x00000019)
+#define TPM_ORD_DisableForceClear                 ((TPM_COMMAND_CODE) 0x0000005E)
+#define TPM_ORD_DisableOwnerClear                 ((TPM_COMMAND_CODE) 0x0000005C)
+#define TPM_ORD_DisablePubekRead                  ((TPM_COMMAND_CODE) 0x0000007E)
+#define TPM_ORD_DSAP                              ((TPM_COMMAND_CODE) 0x00000011)
+#define TPM_ORD_EstablishTransport                ((TPM_COMMAND_CODE) 0x000000E6)
+#define TPM_ORD_EvictKey                          ((TPM_COMMAND_CODE) 0x00000022)
+#define TPM_ORD_ExecuteTransport                  ((TPM_COMMAND_CODE) 0x000000E7)
+#define TPM_ORD_Extend                            ((TPM_COMMAND_CODE) 0x00000014)
+#define TPM_ORD_FieldUpgrade                      ((TPM_COMMAND_CODE) 0x000000AA)
+#define TPM_ORD_FlushSpecific                     ((TPM_COMMAND_CODE) 0x000000BA)
+#define TPM_ORD_ForceClear                        ((TPM_COMMAND_CODE) 0x0000005D)
+#define TPM_ORD_GetAuditDigest                    ((TPM_COMMAND_CODE) 0x00000085)
+#define TPM_ORD_GetAuditDigestSigned              ((TPM_COMMAND_CODE) 0x00000086)
+#define TPM_ORD_GetAuditEvent                     ((TPM_COMMAND_CODE) 0x00000082)
+#define TPM_ORD_GetAuditEventSigned               ((TPM_COMMAND_CODE) 0x00000083)
+#define TPM_ORD_GetCapability                     ((TPM_COMMAND_CODE) 0x00000065)
+#define TPM_ORD_GetCapabilityOwner                ((TPM_COMMAND_CODE) 0x00000066)
+#define TPM_ORD_GetCapabilitySigned               ((TPM_COMMAND_CODE) 0x00000064)
+#define TPM_ORD_GetOrdinalAuditStatus             ((TPM_COMMAND_CODE) 0x0000008C)
+#define TPM_ORD_GetPubKey                         ((TPM_COMMAND_CODE) 0x00000021)
+#define TPM_ORD_GetRandom                         ((TPM_COMMAND_CODE) 0x00000046)
+#define TPM_ORD_GetTestResult                     ((TPM_COMMAND_CODE) 0x00000054)
+#define TPM_ORD_GetTicks                          ((TPM_COMMAND_CODE) 0x000000F1)
+#define TPM_ORD_IncrementCounter                  ((TPM_COMMAND_CODE) 0x000000DD)
+#define TPM_ORD_Init                              ((TPM_COMMAND_CODE) 0x00000097)
+#define TPM_ORD_KeyControlOwner                   ((TPM_COMMAND_CODE) 0x00000023)
+#define TPM_ORD_KillMaintenanceFeature            ((TPM_COMMAND_CODE) 0x0000002E)
+#define TPM_ORD_LoadAuthContext                   ((TPM_COMMAND_CODE) 0x000000B7)
+#define TPM_ORD_LoadContext                       ((TPM_COMMAND_CODE) 0x000000B9)
+#define TPM_ORD_LoadKey                           ((TPM_COMMAND_CODE) 0x00000020)
+#define TPM_ORD_LoadKey2                          ((TPM_COMMAND_CODE) 0x00000041)
+#define TPM_ORD_LoadKeyContext                    ((TPM_COMMAND_CODE) 0x000000B5)
+#define TPM_ORD_LoadMaintenanceArchive            ((TPM_COMMAND_CODE) 0x0000002D)
+#define TPM_ORD_LoadManuMaintPub                  ((TPM_COMMAND_CODE) 0x0000002F)
+#define TPM_ORD_MakeIdentity                      ((TPM_COMMAND_CODE) 0x00000079)
+#define TPM_ORD_MigrateKey                        ((TPM_COMMAND_CODE) 0x00000025)
+#define TPM_ORD_NV_DefineSpace                    ((TPM_COMMAND_CODE) 0x000000CC)
+#define TPM_ORD_NV_ReadValue                      ((TPM_COMMAND_CODE) 0x000000CF)
+#define TPM_ORD_NV_ReadValueAuth                  ((TPM_COMMAND_CODE) 0x000000D0)
+#define TPM_ORD_NV_WriteValue                     ((TPM_COMMAND_CODE) 0x000000CD)
+#define TPM_ORD_NV_WriteValueAuth                 ((TPM_COMMAND_CODE) 0x000000CE)
+#define TPM_ORD_OIAP                              ((TPM_COMMAND_CODE) 0x0000000A)
+#define TPM_ORD_OSAP                              ((TPM_COMMAND_CODE) 0x0000000B)
+#define TPM_ORD_OwnerClear                        ((TPM_COMMAND_CODE) 0x0000005B)
+#define TPM_ORD_OwnerReadInternalPub              ((TPM_COMMAND_CODE) 0x00000081)
+#define TPM_ORD_OwnerReadPubek                    ((TPM_COMMAND_CODE) 0x0000007D)
+#define TPM_ORD_OwnerSetDisable                   ((TPM_COMMAND_CODE) 0x0000006E)
+#define TPM_ORD_PCR_Reset                         ((TPM_COMMAND_CODE) 0x000000C8)
+#define TPM_ORD_PcrRead                           ((TPM_COMMAND_CODE) 0x00000015)
+#define TPM_ORD_PhysicalDisable                   ((TPM_COMMAND_CODE) 0x00000070)
+#define TPM_ORD_PhysicalEnable                    ((TPM_COMMAND_CODE) 0x0000006F)
+#define TPM_ORD_PhysicalSetDeactivated            ((TPM_COMMAND_CODE) 0x00000072)
+#define TPM_ORD_Quote                             ((TPM_COMMAND_CODE) 0x00000016)
+#define TPM_ORD_Quote2                            ((TPM_COMMAND_CODE) 0x0000003E)
+#define TPM_ORD_ReadCounter                       ((TPM_COMMAND_CODE) 0x000000DE)
+#define TPM_ORD_ReadManuMaintPub                  ((TPM_COMMAND_CODE) 0x00000030)
+#define TPM_ORD_ReadPubek                         ((TPM_COMMAND_CODE) 0x0000007C)
+#define TPM_ORD_ReleaseCounter                    ((TPM_COMMAND_CODE) 0x000000DF)
+#define TPM_ORD_ReleaseCounterOwner               ((TPM_COMMAND_CODE) 0x000000E0)
+#define TPM_ORD_ReleaseTransportSigned            ((TPM_COMMAND_CODE) 0x000000E8)
+#define TPM_ORD_Reset                             ((TPM_COMMAND_CODE) 0x0000005A)
+#define TPM_ORD_ResetLockValue                    ((TPM_COMMAND_CODE) 0x00000040)
+#define TPM_ORD_RevokeTrust                       ((TPM_COMMAND_CODE) 0x00000080)
+#define TPM_ORD_SaveAuthContext                   ((TPM_COMMAND_CODE) 0x000000B6)
+#define TPM_ORD_SaveContext                       ((TPM_COMMAND_CODE) 0x000000B8)
+#define TPM_ORD_SaveKeyContext                    ((TPM_COMMAND_CODE) 0x000000B4)
+#define TPM_ORD_SaveState                         ((TPM_COMMAND_CODE) 0x00000098)
+#define TPM_ORD_Seal                              ((TPM_COMMAND_CODE) 0x00000017)
+#define TPM_ORD_Sealx                             ((TPM_COMMAND_CODE) 0x0000003D)
+#define TPM_ORD_SelfTestFull                      ((TPM_COMMAND_CODE) 0x00000050)
+#define TPM_ORD_SetCapability                     ((TPM_COMMAND_CODE) 0x0000003F)
+#define TPM_ORD_SetOperatorAuth                   ((TPM_COMMAND_CODE) 0x00000074)
+#define TPM_ORD_SetOrdinalAuditStatus             ((TPM_COMMAND_CODE) 0x0000008D)
+#define TPM_ORD_SetOwnerInstall                   ((TPM_COMMAND_CODE) 0x00000071)
+#define TPM_ORD_SetOwnerPointer                   ((TPM_COMMAND_CODE) 0x00000075)
+#define TPM_ORD_SetRedirection                    ((TPM_COMMAND_CODE) 0x0000009A)
+#define TPM_ORD_SetTempDeactivated                ((TPM_COMMAND_CODE) 0x00000073)
+#define TPM_ORD_SHA1Complete                      ((TPM_COMMAND_CODE) 0x000000A2)
+#define TPM_ORD_SHA1CompleteExtend                ((TPM_COMMAND_CODE) 0x000000A3)
+#define TPM_ORD_SHA1Start                         ((TPM_COMMAND_CODE) 0x000000A0)
+#define TPM_ORD_SHA1Update                        ((TPM_COMMAND_CODE) 0x000000A1)
+#define TPM_ORD_Sign                              ((TPM_COMMAND_CODE) 0x0000003C)
+#define TPM_ORD_Startup                           ((TPM_COMMAND_CODE) 0x00000099)
+#define TPM_ORD_StirRandom                        ((TPM_COMMAND_CODE) 0x00000047)
+#define TPM_ORD_TakeOwnership                     ((TPM_COMMAND_CODE) 0x0000000D)
+#define TPM_ORD_Terminate_Handle                  ((TPM_COMMAND_CODE) 0x00000096)
+#define TPM_ORD_TickStampBlob                     ((TPM_COMMAND_CODE) 0x000000F2)
+#define TPM_ORD_UnBind                            ((TPM_COMMAND_CODE) 0x0000001E)
+#define TPM_ORD_Unseal                            ((TPM_COMMAND_CODE) 0x00000018)
+#define TSC_ORD_PhysicalPresence                  ((TPM_COMMAND_CODE) 0x4000000A)
+#define TSC_ORD_ResetEstablishmentBit             ((TPM_COMMAND_CODE) 0x4000000B)
+
+//
+// Part 2, section 18: Context structures
+//
+
+///
+/// Part 2, section 18.1: TPM_CONTEXT_BLOB
+///
+typedef struct tdTPM_CONTEXT_BLOB {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_RESOURCE_TYPE               resourceType;
+  TPM_HANDLE                      handle;
+  UINT8                           label[16];
+  UINT32                          contextCount;
+  TPM_DIGEST                      integrityDigest;
+  UINT32                          additionalSize;
+  UINT8                           *additionalData;
+  UINT32                          sensitiveSize;
+  UINT8                           *sensitiveData;
+} TPM_CONTEXT_BLOB;
+
+///
+/// Part 2, section 18.2 TPM_CONTEXT_SENSITIVE
+///
+typedef struct tdTPM_CONTEXT_SENSITIVE {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_NONCE                       contextNonce;
+  UINT32                          internalSize;
+  UINT8                           *internalData;
+} TPM_CONTEXT_SENSITIVE;
+
+//
+// Part 2, section 19: NV Structures
+//
+
+//
+// Part 2, section 19.1.1: Required TPM_NV_INDEX values
+//
+#define TPM_NV_INDEX_LOCK              ((UINT32)0xffffffff)
+#define TPM_NV_INDEX0                  ((UINT32)0x00000000)
+#define TPM_NV_INDEX_DIR               ((UINT32)0x10000001)
+#define TPM_NV_INDEX_EKCert            ((UINT32)0x0000f000)
+#define TPM_NV_INDEX_TPM_CC            ((UINT32)0x0000f001)
+#define TPM_NV_INDEX_PlatformCert      ((UINT32)0x0000f002)
+#define TPM_NV_INDEX_Platform_CC       ((UINT32)0x0000f003)
+//
+// Part 2, section 19.1.2: Reserved Index values
+//
+#define TPM_NV_INDEX_TSS_BASE          ((UINT32)0x00011100)
+#define TPM_NV_INDEX_PC_BASE           ((UINT32)0x00011200)
+#define TPM_NV_INDEX_SERVER_BASE       ((UINT32)0x00011300)
+#define TPM_NV_INDEX_MOBILE_BASE       ((UINT32)0x00011400)
+#define TPM_NV_INDEX_PERIPHERAL_BASE   ((UINT32)0x00011500)
+#define TPM_NV_INDEX_GROUP_RESV_BASE   ((UINT32)0x00010000)
+
+///
+/// Part 2, section 19.2: TPM_NV_ATTRIBUTES
+///
+typedef struct tdTPM_NV_ATTRIBUTES {
+  TPM_STRUCTURE_TAG               tag;
+  UINT32                          attributes;
+} TPM_NV_ATTRIBUTES;
+
+#define TPM_NV_PER_READ_STCLEAR        (BIT31)
+#define TPM_NV_PER_AUTHREAD            (BIT18)
+#define TPM_NV_PER_OWNERREAD           (BIT17)
+#define TPM_NV_PER_PPREAD              (BIT16)
+#define TPM_NV_PER_GLOBALLOCK          (BIT15)
+#define TPM_NV_PER_WRITE_STCLEAR       (BIT14)
+#define TPM_NV_PER_WRITEDEFINE         (BIT13)
+#define TPM_NV_PER_WRITEALL            (BIT12)
+#define TPM_NV_PER_AUTHWRITE           (BIT2)
+#define TPM_NV_PER_OWNERWRITE          (BIT1)
+#define TPM_NV_PER_PPWRITE             (BIT0)
+
+///
+/// Part 2, section 19.3: TPM_NV_DATA_PUBLIC
+///
+typedef struct tdTPM_NV_DATA_PUBLIC {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_NV_INDEX                    nvIndex;
+  TPM_PCR_INFO_SHORT              pcrInfoRead;
+  TPM_PCR_INFO_SHORT              pcrInfoWrite;
+  TPM_NV_ATTRIBUTES               permission;
+  BOOLEAN                         bReadSTClear;
+  BOOLEAN                         bWriteSTClear;
+  BOOLEAN                         bWriteDefine;
+  UINT32                          dataSize;
+} TPM_NV_DATA_PUBLIC;
+
+//
+// Part 2, section 20: Delegate Structures
+//
+
+#define TPM_DEL_OWNER_BITS          ((UINT32)0x00000001)
+#define TPM_DEL_KEY_BITS            ((UINT32)0x00000002)
+///
+/// Part 2, section 20.2: Delegate Definitions
+///
+typedef struct tdTPM_DELEGATIONS {
+  TPM_STRUCTURE_TAG               tag;
+  UINT32                          delegateType;
+  UINT32                          per1;
+  UINT32                          per2;
+} TPM_DELEGATIONS;
+
+//
+// Part 2, section 20.2.1: Owner Permission Settings
+//
+#define TPM_DELEGATE_SetOrdinalAuditStatus          (BIT30)
+#define TPM_DELEGATE_DirWriteAuth                   (BIT29)
+#define TPM_DELEGATE_CMK_ApproveMA                  (BIT28)
+#define TPM_DELEGATE_NV_WriteValue                  (BIT27)
+#define TPM_DELEGATE_CMK_CreateTicket               (BIT26)
+#define TPM_DELEGATE_NV_ReadValue                   (BIT25)
+#define TPM_DELEGATE_Delegate_LoadOwnerDelegation   (BIT24)
+#define TPM_DELEGATE_DAA_Join                       (BIT23)
+#define TPM_DELEGATE_AuthorizeMigrationKey          (BIT22)
+#define TPM_DELEGATE_CreateMaintenanceArchive       (BIT21)
+#define TPM_DELEGATE_LoadMaintenanceArchive         (BIT20)
+#define TPM_DELEGATE_KillMaintenanceFeature         (BIT19)
+#define TPM_DELEGATE_OwnerReadInteralPub            (BIT18)
+#define TPM_DELEGATE_ResetLockValue                 (BIT17)
+#define TPM_DELEGATE_OwnerClear                     (BIT16)
+#define TPM_DELEGATE_DisableOwnerClear              (BIT15)
+#define TPM_DELEGATE_NV_DefineSpace                 (BIT14)
+#define TPM_DELEGATE_OwnerSetDisable                (BIT13)
+#define TPM_DELEGATE_SetCapability                  (BIT12)
+#define TPM_DELEGATE_MakeIdentity                   (BIT11)
+#define TPM_DELEGATE_ActivateIdentity               (BIT10)
+#define TPM_DELEGATE_OwnerReadPubek                 (BIT9)
+#define TPM_DELEGATE_DisablePubekRead               (BIT8)
+#define TPM_DELEGATE_SetRedirection                 (BIT7)
+#define TPM_DELEGATE_FieldUpgrade                   (BIT6)
+#define TPM_DELEGATE_Delegate_UpdateVerification    (BIT5)
+#define TPM_DELEGATE_CreateCounter                  (BIT4)
+#define TPM_DELEGATE_ReleaseCounterOwner            (BIT3)
+#define TPM_DELEGATE_DelegateManage                 (BIT2)
+#define TPM_DELEGATE_Delegate_CreateOwnerDelegation (BIT1)
+#define TPM_DELEGATE_DAA_Sign                       (BIT0)
+
+//
+// Part 2, section 20.2.3: Key Permission settings
+//
+#define TPM_KEY_DELEGATE_CMK_ConvertMigration       (BIT28)
+#define TPM_KEY_DELEGATE_TickStampBlob              (BIT27)
+#define TPM_KEY_DELEGATE_ChangeAuthAsymStart        (BIT26)
+#define TPM_KEY_DELEGATE_ChangeAuthAsymFinish       (BIT25)
+#define TPM_KEY_DELEGATE_CMK_CreateKey              (BIT24)
+#define TPM_KEY_DELEGATE_MigrateKey                 (BIT23)
+#define TPM_KEY_DELEGATE_LoadKey2                   (BIT22)
+#define TPM_KEY_DELEGATE_EstablishTransport         (BIT21)
+#define TPM_KEY_DELEGATE_ReleaseTransportSigned     (BIT20)
+#define TPM_KEY_DELEGATE_Quote2                     (BIT19)
+#define TPM_KEY_DELEGATE_Sealx                      (BIT18)
+#define TPM_KEY_DELEGATE_MakeIdentity               (BIT17)
+#define TPM_KEY_DELEGATE_ActivateIdentity           (BIT16)
+#define TPM_KEY_DELEGATE_GetAuditDigestSigned       (BIT15)
+#define TPM_KEY_DELEGATE_Sign                       (BIT14)
+#define TPM_KEY_DELEGATE_CertifyKey2                (BIT13)
+#define TPM_KEY_DELEGATE_CertifyKey                 (BIT12)
+#define TPM_KEY_DELEGATE_CreateWrapKey              (BIT11)
+#define TPM_KEY_DELEGATE_CMK_CreateBlob             (BIT10)
+#define TPM_KEY_DELEGATE_CreateMigrationBlob        (BIT9)
+#define TPM_KEY_DELEGATE_ConvertMigrationBlob       (BIT8)
+#define TPM_KEY_DELEGATE_CreateKeyDelegation        (BIT7)
+#define TPM_KEY_DELEGATE_ChangeAuth                 (BIT6)
+#define TPM_KEY_DELEGATE_GetPubKey                  (BIT5)
+#define TPM_KEY_DELEGATE_UnBind                     (BIT4)
+#define TPM_KEY_DELEGATE_Quote                      (BIT3)
+#define TPM_KEY_DELEGATE_Unseal                     (BIT2)
+#define TPM_KEY_DELEGATE_Seal                       (BIT1)
+#define TPM_KEY_DELEGATE_LoadKey                    (BIT0)
+
+//
+// Part 2, section 20.3: TPM_FAMILY_FLAGS
+//
+#define TPM_DELEGATE_ADMIN_LOCK           (BIT1)
+#define TPM_FAMFLAG_ENABLE                (BIT0)
+
+///
+/// Part 2, section 20.4: TPM_FAMILY_LABEL
+///
+typedef struct tdTPM_FAMILY_LABEL {
+  UINT8                           label;
+} TPM_FAMILY_LABEL;
+
+///
+/// Part 2, section 20.5: TPM_FAMILY_TABLE_ENTRY
+///
+typedef struct tdTPM_FAMILY_TABLE_ENTRY {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_FAMILY_LABEL                label;
+  TPM_FAMILY_ID                   familyID;
+  TPM_FAMILY_VERIFICATION         verificationCount;
+  TPM_FAMILY_FLAGS                flags;
+} TPM_FAMILY_TABLE_ENTRY;
+
+//
+// Part 2, section 20.6: TPM_FAMILY_TABLE
+//
+#define TPM_NUM_FAMILY_TABLE_ENTRY_MIN 8
+
+typedef struct tdTPM_FAMILY_TABLE{
+  TPM_FAMILY_TABLE_ENTRY famTableRow[TPM_NUM_FAMILY_TABLE_ENTRY_MIN];
+} TPM_FAMILY_TABLE;
+
+///
+/// Part 2, section 20.7: TPM_DELEGATE_LABEL
+///
+typedef struct tdTPM_DELEGATE_LABEL {
+  UINT8                           label;
+} TPM_DELEGATE_LABEL;
+
+///
+/// Part 2, section 20.8: TPM_DELEGATE_PUBLIC
+///
+typedef struct tdTPM_DELEGATE_PUBLIC {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_DELEGATE_LABEL              label;
+  TPM_PCR_INFO_SHORT              pcrInfo;
+  TPM_DELEGATIONS                 permissions;
+  TPM_FAMILY_ID                   familyID;
+  TPM_FAMILY_VERIFICATION         verificationCount;
+} TPM_DELEGATE_PUBLIC;
+
+///
+/// Part 2, section 20.9: TPM_DELEGATE_TABLE_ROW
+///
+typedef struct tdTPM_DELEGATE_TABLE_ROW {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_DELEGATE_PUBLIC             pub;
+  TPM_SECRET                      authValue;
+} TPM_DELEGATE_TABLE_ROW;
+
+//
+// Part 2, section 20.10: TPM_DELEGATE_TABLE
+//
+#define TPM_NUM_DELEGATE_TABLE_ENTRY_MIN 2
+
+typedef struct tdTPM_DELEGATE_TABLE{
+  TPM_DELEGATE_TABLE_ROW delRow[TPM_NUM_DELEGATE_TABLE_ENTRY_MIN];
+} TPM_DELEGATE_TABLE;
+
+///
+/// Part 2, section 20.11: TPM_DELEGATE_SENSITIVE
+///
+typedef struct tdTPM_DELEGATE_SENSITIVE {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_SECRET                      authValue;
+} TPM_DELEGATE_SENSITIVE;
+
+///
+/// Part 2, section 20.12: TPM_DELEGATE_OWNER_BLOB
+///
+typedef struct tdTPM_DELEGATE_OWNER_BLOB {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_DELEGATE_PUBLIC             pub;
+  TPM_DIGEST                      integrityDigest;
+  UINT32                          additionalSize;
+  UINT8                           *additionalArea;
+  UINT32                          sensitiveSize;
+  UINT8                           *sensitiveArea;
+} TPM_DELEGATE_OWNER_BLOB;
+
+///
+/// Part 2, section 20.13: TTPM_DELEGATE_KEY_BLOB
+///
+typedef struct tdTPM_DELEGATE_KEY_BLOB {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_DELEGATE_PUBLIC             pub;
+  TPM_DIGEST                      integrityDigest;
+  TPM_DIGEST                      pubKeyDigest;
+  UINT32                          additionalSize;
+  UINT8                           *additionalArea;
+  UINT32                          sensitiveSize;
+  UINT8                           *sensitiveArea;
+} TPM_DELEGATE_KEY_BLOB;
+
+//
+// Part 2, section 20.14: TPM_FAMILY_OPERATION Values
+//
+#define TPM_FAMILY_CREATE                 ((UINT32)0x00000001)
+#define TPM_FAMILY_ENABLE                 ((UINT32)0x00000002)
+#define TPM_FAMILY_ADMIN                  ((UINT32)0x00000003)
+#define TPM_FAMILY_INVALIDATE             ((UINT32)0x00000004)
+
+//
+// Part 2, section 21.1: TPM_CAPABILITY_AREA for GetCapability
+//
+#define TPM_CAP_ORD                     ((TPM_CAPABILITY_AREA) 0x00000001)
+#define TPM_CAP_ALG                     ((TPM_CAPABILITY_AREA) 0x00000002)
+#define TPM_CAP_PID                     ((TPM_CAPABILITY_AREA) 0x00000003)
+#define TPM_CAP_FLAG                    ((TPM_CAPABILITY_AREA) 0x00000004)
+#define TPM_CAP_PROPERTY                ((TPM_CAPABILITY_AREA) 0x00000005)
+#define TPM_CAP_VERSION                 ((TPM_CAPABILITY_AREA) 0x00000006)
+#define TPM_CAP_KEY_HANDLE              ((TPM_CAPABILITY_AREA) 0x00000007)
+#define TPM_CAP_CHECK_LOADED            ((TPM_CAPABILITY_AREA) 0x00000008)
+#define TPM_CAP_SYM_MODE                ((TPM_CAPABILITY_AREA) 0x00000009)
+#define TPM_CAP_KEY_STATUS              ((TPM_CAPABILITY_AREA) 0x0000000C)
+#define TPM_CAP_NV_LIST                 ((TPM_CAPABILITY_AREA) 0x0000000D)
+#define TPM_CAP_MFR                     ((TPM_CAPABILITY_AREA) 0x00000010)
+#define TPM_CAP_NV_INDEX                ((TPM_CAPABILITY_AREA) 0x00000011)
+#define TPM_CAP_TRANS_ALG               ((TPM_CAPABILITY_AREA) 0x00000012)
+#define TPM_CAP_HANDLE                  ((TPM_CAPABILITY_AREA) 0x00000014)
+#define TPM_CAP_TRANS_ES                ((TPM_CAPABILITY_AREA) 0x00000015)
+#define TPM_CAP_AUTH_ENCRYPT            ((TPM_CAPABILITY_AREA) 0x00000017)
+#define TPM_CAP_SELECT_SIZE             ((TPM_CAPABILITY_AREA) 0x00000018)
+#define TPM_CAP_VERSION_VAL             ((TPM_CAPABILITY_AREA) 0x0000001A)
+
+#define TPM_CAP_FLAG_PERMANENT          ((TPM_CAPABILITY_AREA) 0x00000108)
+#define TPM_CAP_FLAG_VOLATILE           ((TPM_CAPABILITY_AREA) 0x00000109)
+
+//
+// Part 2, section 21.2: CAP_PROPERTY Subcap values for GetCapability
+//
+#define TPM_CAP_PROP_PCR                ((TPM_CAPABILITY_AREA) 0x00000101)
+#define TPM_CAP_PROP_DIR                ((TPM_CAPABILITY_AREA) 0x00000102)
+#define TPM_CAP_PROP_MANUFACTURER       ((TPM_CAPABILITY_AREA) 0x00000103)
+#define TPM_CAP_PROP_KEYS               ((TPM_CAPABILITY_AREA) 0x00000104)
+#define TPM_CAP_PROP_MIN_COUNTER        ((TPM_CAPABILITY_AREA) 0x00000107)
+#define TPM_CAP_PROP_AUTHSESS           ((TPM_CAPABILITY_AREA) 0x0000010A)
+#define TPM_CAP_PROP_TRANSESS           ((TPM_CAPABILITY_AREA) 0x0000010B)
+#define TPM_CAP_PROP_COUNTERS           ((TPM_CAPABILITY_AREA) 0x0000010C)
+#define TPM_CAP_PROP_MAX_AUTHSESS       ((TPM_CAPABILITY_AREA) 0x0000010D)
+#define TPM_CAP_PROP_MAX_TRANSESS       ((TPM_CAPABILITY_AREA) 0x0000010E)
+#define TPM_CAP_PROP_MAX_COUNTERS       ((TPM_CAPABILITY_AREA) 0x0000010F)
+#define TPM_CAP_PROP_MAX_KEYS           ((TPM_CAPABILITY_AREA) 0x00000110)
+#define TPM_CAP_PROP_OWNER              ((TPM_CAPABILITY_AREA) 0x00000111)
+#define TPM_CAP_PROP_CONTEXT            ((TPM_CAPABILITY_AREA) 0x00000112)
+#define TPM_CAP_PROP_MAX_CONTEXT        ((TPM_CAPABILITY_AREA) 0x00000113)
+#define TPM_CAP_PROP_FAMILYROWS         ((TPM_CAPABILITY_AREA) 0x00000114)
+#define TPM_CAP_PROP_TIS_TIMEOUT        ((TPM_CAPABILITY_AREA) 0x00000115)
+#define TPM_CAP_PROP_STARTUP_EFFECT     ((TPM_CAPABILITY_AREA) 0x00000116)
+#define TPM_CAP_PROP_DELEGATE_ROW       ((TPM_CAPABILITY_AREA) 0x00000117)
+#define TPM_CAP_PROP_DAA_MAX            ((TPM_CAPABILITY_AREA) 0x00000119)
+#define CAP_PROP_SESSION_DAA            ((TPM_CAPABILITY_AREA) 0x0000011A)
+#define TPM_CAP_PROP_CONTEXT_DIST       ((TPM_CAPABILITY_AREA) 0x0000011B)
+#define TPM_CAP_PROP_DAA_INTERRUPT      ((TPM_CAPABILITY_AREA) 0x0000011C)
+#define TPM_CAP_PROP_SESSIONS           ((TPM_CAPABILITY_AREA) 0x0000011D)
+#define TPM_CAP_PROP_MAX_SESSIONS       ((TPM_CAPABILITY_AREA) 0x0000011E)
+#define TPM_CAP_PROP_CMK_RESTRICTION    ((TPM_CAPABILITY_AREA) 0x0000011F)
+#define TPM_CAP_PROP_DURATION           ((TPM_CAPABILITY_AREA) 0x00000120)
+#define TPM_CAP_PROP_ACTIVE_COUNTER     ((TPM_CAPABILITY_AREA) 0x00000122)
+#define TPM_CAP_PROP_MAX_NV_AVAILABLE   ((TPM_CAPABILITY_AREA) 0x00000123)
+#define TPM_CAP_PROP_INPUT_BUFFER       ((TPM_CAPABILITY_AREA) 0x00000124)
+
+//
+// Part 2, section 21.4: TPM_CAPABILITY_AREA for SetCapability
+//
+#define TPM_SET_PERM_FLAGS              ((TPM_CAPABILITY_AREA) 0x00000001)
+#define TPM_SET_PERM_DATA               ((TPM_CAPABILITY_AREA) 0x00000002)
+#define TPM_SET_STCLEAR_FLAGS           ((TPM_CAPABILITY_AREA) 0x00000003)
+#define TPM_SET_STCLEAR_DATA            ((TPM_CAPABILITY_AREA) 0x00000004)
+#define TPM_SET_STANY_FLAGS             ((TPM_CAPABILITY_AREA) 0x00000005)
+#define TPM_SET_STANY_DATA              ((TPM_CAPABILITY_AREA) 0x00000006)
+
+///
+/// Part 2, section 21.6: TPM_CAP_VERSION_INFO
+///   [size_is(vendorSpecificSize)] BYTE* vendorSpecific;
+///
+typedef struct tdTPM_CAP_VERSION_INFO {
+  TPM_STRUCTURE_TAG                 tag;
+  TPM_VERSION                       version;
+  UINT16                            specLevel;
+  UINT8                             errataRev;
+  UINT8                             tpmVendorID[4];
+  UINT16                            vendorSpecificSize;
+  UINT8                             *vendorSpecific;
+} TPM_CAP_VERSION_INFO;
+
+///
+/// Part 2, section 21.10: TPM_DA_ACTION_TYPE
+///
+typedef struct tdTPM_DA_ACTION_TYPE {
+  TPM_STRUCTURE_TAG                 tag;
+  UINT32                            actions;
+} TPM_DA_ACTION_TYPE;
+
+#define TPM_DA_ACTION_FAILURE_MODE     (((UINT32)1)<<3)
+#define TPM_DA_ACTION_DEACTIVATE       (((UINT32)1)<<2)
+#define TPM_DA_ACTION_DISABLE          (((UINT32)1)<<1)
+#define TPM_DA_ACTION_TIMEOUT          (((UINT32)1)<<0)
+
+///
+/// Part 2, section 21.7: TPM_DA_INFO
+///
+typedef struct tdTPM_DA_INFO {
+  TPM_STRUCTURE_TAG                 tag;
+  TPM_DA_STATE                      state;
+  UINT16                            currentCount;
+  UINT16                            thresholdCount;
+  TPM_DA_ACTION_TYPE                actionAtThreshold;
+  UINT32                            actionDependValue;
+  UINT32                            vendorDataSize;
+  UINT8                             *vendorData;
+} TPM_DA_INFO;
+
+///
+/// Part 2, section 21.8: TPM_DA_INFO_LIMITED
+///
+typedef struct tdTPM_DA_INFO_LIMITED {
+  TPM_STRUCTURE_TAG                 tag;
+  TPM_DA_STATE                      state;
+  TPM_DA_ACTION_TYPE                actionAtThreshold;
+  UINT32                            vendorDataSize;
+  UINT8                             *vendorData;
+} TPM_DA_INFO_LIMITED;
+
+//
+// Part 2, section 21.9: CAP_PROPERTY Subcap values for GetCapability
+//
+#define TPM_DA_STATE_INACTIVE          ((UINT8)0x00)
+#define TPM_DA_STATE_ACTIVE            ((UINT8)0x01)
+
+//
+// Part 2, section 22: DAA Structures
+//
+
+//
+// Part 2, section 22.1: Size definitions
+//
+#define TPM_DAA_SIZE_r0                (43)
+#define TPM_DAA_SIZE_r1                (43)
+#define TPM_DAA_SIZE_r2                (128)
+#define TPM_DAA_SIZE_r3                (168)
+#define TPM_DAA_SIZE_r4                (219)
+#define TPM_DAA_SIZE_NT                (20)
+#define TPM_DAA_SIZE_v0                (128)
+#define TPM_DAA_SIZE_v1                (192)
+#define TPM_DAA_SIZE_NE                (256)
+#define TPM_DAA_SIZE_w                 (256)
+#define TPM_DAA_SIZE_issuerModulus     (256)
+//
+// Part 2, section 22.2: Constant definitions
+//
+#define TPM_DAA_power0                 (104)
+#define TPM_DAA_power1                 (1024)
+
+///
+/// Part 2, section 22.3: TPM_DAA_ISSUER
+///
+typedef struct tdTPM_DAA_ISSUER {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_DIGEST                      DAA_digest_R0;
+  TPM_DIGEST                      DAA_digest_R1;
+  TPM_DIGEST                      DAA_digest_S0;
+  TPM_DIGEST                      DAA_digest_S1;
+  TPM_DIGEST                      DAA_digest_n;
+  TPM_DIGEST                      DAA_digest_gamma;
+  UINT8                           DAA_generic_q[26];
+} TPM_DAA_ISSUER;
+
+///
+/// Part 2, section 22.4: TPM_DAA_TPM
+///
+typedef struct tdTPM_DAA_TPM {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_DIGEST                      DAA_digestIssuer;
+  TPM_DIGEST                      DAA_digest_v0;
+  TPM_DIGEST                      DAA_digest_v1;
+  TPM_DIGEST                      DAA_rekey;
+  UINT32                          DAA_count;
+} TPM_DAA_TPM;
+
+///
+/// Part 2, section 22.5: TPM_DAA_CONTEXT
+///
+typedef struct tdTPM_DAA_CONTEXT {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_DIGEST                      DAA_digestContext;
+  TPM_DIGEST                      DAA_digest;
+  TPM_DAA_CONTEXT_SEED            DAA_contextSeed;
+  UINT8                           DAA_scratch[256];
+  UINT8                           DAA_stage;
+} TPM_DAA_CONTEXT;
+
+///
+/// Part 2, section 22.6: TPM_DAA_JOINDATA
+///
+typedef struct tdTPM_DAA_JOINDATA {
+  UINT8                           DAA_join_u0[128];
+  UINT8                           DAA_join_u1[138];
+  TPM_DIGEST                      DAA_digest_n0;
+} TPM_DAA_JOINDATA;
+
+///
+/// Part 2, section 22.8: TPM_DAA_BLOB
+///
+typedef struct tdTPM_DAA_BLOB {
+  TPM_STRUCTURE_TAG               tag;
+  TPM_RESOURCE_TYPE               resourceType;
+  UINT8                           label[16];
+  TPM_DIGEST                      blobIntegrity;
+  UINT32                          additionalSize;
+  UINT8                           *additionalData;
+  UINT32                          sensitiveSize;
+  UINT8                           *sensitiveData;
+} TPM_DAA_BLOB;
+
+///
+/// Part 2, section 22.9: TPM_DAA_SENSITIVE
+///
+typedef struct tdTPM_DAA_SENSITIVE {
+  TPM_STRUCTURE_TAG               tag;
+  UINT32                          internalSize;
+  UINT8                           *internalData;
+} TPM_DAA_SENSITIVE;
+
+
+//
+// Part 2, section 23: Redirection
+//
+
+///
+/// Part 2 section 23.1: TPM_REDIR_COMMAND
+/// This section defines exactly one value but does not
+/// give it a name. The definition of TPM_SetRedirection in Part3
+/// refers to exactly one name but does not give its value. We join
+/// them here.
+///
+#define TPM_REDIR_GPIO              (0x00000001)
+
+///
+/// TPM Command Headers defined in Part 3
+///
+typedef struct tdTPM_RQU_COMMAND_HDR {
+  TPM_STRUCTURE_TAG                 tag;
+  UINT32                            paramSize;
+  TPM_COMMAND_CODE                  ordinal;
+} TPM_RQU_COMMAND_HDR;
+
+///
+/// TPM Response Headers defined in Part 3
+///
+typedef struct tdTPM_RSP_COMMAND_HDR {
+  TPM_STRUCTURE_TAG                 tag;
+  UINT32                            paramSize;
+  TPM_RESULT                        returnCode;
+} TPM_RSP_COMMAND_HDR;
+
+#pragma pack ()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tpm20.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tpm20.h
new file mode 100644
index 0000000000..697a2d7be4
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tpm20.h
@@ -0,0 +1,1820 @@
+/** @file
+  TPM2.0 Specification data structures
+  (Trusted Platform Module Library Specification, Family "2.0", Level 00, Revision 00.96,
+  @http://www.trustedcomputinggroup.org/resources/tpm_library_specification)
+
+  Check http://trustedcomputinggroup.org for latest specification updates.
+
+Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved. <BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#ifndef _TPM20_H_
+#define _TPM20_H_
+
+#include <IndustryStandard/Tpm12.h>
+
+#pragma pack (1)
+
+// Annex A Algorithm Constants
+
+// Table 205 - Defines for SHA1 Hash Values
+#define SHA1_DIGEST_SIZE 20
+#define SHA1_BLOCK_SIZE  64
+
+// Table 206 - Defines for SHA256 Hash Values
+#define SHA256_DIGEST_SIZE 32
+#define SHA256_BLOCK_SIZE  64
+
+// Table 207 - Defines for SHA384 Hash Values
+#define SHA384_DIGEST_SIZE 48
+#define SHA384_BLOCK_SIZE  128
+
+// Table 208 - Defines for SHA512 Hash Values
+#define SHA512_DIGEST_SIZE 64
+#define SHA512_BLOCK_SIZE  128
+
+// Table 209 - Defines for SM3_256 Hash Values
+#define SM3_256_DIGEST_SIZE 32
+#define SM3_256_BLOCK_SIZE  64
+
+// Table 210 - Defines for Architectural Limits Values
+#define MAX_SESSION_NUMBER 3
+
+// Annex B Implementation Definitions
+
+// Table 211 - Defines for Logic Values
+#define YES   1
+#define NO    0
+#define SET   1
+#define CLEAR 0
+
+// Table 215 - Defines for RSA Algorithm Constants
+#define MAX_RSA_KEY_BITS  2048
+#define MAX_RSA_KEY_BYTES ((MAX_RSA_KEY_BITS + 7) / 8)
+
+// Table 216 - Defines for ECC Algorithm Constants
+#define MAX_ECC_KEY_BITS  256
+#define MAX_ECC_KEY_BYTES ((MAX_ECC_KEY_BITS + 7) / 8)
+
+// Table 217 - Defines for AES Algorithm Constants
+#define MAX_AES_KEY_BITS         128
+#define MAX_AES_BLOCK_SIZE_BYTES 16
+#define MAX_AES_KEY_BYTES        ((MAX_AES_KEY_BITS + 7) / 8)
+
+// Table 218 - Defines for SM4 Algorithm Constants
+#define MAX_SM4_KEY_BITS         128
+#define MAX_SM4_BLOCK_SIZE_BYTES 16
+#define MAX_SM4_KEY_BYTES        ((MAX_SM4_KEY_BITS + 7) / 8)
+
+// Table 219 - Defines for Symmetric Algorithm Constants
+#define MAX_SYM_KEY_BITS   MAX_AES_KEY_BITS
+#define MAX_SYM_KEY_BYTES  MAX_AES_KEY_BYTES
+#define MAX_SYM_BLOCK_SIZE MAX_AES_BLOCK_SIZE_BYTES
+
+// Table 220 - Defines for Implementation Values
+typedef UINT16                        BSIZE;
+#define BUFFER_ALIGNMENT              4
+#define IMPLEMENTATION_PCR            24
+#define PLATFORM_PCR                  24
+#define DRTM_PCR                      17
+#define NUM_LOCALITIES                5
+#define MAX_HANDLE_NUM                3
+#define MAX_ACTIVE_SESSIONS           64
+typedef UINT16                        CONTEXT_SLOT;
+typedef UINT64                        CONTEXT_COUNTER;
+#define MAX_LOADED_SESSIONS           3
+#define MAX_SESSION_NUM               3
+#define MAX_LOADED_OBJECTS            3
+#define MIN_EVICT_OBJECTS             2
+#define PCR_SELECT_MIN                ((PLATFORM_PCR + 7) / 8)
+#define PCR_SELECT_MAX                ((IMPLEMENTATION_PCR + 7) / 8)
+#define NUM_POLICY_PCR_GROUP          1
+#define NUM_AUTHVALUE_PCR_GROUP       1
+#define MAX_CONTEXT_SIZE              4000
+#define MAX_DIGEST_BUFFER             1024
+#define MAX_NV_INDEX_SIZE             1024
+#define MAX_CAP_BUFFER                1024
+#define NV_MEMORY_SIZE                16384
+#define NUM_STATIC_PCR                16
+#define MAX_ALG_LIST_SIZE             64
+#define TIMER_PRESCALE                100000
+#define PRIMARY_SEED_SIZE             32
+#define CONTEXT_ENCRYPT_ALG           TPM_ALG_AES
+#define CONTEXT_ENCRYPT_KEY_BITS      MAX_SYM_KEY_BITS
+#define CONTEXT_ENCRYPT_KEY_BYTES     ((CONTEXT_ENCRYPT_KEY_BITS + 7) / 8)
+#define CONTEXT_INTEGRITY_HASH_ALG    TPM_ALG_SHA256
+#define CONTEXT_INTEGRITY_HASH_SIZE   SHA256_DIGEST_SIZE
+#define PROOF_SIZE                    CONTEXT_INTEGRITY_HASH_SIZE
+#define NV_CLOCK_UPDATE_INTERVAL      12
+#define NUM_POLICY_PCR                1
+#define MAX_COMMAND_SIZE              4096
+#define MAX_RESPONSE_SIZE             4096
+#define ORDERLY_BITS                  8
+#define MAX_ORDERLY_COUNT             ((1 << ORDERLY_BITS) - 1)
+#define ALG_ID_FIRST                  TPM_ALG_FIRST
+#define ALG_ID_LAST                   TPM_ALG_LAST
+#define MAX_SYM_DATA                  128
+#define MAX_RNG_ENTROPY_SIZE          64
+#define RAM_INDEX_SPACE               512
+#define RSA_DEFAULT_PUBLIC_EXPONENT   0x00010001
+#define CRT_FORMAT_RSA                YES
+#define PRIVATE_VENDOR_SPECIFIC_BYTES ((MAX_RSA_KEY_BYTES / 2) * ( 3 + CRT_FORMAT_RSA * 2))
+
+// Capability related MAX_ value
+#define MAX_CAP_DATA       (MAX_CAP_BUFFER - sizeof(TPM_CAP) - sizeof(UINT32))
+#define MAX_CAP_ALGS       (MAX_CAP_DATA / sizeof(TPMS_ALG_PROPERTY))
+#define MAX_CAP_HANDLES    (MAX_CAP_DATA / sizeof(TPM_HANDLE))
+#define MAX_CAP_CC         (MAX_CAP_DATA / sizeof(TPM_CC))
+#define MAX_TPM_PROPERTIES (MAX_CAP_DATA / sizeof(TPMS_TAGGED_PROPERTY))
+#define MAX_PCR_PROPERTIES (MAX_CAP_DATA / sizeof(TPMS_TAGGED_PCR_SELECT))
+#define MAX_ECC_CURVES     (MAX_CAP_DATA / sizeof(TPM_ECC_CURVE))
+
+//
+// Always set 5 here, because we want to support all hash algo in BIOS.
+//
+#define HASH_COUNT 5
+
+// 5 Base Types
+
+// Table 3 - Definition of Base Types
+typedef UINT8 BYTE;
+
+// Table 4 - Definition of Types for Documentation Clarity
+//
+// NOTE: Comment because it has same name as TPM1.2 (value is same, so not runtime issue)
+//
+//typedef UINT32 TPM_ALGORITHM_ID;
+//typedef UINT32 TPM_MODIFIER_INDICATOR;
+typedef UINT32 TPM_AUTHORIZATION_SIZE;
+typedef UINT32 TPM_PARAMETER_SIZE;
+typedef UINT16 TPM_KEY_SIZE;
+typedef UINT16 TPM_KEY_BITS;
+
+// 6 Constants
+
+// Table 6 - TPM_GENERATED Constants
+typedef UINT32 TPM_GENERATED;
+#define TPM_GENERATED_VALUE (TPM_GENERATED)(0xff544347)
+
+// Table 7 - TPM_ALG_ID Constants
+typedef UINT16 TPM_ALG_ID;
+//
+// NOTE: Comment some algo which has same name as TPM1.2 (value is same, so not runtime issue)
+//
+#define TPM_ALG_ERROR          (TPM_ALG_ID)(0x0000)
+#define TPM_ALG_FIRST          (TPM_ALG_ID)(0x0001)
+//#define TPM_ALG_RSA            (TPM_ALG_ID)(0x0001)
+//#define TPM_ALG_SHA            (TPM_ALG_ID)(0x0004)
+#define TPM_ALG_SHA1           (TPM_ALG_ID)(0x0004)
+//#define TPM_ALG_HMAC           (TPM_ALG_ID)(0x0005)
+#define TPM_ALG_AES            (TPM_ALG_ID)(0x0006)
+//#define TPM_ALG_MGF1           (TPM_ALG_ID)(0x0007)
+#define TPM_ALG_KEYEDHASH      (TPM_ALG_ID)(0x0008)
+//#define TPM_ALG_XOR            (TPM_ALG_ID)(0x000A)
+#define TPM_ALG_SHA256         (TPM_ALG_ID)(0x000B)
+#define TPM_ALG_SHA384         (TPM_ALG_ID)(0x000C)
+#define TPM_ALG_SHA512         (TPM_ALG_ID)(0x000D)
+#define TPM_ALG_NULL           (TPM_ALG_ID)(0x0010)
+#define TPM_ALG_SM3_256        (TPM_ALG_ID)(0x0012)
+#define TPM_ALG_SM4            (TPM_ALG_ID)(0x0013)
+#define TPM_ALG_RSASSA         (TPM_ALG_ID)(0x0014)
+#define TPM_ALG_RSAES          (TPM_ALG_ID)(0x0015)
+#define TPM_ALG_RSAPSS         (TPM_ALG_ID)(0x0016)
+#define TPM_ALG_OAEP           (TPM_ALG_ID)(0x0017)
+#define TPM_ALG_ECDSA          (TPM_ALG_ID)(0x0018)
+#define TPM_ALG_ECDH           (TPM_ALG_ID)(0x0019)
+#define TPM_ALG_ECDAA          (TPM_ALG_ID)(0x001A)
+#define TPM_ALG_SM2            (TPM_ALG_ID)(0x001B)
+#define TPM_ALG_ECSCHNORR      (TPM_ALG_ID)(0x001C)
+#define TPM_ALG_ECMQV          (TPM_ALG_ID)(0x001D)
+#define TPM_ALG_KDF1_SP800_56a (TPM_ALG_ID)(0x0020)
+#define TPM_ALG_KDF2           (TPM_ALG_ID)(0x0021)
+#define TPM_ALG_KDF1_SP800_108 (TPM_ALG_ID)(0x0022)
+#define TPM_ALG_ECC            (TPM_ALG_ID)(0x0023)
+#define TPM_ALG_SYMCIPHER      (TPM_ALG_ID)(0x0025)
+#define TPM_ALG_CTR            (TPM_ALG_ID)(0x0040)
+#define TPM_ALG_OFB            (TPM_ALG_ID)(0x0041)
+#define TPM_ALG_CBC            (TPM_ALG_ID)(0x0042)
+#define TPM_ALG_CFB            (TPM_ALG_ID)(0x0043)
+#define TPM_ALG_ECB            (TPM_ALG_ID)(0x0044)
+#define TPM_ALG_LAST           (TPM_ALG_ID)(0x0044)
+
+// Table 8 - TPM_ECC_CURVE Constants
+typedef UINT16 TPM_ECC_CURVE;
+#define TPM_ECC_NONE      (TPM_ECC_CURVE)(0x0000)
+#define TPM_ECC_NIST_P192 (TPM_ECC_CURVE)(0x0001)
+#define TPM_ECC_NIST_P224 (TPM_ECC_CURVE)(0x0002)
+#define TPM_ECC_NIST_P256 (TPM_ECC_CURVE)(0x0003)
+#define TPM_ECC_NIST_P384 (TPM_ECC_CURVE)(0x0004)
+#define TPM_ECC_NIST_P521 (TPM_ECC_CURVE)(0x0005)
+#define TPM_ECC_BN_P256   (TPM_ECC_CURVE)(0x0010)
+#define TPM_ECC_BN_P638   (TPM_ECC_CURVE)(0x0011)
+#define TPM_ECC_SM2_P256  (TPM_ECC_CURVE)(0x0020)
+
+// Table 11 - TPM_CC Constants (Numeric Order)
+typedef UINT32 TPM_CC;
+#define TPM_CC_FIRST                      (TPM_CC)(0x0000011F)
+#define TPM_CC_PP_FIRST                   (TPM_CC)(0x0000011F)
+#define TPM_CC_NV_UndefineSpaceSpecial    (TPM_CC)(0x0000011F)
+#define TPM_CC_EvictControl               (TPM_CC)(0x00000120)
+#define TPM_CC_HierarchyControl           (TPM_CC)(0x00000121)
+#define TPM_CC_NV_UndefineSpace           (TPM_CC)(0x00000122)
+#define TPM_CC_ChangeEPS                  (TPM_CC)(0x00000124)
+#define TPM_CC_ChangePPS                  (TPM_CC)(0x00000125)
+#define TPM_CC_Clear                      (TPM_CC)(0x00000126)
+#define TPM_CC_ClearControl               (TPM_CC)(0x00000127)
+#define TPM_CC_ClockSet                   (TPM_CC)(0x00000128)
+#define TPM_CC_HierarchyChangeAuth        (TPM_CC)(0x00000129)
+#define TPM_CC_NV_DefineSpace             (TPM_CC)(0x0000012A)
+#define TPM_CC_PCR_Allocate               (TPM_CC)(0x0000012B)
+#define TPM_CC_PCR_SetAuthPolicy          (TPM_CC)(0x0000012C)
+#define TPM_CC_PP_Commands                (TPM_CC)(0x0000012D)
+#define TPM_CC_SetPrimaryPolicy           (TPM_CC)(0x0000012E)
+#define TPM_CC_FieldUpgradeStart          (TPM_CC)(0x0000012F)
+#define TPM_CC_ClockRateAdjust            (TPM_CC)(0x00000130)
+#define TPM_CC_CreatePrimary              (TPM_CC)(0x00000131)
+#define TPM_CC_NV_GlobalWriteLock         (TPM_CC)(0x00000132)
+#define TPM_CC_PP_LAST                    (TPM_CC)(0x00000132)
+#define TPM_CC_GetCommandAuditDigest      (TPM_CC)(0x00000133)
+#define TPM_CC_NV_Increment               (TPM_CC)(0x00000134)
+#define TPM_CC_NV_SetBits                 (TPM_CC)(0x00000135)
+#define TPM_CC_NV_Extend                  (TPM_CC)(0x00000136)
+#define TPM_CC_NV_Write                   (TPM_CC)(0x00000137)
+#define TPM_CC_NV_WriteLock               (TPM_CC)(0x00000138)
+#define TPM_CC_DictionaryAttackLockReset  (TPM_CC)(0x00000139)
+#define TPM_CC_DictionaryAttackParameters (TPM_CC)(0x0000013A)
+#define TPM_CC_NV_ChangeAuth              (TPM_CC)(0x0000013B)
+#define TPM_CC_PCR_Event                  (TPM_CC)(0x0000013C)
+#define TPM_CC_PCR_Reset                  (TPM_CC)(0x0000013D)
+#define TPM_CC_SequenceComplete           (TPM_CC)(0x0000013E)
+#define TPM_CC_SetAlgorithmSet            (TPM_CC)(0x0000013F)
+#define TPM_CC_SetCommandCodeAuditStatus  (TPM_CC)(0x00000140)
+#define TPM_CC_FieldUpgradeData           (TPM_CC)(0x00000141)
+#define TPM_CC_IncrementalSelfTest        (TPM_CC)(0x00000142)
+#define TPM_CC_SelfTest                   (TPM_CC)(0x00000143)
+#define TPM_CC_Startup                    (TPM_CC)(0x00000144)
+#define TPM_CC_Shutdown                   (TPM_CC)(0x00000145)
+#define TPM_CC_StirRandom                 (TPM_CC)(0x00000146)
+#define TPM_CC_ActivateCredential         (TPM_CC)(0x00000147)
+#define TPM_CC_Certify                    (TPM_CC)(0x00000148)
+#define TPM_CC_PolicyNV                   (TPM_CC)(0x00000149)
+#define TPM_CC_CertifyCreation            (TPM_CC)(0x0000014A)
+#define TPM_CC_Duplicate                  (TPM_CC)(0x0000014B)
+#define TPM_CC_GetTime                    (TPM_CC)(0x0000014C)
+#define TPM_CC_GetSessionAuditDigest      (TPM_CC)(0x0000014D)
+#define TPM_CC_NV_Read                    (TPM_CC)(0x0000014E)
+#define TPM_CC_NV_ReadLock                (TPM_CC)(0x0000014F)
+#define TPM_CC_ObjectChangeAuth           (TPM_CC)(0x00000150)
+#define TPM_CC_PolicySecret               (TPM_CC)(0x00000151)
+#define TPM_CC_Rewrap                     (TPM_CC)(0x00000152)
+#define TPM_CC_Create                     (TPM_CC)(0x00000153)
+#define TPM_CC_ECDH_ZGen                  (TPM_CC)(0x00000154)
+#define TPM_CC_HMAC                       (TPM_CC)(0x00000155)
+#define TPM_CC_Import                     (TPM_CC)(0x00000156)
+#define TPM_CC_Load                       (TPM_CC)(0x00000157)
+#define TPM_CC_Quote                      (TPM_CC)(0x00000158)
+#define TPM_CC_RSA_Decrypt                (TPM_CC)(0x00000159)
+#define TPM_CC_HMAC_Start                 (TPM_CC)(0x0000015B)
+#define TPM_CC_SequenceUpdate             (TPM_CC)(0x0000015C)
+#define TPM_CC_Sign                       (TPM_CC)(0x0000015D)
+#define TPM_CC_Unseal                     (TPM_CC)(0x0000015E)
+#define TPM_CC_PolicySigned               (TPM_CC)(0x00000160)
+#define TPM_CC_ContextLoad                (TPM_CC)(0x00000161)
+#define TPM_CC_ContextSave                (TPM_CC)(0x00000162)
+#define TPM_CC_ECDH_KeyGen                (TPM_CC)(0x00000163)
+#define TPM_CC_EncryptDecrypt             (TPM_CC)(0x00000164)
+#define TPM_CC_FlushContext               (TPM_CC)(0x00000165)
+#define TPM_CC_LoadExternal               (TPM_CC)(0x00000167)
+#define TPM_CC_MakeCredential             (TPM_CC)(0x00000168)
+#define TPM_CC_NV_ReadPublic              (TPM_CC)(0x00000169)
+#define TPM_CC_PolicyAuthorize            (TPM_CC)(0x0000016A)
+#define TPM_CC_PolicyAuthValue            (TPM_CC)(0x0000016B)
+#define TPM_CC_PolicyCommandCode          (TPM_CC)(0x0000016C)
+#define TPM_CC_PolicyCounterTimer         (TPM_CC)(0x0000016D)
+#define TPM_CC_PolicyCpHash               (TPM_CC)(0x0000016E)
+#define TPM_CC_PolicyLocality             (TPM_CC)(0x0000016F)
+#define TPM_CC_PolicyNameHash             (TPM_CC)(0x00000170)
+#define TPM_CC_PolicyOR                   (TPM_CC)(0x00000171)
+#define TPM_CC_PolicyTicket               (TPM_CC)(0x00000172)
+#define TPM_CC_ReadPublic                 (TPM_CC)(0x00000173)
+#define TPM_CC_RSA_Encrypt                (TPM_CC)(0x00000174)
+#define TPM_CC_StartAuthSession           (TPM_CC)(0x00000176)
+#define TPM_CC_VerifySignature            (TPM_CC)(0x00000177)
+#define TPM_CC_ECC_Parameters             (TPM_CC)(0x00000178)
+#define TPM_CC_FirmwareRead               (TPM_CC)(0x00000179)
+#define TPM_CC_GetCapability              (TPM_CC)(0x0000017A)
+#define TPM_CC_GetRandom                  (TPM_CC)(0x0000017B)
+#define TPM_CC_GetTestResult              (TPM_CC)(0x0000017C)
+#define TPM_CC_Hash                       (TPM_CC)(0x0000017D)
+#define TPM_CC_PCR_Read                   (TPM_CC)(0x0000017E)
+#define TPM_CC_PolicyPCR                  (TPM_CC)(0x0000017F)
+#define TPM_CC_PolicyRestart              (TPM_CC)(0x00000180)
+#define TPM_CC_ReadClock                  (TPM_CC)(0x00000181)
+#define TPM_CC_PCR_Extend                 (TPM_CC)(0x00000182)
+#define TPM_CC_PCR_SetAuthValue           (TPM_CC)(0x00000183)
+#define TPM_CC_NV_Certify                 (TPM_CC)(0x00000184)
+#define TPM_CC_EventSequenceComplete      (TPM_CC)(0x00000185)
+#define TPM_CC_HashSequenceStart          (TPM_CC)(0x00000186)
+#define TPM_CC_PolicyPhysicalPresence     (TPM_CC)(0x00000187)
+#define TPM_CC_PolicyDuplicationSelect    (TPM_CC)(0x00000188)
+#define TPM_CC_PolicyGetDigest            (TPM_CC)(0x00000189)
+#define TPM_CC_TestParms                  (TPM_CC)(0x0000018A)
+#define TPM_CC_Commit                     (TPM_CC)(0x0000018B)
+#define TPM_CC_PolicyPassword             (TPM_CC)(0x0000018C)
+#define TPM_CC_ZGen_2Phase                (TPM_CC)(0x0000018D)
+#define TPM_CC_EC_Ephemeral               (TPM_CC)(0x0000018E)
+#define TPM_CC_LAST                       (TPM_CC)(0x0000018E)
+
+// Table 15 - TPM_RC Constants (Actions)
+typedef UINT32 TPM_RC;
+#define TPM_RC_SUCCESS           (TPM_RC)(0x000)
+#define TPM_RC_BAD_TAG           (TPM_RC)(0x030)
+#define RC_VER1                  (TPM_RC)(0x100)
+#define TPM_RC_INITIALIZE        (TPM_RC)(RC_VER1 + 0x000)
+#define TPM_RC_FAILURE           (TPM_RC)(RC_VER1 + 0x001)
+#define TPM_RC_SEQUENCE          (TPM_RC)(RC_VER1 + 0x003)
+#define TPM_RC_PRIVATE           (TPM_RC)(RC_VER1 + 0x00B)
+#define TPM_RC_HMAC              (TPM_RC)(RC_VER1 + 0x019)
+#define TPM_RC_DISABLED          (TPM_RC)(RC_VER1 + 0x020)
+#define TPM_RC_EXCLUSIVE         (TPM_RC)(RC_VER1 + 0x021)
+#define TPM_RC_AUTH_TYPE         (TPM_RC)(RC_VER1 + 0x024)
+#define TPM_RC_AUTH_MISSING      (TPM_RC)(RC_VER1 + 0x025)
+#define TPM_RC_POLICY            (TPM_RC)(RC_VER1 + 0x026)
+#define TPM_RC_PCR               (TPM_RC)(RC_VER1 + 0x027)
+#define TPM_RC_PCR_CHANGED       (TPM_RC)(RC_VER1 + 0x028)
+#define TPM_RC_UPGRADE           (TPM_RC)(RC_VER1 + 0x02D)
+#define TPM_RC_TOO_MANY_CONTEXTS (TPM_RC)(RC_VER1 + 0x02E)
+#define TPM_RC_AUTH_UNAVAILABLE  (TPM_RC)(RC_VER1 + 0x02F)
+#define TPM_RC_REBOOT            (TPM_RC)(RC_VER1 + 0x030)
+#define TPM_RC_UNBALANCED        (TPM_RC)(RC_VER1 + 0x031)
+#define TPM_RC_COMMAND_SIZE      (TPM_RC)(RC_VER1 + 0x042)
+#define TPM_RC_COMMAND_CODE      (TPM_RC)(RC_VER1 + 0x043)
+#define TPM_RC_AUTHSIZE          (TPM_RC)(RC_VER1 + 0x044)
+#define TPM_RC_AUTH_CONTEXT      (TPM_RC)(RC_VER1 + 0x045)
+#define TPM_RC_NV_RANGE          (TPM_RC)(RC_VER1 + 0x046)
+#define TPM_RC_NV_SIZE           (TPM_RC)(RC_VER1 + 0x047)
+#define TPM_RC_NV_LOCKED         (TPM_RC)(RC_VER1 + 0x048)
+#define TPM_RC_NV_AUTHORIZATION  (TPM_RC)(RC_VER1 + 0x049)
+#define TPM_RC_NV_UNINITIALIZED  (TPM_RC)(RC_VER1 + 0x04A)
+#define TPM_RC_NV_SPACE          (TPM_RC)(RC_VER1 + 0x04B)
+#define TPM_RC_NV_DEFINED        (TPM_RC)(RC_VER1 + 0x04C)
+#define TPM_RC_BAD_CONTEXT       (TPM_RC)(RC_VER1 + 0x050)
+#define TPM_RC_CPHASH            (TPM_RC)(RC_VER1 + 0x051)
+#define TPM_RC_PARENT            (TPM_RC)(RC_VER1 + 0x052)
+#define TPM_RC_NEEDS_TEST        (TPM_RC)(RC_VER1 + 0x053)
+#define TPM_RC_NO_RESULT         (TPM_RC)(RC_VER1 + 0x054)
+#define TPM_RC_SENSITIVE         (TPM_RC)(RC_VER1 + 0x055)
+#define RC_MAX_FM0               (TPM_RC)(RC_VER1 + 0x07F)
+#define RC_FMT1                  (TPM_RC)(0x080)
+#define TPM_RC_ASYMMETRIC        (TPM_RC)(RC_FMT1 + 0x001)
+#define TPM_RC_ATTRIBUTES        (TPM_RC)(RC_FMT1 + 0x002)
+#define TPM_RC_HASH              (TPM_RC)(RC_FMT1 + 0x003)
+#define TPM_RC_VALUE             (TPM_RC)(RC_FMT1 + 0x004)
+#define TPM_RC_HIERARCHY         (TPM_RC)(RC_FMT1 + 0x005)
+#define TPM_RC_KEY_SIZE          (TPM_RC)(RC_FMT1 + 0x007)
+#define TPM_RC_MGF               (TPM_RC)(RC_FMT1 + 0x008)
+#define TPM_RC_MODE              (TPM_RC)(RC_FMT1 + 0x009)
+#define TPM_RC_TYPE              (TPM_RC)(RC_FMT1 + 0x00A)
+#define TPM_RC_HANDLE            (TPM_RC)(RC_FMT1 + 0x00B)
+#define TPM_RC_KDF               (TPM_RC)(RC_FMT1 + 0x00C)
+#define TPM_RC_RANGE             (TPM_RC)(RC_FMT1 + 0x00D)
+#define TPM_RC_AUTH_FAIL         (TPM_RC)(RC_FMT1 + 0x00E)
+#define TPM_RC_NONCE             (TPM_RC)(RC_FMT1 + 0x00F)
+#define TPM_RC_PP                (TPM_RC)(RC_FMT1 + 0x010)
+#define TPM_RC_SCHEME            (TPM_RC)(RC_FMT1 + 0x012)
+#define TPM_RC_SIZE              (TPM_RC)(RC_FMT1 + 0x015)
+#define TPM_RC_SYMMETRIC         (TPM_RC)(RC_FMT1 + 0x016)
+#define TPM_RC_TAG               (TPM_RC)(RC_FMT1 + 0x017)
+#define TPM_RC_SELECTOR          (TPM_RC)(RC_FMT1 + 0x018)
+#define TPM_RC_INSUFFICIENT      (TPM_RC)(RC_FMT1 + 0x01A)
+#define TPM_RC_SIGNATURE         (TPM_RC)(RC_FMT1 + 0x01B)
+#define TPM_RC_KEY               (TPM_RC)(RC_FMT1 + 0x01C)
+#define TPM_RC_POLICY_FAIL       (TPM_RC)(RC_FMT1 + 0x01D)
+#define TPM_RC_INTEGRITY         (TPM_RC)(RC_FMT1 + 0x01F)
+#define TPM_RC_TICKET            (TPM_RC)(RC_FMT1 + 0x020)
+#define TPM_RC_RESERVED_BITS     (TPM_RC)(RC_FMT1 + 0x021)
+#define TPM_RC_BAD_AUTH          (TPM_RC)(RC_FMT1 + 0x022)
+#define TPM_RC_EXPIRED           (TPM_RC)(RC_FMT1 + 0x023)
+#define TPM_RC_POLICY_CC         (TPM_RC)(RC_FMT1 + 0x024 )
+#define TPM_RC_BINDING           (TPM_RC)(RC_FMT1 + 0x025)
+#define TPM_RC_CURVE             (TPM_RC)(RC_FMT1 + 0x026)
+#define TPM_RC_ECC_POINT         (TPM_RC)(RC_FMT1 + 0x027)
+#define RC_WARN                  (TPM_RC)(0x900)
+#define TPM_RC_CONTEXT_GAP       (TPM_RC)(RC_WARN + 0x001)
+#define TPM_RC_OBJECT_MEMORY     (TPM_RC)(RC_WARN + 0x002)
+#define TPM_RC_SESSION_MEMORY    (TPM_RC)(RC_WARN + 0x003)
+#define TPM_RC_MEMORY            (TPM_RC)(RC_WARN + 0x004)
+#define TPM_RC_SESSION_HANDLES   (TPM_RC)(RC_WARN + 0x005)
+#define TPM_RC_OBJECT_HANDLES    (TPM_RC)(RC_WARN + 0x006)
+#define TPM_RC_LOCALITY          (TPM_RC)(RC_WARN + 0x007)
+#define TPM_RC_YIELDED           (TPM_RC)(RC_WARN + 0x008)
+#define TPM_RC_CANCELED          (TPM_RC)(RC_WARN + 0x009)
+#define TPM_RC_TESTING           (TPM_RC)(RC_WARN + 0x00A)
+#define TPM_RC_REFERENCE_H0      (TPM_RC)(RC_WARN + 0x010)
+#define TPM_RC_REFERENCE_H1      (TPM_RC)(RC_WARN + 0x011)
+#define TPM_RC_REFERENCE_H2      (TPM_RC)(RC_WARN + 0x012)
+#define TPM_RC_REFERENCE_H3      (TPM_RC)(RC_WARN + 0x013)
+#define TPM_RC_REFERENCE_H4      (TPM_RC)(RC_WARN + 0x014)
+#define TPM_RC_REFERENCE_H5      (TPM_RC)(RC_WARN + 0x015)
+#define TPM_RC_REFERENCE_H6      (TPM_RC)(RC_WARN + 0x016)
+#define TPM_RC_REFERENCE_S0      (TPM_RC)(RC_WARN + 0x018)
+#define TPM_RC_REFERENCE_S1      (TPM_RC)(RC_WARN + 0x019)
+#define TPM_RC_REFERENCE_S2      (TPM_RC)(RC_WARN + 0x01A)
+#define TPM_RC_REFERENCE_S3      (TPM_RC)(RC_WARN + 0x01B)
+#define TPM_RC_REFERENCE_S4      (TPM_RC)(RC_WARN + 0x01C)
+#define TPM_RC_REFERENCE_S5      (TPM_RC)(RC_WARN + 0x01D)
+#define TPM_RC_REFERENCE_S6      (TPM_RC)(RC_WARN + 0x01E)
+#define TPM_RC_NV_RATE           (TPM_RC)(RC_WARN + 0x020)
+#define TPM_RC_LOCKOUT           (TPM_RC)(RC_WARN + 0x021)
+#define TPM_RC_RETRY             (TPM_RC)(RC_WARN + 0x022)
+#define TPM_RC_NV_UNAVAILABLE    (TPM_RC)(RC_WARN + 0x023)
+#define TPM_RC_NOT_USED          (TPM_RC)(RC_WARN + 0x7F)
+#define TPM_RC_H                 (TPM_RC)(0x000)
+#define TPM_RC_P                 (TPM_RC)(0x040)
+#define TPM_RC_S                 (TPM_RC)(0x800)
+#define TPM_RC_1                 (TPM_RC)(0x100)
+#define TPM_RC_2                 (TPM_RC)(0x200)
+#define TPM_RC_3                 (TPM_RC)(0x300)
+#define TPM_RC_4                 (TPM_RC)(0x400)
+#define TPM_RC_5                 (TPM_RC)(0x500)
+#define TPM_RC_6                 (TPM_RC)(0x600)
+#define TPM_RC_7                 (TPM_RC)(0x700)
+#define TPM_RC_8                 (TPM_RC)(0x800)
+#define TPM_RC_9                 (TPM_RC)(0x900)
+#define TPM_RC_A                 (TPM_RC)(0xA00)
+#define TPM_RC_B                 (TPM_RC)(0xB00)
+#define TPM_RC_C                 (TPM_RC)(0xC00)
+#define TPM_RC_D                 (TPM_RC)(0xD00)
+#define TPM_RC_E                 (TPM_RC)(0xE00)
+#define TPM_RC_F                 (TPM_RC)(0xF00)
+#define TPM_RC_N_MASK            (TPM_RC)(0xF00)
+
+// Table 16 - TPM_CLOCK_ADJUST Constants
+typedef INT8 TPM_CLOCK_ADJUST;
+#define TPM_CLOCK_COARSE_SLOWER (TPM_CLOCK_ADJUST)(-3)
+#define TPM_CLOCK_MEDIUM_SLOWER (TPM_CLOCK_ADJUST)(-2)
+#define TPM_CLOCK_FINE_SLOWER   (TPM_CLOCK_ADJUST)(-1)
+#define TPM_CLOCK_NO_CHANGE     (TPM_CLOCK_ADJUST)(0)
+#define TPM_CLOCK_FINE_FASTER   (TPM_CLOCK_ADJUST)(1)
+#define TPM_CLOCK_MEDIUM_FASTER (TPM_CLOCK_ADJUST)(2)
+#define TPM_CLOCK_COARSE_FASTER (TPM_CLOCK_ADJUST)(3)
+
+// Table 17 - TPM_EO Constants
+typedef UINT16 TPM_EO;
+#define TPM_EO_EQ          (TPM_EO)(0x0000)
+#define TPM_EO_NEQ         (TPM_EO)(0x0001)
+#define TPM_EO_SIGNED_GT   (TPM_EO)(0x0002)
+#define TPM_EO_UNSIGNED_GT (TPM_EO)(0x0003)
+#define TPM_EO_SIGNED_LT   (TPM_EO)(0x0004)
+#define TPM_EO_UNSIGNED_LT (TPM_EO)(0x0005)
+#define TPM_EO_SIGNED_GE   (TPM_EO)(0x0006)
+#define TPM_EO_UNSIGNED_GE (TPM_EO)(0x0007)
+#define TPM_EO_SIGNED_LE   (TPM_EO)(0x0008)
+#define TPM_EO_UNSIGNED_LE (TPM_EO)(0x0009)
+#define TPM_EO_BITSET      (TPM_EO)(0x000A)
+#define TPM_EO_BITCLEAR    (TPM_EO)(0x000B)
+
+// Table 18 - TPM_ST Constants
+typedef UINT16 TPM_ST;
+#define TPM_ST_RSP_COMMAND          (TPM_ST)(0x00C4)
+#define TPM_ST_NULL                 (TPM_ST)(0X8000)
+#define TPM_ST_NO_SESSIONS          (TPM_ST)(0x8001)
+#define TPM_ST_SESSIONS             (TPM_ST)(0x8002)
+#define TPM_ST_ATTEST_NV            (TPM_ST)(0x8014)
+#define TPM_ST_ATTEST_COMMAND_AUDIT (TPM_ST)(0x8015)
+#define TPM_ST_ATTEST_SESSION_AUDIT (TPM_ST)(0x8016)
+#define TPM_ST_ATTEST_CERTIFY       (TPM_ST)(0x8017)
+#define TPM_ST_ATTEST_QUOTE         (TPM_ST)(0x8018)
+#define TPM_ST_ATTEST_TIME          (TPM_ST)(0x8019)
+#define TPM_ST_ATTEST_CREATION      (TPM_ST)(0x801A)
+#define TPM_ST_CREATION             (TPM_ST)(0x8021)
+#define TPM_ST_VERIFIED             (TPM_ST)(0x8022)
+#define TPM_ST_AUTH_SECRET          (TPM_ST)(0x8023)
+#define TPM_ST_HASHCHECK            (TPM_ST)(0x8024)
+#define TPM_ST_AUTH_SIGNED          (TPM_ST)(0x8025)
+#define TPM_ST_FU_MANIFEST          (TPM_ST)(0x8029)
+
+// Table 19 - TPM_SU Constants
+typedef UINT16 TPM_SU;
+#define TPM_SU_CLEAR (TPM_SU)(0x0000)
+#define TPM_SU_STATE (TPM_SU)(0x0001)
+
+// Table 20 - TPM_SE Constants
+typedef UINT8 TPM_SE;
+#define TPM_SE_HMAC   (TPM_SE)(0x00)
+#define TPM_SE_POLICY (TPM_SE)(0x01)
+#define TPM_SE_TRIAL  (TPM_SE)(0x03)
+
+// Table 21 - TPM_CAP Constants
+typedef UINT32 TPM_CAP;
+#define TPM_CAP_FIRST           (TPM_CAP)(0x00000000)
+#define TPM_CAP_ALGS            (TPM_CAP)(0x00000000)
+#define TPM_CAP_HANDLES         (TPM_CAP)(0x00000001)
+#define TPM_CAP_COMMANDS        (TPM_CAP)(0x00000002)
+#define TPM_CAP_PP_COMMANDS     (TPM_CAP)(0x00000003)
+#define TPM_CAP_AUDIT_COMMANDS  (TPM_CAP)(0x00000004)
+#define TPM_CAP_PCRS            (TPM_CAP)(0x00000005)
+#define TPM_CAP_TPM_PROPERTIES  (TPM_CAP)(0x00000006)
+#define TPM_CAP_PCR_PROPERTIES  (TPM_CAP)(0x00000007)
+#define TPM_CAP_ECC_CURVES      (TPM_CAP)(0x00000008)
+#define TPM_CAP_LAST            (TPM_CAP)(0x00000008)
+#define TPM_CAP_VENDOR_PROPERTY (TPM_CAP)(0x00000100)
+
+// Table 22 - TPM_PT Constants
+typedef UINT32 TPM_PT;
+#define TPM_PT_NONE                (TPM_PT)(0x00000000)
+#define PT_GROUP                   (TPM_PT)(0x00000100)
+#define PT_FIXED                   (TPM_PT)(PT_GROUP * 1)
+#define TPM_PT_FAMILY_INDICATOR    (TPM_PT)(PT_FIXED + 0)
+#define TPM_PT_LEVEL               (TPM_PT)(PT_FIXED + 1)
+#define TPM_PT_REVISION            (TPM_PT)(PT_FIXED + 2)
+#define TPM_PT_DAY_OF_YEAR         (TPM_PT)(PT_FIXED + 3)
+#define TPM_PT_YEAR                (TPM_PT)(PT_FIXED + 4)
+#define TPM_PT_MANUFACTURER        (TPM_PT)(PT_FIXED + 5)
+#define TPM_PT_VENDOR_STRING_1     (TPM_PT)(PT_FIXED + 6)
+#define TPM_PT_VENDOR_STRING_2     (TPM_PT)(PT_FIXED + 7)
+#define TPM_PT_VENDOR_STRING_3     (TPM_PT)(PT_FIXED + 8)
+#define TPM_PT_VENDOR_STRING_4     (TPM_PT)(PT_FIXED + 9)
+#define TPM_PT_VENDOR_TPM_TYPE     (TPM_PT)(PT_FIXED + 10)
+#define TPM_PT_FIRMWARE_VERSION_1  (TPM_PT)(PT_FIXED + 11)
+#define TPM_PT_FIRMWARE_VERSION_2  (TPM_PT)(PT_FIXED + 12)
+#define TPM_PT_INPUT_BUFFER        (TPM_PT)(PT_FIXED + 13)
+#define TPM_PT_HR_TRANSIENT_MIN    (TPM_PT)(PT_FIXED + 14)
+#define TPM_PT_HR_PERSISTENT_MIN   (TPM_PT)(PT_FIXED + 15)
+#define TPM_PT_HR_LOADED_MIN       (TPM_PT)(PT_FIXED + 16)
+#define TPM_PT_ACTIVE_SESSIONS_MAX (TPM_PT)(PT_FIXED + 17)
+#define TPM_PT_PCR_COUNT           (TPM_PT)(PT_FIXED + 18)
+#define TPM_PT_PCR_SELECT_MIN      (TPM_PT)(PT_FIXED + 19)
+#define TPM_PT_CONTEXT_GAP_MAX     (TPM_PT)(PT_FIXED + 20)
+#define TPM_PT_NV_COUNTERS_MAX     (TPM_PT)(PT_FIXED + 22)
+#define TPM_PT_NV_INDEX_MAX        (TPM_PT)(PT_FIXED + 23)
+#define TPM_PT_MEMORY              (TPM_PT)(PT_FIXED + 24)
+#define TPM_PT_CLOCK_UPDATE        (TPM_PT)(PT_FIXED + 25)
+#define TPM_PT_CONTEXT_HASH        (TPM_PT)(PT_FIXED + 26)
+#define TPM_PT_CONTEXT_SYM         (TPM_PT)(PT_FIXED + 27)
+#define TPM_PT_CONTEXT_SYM_SIZE    (TPM_PT)(PT_FIXED + 28)
+#define TPM_PT_ORDERLY_COUNT       (TPM_PT)(PT_FIXED + 29)
+#define TPM_PT_MAX_COMMAND_SIZE    (TPM_PT)(PT_FIXED + 30)
+#define TPM_PT_MAX_RESPONSE_SIZE   (TPM_PT)(PT_FIXED + 31)
+#define TPM_PT_MAX_DIGEST          (TPM_PT)(PT_FIXED + 32)
+#define TPM_PT_MAX_OBJECT_CONTEXT  (TPM_PT)(PT_FIXED + 33)
+#define TPM_PT_MAX_SESSION_CONTEXT (TPM_PT)(PT_FIXED + 34)
+#define TPM_PT_PS_FAMILY_INDICATOR (TPM_PT)(PT_FIXED + 35)
+#define TPM_PT_PS_LEVEL            (TPM_PT)(PT_FIXED + 36)
+#define TPM_PT_PS_REVISION         (TPM_PT)(PT_FIXED + 37)
+#define TPM_PT_PS_DAY_OF_YEAR      (TPM_PT)(PT_FIXED + 38)
+#define TPM_PT_PS_YEAR             (TPM_PT)(PT_FIXED + 39)
+#define TPM_PT_SPLIT_MAX           (TPM_PT)(PT_FIXED + 40)
+#define TPM_PT_TOTAL_COMMANDS      (TPM_PT)(PT_FIXED + 41)
+#define TPM_PT_LIBRARY_COMMANDS    (TPM_PT)(PT_FIXED + 42)
+#define TPM_PT_VENDOR_COMMANDS     (TPM_PT)(PT_FIXED + 43)
+#define PT_VAR                     (TPM_PT)(PT_GROUP * 2)
+#define TPM_PT_PERMANENT           (TPM_PT)(PT_VAR + 0)
+#define TPM_PT_STARTUP_CLEAR       (TPM_PT)(PT_VAR + 1)
+#define TPM_PT_HR_NV_INDEX         (TPM_PT)(PT_VAR + 2)
+#define TPM_PT_HR_LOADED           (TPM_PT)(PT_VAR + 3)
+#define TPM_PT_HR_LOADED_AVAIL     (TPM_PT)(PT_VAR + 4)
+#define TPM_PT_HR_ACTIVE           (TPM_PT)(PT_VAR + 5)
+#define TPM_PT_HR_ACTIVE_AVAIL     (TPM_PT)(PT_VAR + 6)
+#define TPM_PT_HR_TRANSIENT_AVAIL  (TPM_PT)(PT_VAR + 7)
+#define TPM_PT_HR_PERSISTENT       (TPM_PT)(PT_VAR + 8)
+#define TPM_PT_HR_PERSISTENT_AVAIL (TPM_PT)(PT_VAR + 9)
+#define TPM_PT_NV_COUNTERS         (TPM_PT)(PT_VAR + 10)
+#define TPM_PT_NV_COUNTERS_AVAIL   (TPM_PT)(PT_VAR + 11)
+#define TPM_PT_ALGORITHM_SET       (TPM_PT)(PT_VAR + 12)
+#define TPM_PT_LOADED_CURVES       (TPM_PT)(PT_VAR + 13)
+#define TPM_PT_LOCKOUT_COUNTER     (TPM_PT)(PT_VAR + 14)
+#define TPM_PT_MAX_AUTH_FAIL       (TPM_PT)(PT_VAR + 15)
+#define TPM_PT_LOCKOUT_INTERVAL    (TPM_PT)(PT_VAR + 16)
+#define TPM_PT_LOCKOUT_RECOVERY    (TPM_PT)(PT_VAR + 17)
+#define TPM_PT_NV_WRITE_RECOVERY   (TPM_PT)(PT_VAR + 18)
+#define TPM_PT_AUDIT_COUNTER_0     (TPM_PT)(PT_VAR + 19)
+#define TPM_PT_AUDIT_COUNTER_1     (TPM_PT)(PT_VAR + 20)
+
+// Table 23 - TPM_PT_PCR Constants
+typedef UINT32 TPM_PT_PCR;
+#define TPM_PT_PCR_FIRST        (TPM_PT_PCR)(0x00000000)
+#define TPM_PT_PCR_SAVE         (TPM_PT_PCR)(0x00000000)
+#define TPM_PT_PCR_EXTEND_L0    (TPM_PT_PCR)(0x00000001)
+#define TPM_PT_PCR_RESET_L0     (TPM_PT_PCR)(0x00000002)
+#define TPM_PT_PCR_EXTEND_L1    (TPM_PT_PCR)(0x00000003)
+#define TPM_PT_PCR_RESET_L1     (TPM_PT_PCR)(0x00000004)
+#define TPM_PT_PCR_EXTEND_L2    (TPM_PT_PCR)(0x00000005)
+#define TPM_PT_PCR_RESET_L2     (TPM_PT_PCR)(0x00000006)
+#define TPM_PT_PCR_EXTEND_L3    (TPM_PT_PCR)(0x00000007)
+#define TPM_PT_PCR_RESET_L3     (TPM_PT_PCR)(0x00000008)
+#define TPM_PT_PCR_EXTEND_L4    (TPM_PT_PCR)(0x00000009)
+#define TPM_PT_PCR_RESET_L4     (TPM_PT_PCR)(0x0000000A)
+#define TPM_PT_PCR_NO_INCREMENT (TPM_PT_PCR)(0x00000011)
+#define TPM_PT_PCR_DRTM_RESET   (TPM_PT_PCR)(0x00000012)
+#define TPM_PT_PCR_POLICY       (TPM_PT_PCR)(0x00000013)
+#define TPM_PT_PCR_AUTH         (TPM_PT_PCR)(0x00000014)
+#define TPM_PT_PCR_LAST         (TPM_PT_PCR)(0x00000014)
+
+// Table 24 - TPM_PS Constants
+typedef UINT32 TPM_PS;
+#define TPM_PS_MAIN           (TPM_PS)(0x00000000)
+#define TPM_PS_PC             (TPM_PS)(0x00000001)
+#define TPM_PS_PDA            (TPM_PS)(0x00000002)
+#define TPM_PS_CELL_PHONE     (TPM_PS)(0x00000003)
+#define TPM_PS_SERVER         (TPM_PS)(0x00000004)
+#define TPM_PS_PERIPHERAL     (TPM_PS)(0x00000005)
+#define TPM_PS_TSS            (TPM_PS)(0x00000006)
+#define TPM_PS_STORAGE        (TPM_PS)(0x00000007)
+#define TPM_PS_AUTHENTICATION (TPM_PS)(0x00000008)
+#define TPM_PS_EMBEDDED       (TPM_PS)(0x00000009)
+#define TPM_PS_HARDCOPY       (TPM_PS)(0x0000000A)
+#define TPM_PS_INFRASTRUCTURE (TPM_PS)(0x0000000B)
+#define TPM_PS_VIRTUALIZATION (TPM_PS)(0x0000000C)
+#define TPM_PS_TNC            (TPM_PS)(0x0000000D)
+#define TPM_PS_MULTI_TENANT   (TPM_PS)(0x0000000E)
+#define TPM_PS_TC             (TPM_PS)(0x0000000F)
+
+// 7 Handles
+
+// Table 25 - Handles Types
+//
+// NOTE: Comment because it has same name as TPM1.2 (value is same, so not runtime issue)
+//
+//typedef UINT32    TPM_HANDLE;
+
+// Table 26 - TPM_HT Constants
+typedef UINT8 TPM_HT;
+#define TPM_HT_PCR            (TPM_HT)(0x00)
+#define TPM_HT_NV_INDEX       (TPM_HT)(0x01)
+#define TPM_HT_HMAC_SESSION   (TPM_HT)(0x02)
+#define TPM_HT_LOADED_SESSION (TPM_HT)(0x02)
+#define TPM_HT_POLICY_SESSION (TPM_HT)(0x03)
+#define TPM_HT_ACTIVE_SESSION (TPM_HT)(0x03)
+#define TPM_HT_PERMANENT      (TPM_HT)(0x40)
+#define TPM_HT_TRANSIENT      (TPM_HT)(0x80)
+#define TPM_HT_PERSISTENT     (TPM_HT)(0x81)
+
+// Table 27 - TPM_RH Constants
+typedef UINT32 TPM_RH;
+#define TPM_RH_FIRST       (TPM_RH)(0x40000000)
+#define TPM_RH_SRK         (TPM_RH)(0x40000000)
+#define TPM_RH_OWNER       (TPM_RH)(0x40000001)
+#define TPM_RH_REVOKE      (TPM_RH)(0x40000002)
+#define TPM_RH_TRANSPORT   (TPM_RH)(0x40000003)
+#define TPM_RH_OPERATOR    (TPM_RH)(0x40000004)
+#define TPM_RH_ADMIN       (TPM_RH)(0x40000005)
+#define TPM_RH_EK          (TPM_RH)(0x40000006)
+#define TPM_RH_NULL        (TPM_RH)(0x40000007)
+#define TPM_RH_UNASSIGNED  (TPM_RH)(0x40000008)
+#define TPM_RS_PW          (TPM_RH)(0x40000009)
+#define TPM_RH_LOCKOUT     (TPM_RH)(0x4000000A)
+#define TPM_RH_ENDORSEMENT (TPM_RH)(0x4000000B)
+#define TPM_RH_PLATFORM    (TPM_RH)(0x4000000C)
+#define TPM_RH_PLATFORM_NV (TPM_RH)(0x4000000D)
+#define TPM_RH_AUTH_00     (TPM_RH)(0x40000010)
+#define TPM_RH_AUTH_FF     (TPM_RH)(0x4000010F)
+#define TPM_RH_LAST        (TPM_RH)(0x4000010F)
+
+// Table 28 - TPM_HC Constants
+typedef TPM_HANDLE TPM_HC;
+#define HR_HANDLE_MASK       (TPM_HC)(0x00FFFFFF)
+#define HR_RANGE_MASK        (TPM_HC)(0xFF000000)
+#define HR_SHIFT             (TPM_HC)(24)
+#define HR_PCR               (TPM_HC)((TPM_HC)TPM_HT_PCR << HR_SHIFT)
+#define HR_HMAC_SESSION      (TPM_HC)((TPM_HC)TPM_HT_HMAC_SESSION << HR_SHIFT)
+#define HR_POLICY_SESSION    (TPM_HC)((TPM_HC)TPM_HT_POLICY_SESSION << HR_SHIFT)
+#define HR_TRANSIENT         (TPM_HC)((TPM_HC)TPM_HT_TRANSIENT << HR_SHIFT)
+#define HR_PERSISTENT        (TPM_HC)((TPM_HC)TPM_HT_PERSISTENT << HR_SHIFT)
+#define HR_NV_INDEX          (TPM_HC)((TPM_HC)TPM_HT_NV_INDEX << HR_SHIFT)
+#define HR_PERMANENT         (TPM_HC)((TPM_HC)TPM_HT_PERMANENT << HR_SHIFT)
+#define PCR_FIRST            (TPM_HC)(HR_PCR + 0)
+#define PCR_LAST             (TPM_HC)(PCR_FIRST + IMPLEMENTATION_PCR - 1)
+#define HMAC_SESSION_FIRST   (TPM_HC)(HR_HMAC_SESSION + 0)
+#define HMAC_SESSION_LAST    (TPM_HC)(HMAC_SESSION_FIRST + MAX_ACTIVE_SESSIONS - 1)
+#define LOADED_SESSION_FIRST (TPM_HC)(HMAC_SESSION_FIRST)
+#define LOADED_SESSION_LAST  (TPM_HC)(HMAC_SESSION_LAST)
+#define POLICY_SESSION_FIRST (TPM_HC)(HR_POLICY_SESSION + 0)
+#define POLICY_SESSION_LAST  (TPM_HC)(POLICY_SESSION_FIRST + MAX_ACTIVE_SESSIONS - 1)
+#define TRANSIENT_FIRST      (TPM_HC)(HR_TRANSIENT + 0)
+#define ACTIVE_SESSION_FIRST (TPM_HC)(POLICY_SESSION_FIRST)
+#define ACTIVE_SESSION_LAST  (TPM_HC)(POLICY_SESSION_LAST)
+#define TRANSIENT_LAST       (TPM_HC)(TRANSIENT_FIRST+MAX_LOADED_OBJECTS - 1)
+#define PERSISTENT_FIRST     (TPM_HC)(HR_PERSISTENT + 0)
+#define PERSISTENT_LAST      (TPM_HC)(PERSISTENT_FIRST + 0x00FFFFFF)
+#define PLATFORM_PERSISTENT  (TPM_HC)(PERSISTENT_FIRST + 0x00800000)
+#define NV_INDEX_FIRST       (TPM_HC)(HR_NV_INDEX + 0)
+#define NV_INDEX_LAST        (TPM_HC)(NV_INDEX_FIRST + 0x00FFFFFF)
+#define PERMANENT_FIRST      (TPM_HC)(TPM_RH_FIRST)
+#define PERMANENT_LAST       (TPM_HC)(TPM_RH_LAST)
+
+// 8 Attribute Structures
+
+// Table 29 - TPMA_ALGORITHM Bits
+typedef struct {
+  UINT32 asymmetric    : 1;
+  UINT32 symmetric     : 1;
+  UINT32 hash          : 1;
+  UINT32 object        : 1;
+  UINT32 reserved4_7   : 4;
+  UINT32 signing       : 1;
+  UINT32 encrypting    : 1;
+  UINT32 method        : 1;
+  UINT32 reserved11_31 : 21;
+} TPMA_ALGORITHM;
+
+// Table 30 - TPMA_OBJECT Bits
+typedef struct {
+  UINT32 reserved1            : 1;
+  UINT32 fixedTPM             : 1;
+  UINT32 stClear              : 1;
+  UINT32 reserved4            : 1;
+  UINT32 fixedParent          : 1;
+  UINT32 sensitiveDataOrigin  : 1;
+  UINT32 userWithAuth         : 1;
+  UINT32 adminWithPolicy      : 1;
+  UINT32 reserved8_9          : 2;
+  UINT32 noDA                 : 1;
+  UINT32 encryptedDuplication : 1;
+  UINT32 reserved12_15        : 4;
+  UINT32 restricted           : 1;
+  UINT32 decrypt              : 1;
+  UINT32 sign                 : 1;
+  UINT32 reserved19_31        : 13;
+} TPMA_OBJECT;
+
+// Table 31 - TPMA_SESSION Bits
+typedef struct {
+  UINT8 continueSession : 1;
+  UINT8 auditExclusive  : 1;
+  UINT8 auditReset      : 1;
+  UINT8 reserved3_4     : 2;
+  UINT8 decrypt         : 1;
+  UINT8 encrypt         : 1;
+  UINT8 audit           : 1;
+} TPMA_SESSION;
+
+// Table 32 - TPMA_LOCALITY Bits
+//
+// NOTE: Use low case here to resolve conflict
+//
+typedef struct {
+  UINT8 locZero  : 1;
+  UINT8 locOne   : 1;
+  UINT8 locTwo   : 1;
+  UINT8 locThree : 1;
+  UINT8 locFour  : 1;
+  UINT8 Extended : 3;
+} TPMA_LOCALITY;
+
+// Table 33 - TPMA_PERMANENT Bits
+typedef struct {
+  UINT32 ownerAuthSet       : 1;
+  UINT32 endorsementAuthSet : 1;
+  UINT32 lockoutAuthSet     : 1;
+  UINT32 reserved3_7        : 5;
+  UINT32 disableClear       : 1;
+  UINT32 inLockout          : 1;
+  UINT32 tpmGeneratedEPS    : 1;
+  UINT32 reserved11_31      : 21;
+} TPMA_PERMANENT;
+
+// Table 34 - TPMA_STARTUP_CLEAR Bits
+typedef struct {
+  UINT32 phEnable     : 1;
+  UINT32 shEnable     : 1;
+  UINT32 ehEnable     : 1;
+  UINT32 reserved3_30 : 28;
+  UINT32 orderly      : 1;
+} TPMA_STARTUP_CLEAR;
+
+// Table 35 - TPMA_MEMORY Bits
+typedef struct {
+  UINT32 sharedRAM         : 1;
+  UINT32 sharedNV          : 1;
+  UINT32 objectCopiedToRam : 1;
+  UINT32 reserved3_31      : 29;
+} TPMA_MEMORY;
+
+// Table 36 - TPMA_CC Bits
+typedef struct {
+  UINT32 commandIndex  : 16;
+  UINT32 reserved16_21 : 6;
+  UINT32 nv            : 1;
+  UINT32 extensive     : 1;
+  UINT32 flushed       : 1;
+  UINT32 cHandles      : 3;
+  UINT32 rHandle       : 1;
+  UINT32 V             : 1;
+  UINT32 Res           : 2;
+} TPMA_CC;
+
+// 9 Interface Types
+
+// Table 37 - TPMI_YES_NO Type
+typedef BYTE TPMI_YES_NO;
+
+// Table 38 - TPMI_DH_OBJECT Type
+typedef TPM_HANDLE TPMI_DH_OBJECT;
+
+// Table 39 - TPMI_DH_PERSISTENT Type
+typedef TPM_HANDLE TPMI_DH_PERSISTENT;
+
+// Table 40 - TPMI_DH_ENTITY Type
+typedef TPM_HANDLE TPMI_DH_ENTITY;
+
+// Table 41 - TPMI_DH_PCR Type
+typedef TPM_HANDLE TPMI_DH_PCR;
+
+// Table 42 - TPMI_SH_AUTH_SESSION Type
+typedef TPM_HANDLE TPMI_SH_AUTH_SESSION;
+
+// Table 43 - TPMI_SH_HMAC Type
+typedef TPM_HANDLE TPMI_SH_HMAC;
+
+// Table 44 - TPMI_SH_POLICY Type
+typedef TPM_HANDLE TPMI_SH_POLICY;
+
+// Table 45 - TPMI_DH_CONTEXT Type
+typedef TPM_HANDLE TPMI_DH_CONTEXT;
+
+// Table 46 - TPMI_RH_HIERARCHY Type
+typedef TPM_HANDLE TPMI_RH_HIERARCHY;
+
+// Table 47 - TPMI_RH_HIERARCHY_AUTH Type
+typedef TPM_HANDLE TPMI_RH_HIERARCHY_AUTH;
+
+// Table 48 - TPMI_RH_PLATFORM Type
+typedef TPM_HANDLE TPMI_RH_PLATFORM;
+
+// Table 49 - TPMI_RH_OWNER Type
+typedef TPM_HANDLE TPMI_RH_OWNER;
+
+// Table 50 - TPMI_RH_ENDORSEMENT Type
+typedef TPM_HANDLE TPMI_RH_ENDORSEMENT;
+
+// Table 51 - TPMI_RH_PROVISION Type
+typedef TPM_HANDLE TPMI_RH_PROVISION;
+
+// Table 52 - TPMI_RH_CLEAR Type
+typedef TPM_HANDLE TPMI_RH_CLEAR;
+
+// Table 53 - TPMI_RH_NV_AUTH Type
+typedef TPM_HANDLE TPMI_RH_NV_AUTH;
+
+// Table 54 - TPMI_RH_LOCKOUT Type
+typedef TPM_HANDLE TPMI_RH_LOCKOUT;
+
+// Table 55 - TPMI_RH_NV_INDEX Type
+typedef TPM_HANDLE TPMI_RH_NV_INDEX;
+
+// Table 56 - TPMI_ALG_HASH Type
+typedef TPM_ALG_ID TPMI_ALG_HASH;
+
+// Table 57 - TPMI_ALG_ASYM Type
+typedef TPM_ALG_ID TPMI_ALG_ASYM;
+
+// Table 58 - TPMI_ALG_SYM Type
+typedef TPM_ALG_ID TPMI_ALG_SYM;
+
+// Table 59 - TPMI_ALG_SYM_OBJECT Type
+typedef TPM_ALG_ID TPMI_ALG_SYM_OBJECT;
+
+// Table 60 - TPMI_ALG_SYM_MODE Type
+typedef TPM_ALG_ID TPMI_ALG_SYM_MODE;
+
+// Table 61 - TPMI_ALG_KDF Type
+typedef TPM_ALG_ID TPMI_ALG_KDF;
+
+// Table 62 - TPMI_ALG_SIG_SCHEME Type
+typedef TPM_ALG_ID TPMI_ALG_SIG_SCHEME;
+
+// Table 63 - TPMI_ECC_KEY_EXCHANGE Type
+typedef TPM_ALG_ID TPMI_ECC_KEY_EXCHANGE;
+
+// Table 64 - TPMI_ST_COMMAND_TAG Type
+typedef TPM_ST TPMI_ST_COMMAND_TAG;
+
+// 10 Structure Definitions
+
+// Table 65 - TPMS_ALGORITHM_DESCRIPTION Structure
+typedef struct {
+  TPM_ALG_ID     alg;
+  TPMA_ALGORITHM attributes;
+} TPMS_ALGORITHM_DESCRIPTION;
+
+// Table 66 - TPMU_HA Union
+typedef union {
+  BYTE sha1[SHA1_DIGEST_SIZE];
+  BYTE sha256[SHA256_DIGEST_SIZE];
+  BYTE sm3_256[SM3_256_DIGEST_SIZE];
+  BYTE sha384[SHA384_DIGEST_SIZE];
+  BYTE sha512[SHA512_DIGEST_SIZE];
+} TPMU_HA;
+
+// Table 67 - TPMT_HA Structure
+typedef struct {
+  TPMI_ALG_HASH hashAlg;
+  TPMU_HA       digest;
+} TPMT_HA;
+
+// Table 68 - TPM2B_DIGEST Structure
+typedef struct {
+  UINT16 size;
+  BYTE   buffer[sizeof(TPMU_HA)];
+} TPM2B_DIGEST;
+
+// Table 69 - TPM2B_DATA Structure
+typedef struct {
+  UINT16 size;
+  BYTE   buffer[sizeof(TPMT_HA)];
+} TPM2B_DATA;
+
+// Table 70 - TPM2B_NONCE Types
+typedef TPM2B_DIGEST TPM2B_NONCE;
+
+// Table 71 - TPM2B_AUTH Types
+typedef TPM2B_DIGEST TPM2B_AUTH;
+
+// Table 72 - TPM2B_OPERAND Types
+typedef TPM2B_DIGEST TPM2B_OPERAND;
+
+// Table 73 - TPM2B_EVENT Structure
+typedef struct {
+  UINT16 size;
+  BYTE   buffer[1024];
+} TPM2B_EVENT;
+
+// Table 74 - TPM2B_MAX_BUFFER Structure
+typedef struct {
+  UINT16 size;
+  BYTE   buffer[MAX_DIGEST_BUFFER];
+} TPM2B_MAX_BUFFER;
+
+// Table 75 - TPM2B_MAX_NV_BUFFER Structure
+typedef struct {
+  UINT16 size;
+  BYTE   buffer[MAX_NV_INDEX_SIZE];
+} TPM2B_MAX_NV_BUFFER;
+
+// Table 76 - TPM2B_TIMEOUT Structure
+typedef struct {
+  UINT16 size;
+  BYTE   buffer[sizeof(UINT64)];
+} TPM2B_TIMEOUT;
+
+// Table 77 -- TPM2B_IV Structure <I/O>
+typedef struct {
+  UINT16 size;
+  BYTE   buffer[MAX_SYM_BLOCK_SIZE];
+} TPM2B_IV;
+
+// Table 78 - TPMU_NAME Union
+typedef union {
+  TPMT_HA    digest;
+  TPM_HANDLE handle;
+} TPMU_NAME;
+
+// Table 79 - TPM2B_NAME Structure
+typedef struct {
+  UINT16 size;
+  BYTE   name[sizeof(TPMU_NAME)];
+} TPM2B_NAME;
+
+// Table 80 - TPMS_PCR_SELECT Structure
+typedef struct {
+  UINT8 sizeofSelect;
+  BYTE  pcrSelect[PCR_SELECT_MAX];
+} TPMS_PCR_SELECT;
+
+// Table 81 - TPMS_PCR_SELECTION Structure
+typedef struct {
+  TPMI_ALG_HASH hash;
+  UINT8         sizeofSelect;
+  BYTE          pcrSelect[PCR_SELECT_MAX];
+} TPMS_PCR_SELECTION;
+
+// Table 84 - TPMT_TK_CREATION Structure
+typedef struct {
+  TPM_ST            tag;
+  TPMI_RH_HIERARCHY hierarchy;
+  TPM2B_DIGEST      digest;
+} TPMT_TK_CREATION;
+
+// Table 85 - TPMT_TK_VERIFIED Structure
+typedef struct {
+  TPM_ST            tag;
+  TPMI_RH_HIERARCHY hierarchy;
+  TPM2B_DIGEST      digest;
+} TPMT_TK_VERIFIED;
+
+// Table 86 - TPMT_TK_AUTH Structure
+typedef struct {
+  TPM_ST            tag;
+  TPMI_RH_HIERARCHY hierarchy;
+  TPM2B_DIGEST      digest;
+} TPMT_TK_AUTH;
+
+// Table 87 - TPMT_TK_HASHCHECK Structure
+typedef struct {
+  TPM_ST            tag;
+  TPMI_RH_HIERARCHY hierarchy;
+  TPM2B_DIGEST      digest;
+} TPMT_TK_HASHCHECK;
+
+// Table 88 - TPMS_ALG_PROPERTY Structure
+typedef struct {
+  TPM_ALG_ID     alg;
+  TPMA_ALGORITHM algProperties;
+} TPMS_ALG_PROPERTY;
+
+// Table 89 - TPMS_TAGGED_PROPERTY Structure
+typedef struct {
+  TPM_PT property;
+  UINT32 value;
+} TPMS_TAGGED_PROPERTY;
+
+// Table 90 - TPMS_TAGGED_PCR_SELECT Structure
+typedef struct {
+  TPM_PT tag;
+  UINT8  sizeofSelect;
+  BYTE   pcrSelect[PCR_SELECT_MAX];
+} TPMS_TAGGED_PCR_SELECT;
+
+// Table 91 - TPML_CC Structure
+typedef struct {
+  UINT32 count;
+  TPM_CC commandCodes[MAX_CAP_CC];
+} TPML_CC;
+
+// Table 92 - TPML_CCA Structure
+typedef struct {
+  UINT32  count;
+  TPMA_CC commandAttributes[MAX_CAP_CC];
+} TPML_CCA;
+
+// Table 93 - TPML_ALG Structure
+typedef struct {
+  UINT32     count;
+  TPM_ALG_ID algorithms[MAX_ALG_LIST_SIZE];
+} TPML_ALG;
+
+// Table 94 - TPML_HANDLE Structure
+typedef struct {
+  UINT32     count;
+  TPM_HANDLE handle[MAX_CAP_HANDLES];
+} TPML_HANDLE;
+
+// Table 95 - TPML_DIGEST Structure
+typedef struct {
+  UINT32       count;
+  TPM2B_DIGEST digests[8];
+} TPML_DIGEST;
+
+// Table 96 -- TPML_DIGEST_VALUES Structure <I/O>
+typedef struct {
+  UINT32  count;
+  TPMT_HA digests[HASH_COUNT];
+} TPML_DIGEST_VALUES;
+
+// Table 97 - TPM2B_DIGEST_VALUES Structure
+typedef struct {
+  UINT16 size;
+  BYTE   buffer[sizeof(TPML_DIGEST_VALUES)];
+} TPM2B_DIGEST_VALUES;
+
+// Table 98 - TPML_PCR_SELECTION Structure
+typedef struct {
+  UINT32             count;
+  TPMS_PCR_SELECTION pcrSelections[HASH_COUNT];
+} TPML_PCR_SELECTION;
+
+// Table 99 - TPML_ALG_PROPERTY Structure
+typedef struct {
+  UINT32            count;
+  TPMS_ALG_PROPERTY algProperties[MAX_CAP_ALGS];
+} TPML_ALG_PROPERTY;
+
+// Table 100 - TPML_TAGGED_TPM_PROPERTY Structure
+typedef struct {
+  UINT32               count;
+  TPMS_TAGGED_PROPERTY tpmProperty[MAX_TPM_PROPERTIES];
+} TPML_TAGGED_TPM_PROPERTY;
+
+// Table 101 - TPML_TAGGED_PCR_PROPERTY Structure
+typedef struct {
+  UINT32                 count;
+  TPMS_TAGGED_PCR_SELECT pcrProperty[MAX_PCR_PROPERTIES];
+} TPML_TAGGED_PCR_PROPERTY;
+
+// Table 102 - TPML_ECC_CURVE Structure
+typedef struct {
+  UINT32        count;
+  TPM_ECC_CURVE eccCurves[MAX_ECC_CURVES];
+} TPML_ECC_CURVE;
+
+// Table 103 - TPMU_CAPABILITIES Union
+typedef union {
+  TPML_ALG_PROPERTY        algorithms;
+  TPML_HANDLE              handles;
+  TPML_CCA                 command;
+  TPML_CC                  ppCommands;
+  TPML_CC                  auditCommands;
+  TPML_PCR_SELECTION       assignedPCR;
+  TPML_TAGGED_TPM_PROPERTY tpmProperties;
+  TPML_TAGGED_PCR_PROPERTY pcrProperties;
+  TPML_ECC_CURVE           eccCurves;
+} TPMU_CAPABILITIES;
+
+// Table 104 - TPMS_CAPABILITY_DATA Structure
+typedef struct {
+  TPM_CAP           capability;
+  TPMU_CAPABILITIES data;
+} TPMS_CAPABILITY_DATA;
+
+// Table 105 - TPMS_CLOCK_INFO Structure
+typedef struct {
+  UINT64      clock;
+  UINT32      resetCount;
+  UINT32      restartCount;
+  TPMI_YES_NO safe;
+} TPMS_CLOCK_INFO;
+
+// Table 106 - TPMS_TIME_INFO Structure
+typedef struct {
+  UINT64          time;
+  TPMS_CLOCK_INFO clockInfo;
+} TPMS_TIME_INFO;
+
+// Table 107 - TPMS_TIME_ATTEST_INFO Structure
+typedef struct {
+  TPMS_TIME_INFO time;
+  UINT64         firmwareVersion;
+} TPMS_TIME_ATTEST_INFO;
+
+// Table 108 - TPMS_CERTIFY_INFO Structure
+typedef struct {
+  TPM2B_NAME name;
+  TPM2B_NAME qualifiedName;
+} TPMS_CERTIFY_INFO;
+
+// Table 109 - TPMS_QUOTE_INFO Structure
+typedef struct {
+  TPML_PCR_SELECTION pcrSelect;
+  TPM2B_DIGEST       pcrDigest;
+} TPMS_QUOTE_INFO;
+
+// Table 110 - TPMS_COMMAND_AUDIT_INFO Structure
+typedef struct {
+  UINT64       auditCounter;
+  TPM_ALG_ID   digestAlg;
+  TPM2B_DIGEST auditDigest;
+  TPM2B_DIGEST commandDigest;
+} TPMS_COMMAND_AUDIT_INFO;
+
+// Table 111 - TPMS_SESSION_AUDIT_INFO Structure
+typedef struct {
+  TPMI_YES_NO  exclusiveSession;
+  TPM2B_DIGEST sessionDigest;
+} TPMS_SESSION_AUDIT_INFO;
+
+// Table 112 - TPMS_CREATION_INFO Structure
+typedef struct {
+  TPM2B_NAME   objectName;
+  TPM2B_DIGEST creationHash;
+} TPMS_CREATION_INFO;
+
+// Table 113 - TPMS_NV_CERTIFY_INFO Structure
+typedef struct {
+  TPM2B_NAME          indexName;
+  UINT16              offset;
+  TPM2B_MAX_NV_BUFFER nvContents;
+} TPMS_NV_CERTIFY_INFO;
+
+// Table 114 - TPMI_ST_ATTEST Type
+typedef TPM_ST TPMI_ST_ATTEST;
+
+// Table 115 - TPMU_ATTEST Union
+typedef union {
+  TPMS_CERTIFY_INFO       certify;
+  TPMS_CREATION_INFO      creation;
+  TPMS_QUOTE_INFO         quote;
+  TPMS_COMMAND_AUDIT_INFO commandAudit;
+  TPMS_SESSION_AUDIT_INFO sessionAudit;
+  TPMS_TIME_ATTEST_INFO   time;
+  TPMS_NV_CERTIFY_INFO    nv;
+} TPMU_ATTEST;
+
+// Table 116 - TPMS_ATTEST Structure
+typedef struct {
+  TPM_GENERATED   magic;
+  TPMI_ST_ATTEST  type;
+  TPM2B_NAME      qualifiedSigner;
+  TPM2B_DATA      extraData;
+  TPMS_CLOCK_INFO clockInfo;
+  UINT64          firmwareVersion;
+  TPMU_ATTEST     attested;
+} TPMS_ATTEST;
+
+// Table 117 - TPM2B_ATTEST Structure
+typedef struct {
+  UINT16 size;
+  BYTE   attestationData[sizeof(TPMS_ATTEST)];
+} TPM2B_ATTEST;
+
+// Table 118 - TPMS_AUTH_COMMAND Structure
+typedef struct {
+  TPMI_SH_AUTH_SESSION sessionHandle;
+  TPM2B_NONCE          nonce;
+  TPMA_SESSION         sessionAttributes;
+  TPM2B_AUTH           hmac;
+} TPMS_AUTH_COMMAND;
+
+// Table 119 - TPMS_AUTH_RESPONSE Structure
+typedef struct {
+  TPM2B_NONCE  nonce;
+  TPMA_SESSION sessionAttributes;
+  TPM2B_AUTH   hmac;
+} TPMS_AUTH_RESPONSE;
+
+// 11 Algorithm Parameters and Structures
+
+// Table 120 - TPMI_AES_KEY_BITS Type
+typedef TPM_KEY_BITS TPMI_AES_KEY_BITS;
+
+// Table 121 - TPMI_SM4_KEY_BITS Type
+typedef TPM_KEY_BITS TPMI_SM4_KEY_BITS;
+
+// Table 122 - TPMU_SYM_KEY_BITS Union
+typedef union {
+  TPMI_AES_KEY_BITS aes;
+  TPMI_SM4_KEY_BITS SM4;
+  TPM_KEY_BITS      sym;
+  TPMI_ALG_HASH     xor;
+} TPMU_SYM_KEY_BITS;
+
+// Table 123 - TPMU_SYM_MODE Union
+typedef union {
+  TPMI_ALG_SYM_MODE aes;
+  TPMI_ALG_SYM_MODE SM4;
+  TPMI_ALG_SYM_MODE sym;
+} TPMU_SYM_MODE;
+
+// Table 125 - TPMT_SYM_DEF Structure
+typedef struct {
+  TPMI_ALG_SYM      algorithm;
+  TPMU_SYM_KEY_BITS keyBits;
+  TPMU_SYM_MODE     mode;
+} TPMT_SYM_DEF;
+
+// Table 126 - TPMT_SYM_DEF_OBJECT Structure
+typedef struct {
+  TPMI_ALG_SYM_OBJECT algorithm;
+  TPMU_SYM_KEY_BITS   keyBits;
+  TPMU_SYM_MODE       mode;
+} TPMT_SYM_DEF_OBJECT;
+
+// Table 127 - TPM2B_SYM_KEY Structure
+typedef struct {
+  UINT16 size;
+  BYTE   buffer[MAX_SYM_KEY_BYTES];
+} TPM2B_SYM_KEY;
+
+// Table 128 - TPMS_SYMCIPHER_PARMS Structure
+typedef struct {
+  TPMT_SYM_DEF_OBJECT sym;
+} TPMS_SYMCIPHER_PARMS;
+
+// Table 129 - TPM2B_SENSITIVE_DATA Structure
+typedef struct {
+  UINT16 size;
+  BYTE   buffer[MAX_SYM_DATA];
+} TPM2B_SENSITIVE_DATA;
+
+// Table 130 - TPMS_SENSITIVE_CREATE Structure
+typedef struct {
+  TPM2B_AUTH           userAuth;
+  TPM2B_SENSITIVE_DATA data;
+} TPMS_SENSITIVE_CREATE;
+
+// Table 131 - TPM2B_SENSITIVE_CREATE Structure
+typedef struct {
+  UINT16                size;
+  TPMS_SENSITIVE_CREATE sensitive;
+} TPM2B_SENSITIVE_CREATE;
+
+// Table 132 - TPMS_SCHEME_SIGHASH Structure
+typedef struct {
+  TPMI_ALG_HASH hashAlg;
+} TPMS_SCHEME_SIGHASH;
+
+// Table 133 - TPMI_ALG_KEYEDHASH_SCHEME Type
+typedef TPM_ALG_ID TPMI_ALG_KEYEDHASH_SCHEME;
+
+// Table 134 - HMAC_SIG_SCHEME Types
+typedef TPMS_SCHEME_SIGHASH TPMS_SCHEME_HMAC;
+
+// Table 135 - TPMS_SCHEME_XOR Structure
+typedef struct {
+  TPMI_ALG_HASH hashAlg;
+  TPMI_ALG_KDF  kdf;
+} TPMS_SCHEME_XOR;
+
+// Table 136 - TPMU_SCHEME_KEYEDHASH Union
+typedef union {
+  TPMS_SCHEME_HMAC hmac;
+  TPMS_SCHEME_XOR  xor;
+} TPMU_SCHEME_KEYEDHASH;
+
+// Table 137 - TPMT_KEYEDHASH_SCHEME Structure
+typedef struct {
+  TPMI_ALG_KEYEDHASH_SCHEME scheme;
+  TPMU_SCHEME_KEYEDHASH     details;
+} TPMT_KEYEDHASH_SCHEME;
+
+// Table 138 - RSA_SIG_SCHEMES Types
+typedef TPMS_SCHEME_SIGHASH TPMS_SCHEME_RSASSA;
+typedef TPMS_SCHEME_SIGHASH TPMS_SCHEME_RSAPSS;
+
+// Table 139 - ECC_SIG_SCHEMES Types
+typedef TPMS_SCHEME_SIGHASH TPMS_SCHEME_ECDSA;
+typedef TPMS_SCHEME_SIGHASH TPMS_SCHEME_SM2;
+typedef TPMS_SCHEME_SIGHASH TPMS_SCHEME_ECSCHNORR;
+
+// Table 140 - TPMS_SCHEME_ECDAA Structure
+typedef struct {
+  TPMI_ALG_HASH hashAlg;
+  UINT16        count;
+} TPMS_SCHEME_ECDAA;
+
+// Table 141 - TPMU_SIG_SCHEME Union
+typedef union {
+  TPMS_SCHEME_RSASSA    rsassa;
+  TPMS_SCHEME_RSAPSS    rsapss;
+  TPMS_SCHEME_ECDSA     ecdsa;
+  TPMS_SCHEME_ECDAA     ecdaa;
+  TPMS_SCHEME_ECSCHNORR ecSchnorr;
+  TPMS_SCHEME_HMAC      hmac;
+  TPMS_SCHEME_SIGHASH   any;
+} TPMU_SIG_SCHEME;
+
+// Table 142 - TPMT_SIG_SCHEME Structure
+typedef struct {
+  TPMI_ALG_SIG_SCHEME scheme;
+  TPMU_SIG_SCHEME     details;
+} TPMT_SIG_SCHEME;
+
+// Table 143 - TPMS_SCHEME_OAEP Structure
+typedef struct {
+  TPMI_ALG_HASH hashAlg;
+} TPMS_SCHEME_OAEP;
+
+// Table 144 - TPMS_SCHEME_ECDH Structure
+typedef struct {
+  TPMI_ALG_HASH hashAlg;
+} TPMS_SCHEME_ECDH;
+
+// Table 145 - TPMS_SCHEME_MGF1 Structure
+typedef struct {
+  TPMI_ALG_HASH hashAlg;
+} TPMS_SCHEME_MGF1;
+
+// Table 146 - TPMS_SCHEME_KDF1_SP800_56a Structure
+typedef struct {
+  TPMI_ALG_HASH hashAlg;
+} TPMS_SCHEME_KDF1_SP800_56a;
+
+// Table 147 - TPMS_SCHEME_KDF2 Structure
+typedef struct {
+  TPMI_ALG_HASH hashAlg;
+} TPMS_SCHEME_KDF2;
+
+// Table 148 - TPMS_SCHEME_KDF1_SP800_108 Structure
+typedef struct {
+  TPMI_ALG_HASH hashAlg;
+} TPMS_SCHEME_KDF1_SP800_108;
+
+// Table 149 - TPMU_KDF_SCHEME Union
+typedef union {
+  TPMS_SCHEME_MGF1           mgf1;
+  TPMS_SCHEME_KDF1_SP800_56a kdf1_SP800_56a;
+  TPMS_SCHEME_KDF2           kdf2;
+  TPMS_SCHEME_KDF1_SP800_108 kdf1_sp800_108;
+} TPMU_KDF_SCHEME;
+
+// Table 150 - TPMT_KDF_SCHEME Structure
+typedef struct {
+  TPMI_ALG_KDF    scheme;
+  TPMU_KDF_SCHEME details;
+} TPMT_KDF_SCHEME;
+
+// Table 151 - TPMI_ALG_ASYM_SCHEME Type
+typedef TPM_ALG_ID TPMI_ALG_ASYM_SCHEME;
+
+// Table 152 - TPMU_ASYM_SCHEME Union
+typedef union {
+  TPMS_SCHEME_RSASSA    rsassa;
+  TPMS_SCHEME_RSAPSS    rsapss;
+  TPMS_SCHEME_OAEP      oaep;
+  TPMS_SCHEME_ECDSA     ecdsa;
+  TPMS_SCHEME_ECDAA     ecdaa;
+  TPMS_SCHEME_ECSCHNORR ecSchnorr;
+  TPMS_SCHEME_SIGHASH   anySig;
+} TPMU_ASYM_SCHEME;
+
+// Table 153 - TPMT_ASYM_SCHEME Structure
+typedef struct {
+  TPMI_ALG_ASYM_SCHEME scheme;
+  TPMU_ASYM_SCHEME     details;
+} TPMT_ASYM_SCHEME;
+
+// Table 154 - TPMI_ALG_RSA_SCHEME Type
+typedef TPM_ALG_ID TPMI_ALG_RSA_SCHEME;
+
+// Table 155 - TPMT_RSA_SCHEME Structure
+typedef struct {
+  TPMI_ALG_RSA_SCHEME scheme;
+  TPMU_ASYM_SCHEME    details;
+} TPMT_RSA_SCHEME;
+
+// Table 156 - TPMI_ALG_RSA_DECRYPT Type
+typedef TPM_ALG_ID TPMI_ALG_RSA_DECRYPT;
+
+// Table 157 - TPMT_RSA_DECRYPT Structure
+typedef struct {
+  TPMI_ALG_RSA_DECRYPT scheme;
+  TPMU_ASYM_SCHEME     details;
+} TPMT_RSA_DECRYPT;
+
+// Table 158 - TPM2B_PUBLIC_KEY_RSA Structure
+typedef struct {
+  UINT16 size;
+  BYTE   buffer[MAX_RSA_KEY_BYTES];
+} TPM2B_PUBLIC_KEY_RSA;
+
+// Table 159 - TPMI_RSA_KEY_BITS Type
+typedef TPM_KEY_BITS TPMI_RSA_KEY_BITS;
+
+// Table 160 - TPM2B_PRIVATE_KEY_RSA Structure
+typedef struct {
+  UINT16 size;
+  BYTE   buffer[MAX_RSA_KEY_BYTES/2];
+} TPM2B_PRIVATE_KEY_RSA;
+
+// Table 161 - TPM2B_ECC_PARAMETER Structure
+typedef struct {
+  UINT16 size;
+  BYTE   buffer[MAX_ECC_KEY_BYTES];
+} TPM2B_ECC_PARAMETER;
+
+// Table 162 - TPMS_ECC_POINT Structure
+typedef struct {
+  TPM2B_ECC_PARAMETER x;
+  TPM2B_ECC_PARAMETER y;
+} TPMS_ECC_POINT;
+
+// Table 163 -- TPM2B_ECC_POINT Structure <I/O>
+typedef struct {
+  UINT16         size;
+  TPMS_ECC_POINT point;
+} TPM2B_ECC_POINT;
+
+// Table 164 - TPMI_ALG_ECC_SCHEME Type
+typedef TPM_ALG_ID TPMI_ALG_ECC_SCHEME;
+
+// Table 165 - TPMI_ECC_CURVE Type
+typedef TPM_ECC_CURVE TPMI_ECC_CURVE;
+
+// Table 166 - TPMT_ECC_SCHEME Structure
+typedef struct {
+  TPMI_ALG_ECC_SCHEME scheme;
+  TPMU_SIG_SCHEME     details;
+} TPMT_ECC_SCHEME;
+
+// Table 167 - TPMS_ALGORITHM_DETAIL_ECC Structure
+typedef struct {
+  TPM_ECC_CURVE       curveID;
+  UINT16              keySize;
+  TPMT_KDF_SCHEME     kdf;
+  TPMT_ECC_SCHEME     sign;
+  TPM2B_ECC_PARAMETER p;
+  TPM2B_ECC_PARAMETER a;
+  TPM2B_ECC_PARAMETER b;
+  TPM2B_ECC_PARAMETER gX;
+  TPM2B_ECC_PARAMETER gY;
+  TPM2B_ECC_PARAMETER n;
+  TPM2B_ECC_PARAMETER h;
+} TPMS_ALGORITHM_DETAIL_ECC;
+
+// Table 168 - TPMS_SIGNATURE_RSASSA Structure
+typedef struct {
+  TPMI_ALG_HASH        hash;
+  TPM2B_PUBLIC_KEY_RSA sig;
+} TPMS_SIGNATURE_RSASSA;
+
+// Table 169 - TPMS_SIGNATURE_RSAPSS Structure
+typedef struct {
+  TPMI_ALG_HASH        hash;
+  TPM2B_PUBLIC_KEY_RSA sig;
+} TPMS_SIGNATURE_RSAPSS;
+
+// Table 170 - TPMS_SIGNATURE_ECDSA Structure
+typedef struct {
+  TPMI_ALG_HASH       hash;
+  TPM2B_ECC_PARAMETER signatureR;
+  TPM2B_ECC_PARAMETER signatureS;
+} TPMS_SIGNATURE_ECDSA;
+
+// Table 171 - TPMU_SIGNATURE Union
+typedef union {
+  TPMS_SIGNATURE_RSASSA rsassa;
+  TPMS_SIGNATURE_RSAPSS rsapss;
+  TPMS_SIGNATURE_ECDSA  ecdsa;
+  TPMS_SIGNATURE_ECDSA  sm2;
+  TPMS_SIGNATURE_ECDSA  ecdaa;
+  TPMS_SIGNATURE_ECDSA  ecschnorr;
+  TPMT_HA               hmac;
+  TPMS_SCHEME_SIGHASH   any;
+} TPMU_SIGNATURE;
+
+// Table 172 - TPMT_SIGNATURE Structure
+typedef struct {
+  TPMI_ALG_SIG_SCHEME sigAlg;
+  TPMU_SIGNATURE      signature;
+} TPMT_SIGNATURE;
+
+// Table 173 - TPMU_ENCRYPTED_SECRET Union
+typedef union {
+  BYTE ecc[sizeof(TPMS_ECC_POINT)];
+  BYTE rsa[MAX_RSA_KEY_BYTES];
+  BYTE symmetric[sizeof(TPM2B_DIGEST)];
+  BYTE keyedHash[sizeof(TPM2B_DIGEST)];
+} TPMU_ENCRYPTED_SECRET;
+
+// Table 174 - TPM2B_ENCRYPTED_SECRET Structure
+typedef struct {
+  UINT16 size;
+  BYTE   secret[sizeof(TPMU_ENCRYPTED_SECRET)];
+} TPM2B_ENCRYPTED_SECRET;
+
+// 12 Key/Object Complex
+
+// Table 175 - TPMI_ALG_PUBLIC Type
+typedef TPM_ALG_ID TPMI_ALG_PUBLIC;
+
+// Table 176 - TPMU_PUBLIC_ID Union
+typedef union {
+  TPM2B_DIGEST         keyedHash;
+  TPM2B_DIGEST         sym;
+  TPM2B_PUBLIC_KEY_RSA rsa;
+  TPMS_ECC_POINT       ecc;
+} TPMU_PUBLIC_ID;
+
+// Table 177 - TPMS_KEYEDHASH_PARMS Structure
+typedef struct {
+  TPMT_KEYEDHASH_SCHEME scheme;
+} TPMS_KEYEDHASH_PARMS;
+
+// Table 178 - TPMS_ASYM_PARMS Structure
+typedef struct {
+  TPMT_SYM_DEF_OBJECT symmetric;
+  TPMT_ASYM_SCHEME    scheme;
+} TPMS_ASYM_PARMS;
+
+// Table 179 - TPMS_RSA_PARMS Structure
+typedef struct {
+  TPMT_SYM_DEF_OBJECT symmetric;
+  TPMT_RSA_SCHEME     scheme;
+  TPMI_RSA_KEY_BITS   keyBits;
+  UINT32              exponent;
+} TPMS_RSA_PARMS;
+
+// Table 180 - TPMS_ECC_PARMS Structure
+typedef struct {
+  TPMT_SYM_DEF_OBJECT symmetric;
+  TPMT_ECC_SCHEME     scheme;
+  TPMI_ECC_CURVE      curveID;
+  TPMT_KDF_SCHEME     kdf;
+} TPMS_ECC_PARMS;
+
+// Table 181 - TPMU_PUBLIC_PARMS Union
+typedef union {
+  TPMS_KEYEDHASH_PARMS keyedHashDetail;
+  TPMT_SYM_DEF_OBJECT  symDetail;
+  TPMS_RSA_PARMS       rsaDetail;
+  TPMS_ECC_PARMS       eccDetail;
+  TPMS_ASYM_PARMS      asymDetail;
+} TPMU_PUBLIC_PARMS;
+
+// Table 182 - TPMT_PUBLIC_PARMS Structure
+typedef struct {
+  TPMI_ALG_PUBLIC   type;
+  TPMU_PUBLIC_PARMS parameters;
+} TPMT_PUBLIC_PARMS;
+
+// Table 183 - TPMT_PUBLIC Structure
+typedef struct {
+  TPMI_ALG_PUBLIC   type;
+  TPMI_ALG_HASH     nameAlg;
+  TPMA_OBJECT       objectAttributes;
+  TPM2B_DIGEST      authPolicy;
+  TPMU_PUBLIC_PARMS parameters;
+  TPMU_PUBLIC_ID    unique;
+} TPMT_PUBLIC;
+
+// Table 184 - TPM2B_PUBLIC Structure
+typedef struct {
+  UINT16      size;
+  TPMT_PUBLIC publicArea;
+} TPM2B_PUBLIC;
+
+// Table 185 - TPM2B_PRIVATE_VENDOR_SPECIFIC Structure
+typedef struct {
+  UINT16 size;
+  BYTE   buffer[PRIVATE_VENDOR_SPECIFIC_BYTES];
+} TPM2B_PRIVATE_VENDOR_SPECIFIC;
+
+// Table 186 - TPMU_SENSITIVE_COMPOSITE Union
+typedef union {
+  TPM2B_PRIVATE_KEY_RSA         rsa;
+  TPM2B_ECC_PARAMETER           ecc;
+  TPM2B_SENSITIVE_DATA          bits;
+  TPM2B_SYM_KEY                 sym;
+  TPM2B_PRIVATE_VENDOR_SPECIFIC any;
+} TPMU_SENSITIVE_COMPOSITE;
+
+// Table 187 - TPMT_SENSITIVE Structure
+typedef struct {
+  TPMI_ALG_PUBLIC          sensitiveType;
+  TPM2B_AUTH               authValue;
+  TPM2B_DIGEST             seedValue;
+  TPMU_SENSITIVE_COMPOSITE sensitive;
+} TPMT_SENSITIVE;
+
+// Table 188 - TPM2B_SENSITIVE Structure
+typedef struct {
+  UINT16         size;
+  TPMT_SENSITIVE sensitiveArea;
+} TPM2B_SENSITIVE;
+
+// Table 189 - _PRIVATE Structure
+typedef struct {
+  TPM2B_DIGEST   integrityOuter;
+  TPM2B_DIGEST   integrityInner;
+  TPMT_SENSITIVE sensitive;
+} _PRIVATE;
+
+// Table 190 - TPM2B_PRIVATE Structure
+typedef struct {
+  UINT16 size;
+  BYTE   buffer[sizeof(_PRIVATE)];
+} TPM2B_PRIVATE;
+
+// Table 191 - _ID_OBJECT Structure
+typedef struct {
+  TPM2B_DIGEST integrityHMAC;
+  TPM2B_DIGEST encIdentity;
+} _ID_OBJECT;
+
+// Table 192 - TPM2B_ID_OBJECT Structure
+typedef struct {
+  UINT16 size;
+  BYTE   credential[sizeof(_ID_OBJECT)];
+} TPM2B_ID_OBJECT;
+
+// 13 NV Storage Structures
+
+// Table 193 - TPM_NV_INDEX Bits
+//
+// NOTE: Comment here to resolve conflict
+//
+//typedef struct {
+//  UINT32 index : 22;
+//  UINT32 space : 2;
+//  UINT32 RH_NV : 8;
+//} TPM_NV_INDEX;
+
+// Table 195 - TPMA_NV Bits
+typedef struct {
+  UINT32 TPMA_NV_PPWRITE        : 1;
+  UINT32 TPMA_NV_OWNERWRITE     : 1;
+  UINT32 TPMA_NV_AUTHWRITE      : 1;
+  UINT32 TPMA_NV_POLICYWRITE    : 1;
+  UINT32 TPMA_NV_COUNTER        : 1;
+  UINT32 TPMA_NV_BITS           : 1;
+  UINT32 TPMA_NV_EXTEND         : 1;
+  UINT32 reserved7_9            : 3;
+  UINT32 TPMA_NV_POLICY_DELETE  : 1;
+  UINT32 TPMA_NV_WRITELOCKED    : 1;
+  UINT32 TPMA_NV_WRITEALL       : 1;
+  UINT32 TPMA_NV_WRITEDEFINE    : 1;
+  UINT32 TPMA_NV_WRITE_STCLEAR  : 1;
+  UINT32 TPMA_NV_GLOBALLOCK     : 1;
+  UINT32 TPMA_NV_PPREAD         : 1;
+  UINT32 TPMA_NV_OWNERREAD      : 1;
+  UINT32 TPMA_NV_AUTHREAD       : 1;
+  UINT32 TPMA_NV_POLICYREAD     : 1;
+  UINT32 reserved20_24          : 5;
+  UINT32 TPMA_NV_NO_DA          : 1;
+  UINT32 TPMA_NV_ORDERLY        : 1;
+  UINT32 TPMA_NV_CLEAR_STCLEAR  : 1;
+  UINT32 TPMA_NV_READLOCKED     : 1;
+  UINT32 TPMA_NV_WRITTEN        : 1;
+  UINT32 TPMA_NV_PLATFORMCREATE : 1;
+  UINT32 TPMA_NV_READ_STCLEAR   : 1;
+} TPMA_NV;
+
+// Table 196 - TPMS_NV_PUBLIC Structure
+typedef struct {
+  TPMI_RH_NV_INDEX nvIndex;
+  TPMI_ALG_HASH    nameAlg;
+  TPMA_NV          attributes;
+  TPM2B_DIGEST     authPolicy;
+  UINT16           dataSize;
+} TPMS_NV_PUBLIC;
+
+// Table 197 - TPM2B_NV_PUBLIC Structure
+typedef struct {
+  UINT16         size;
+  TPMS_NV_PUBLIC nvPublic;
+} TPM2B_NV_PUBLIC;
+
+// 14 Context Data
+
+// Table 198 - TPM2B_CONTEXT_SENSITIVE Structure
+typedef struct {
+  UINT16 size;
+  BYTE   buffer[MAX_CONTEXT_SIZE];
+} TPM2B_CONTEXT_SENSITIVE;
+
+// Table 199 - TPMS_CONTEXT_DATA Structure
+typedef struct {
+  TPM2B_DIGEST            integrity;
+  TPM2B_CONTEXT_SENSITIVE encrypted;
+} TPMS_CONTEXT_DATA;
+
+// Table 200 - TPM2B_CONTEXT_DATA Structure
+typedef struct {
+  UINT16 size;
+  BYTE   buffer[sizeof(TPMS_CONTEXT_DATA)];
+} TPM2B_CONTEXT_DATA;
+
+// Table 201 - TPMS_CONTEXT Structure
+typedef struct {
+  UINT64             sequence;
+  TPMI_DH_CONTEXT    savedHandle;
+  TPMI_RH_HIERARCHY  hierarchy;
+  TPM2B_CONTEXT_DATA contextBlob;
+} TPMS_CONTEXT;
+
+// 15 Creation Data
+
+// Table 203 - TPMS_CREATION_DATA Structure
+typedef struct {
+  TPML_PCR_SELECTION pcrSelect;
+  TPM2B_DIGEST       pcrDigest;
+  TPMA_LOCALITY      locality;
+  TPM_ALG_ID         parentNameAlg;
+  TPM2B_NAME         parentName;
+  TPM2B_NAME         parentQualifiedName;
+  TPM2B_DATA         outsideInfo;
+} TPMS_CREATION_DATA;
+
+// Table 204 - TPM2B_CREATION_DATA Structure
+typedef struct {
+  UINT16             size;
+  TPMS_CREATION_DATA creationData;
+} TPM2B_CREATION_DATA;
+
+
+//
+// Command Header
+//
+typedef struct {
+  TPM_ST tag;
+  UINT32 paramSize;
+  TPM_CC commandCode;
+} TPM2_COMMAND_HEADER;
+
+typedef struct {
+  TPM_ST tag;
+  UINT32 paramSize;
+  TPM_RC responseCode;
+} TPM2_RESPONSE_HEADER;
+
+#pragma pack ()
+
+//
+// TCG Algorithm Registry
+//
+#define HASH_ALG_SHA1    0x00000001
+#define HASH_ALG_SHA256  0x00000002
+#define HASH_ALG_SHA384  0x00000004
+#define HASH_ALG_SHA512  0x00000008
+#define HASH_ALG_SM3_256 0x00000010
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tpm2Acpi.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tpm2Acpi.h
new file mode 100644
index 0000000000..b5d5e522dd
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tpm2Acpi.h
@@ -0,0 +1,56 @@
+/** @file
+  TPM2 ACPI table definition.
+
+Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved. <BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _TPM2_ACPI_H_
+#define _TPM2_ACPI_H_
+
+#include <IndustryStandard/Acpi.h>
+
+#pragma pack (1)
+
+#define EFI_TPM2_ACPI_TABLE_REVISION_3  3
+#define EFI_TPM2_ACPI_TABLE_REVISION_4  4
+#define EFI_TPM2_ACPI_TABLE_REVISION    EFI_TPM2_ACPI_TABLE_REVISION_4
+
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  // Flags field is replaced in version 4 and above
+  //    BIT0~15:  PlatformClass      This field is only valid for version 4 and above
+  //    BIT16~31: Reserved
+  UINT32                      Flags;
+  UINT64                      AddressOfControlArea;
+  UINT32                      StartMethod;
+//UINT8                       PlatformSpecificParameters[];
+} EFI_TPM2_ACPI_TABLE;
+
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_ACPI                                          2
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_TIS                                           6
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE             7
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE_WITH_ACPI   8
+
+typedef struct {
+  UINT32   Reserved;
+  UINT32   Error;
+  UINT32   Cancel;
+  UINT32   Start;
+  UINT64   InterruptControl;
+  UINT32   CommandSize;
+  UINT64   Command;
+  UINT32   ResponseSize;
+  UINT64   Response;
+} EFI_TPM2_ACPI_CONTROL_AREA;
+
+#pragma pack ()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/TpmPtp.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/TpmPtp.h
new file mode 100644
index 0000000000..f4c6b0676b
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/TpmPtp.h
@@ -0,0 +1,522 @@
+/** @file
+  Platform TPM Profile Specification definition for TPM2.0.
+  It covers both FIFO and CRB interface.
+
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _TPM_PTP_H_
+#define _TPM_PTP_H_
+
+//
+// PTP FIFO definition
+//
+
+//
+// Set structure alignment to 1-byte
+//
+#pragma pack (1)
+
+//
+// Register set map as specified in PTP specification Chapter 5
+//
+typedef struct {
+  ///
+  /// Used to gain ownership for this particular port.
+  ///
+  UINT8                             Access;             // 0
+  UINT8                             Reserved1[7];       // 1
+  ///
+  /// Controls interrupts.
+  ///
+  UINT32                            IntEnable;          // 8
+  ///
+  /// SIRQ vector to be used by the TPM.
+  ///
+  UINT8                             IntVector;          // 0ch
+  UINT8                             Reserved2[3];       // 0dh
+  ///
+  /// What caused interrupt.
+  ///
+  UINT32                            IntSts;             // 10h
+  ///
+  /// Shows which interrupts are supported by that particular TPM.
+  ///
+  UINT32                            InterfaceCapability;// 14h
+  ///
+  /// Status Register. Provides status of the TPM.
+  ///
+  UINT8                             Status;             // 18h
+  ///
+  /// Number of consecutive writes that can be done to the TPM.
+  ///
+  UINT16                            BurstCount;         // 19h
+  ///
+  /// Additional Status Register.
+  ///
+  UINT8                             StatusEx;           // 1Bh
+  UINT8                             Reserved3[8];
+  ///
+  /// Read or write FIFO, depending on transaction.
+  ///
+  UINT32                            DataFifo;           // 24h
+  UINT8                             Reserved4[8];       // 28h
+  ///
+  /// Used to identify the Interface types supported by the TPM.
+  ///
+  UINT32                            InterfaceId;        // 30h
+  UINT8                             Reserved5[0x4c];    // 34h
+  ///
+  /// Extended ReadFIFO or WriteFIFO, depending on the current bus cycle (read or write)
+  ///
+  UINT32                            XDataFifo;          // 80h
+  UINT8                             Reserved6[0xe7c];   // 84h
+  ///
+  /// Vendor ID
+  ///
+  UINT16                            Vid;                // 0f00h
+  ///
+  /// Device ID
+  ///
+  UINT16                            Did;                // 0f02h
+  ///
+  /// Revision ID
+  ///
+  UINT8                             Rid;                // 0f04h
+  UINT8                             Reserved[0xfb];     // 0f05h
+} PTP_FIFO_REGISTERS;
+
+//
+// Restore original structure alignment
+//
+#pragma pack ()
+
+//
+// Define pointer types used to access TIS registers on PC
+//
+typedef PTP_FIFO_REGISTERS  *PTP_FIFO_REGISTERS_PTR;
+
+//
+// Define bits of FIFO Interface Identifier Register
+//
+typedef union {
+  struct {
+    UINT32   InterfaceType:4;
+    UINT32   InterfaceVersion:4;
+    UINT32   CapLocality:1;
+    UINT32   Reserved1:2;
+    UINT32   CapDataXferSizeSupport:2;
+    UINT32   CapFIFO:1;
+    UINT32   CapCRB:1;
+    UINT32   CapIFRes:2;
+    UINT32   InterfaceSelector:2;
+    UINT32   IntfSelLock:1;
+    UINT32   Reserved2:4;
+    UINT32   Reserved3:8;
+  } Bits;
+  UINT32   Uint32;
+} PTP_FIFO_INTERFACE_IDENTIFIER;
+
+//
+// Define bits of FIFO Interface Capability Register
+//
+typedef union {
+  struct {
+    UINT32   DataAvailIntSupport:1;
+    UINT32   StsValidIntSupport:1;
+    UINT32   LocalityChangeIntSupport:1;
+    UINT32   InterruptLevelHigh:1;
+    UINT32   InterruptLevelLow:1;
+    UINT32   InterruptEdgeRising:1;
+    UINT32   InterruptEdgeFalling:1;
+    UINT32   CommandReadyIntSupport:1;
+    UINT32   BurstCountStatic:1;
+    UINT32   DataTransferSizeSupport:2;
+    UINT32   Reserved:17;
+    UINT32   InterfaceVersion:3;
+    UINT32   Reserved2:1;
+  } Bits;
+  UINT32   Uint32;
+} PTP_FIFO_INTERFACE_CAPABILITY;
+
+///
+/// InterfaceVersion
+///
+#define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_12  0x0
+#define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_13  0x2
+#define INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP     0x3
+
+
+//
+// Define bits of ACCESS and STATUS registers
+//
+
+///
+/// This bit is a 1 to indicate that the other bits in this register are valid.
+///
+#define PTP_FIFO_VALID                BIT7
+///
+/// Indicate that this locality is active.
+///
+#define PTP_FIFO_ACC_ACTIVE           BIT5
+///
+/// Set to 1 to indicate that this locality had the TPM taken away while
+/// this locality had the TIS_PC_ACC_ACTIVE bit set.
+///
+#define PTP_FIFO_ACC_SEIZED           BIT4
+///
+/// Set to 1 to indicate that TPM MUST reset the
+/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
+/// locality that is writing this bit.
+///
+#define PTP_FIFO_ACC_SEIZE            BIT3
+///
+/// When this bit is 1, another locality is requesting usage of the TPM.
+///
+#define PTP_FIFO_ACC_PENDIND          BIT2
+///
+/// Set to 1 to indicate that this locality is requesting to use TPM.
+///
+#define PTP_FIFO_ACC_RQUUSE           BIT1
+///
+/// A value of 1 indicates that a T/OS has not been established on the platform
+///
+#define PTP_FIFO_ACC_ESTABLISH        BIT0
+
+///
+/// This field indicates that STS_DATA and STS_EXPECT are valid
+///
+#define PTP_FIFO_STS_VALID            BIT7
+///
+/// When this bit is 1, TPM is in the Ready state,
+/// indicating it is ready to receive a new command.
+///
+#define PTP_FIFO_STS_READY            BIT6
+///
+/// Write a 1 to this bit to cause the TPM to execute that command.
+///
+#define PTP_FIFO_STS_GO               BIT5
+///
+/// This bit indicates that the TPM has data available as a response.
+///
+#define PTP_FIFO_STS_DATA             BIT4
+///
+/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
+///
+#define PTP_FIFO_STS_EXPECT           BIT3
+///
+/// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.
+///
+#define PTP_FIFO_STS_SELFTEST_DONE    BIT2
+///
+/// Writes a 1 to this bit to force the TPM to re-send the response.
+///
+#define PTP_FIFO_STS_RETRY            BIT1
+
+///
+/// TPM Family Identifier.
+/// 00: TPM 1.2 Family
+/// 01: TPM 2.0 Family
+///
+#define PTP_FIFO_STS_EX_TPM_FAMILY    (BIT2 | BIT3)
+#define PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET    (2)
+#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM12    (0)
+#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20    (BIT2)
+///
+/// A write of 1 after tpmGo and before dataAvail aborts the currently executing command, resulting in a response of TPM_RC_CANCELLED.
+/// A write of 1 after dataAvail and before tpmGo is ignored by the TPM.
+///
+#define PTP_FIFO_STS_EX_CANCEL        BIT0
+
+
+//
+// PTP CRB definition
+//
+
+//
+// Set structure alignment to 1-byte
+//
+#pragma pack (1)
+
+//
+// Register set map as specified in PTP specification Chapter 5
+//
+typedef struct {
+  ///
+  /// Used to determine current state of Locality of the TPM.
+  ///
+  UINT32                            LocalityState;             // 0
+  UINT8                             Reserved1[4];              // 4
+  ///
+  /// Used to gain control of the TPM by this Locality.
+  ///
+  UINT32                            LocalityControl;           // 8
+  ///
+  /// Used to determine whether Locality has been granted or Seized.
+  ///
+  UINT32                            LocalityStatus;            // 0ch
+  UINT8                             Reserved2[0x20];           // 10h
+  ///
+  /// Used to identify the Interface types supported by the TPM.
+  ///
+  UINT32                            InterfaceId;               // 30h
+  ///
+  /// Vendor ID
+  ///
+  UINT16                            Vid;                       // 34h
+  ///
+  /// Device ID
+  ///
+  UINT16                            Did;                       // 36h
+  ///
+  /// Optional Register used in low memory environments prior to CRB_DATA_BUFFER availability.
+  ///
+  UINT64                            CrbControlExtension;       // 38h
+  ///
+  /// Register used to initiate transactions for the CRB interface.
+  ///
+  UINT32                            CrbControlRequest;         // 40h
+  ///
+  /// Register used by the TPM to provide status of the CRB interface.
+  ///
+  UINT32                            CrbControlStatus;          // 44h
+  ///
+  /// Register used by software to cancel command processing.
+  ///
+  UINT32                            CrbControlCancel;          // 48h
+  ///
+  /// Register used to indicate presence of command or response data in the CRB buffer.
+  ///
+  UINT32                            CrbControlStart;           // 4Ch
+  ///
+  /// Register used to configure and respond to interrupts.
+  ///
+  UINT32                            CrbInterruptEnable;        // 50h
+  UINT32                            CrbInterruptStatus;        // 54h
+  ///
+  /// Size of the Command buffer.
+  ///
+  UINT32                            CrbControlCommandSize;     // 58h
+  ///
+  /// Command buffer start address
+  ///
+  UINT32                            CrbControlCommandAddressLow;   // 5Ch
+  UINT32                            CrbControlCommandAddressHigh;  // 60h
+  ///
+  /// Size of the Response buffer
+  ///
+  UINT32                            CrbControlResponseSize;    // 64h
+  ///
+  /// Address of the start of the Response buffer
+  ///
+  UINT64                            CrbControlResponseAddrss;  // 68h
+  UINT8                             Reserved4[0x10];           // 70h
+  ///
+  /// Command/Response Data may be defined as large as 3968 (0xF80).
+  ///
+  UINT8                             CrbDataBuffer[0xF80];      // 80h
+} PTP_CRB_REGISTERS;
+
+//
+// Define pointer types used to access CRB registers on PTP
+//
+typedef PTP_CRB_REGISTERS  *PTP_CRB_REGISTERS_PTR;
+
+//
+// Define bits of CRB Interface Identifier Register
+//
+typedef union {
+  struct {
+    UINT32   InterfaceType:4;
+    UINT32   InterfaceVersion:4;
+    UINT32   CapLocality:1;
+    UINT32   Reserved1:2;
+    UINT32   CapDataXferSizeSupport:2;
+    UINT32   CapFIFO:1;
+    UINT32   CapCRB:1;
+    UINT32   CapIFRes:2;
+    UINT32   InterfaceSelector:2;
+    UINT32   IntfSelLock:1;
+    UINT32   Reserved2:4;
+    UINT32   Rid:8;
+  } Bits;
+  UINT32   Uint32;
+} PTP_CRB_INTERFACE_IDENTIFIER;
+
+///
+/// InterfaceType
+///
+#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO  0x0
+#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB   0x1
+#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS   0xF
+
+///
+/// InterfaceVersion
+///
+#define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO  0x0
+#define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB   0x1
+
+///
+/// InterfaceSelector
+///
+#define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_FIFO  0x0
+#define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_CRB   0x1
+
+//
+// Define bits of Locality State Register
+//
+
+///
+/// This bit indicates whether all other bits of this register contain valid values, if it is a 1.
+///
+#define PTP_CRB_LOCALITY_STATE_TPM_REG_VALID_STATUS       BIT7
+
+///
+/// 000 - Locality 0
+/// 001 - Locality 1
+/// 010 - Locality 2
+/// 011 - Locality 3
+/// 100 - Locality 4
+///
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK       (BIT2 | BIT3 | BIT4)
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_0          (0)
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1          (BIT2)
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_2          (BIT3)
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3          (BIT2 | BIT3)
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_4          (BIT4)
+
+///
+/// A 0 indicates to the host that no locality is assigned.
+/// A 1 indicates a locality has been assigned.
+///
+#define PTP_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED          BIT1
+
+///
+/// The TPM clears this bit to 0 upon receipt of _TPM_Hash_End
+/// The TPM sets this bit to a 1 when the TPM_LOC_CTRL_x.resetEstablishment field is set to 1.
+///
+#define PTP_CRB_LOCALITY_STATE_TPM_ESTABLISHED            BIT0
+
+//
+// Define bits of Locality Control Register
+//
+
+///
+/// Writes (1): Reset TPM_LOC_STATE_x.tpmEstablished bit if the write occurs from Locality 3 or 4.
+///
+#define PTP_CRB_LOCALITY_CONTROL_RESET_ESTABLISHMENT_BIT  BIT3
+
+///
+/// Writes (1): The TPM gives control of the TPM to the locality setting this bit if it is the higher priority locality.
+///
+#define PTP_CRB_LOCALITY_CONTROL_SEIZE                    BIT2
+
+///
+/// Writes (1): The active Locality is done with the TPM.
+///
+#define PTP_CRB_LOCALITY_CONTROL_RELINQUISH               BIT1
+
+///
+/// Writes (1): Interrupt the TPM and generate a locality arbitration algorithm.
+///
+#define PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS           BIT0
+
+//
+// Define bits of Locality Status Register
+//
+
+///
+/// 0: A higher locality has not initiated a Seize arbitration process.
+/// 1: A higher locality has Seized the TPM from this locality.
+///
+#define PTP_CRB_LOCALITY_STATUS_BEEN_SEIZED               BIT1
+
+///
+/// 0: Locality has not been granted to the TPM.
+/// 1: Locality has been granted access to the TPM
+///
+#define PTP_CRB_LOCALITY_STATUS_GRANTED                   BIT0
+
+//
+// Define bits of CRB Control Area Request Register
+//
+
+///
+/// Used by Software to indicate transition the TPM to and from the Idle state
+/// 1: Set by Software to indicate response has been read from the response buffer and TPM can transition to Idle
+/// 0: Cleared to 0 by TPM to acknowledge the request when TPM enters Idle state.
+/// TPM SHALL complete this transition within TIMEOUT_C.
+///
+#define PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE              BIT1
+
+///
+/// Used by Software to request the TPM transition to the Ready State.
+/// 1: Set to 1 by Software to indicate the TPM should be ready to receive a command.
+/// 0: Cleared to 0 by TPM to acknowledge the request.
+/// TPM SHALL complete this transition within TIMEOUT_C.
+///
+#define PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY        BIT0
+
+//
+// Define bits of CRB Control Area Status Register
+//
+
+///
+/// Used by TPM to indicate it is in the Idle State
+/// 1: Set by TPM when in the Idle State
+/// 0: Cleared by TPM on receipt of TPM_CRB_CTRL_REQ_x.cmdReady when TPM transitions to the Ready State.
+/// SHALL be cleared by TIMEOUT_C.
+///
+#define PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE              BIT1
+
+///
+/// Used by the TPM to indicate current status.
+/// 1: Set by TPM to indicate a FATAL Error
+/// 0: Indicates TPM is operational
+///
+#define PTP_CRB_CONTROL_AREA_STATUS_TPM_STATUS            BIT0
+
+//
+// Define bits of CRB Control Cancel Register
+//
+
+///
+/// Used by software to cancel command processing Reads return correct value
+/// Writes (0000 0001h): Cancel a command
+/// Writes (0000 0000h): Clears field when command has been cancelled
+///
+#define PTP_CRB_CONTROL_CANCEL                            BIT0
+
+//
+// Define bits of CRB Control Start Register
+//
+
+///
+/// When set by software, indicates a command is ready for processing.
+/// Writes (0000 0001h): TPM transitions to Command Execution
+/// Writes (0000 0000h): TPM clears this field and transitions to Command Completion
+///
+#define PTP_CRB_CONTROL_START                             BIT0
+
+//
+// Restore original structure alignment
+//
+#pragma pack ()
+
+//
+// Default TimeOut value
+//
+#define PTP_TIMEOUT_A               (750 * 1000)   // 750ms
+#define PTP_TIMEOUT_B               (2000 * 1000)  // 2s
+#define PTP_TIMEOUT_C               (200 * 1000)   // 200ms
+#define PTP_TIMEOUT_D               (30 * 1000)    // 30ms
+
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/TpmTis.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/TpmTis.h
new file mode 100644
index 0000000000..1e1d23725d
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/TpmTis.h
@@ -0,0 +1,183 @@
+/** @file
+  TPM Interface Specification definition.
+  It covers both TPM1.2 and TPM2.0.
+
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _TPM_TIS_H_
+#define _TPM_TIS_H_
+
+//
+// Set structure alignment to 1-byte
+//
+#pragma pack (1)
+
+//
+// Register set map as specified in TIS specification Chapter 10
+//
+typedef struct {
+  ///
+  /// Used to gain ownership for this particular port.
+  ///
+  UINT8                             Access;             // 0
+  UINT8                             Reserved1[7];       // 1
+  ///
+  /// Controls interrupts.
+  ///
+  UINT32                            IntEnable;          // 8
+  ///
+  /// SIRQ vector to be used by the TPM.
+  ///
+  UINT8                             IntVector;          // 0ch
+  UINT8                             Reserved2[3];       // 0dh
+  ///
+  /// What caused interrupt.
+  ///
+  UINT32                            IntSts;             // 10h
+  ///
+  /// Shows which interrupts are supported by that particular TPM.
+  ///
+  UINT32                            IntfCapability;     // 14h
+  ///
+  /// Status Register. Provides status of the TPM.
+  ///
+  UINT8                             Status;             // 18h
+  ///
+  /// Number of consecutive writes that can be done to the TPM.
+  ///
+  UINT16                            BurstCount;         // 19h
+  UINT8                             Reserved3[9];
+  ///
+  /// Read or write FIFO, depending on transaction.
+  ///
+  UINT32                            DataFifo;           // 24h
+  UINT8                             Reserved4[0xed8];   // 28h
+  ///
+  /// Vendor ID
+  ///
+  UINT16                            Vid;                // 0f00h
+  ///
+  /// Device ID
+  ///
+  UINT16                            Did;                // 0f02h
+  ///
+  /// Revision ID
+  ///
+  UINT8                             Rid;                // 0f04h
+  UINT8                             Reserved[0x7b];     // 0f05h
+  ///
+  /// Alias to I/O legacy space.
+  ///
+  UINT32                            LegacyAddress1;     // 0f80h
+  ///
+  /// Additional 8 bits for I/O legacy space extension.
+  ///
+  UINT32                            LegacyAddress1Ex;   // 0f84h
+  ///
+  /// Alias to second I/O legacy space.
+  ///
+  UINT32                            LegacyAddress2;     // 0f88h
+  ///
+  /// Additional 8 bits for second I/O legacy space extension.
+  ///
+  UINT32                            LegacyAddress2Ex;   // 0f8ch
+  ///
+  /// Vendor-defined configuration registers.
+  ///
+  UINT8                             VendorDefined[0x70];// 0f90h
+} TIS_PC_REGISTERS;
+
+//
+// Restore original structure alignment
+//
+#pragma pack ()
+
+//
+// Define pointer types used to access TIS registers on PC
+//
+typedef TIS_PC_REGISTERS  *TIS_PC_REGISTERS_PTR;
+
+//
+// Define bits of ACCESS and STATUS registers
+//
+
+///
+/// This bit is a 1 to indicate that the other bits in this register are valid.
+///
+#define TIS_PC_VALID                BIT7
+///
+/// Indicate that this locality is active.
+///
+#define TIS_PC_ACC_ACTIVE           BIT5
+///
+/// Set to 1 to indicate that this locality had the TPM taken away while
+/// this locality had the TIS_PC_ACC_ACTIVE bit set.
+///
+#define TIS_PC_ACC_SEIZED           BIT4
+///
+/// Set to 1 to indicate that TPM MUST reset the
+/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
+/// locality that is writing this bit.
+///
+#define TIS_PC_ACC_SEIZE            BIT3
+///
+/// When this bit is 1, another locality is requesting usage of the TPM.
+///
+#define TIS_PC_ACC_PENDIND          BIT2
+///
+/// Set to 1 to indicate that this locality is requesting to use TPM.
+///
+#define TIS_PC_ACC_RQUUSE           BIT1
+///
+/// A value of 1 indicates that a T/OS has not been established on the platform
+///
+#define TIS_PC_ACC_ESTABLISH        BIT0
+
+///
+/// This field indicates that STS_DATA and STS_EXPECT are valid
+///
+#define TIS_PC_STS_VALID            BIT7
+///
+/// When this bit is 1, TPM is in the Ready state,
+/// indicating it is ready to receive a new command.
+///
+#define TIS_PC_STS_READY            BIT6
+///
+/// Write a 1 to this bit to cause the TPM to execute that command.
+///
+#define TIS_PC_STS_GO               BIT5
+///
+/// This bit indicates that the TPM has data available as a response.
+///
+#define TIS_PC_STS_DATA             BIT4
+///
+/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
+///
+#define TIS_PC_STS_EXPECT           BIT3
+///
+/// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.
+///
+#define TIS_PC_STS_SELFTEST_DONE    BIT2
+///
+/// Writes a 1 to this bit to force the TPM to re-send the response.
+///
+#define TIS_PC_STS_RETRY            BIT1
+
+//
+// Default TimeOut value
+//
+#define TIS_TIMEOUT_A               (750  * 1000)  // 750ms
+#define TIS_TIMEOUT_B               (2000 * 1000)  // 2s
+#define TIS_TIMEOUT_C               (750  * 1000)  // 750ms
+#define TIS_TIMEOUT_D               (750  * 1000)  // 750ms
+
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Udf.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Udf.h
new file mode 100644
index 0000000000..c277a0f1d9
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Udf.h
@@ -0,0 +1,147 @@
+/** @file
+  OSTA Universal Disk Format (UDF) definitions.
+
+  Copyright (C) 2014-2017 Paulo Alcantara <pcacjr@zytor.com>
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#ifndef __UDF_H__
+#define __UDF_H__
+
+#define UDF_BEA_IDENTIFIER   "BEA01"
+#define UDF_NSR2_IDENTIFIER  "NSR02"
+#define UDF_NSR3_IDENTIFIER  "NSR03"
+#define UDF_TEA_IDENTIFIER   "TEA01"
+
+#define UDF_LOGICAL_SECTOR_SHIFT  11
+#define UDF_LOGICAL_SECTOR_SIZE   ((UINT64)(1ULL << UDF_LOGICAL_SECTOR_SHIFT))
+#define UDF_VRS_START_OFFSET      ((UINT64)(16ULL << UDF_LOGICAL_SECTOR_SHIFT))
+
+typedef enum {
+  UdfPrimaryVolumeDescriptor = 1,
+  UdfAnchorVolumeDescriptorPointer = 2,
+  UdfVolumeDescriptorPointer = 3,
+  UdfImplemenationUseVolumeDescriptor = 4,
+  UdfPartitionDescriptor = 5,
+  UdfLogicalVolumeDescriptor = 6,
+  UdfUnallocatedSpaceDescriptor = 7,
+  UdfTerminatingDescriptor = 8,
+  UdfLogicalVolumeIntegrityDescriptor = 9,
+  UdfFileSetDescriptor = 256,
+  UdfFileIdentifierDescriptor = 257,
+  UdfAllocationExtentDescriptor = 258,
+  UdfFileEntry = 261,
+  UdfExtendedFileEntry = 266,
+} UDF_VOLUME_DESCRIPTOR_ID;
+
+#pragma pack(1)
+
+typedef struct {
+  UINT16  TagIdentifier;
+  UINT16  DescriptorVersion;
+  UINT8   TagChecksum;
+  UINT8   Reserved;
+  UINT16  TagSerialNumber;
+  UINT16  DescriptorCRC;
+  UINT16  DescriptorCRCLength;
+  UINT32  TagLocation;
+} UDF_DESCRIPTOR_TAG;
+
+typedef struct {
+  UINT32  ExtentLength;
+  UINT32  ExtentLocation;
+} UDF_EXTENT_AD;
+
+typedef struct {
+  UINT8           CharacterSetType;
+  UINT8           CharacterSetInfo[63];
+} UDF_CHAR_SPEC;
+
+typedef struct {
+  UINT8           Flags;
+  UINT8           Identifier[23];
+  union {
+    //
+    // Domain Entity Identifier
+    //
+    struct {
+      UINT16      UdfRevision;
+      UINT8       DomainFlags;
+      UINT8       Reserved[5];
+    } Domain;
+    //
+    // UDF Entity Identifier
+    //
+    struct {
+      UINT16      UdfRevision;
+      UINT8       OSClass;
+      UINT8       OSIdentifier;
+      UINT8       Reserved[4];
+    } Entity;
+    //
+    // Implementation Entity Identifier
+    //
+    struct {
+      UINT8       OSClass;
+      UINT8       OSIdentifier;
+      UINT8       ImplementationUseArea[6];
+    } ImplementationEntity;
+    //
+    // Application Entity Identifier
+    //
+    struct {
+      UINT8       ApplicationUseArea[8];
+    } ApplicationEntity;
+    //
+    // Raw Identifier Suffix
+    //
+    struct {
+      UINT8       Data[8];
+    } Raw;
+  } Suffix;
+} UDF_ENTITY_ID;
+
+typedef struct {
+  UINT32        LogicalBlockNumber;
+  UINT16        PartitionReferenceNumber;
+} UDF_LB_ADDR;
+
+typedef struct {
+  UINT32                           ExtentLength;
+  UDF_LB_ADDR                      ExtentLocation;
+  UINT8                            ImplementationUse[6];
+} UDF_LONG_ALLOCATION_DESCRIPTOR;
+
+typedef struct {
+  UDF_DESCRIPTOR_TAG  DescriptorTag;
+  UDF_EXTENT_AD       MainVolumeDescriptorSequenceExtent;
+  UDF_EXTENT_AD       ReserveVolumeDescriptorSequenceExtent;
+  UINT8               Reserved[480];
+} UDF_ANCHOR_VOLUME_DESCRIPTOR_POINTER;
+
+typedef struct {
+  UDF_DESCRIPTOR_TAG              DescriptorTag;
+  UINT32                          VolumeDescriptorSequenceNumber;
+  UDF_CHAR_SPEC                   DescriptorCharacterSet;
+  UINT8                           LogicalVolumeIdentifier[128];
+  UINT32                          LogicalBlockSize;
+  UDF_ENTITY_ID                   DomainIdentifier;
+  UDF_LONG_ALLOCATION_DESCRIPTOR  LogicalVolumeContentsUse;
+  UINT32                          MapTableLength;
+  UINT32                          NumberOfPartitionMaps;
+  UDF_ENTITY_ID                   ImplementationIdentifier;
+  UINT8                           ImplementationUse[128];
+  UDF_EXTENT_AD                   IntegritySequenceExtent;
+  UINT8                           PartitionMaps[6];
+} UDF_LOGICAL_VOLUME_DESCRIPTOR;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h
new file mode 100644
index 0000000000..0a7469ad41
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h
@@ -0,0 +1,333 @@
+/** @file
+  TCG EFI Platform Definition in TCG_EFI_Platform_1_20_Final
+
+  Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __UEFI_TCG_PLATFORM_H__
+#define __UEFI_TCG_PLATFORM_H__
+
+#include <IndustryStandard/Tpm12.h>
+#include <IndustryStandard/Tpm20.h>
+#include <Uefi.h>
+
+//
+// Standard event types
+//
+#define EV_POST_CODE                ((TCG_EVENTTYPE) 0x00000001)
+#define EV_NO_ACTION                ((TCG_EVENTTYPE) 0x00000003)
+#define EV_SEPARATOR                ((TCG_EVENTTYPE) 0x00000004)
+#define EV_S_CRTM_CONTENTS          ((TCG_EVENTTYPE) 0x00000007)
+#define EV_S_CRTM_VERSION           ((TCG_EVENTTYPE) 0x00000008)
+#define EV_CPU_MICROCODE            ((TCG_EVENTTYPE) 0x00000009)
+#define EV_TABLE_OF_DEVICES         ((TCG_EVENTTYPE) 0x0000000B)
+
+//
+// EFI specific event types
+//
+#define EV_EFI_EVENT_BASE                   ((TCG_EVENTTYPE) 0x80000000)
+#define EV_EFI_VARIABLE_DRIVER_CONFIG       (EV_EFI_EVENT_BASE + 1)
+#define EV_EFI_VARIABLE_BOOT                (EV_EFI_EVENT_BASE + 2)
+#define EV_EFI_BOOT_SERVICES_APPLICATION    (EV_EFI_EVENT_BASE + 3)
+#define EV_EFI_BOOT_SERVICES_DRIVER         (EV_EFI_EVENT_BASE + 4)
+#define EV_EFI_RUNTIME_SERVICES_DRIVER      (EV_EFI_EVENT_BASE + 5)
+#define EV_EFI_GPT_EVENT                    (EV_EFI_EVENT_BASE + 6)
+#define EV_EFI_ACTION                       (EV_EFI_EVENT_BASE + 7)
+#define EV_EFI_PLATFORM_FIRMWARE_BLOB       (EV_EFI_EVENT_BASE + 8)
+#define EV_EFI_HANDOFF_TABLES               (EV_EFI_EVENT_BASE + 9)
+#define EV_EFI_VARIABLE_AUTHORITY           (EV_EFI_EVENT_BASE + 0xE0)
+
+#define EFI_CALLING_EFI_APPLICATION         \
+  "Calling EFI Application from Boot Option"
+#define EFI_RETURNING_FROM_EFI_APPLICATOIN  \
+  "Returning from EFI Application from Boot Option"
+#define EFI_EXIT_BOOT_SERVICES_INVOCATION   \
+  "Exit Boot Services Invocation"
+#define EFI_EXIT_BOOT_SERVICES_FAILED       \
+  "Exit Boot Services Returned with Failure"
+#define EFI_EXIT_BOOT_SERVICES_SUCCEEDED    \
+  "Exit Boot Services Returned with Success"
+
+
+#define EV_POSTCODE_INFO_POST_CODE    "POST CODE"
+#define POST_CODE_STR_LEN             (sizeof(EV_POSTCODE_INFO_POST_CODE) - 1)
+
+#define EV_POSTCODE_INFO_SMM_CODE     "SMM CODE"
+#define SMM_CODE_STR_LEN              (sizeof(EV_POSTCODE_INFO_SMM_CODE) - 1)
+
+#define EV_POSTCODE_INFO_ACPI_DATA    "ACPI DATA"
+#define ACPI_DATA_LEN                 (sizeof(EV_POSTCODE_INFO_ACPI_DATA) - 1)
+
+#define EV_POSTCODE_INFO_BIS_CODE     "BIS CODE"
+#define BIS_CODE_LEN                  (sizeof(EV_POSTCODE_INFO_BIS_CODE) - 1)
+
+#define EV_POSTCODE_INFO_UEFI_PI      "UEFI PI"
+#define UEFI_PI_LEN                   (sizeof(EV_POSTCODE_INFO_UEFI_PI) - 1)
+
+#define EV_POSTCODE_INFO_OPROM        "Embedded Option ROM"
+#define OPROM_LEN                     (sizeof(EV_POSTCODE_INFO_OPROM) - 1)
+
+#define FIRMWARE_DEBUGGER_EVENT_STRING      "UEFI Debug Mode"
+#define FIRMWARE_DEBUGGER_EVENT_STRING_LEN  (sizeof(FIRMWARE_DEBUGGER_EVENT_STRING) - 1)
+
+//
+// Set structure alignment to 1-byte
+//
+#pragma pack (1)
+
+typedef UINT32                     TCG_EVENTTYPE;
+typedef TPM_PCRINDEX               TCG_PCRINDEX;
+typedef TPM_DIGEST                 TCG_DIGEST;
+///
+/// Event Log Entry Structure Definition
+///
+typedef struct tdTCG_PCR_EVENT {
+  TCG_PCRINDEX                      PCRIndex;  ///< PCRIndex event extended to
+  TCG_EVENTTYPE                     EventType; ///< TCG EFI event type
+  TCG_DIGEST                        Digest;    ///< Value extended into PCRIndex
+  UINT32                            EventSize; ///< Size of the event data
+  UINT8                             Event[1];  ///< The event data
+} TCG_PCR_EVENT;
+
+#define TSS_EVENT_DATA_MAX_SIZE   256
+
+///
+/// TCG_PCR_EVENT_HDR
+///
+typedef struct tdTCG_PCR_EVENT_HDR {
+  TCG_PCRINDEX                      PCRIndex;
+  TCG_EVENTTYPE                     EventType;
+  TCG_DIGEST                        Digest;
+  UINT32                            EventSize;
+} TCG_PCR_EVENT_HDR;
+
+///
+/// EFI_PLATFORM_FIRMWARE_BLOB
+///
+/// BlobLength should be of type UINTN but we use UINT64 here
+/// because PEI is 32-bit while DXE is 64-bit on x64 platforms
+///
+typedef struct tdEFI_PLATFORM_FIRMWARE_BLOB {
+  EFI_PHYSICAL_ADDRESS              BlobBase;
+  UINT64                            BlobLength;
+} EFI_PLATFORM_FIRMWARE_BLOB;
+
+///
+/// EFI_IMAGE_LOAD_EVENT
+///
+/// This structure is used in EV_EFI_BOOT_SERVICES_APPLICATION,
+/// EV_EFI_BOOT_SERVICES_DRIVER and EV_EFI_RUNTIME_SERVICES_DRIVER
+///
+typedef struct tdEFI_IMAGE_LOAD_EVENT {
+  EFI_PHYSICAL_ADDRESS              ImageLocationInMemory;
+  UINTN                             ImageLengthInMemory;
+  UINTN                             ImageLinkTimeAddress;
+  UINTN                             LengthOfDevicePath;
+  EFI_DEVICE_PATH_PROTOCOL          DevicePath[1];
+} EFI_IMAGE_LOAD_EVENT;
+
+///
+/// EFI_HANDOFF_TABLE_POINTERS
+///
+/// This structure is used in EV_EFI_HANDOFF_TABLES event to facilitate
+/// the measurement of given configuration tables.
+///
+typedef struct tdEFI_HANDOFF_TABLE_POINTERS {
+  UINTN                             NumberOfTables;
+  EFI_CONFIGURATION_TABLE           TableEntry[1];
+} EFI_HANDOFF_TABLE_POINTERS;
+
+///
+/// EFI_VARIABLE_DATA
+///
+/// This structure serves as the header for measuring variables. The name of the
+/// variable (in Unicode format) should immediately follow, then the variable
+/// data.
+/// This is defined in TCG EFI Platform Spec for TPM1.1 or 1.2 V1.22
+///
+typedef struct tdEFI_VARIABLE_DATA {
+  EFI_GUID                          VariableName;
+  UINTN                             UnicodeNameLength;
+  UINTN                             VariableDataLength;
+  CHAR16                            UnicodeName[1];
+  INT8                              VariableData[1];  ///< Driver or platform-specific data
+} EFI_VARIABLE_DATA;
+
+///
+/// UEFI_VARIABLE_DATA
+///
+/// This structure serves as the header for measuring variables. The name of the
+/// variable (in Unicode format) should immediately follow, then the variable
+/// data.
+/// This is defined in TCG PC Client Firmware Profile Spec 00.21
+///
+typedef struct tdUEFI_VARIABLE_DATA {
+  EFI_GUID                          VariableName;
+  UINT64                            UnicodeNameLength;
+  UINT64                            VariableDataLength;
+  CHAR16                            UnicodeName[1];
+  INT8                              VariableData[1];  ///< Driver or platform-specific data
+} UEFI_VARIABLE_DATA;
+
+//
+// For TrEE1.0 compatibility
+//
+typedef struct {
+  EFI_GUID                          VariableName;
+  UINT64                            UnicodeNameLength;   // The TCG Definition used UINTN
+  UINT64                            VariableDataLength;  // The TCG Definition used UINTN
+  CHAR16                            UnicodeName[1];
+  INT8                              VariableData[1];
+} EFI_VARIABLE_DATA_TREE;
+
+typedef struct tdEFI_GPT_DATA {
+  EFI_PARTITION_TABLE_HEADER  EfiPartitionHeader;
+  UINTN                       NumberOfPartitions; 
+  EFI_PARTITION_ENTRY         Partitions[1];
+} EFI_GPT_DATA;
+
+//
+// Crypto Agile Log Entry Format
+//
+typedef struct tdTCG_PCR_EVENT2 {
+  TCG_PCRINDEX        PCRIndex;
+  TCG_EVENTTYPE       EventType;
+  TPML_DIGEST_VALUES  Digest;
+  UINT32              EventSize;
+  UINT8               Event[1];
+} TCG_PCR_EVENT2;
+
+//
+// TCG PCR Event2 Header
+// Follow TCG EFI Protocol Spec 5.2 Crypto Agile Log Entry Format
+//
+typedef struct tdTCG_PCR_EVENT2_HDR{
+  TCG_PCRINDEX        PCRIndex;
+  TCG_EVENTTYPE       EventType;
+  TPML_DIGEST_VALUES  Digests;
+  UINT32              EventSize;
+} TCG_PCR_EVENT2_HDR;
+
+//
+// Log Header Entry Data
+//
+typedef struct {
+  //
+  // TCG defined hashing algorithm ID.
+  //
+  UINT16              algorithmId;
+  //
+  // The size of the digest for the respective hashing algorithm.
+  //
+  UINT16              digestSize;
+} TCG_EfiSpecIdEventAlgorithmSize;
+
+#define TCG_EfiSpecIDEventStruct_SIGNATURE_02 "Spec ID Event02"
+#define TCG_EfiSpecIDEventStruct_SIGNATURE_03 "Spec ID Event03"
+
+#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MAJOR_TPM12   1
+#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MINOR_TPM12   2
+#define TCG_EfiSpecIDEventStruct_SPEC_ERRATA_TPM12          2
+
+#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MAJOR_TPM2   2
+#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MINOR_TPM2   0
+#define TCG_EfiSpecIDEventStruct_SPEC_ERRATA_TPM2          0
+
+typedef struct {
+  UINT8               signature[16];
+  //
+  // The value for the Platform Class.
+  // The enumeration is defined in the TCG ACPI Specification Client Common Header.
+  //
+  UINT32              platformClass;
+  //
+  // The TCG EFI Platform Specification minor version number this BIOS supports.
+  // Any BIOS supporting version (1.22) MUST set this value to 02h.
+  // Any BIOS supporting version (2.0) SHALL set this value to 0x00.
+  //
+  UINT8               specVersionMinor;
+  //
+  // The TCG EFI Platform Specification major version number this BIOS supports.
+  // Any BIOS supporting version (1.22) MUST set this value to 01h.
+  // Any BIOS supporting version (2.0) SHALL set this value to 0x02.
+  //
+  UINT8               specVersionMajor;
+  //
+  // The TCG EFI Platform Specification errata for this specification this BIOS supports.
+  // Any BIOS supporting version and errata (1.22) MUST set this value to 02h.
+  // Any BIOS supporting version and errata (2.0) SHALL set this value to 0x00.
+  //
+  UINT8               specErrata;
+  //
+  // Specifies the size of the UINTN fields used in various data structures used in this specification.
+  // 0x01 indicates UINT32 and 0x02 indicates UINT64.
+  //
+  UINT8               uintnSize;
+  //
+  // This field is added in "Spec ID Event03".
+  // The number of hashing algorithms used in this event log (except the first event).
+  // All events in this event log use all hashing algorithms defined here.
+  //
+//UINT32              numberOfAlgorithms;
+  //
+  // This field is added in "Spec ID Event03".
+  // An array of size numberOfAlgorithms of value pairs.
+  //
+//TCG_EfiSpecIdEventAlgorithmSize digestSize[numberOfAlgorithms];
+  //
+  // Size in bytes of the VendorInfo field.
+  // Maximum value SHALL be FFh bytes.
+  //
+//UINT8               vendorInfoSize;
+  //
+  // Provided for use by the BIOS implementer.
+  // The value might be used, for example, to provide more detailed information about the specific BIOS such as BIOS revision numbers, etc.
+  // The values within this field are not standardized and are implementer-specific.
+  // Platform-specific or -unique information SHALL NOT be provided in this field.
+  //
+//UINT8               vendorInfo[vendorInfoSize];
+} TCG_EfiSpecIDEventStruct;
+
+
+
+#define TCG_EfiStartupLocalityEvent_SIGNATURE      "StartupLocality"
+
+
+//
+// PC Client PTP spec Table 8 Relationship between Locality and Locality Attribute
+//
+#define LOCALITY_0_INDICATOR        0x01
+#define LOCALITY_1_INDICATOR        0x02
+#define LOCALITY_2_INDICATOR        0x03
+#define LOCALITY_3_INDICATOR        0x04
+#define LOCALITY_4_INDICATOR        0x05
+
+
+//
+// Startup Locality Event
+//
+typedef struct tdTCG_EfiStartupLocalityEvent{
+  UINT8       Signature[16];
+  //
+  // The Locality Indicator which sent the TPM2_Startup command
+  //
+  UINT8       StartupLocality;
+} TCG_EfiStartupLocalityEvent;
+
+
+//
+// Restore original structure alignment
+//
+#pragma pack ()
+
+#endif
+
+
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Usb.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Usb.h
new file mode 100644
index 0000000000..38c4d853e5
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Usb.h
@@ -0,0 +1,386 @@
+/** @file
+  Support for USB 2.0 standard.
+
+  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __USB_H__
+#define __USB_H__
+
+//
+// Subset of Class and Subclass definitions from USB Specs
+//
+
+//
+// Usb mass storage class code
+//
+#define USB_MASS_STORE_CLASS    0x08
+
+//
+// Usb mass storage subclass code, specify the command set used.
+//
+#define USB_MASS_STORE_RBC      0x01 ///< Reduced Block Commands
+#define USB_MASS_STORE_8020I    0x02 ///< SFF-8020i, typically a CD/DVD device
+#define USB_MASS_STORE_QIC      0x03 ///< Typically a tape device
+#define USB_MASS_STORE_UFI      0x04 ///< Typically a floppy disk driver device
+#define USB_MASS_STORE_8070I    0x05 ///< SFF-8070i, typically a floppy disk driver device.
+#define USB_MASS_STORE_SCSI     0x06 ///< SCSI transparent command set
+
+//
+// Usb mass storage protocol code, specify the transport protocol
+//
+#define USB_MASS_STORE_CBI0     0x00 ///< CBI protocol with command completion interrupt
+#define USB_MASS_STORE_CBI1     0x01 ///< CBI protocol without command completion interrupt
+#define USB_MASS_STORE_BOT      0x50 ///< Bulk-Only Transport
+
+//
+// Standard device request and request type
+// USB 2.0 spec, Section 9.4
+//
+#define USB_DEV_GET_STATUS                  0x00
+#define USB_DEV_GET_STATUS_REQ_TYPE_D       0x80 // Receiver : Device
+#define USB_DEV_GET_STATUS_REQ_TYPE_I       0x81 // Receiver : Interface
+#define USB_DEV_GET_STATUS_REQ_TYPE_E       0x82 // Receiver : Endpoint
+
+#define USB_DEV_CLEAR_FEATURE               0x01
+#define USB_DEV_CLEAR_FEATURE_REQ_TYPE_D    0x00 // Receiver : Device
+#define USB_DEV_CLEAR_FEATURE_REQ_TYPE_I    0x01 // Receiver : Interface
+#define USB_DEV_CLEAR_FEATURE_REQ_TYPE_E    0x02 // Receiver : Endpoint
+
+#define USB_DEV_SET_FEATURE                 0x03
+#define USB_DEV_SET_FEATURE_REQ_TYPE_D      0x00 // Receiver : Device
+#define USB_DEV_SET_FEATURE_REQ_TYPE_I      0x01 // Receiver : Interface
+#define USB_DEV_SET_FEATURE_REQ_TYPE_E      0x02 // Receiver : Endpoint
+
+#define USB_DEV_SET_ADDRESS                 0x05
+#define USB_DEV_SET_ADDRESS_REQ_TYPE        0x00
+
+#define USB_DEV_GET_DESCRIPTOR              0x06
+#define USB_DEV_GET_DESCRIPTOR_REQ_TYPE     0x80
+
+#define USB_DEV_SET_DESCRIPTOR              0x07
+#define USB_DEV_SET_DESCRIPTOR_REQ_TYPE     0x00
+
+#define USB_DEV_GET_CONFIGURATION           0x08
+#define USB_DEV_GET_CONFIGURATION_REQ_TYPE  0x80
+
+#define USB_DEV_SET_CONFIGURATION           0x09
+#define USB_DEV_SET_CONFIGURATION_REQ_TYPE  0x00
+
+#define USB_DEV_GET_INTERFACE               0x0A
+#define USB_DEV_GET_INTERFACE_REQ_TYPE      0x81
+
+#define USB_DEV_SET_INTERFACE               0x0B
+#define USB_DEV_SET_INTERFACE_REQ_TYPE      0x01
+
+#define USB_DEV_SYNCH_FRAME                 0x0C
+#define USB_DEV_SYNCH_FRAME_REQ_TYPE        0x82
+
+
+//
+// USB standard descriptors and reqeust
+//
+#pragma pack(1)
+
+///
+/// Format of Setup Data for USB Device Requests
+/// USB 2.0 spec, Section 9.3
+///
+typedef struct {
+  UINT8           RequestType;
+  UINT8           Request;
+  UINT16          Value;
+  UINT16          Index;
+  UINT16          Length;
+} USB_DEVICE_REQUEST;
+
+///
+/// Standard Device Descriptor
+/// USB 2.0 spec, Section 9.6.1
+///
+typedef struct {
+  UINT8           Length;
+  UINT8           DescriptorType;
+  UINT16          BcdUSB;
+  UINT8           DeviceClass;
+  UINT8           DeviceSubClass;
+  UINT8           DeviceProtocol;
+  UINT8           MaxPacketSize0;
+  UINT16          IdVendor;
+  UINT16          IdProduct;
+  UINT16          BcdDevice;
+  UINT8           StrManufacturer;
+  UINT8           StrProduct;
+  UINT8           StrSerialNumber;
+  UINT8           NumConfigurations;
+} USB_DEVICE_DESCRIPTOR;
+
+///
+/// Standard Configuration Descriptor
+/// USB 2.0 spec, Section 9.6.3
+///
+typedef struct {
+  UINT8           Length;
+  UINT8           DescriptorType;
+  UINT16          TotalLength;
+  UINT8           NumInterfaces;
+  UINT8           ConfigurationValue;
+  UINT8           Configuration;
+  UINT8           Attributes;
+  UINT8           MaxPower;
+} USB_CONFIG_DESCRIPTOR;
+
+///
+/// Standard Interface Descriptor
+/// USB 2.0 spec, Section 9.6.5
+///
+typedef struct {
+  UINT8           Length;
+  UINT8           DescriptorType;
+  UINT8           InterfaceNumber;
+  UINT8           AlternateSetting;
+  UINT8           NumEndpoints;
+  UINT8           InterfaceClass;
+  UINT8           InterfaceSubClass;
+  UINT8           InterfaceProtocol;
+  UINT8           Interface;
+} USB_INTERFACE_DESCRIPTOR;
+
+///
+/// Standard Endpoint Descriptor
+/// USB 2.0 spec, Section 9.6.6
+///
+typedef struct {
+  UINT8           Length;
+  UINT8           DescriptorType;
+  UINT8           EndpointAddress;
+  UINT8           Attributes;
+  UINT16          MaxPacketSize;
+  UINT8           Interval;
+} USB_ENDPOINT_DESCRIPTOR;
+
+///
+/// UNICODE String Descriptor
+/// USB 2.0 spec, Section 9.6.7
+///
+typedef struct {
+  UINT8           Length;
+  UINT8           DescriptorType;
+  CHAR16          String[1];
+} EFI_USB_STRING_DESCRIPTOR;
+
+#pragma pack()
+
+
+typedef enum {
+  //
+  // USB request type
+  //
+  USB_REQ_TYPE_STANDARD   = (0x00 << 5),
+  USB_REQ_TYPE_CLASS      = (0x01 << 5),
+  USB_REQ_TYPE_VENDOR     = (0x02 << 5),
+
+  //
+  // Standard control transfer request type, or the value
+  // to fill in EFI_USB_DEVICE_REQUEST.Request
+  //
+  USB_REQ_GET_STATUS      = 0x00,
+  USB_REQ_CLEAR_FEATURE   = 0x01,
+  USB_REQ_SET_FEATURE     = 0x03,
+  USB_REQ_SET_ADDRESS     = 0x05,
+  USB_REQ_GET_DESCRIPTOR  = 0x06,
+  USB_REQ_SET_DESCRIPTOR  = 0x07,
+  USB_REQ_GET_CONFIG      = 0x08,
+  USB_REQ_SET_CONFIG      = 0x09,
+  USB_REQ_GET_INTERFACE   = 0x0A,
+  USB_REQ_SET_INTERFACE   = 0x0B,
+  USB_REQ_SYNCH_FRAME     = 0x0C,
+
+  //
+  // Usb control transfer target
+  //
+  USB_TARGET_DEVICE       = 0,
+  USB_TARGET_INTERFACE    = 0x01,
+  USB_TARGET_ENDPOINT     = 0x02,
+  USB_TARGET_OTHER        = 0x03,
+
+  //
+  // USB Descriptor types
+  //
+  USB_DESC_TYPE_DEVICE    = 0x01,
+  USB_DESC_TYPE_CONFIG    = 0x02,
+  USB_DESC_TYPE_STRING    = 0x03,
+  USB_DESC_TYPE_INTERFACE = 0x04,
+  USB_DESC_TYPE_ENDPOINT  = 0x05,
+  USB_DESC_TYPE_HID       = 0x21,
+  USB_DESC_TYPE_REPORT    = 0x22,
+
+  //
+  // Features to be cleared by CLEAR_FEATURE requests
+  //
+  USB_FEATURE_ENDPOINT_HALT = 0,
+
+  //
+  // USB endpoint types: 00: control, 01: isochronous, 10: bulk, 11: interrupt
+  //
+  USB_ENDPOINT_CONTROL    = 0x00,
+  USB_ENDPOINT_ISO        = 0x01,
+  USB_ENDPOINT_BULK       = 0x02,
+  USB_ENDPOINT_INTERRUPT  = 0x03,
+
+  USB_ENDPOINT_TYPE_MASK  = 0x03,
+  USB_ENDPOINT_DIR_IN     = 0x80,
+
+  //
+  //Use 200 ms to increase the error handling response time
+  //
+  EFI_USB_INTERRUPT_DELAY = 2000000
+} USB_TYPES_DEFINITION;
+
+
+//
+// HID constants definition, see Device Class Definition
+// for Human Interface Devices (HID) rev1.11
+//
+
+//
+// HID standard GET_DESCRIPTOR request.
+//
+#define USB_HID_GET_DESCRIPTOR_REQ_TYPE  0x81
+
+//
+// HID specific requests.
+//
+#define USB_HID_CLASS_GET_REQ_TYPE       0xa1
+#define USB_HID_CLASS_SET_REQ_TYPE       0x21
+
+//
+// HID report item format
+//
+#define HID_ITEM_FORMAT_SHORT 0
+#define HID_ITEM_FORMAT_LONG  1
+
+//
+// Special tag indicating long items
+//
+#define HID_ITEM_TAG_LONG 15
+
+//
+// HID report descriptor item type (prefix bit 2,3)
+//
+#define HID_ITEM_TYPE_MAIN      0
+#define HID_ITEM_TYPE_GLOBAL    1
+#define HID_ITEM_TYPE_LOCAL     2
+#define HID_ITEM_TYPE_RESERVED  3
+
+//
+// HID report descriptor main item tags
+//
+#define HID_MAIN_ITEM_TAG_INPUT             8
+#define HID_MAIN_ITEM_TAG_OUTPUT            9
+#define HID_MAIN_ITEM_TAG_FEATURE           11
+#define HID_MAIN_ITEM_TAG_BEGIN_COLLECTION  10
+#define HID_MAIN_ITEM_TAG_END_COLLECTION    12
+
+//
+// HID report descriptor main item contents
+//
+#define HID_MAIN_ITEM_CONSTANT      0x001
+#define HID_MAIN_ITEM_VARIABLE      0x002
+#define HID_MAIN_ITEM_RELATIVE      0x004
+#define HID_MAIN_ITEM_WRAP          0x008
+#define HID_MAIN_ITEM_NONLINEAR     0x010
+#define HID_MAIN_ITEM_NO_PREFERRED  0x020
+#define HID_MAIN_ITEM_NULL_STATE    0x040
+#define HID_MAIN_ITEM_VOLATILE      0x080
+#define HID_MAIN_ITEM_BUFFERED_BYTE 0x100
+
+//
+// HID report descriptor collection item types
+//
+#define HID_COLLECTION_PHYSICAL     0
+#define HID_COLLECTION_APPLICATION  1
+#define HID_COLLECTION_LOGICAL      2
+
+//
+// HID report descriptor global item tags
+//
+#define HID_GLOBAL_ITEM_TAG_USAGE_PAGE        0
+#define HID_GLOBAL_ITEM_TAG_LOGICAL_MINIMUM   1
+#define HID_GLOBAL_ITEM_TAG_LOGICAL_MAXIMUM   2
+#define HID_GLOBAL_ITEM_TAG_PHYSICAL_MINIMUM  3
+#define HID_GLOBAL_ITEM_TAG_PHYSICAL_MAXIMUM  4
+#define HID_GLOBAL_ITEM_TAG_UNIT_EXPONENT     5
+#define HID_GLOBAL_ITEM_TAG_UNIT              6
+#define HID_GLOBAL_ITEM_TAG_REPORT_SIZE       7
+#define HID_GLOBAL_ITEM_TAG_REPORT_ID         8
+#define HID_GLOBAL_ITEM_TAG_REPORT_COUNT      9
+#define HID_GLOBAL_ITEM_TAG_PUSH              10
+#define HID_GLOBAL_ITEM_TAG_POP               11
+
+//
+// HID report descriptor local item tags
+//
+#define HID_LOCAL_ITEM_TAG_USAGE              0
+#define HID_LOCAL_ITEM_TAG_USAGE_MINIMUM      1
+#define HID_LOCAL_ITEM_TAG_USAGE_MAXIMUM      2
+#define HID_LOCAL_ITEM_TAG_DESIGNATOR_INDEX   3
+#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MINIMUM 4
+#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MAXIMUM 5
+#define HID_LOCAL_ITEM_TAG_STRING_INDEX       7
+#define HID_LOCAL_ITEM_TAG_STRING_MINIMUM     8
+#define HID_LOCAL_ITEM_TAG_STRING_MAXIMUM     9
+#define HID_LOCAL_ITEM_TAG_DELIMITER          10
+
+//
+// HID report types
+//
+#define HID_INPUT_REPORT    1
+#define HID_OUTPUT_REPORT   2
+#define HID_FEATURE_REPORT  3
+
+//
+// HID class protocol request
+//
+#define EFI_USB_GET_REPORT_REQUEST    0x01
+#define EFI_USB_GET_IDLE_REQUEST      0x02
+#define EFI_USB_GET_PROTOCOL_REQUEST  0x03
+#define EFI_USB_SET_REPORT_REQUEST    0x09
+#define EFI_USB_SET_IDLE_REQUEST      0x0a
+#define EFI_USB_SET_PROTOCOL_REQUEST  0x0b
+
+#pragma pack(1)
+///
+/// Descriptor header for Report/Physical Descriptors
+/// HID 1.1, section 6.2.1
+///
+typedef struct hid_class_descriptor {
+  UINT8   DescriptorType;
+  UINT16  DescriptorLength;
+} EFI_USB_HID_CLASS_DESCRIPTOR;
+
+///
+/// The HID descriptor identifies the length and type
+/// of subordinate descriptors for a device.
+/// HID 1.1, section 6.2.1
+///
+typedef struct hid_descriptor {
+  UINT8                         Length;
+  UINT8                         DescriptorType;
+  UINT16                        BcdHID;
+  UINT8                         CountryCode;
+  UINT8                         NumDescriptors;
+  EFI_USB_HID_CLASS_DESCRIPTOR  HidClassDesc[1];
+} EFI_USB_HID_DESCRIPTOR;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/WatchdogActionTable.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/WatchdogActionTable.h
new file mode 100644
index 0000000000..124a5e7775
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/WatchdogActionTable.h
@@ -0,0 +1,96 @@
+/** @file   
+  ACPI Watchdog Action Table (WADT) as defined at
+  Microsoft Hardware Watchdog Timers Design Specification.
+
+  Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+**/
+
+
+#ifndef _WATCHDOG_ACTION_TABLE_H_
+#define _WATCHDOG_ACTION_TABLE_H_
+
+#include <IndustryStandard/Acpi.h>
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+///
+/// Watchdog Action Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  UINT32                                  WatchdogHeaderLength;
+  UINT16                                  PCISegment;
+  UINT8                                   PCIBusNumber;
+  UINT8                                   PCIDeviceNumber;
+  UINT8                                   PCIFunctionNumber;
+  UINT8                                   Reserved_45[3];
+  UINT32                                  TimerPeriod;
+  UINT32                                  MaxCount;
+  UINT32                                  MinCount;
+  UINT8                                   WatchdogFlags;  
+  UINT8                                   Reserved_61[3];  
+  UINT32                                  NumberWatchdogInstructionEntries;
+} EFI_ACPI_WATCHDOG_ACTION_1_0_TABLE;
+
+///
+/// Watchdog Instruction Entries
+///
+typedef struct {
+  UINT8                                   WatchdogAction;
+  UINT8                                   InstructionFlags;
+  UINT8                                   Reserved_2[2];
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  RegisterRegion;
+  UINT32                                  Value;
+  UINT32                                  Mask;
+} EFI_ACPI_WATCHDOG_ACTION_1_0_WATCHDOG_ACTION_INSTRUCTION_ENTRY;
+
+#pragma pack()
+
+///
+/// WDAT Revision (defined in spec)
+///
+#define EFI_ACPI_WATCHDOG_ACTION_1_0_TABLE_REVISION       0x01
+
+//
+// WDAT 1.0 Flags
+//
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ENABLED                0x1
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_STOPPED_IN_SLEEP_STATE 0x80
+
+//
+// WDAT 1.0 Watchdog Actions
+//
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_RESET                          0x1
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_CURRENT_COUNTDOWN_PERIOD 0x4
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_COUNTDOWN_PERIOD         0x5
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_COUNTDOWN_PERIOD           0x6
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_RUNNING_STATE            0x8
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_RUNNING_STATE              0x9
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_STOPPED_STATE            0xA
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_STOPPED_STATE              0xB
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_REBOOT                   0x10
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_REBOOT                     0x11
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_SHUTDOWN                 0x12
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_SHUTDOWN                   0x13
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_WATCHDOG_STATUS          0x20
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_WATCHDOG_STATUS            0x21
+
+//
+// WDAT 1.0 Watchdog Action Entry Instruction Flags
+//
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_READ_VALUE        0x0
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_READ_COUNTDOWN    0x1
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_WRITE_VALUE       0x2
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_WRITE_COUNTDOWN   0x3
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_PRESERVE_REGISTER 0x80
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/WatchdogResourceTable.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/WatchdogResourceTable.h
new file mode 100644
index 0000000000..a0b0cf2c18
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/WatchdogResourceTable.h
@@ -0,0 +1,56 @@
+/** @file   
+  ACPI Watchdog Resource Table (WDRT) as defined at
+  Microsoft Windows Hardware Developer Central.
+
+  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials                          
+  are licensed and made available under the terms and conditions of the BSD License         
+  which accompanies this distribution.  The full text of the license may be found at        
+  http://opensource.org/licenses/bsd-license.php                                            
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+**/
+
+#ifndef _WATCHDOG_RESOURCE_TABLE_H_
+#define _WATCHDOG_RESOURCE_TABLE_H_
+
+#include <IndustryStandard/Acpi.h>
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// Watchdog Resource Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  ControlRegisterAddress;
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE  CountRegisterAddress;
+  UINT16                                  PCIDeviceID;
+  UINT16                                  PCIVendorID;
+  UINT8                                   PCIBusNumber;
+  UINT8                                   PCIDeviceNumber;
+  UINT8                                   PCIFunctionNumber;
+  UINT8                                   PCISegment;
+  UINT16                                  MaxCount;
+  UINT8                                   Units;
+} EFI_ACPI_WATCHDOG_RESOURCE_1_0_TABLE;
+
+#pragma pack()
+
+//
+// WDRT Revision (defined in spec)
+//
+#define EFI_ACPI_WATCHDOG_RESOURCE_1_0_TABLE_REVISION  0x01
+
+//
+// WDRT 1.0 Count Unit
+//
+#define EFI_ACPI_WDRT_1_0_COUNT_UNIT_1_SEC_PER_COUNT        1
+#define EFI_ACPI_WDRT_1_0_COUNT_UNIT_100_MILLISEC_PER_COUNT 2
+#define EFI_ACPI_WDRT_1_0_COUNT_UNIT_10_MILLISEC_PER_COUNT  3
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/WindowsSmmSecurityMitigationTable.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/WindowsSmmSecurityMitigationTable.h
new file mode 100644
index 0000000000..390a3c8372
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/WindowsSmmSecurityMitigationTable.h
@@ -0,0 +1,39 @@
+/** @file
+  Defines Windows SMM Security Mitigation Table
+  @ https://msdn.microsoft.com/windows/hardware/drivers/bringup/acpi-system-description-tables#wsmt
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials 
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#ifndef _WINDOWS_SMM_SECURITY_MITIGATION_TABLE_H_
+#define _WINDOWS_SMM_SECURITY_MITIGATION_TABLE_H_
+
+#include <IndustryStandard/Acpi.h>
+
+#define EFI_ACPI_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE  SIGNATURE_32('W', 'S', 'M', 'T')
+
+#pragma pack(1)
+
+#define EFI_WSMT_TABLE_REVISION  1
+
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      ProtectionFlags;
+} EFI_ACPI_WSMT_TABLE;
+
+#define EFI_WSMT_PROTECTION_FLAGS_FIXED_COMM_BUFFERS                   0x1
+#define EFI_WSMT_PROTECTION_FLAGS_COMM_BUFFER_NESTED_PTR_PROTECTION    0x2
+#define EFI_WSMT_PROTECTION_FLAGS_SYSTEM_RESOURCE_PROTECTION           0x4
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/WindowsUxCapsule.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/WindowsUxCapsule.h
new file mode 100644
index 0000000000..611c8f6377
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/WindowsUxCapsule.h
@@ -0,0 +1,47 @@
+/** @file
+  Defines Windows UX Capsule GUID and layout defined at Microsoft
+  Windows UEFI Firmware Update Platform specification
+
+  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials 
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#ifndef _WINDOWS_UX_CAPSULE_GUID_H_
+#define _WINDOWS_UX_CAPSULE_GUID_H_
+
+#pragma pack(1)
+
+typedef struct {
+   UINT8  Version;
+   UINT8  Checksum;
+   UINT8  ImageType;
+   UINT8  Reserved;
+   UINT32 Mode;
+   UINT32 OffsetX;
+   UINT32 OffsetY;
+   //UINT8  Image[];
+} DISPLAY_DISPLAY_PAYLOAD;
+
+typedef struct {
+  EFI_CAPSULE_HEADER       CapsuleHeader;
+  DISPLAY_DISPLAY_PAYLOAD  ImagePayload;
+} EFI_DISPLAY_CAPSULE;
+
+#pragma pack()
+
+#define WINDOWS_UX_CAPSULE_GUID \
+  { \
+    0x3b8c8162, 0x188c, 0x46a4, { 0xae, 0xc9, 0xbe, 0x43, 0xf1, 0xd6, 0x56, 0x97}  \
+  }
+
+extern EFI_GUID gWindowsUxCapsuleGuid;
+
+#endif