vendorcode/intel: Add UDK2017 support

This patch includes (edk2/UDK2017) all required headers for UDK2017
from EDK2 github project using below command

>> git clone https://github.com/tianocore/edk2.git vUDK2017

commit hash: 66833b2a87d98be8d81d1337c193bcbf0de47d47

Change-Id: If0d5a3fef016c67e9eed6aed9b698b3b13b930c4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

1 files changed, 78 insertions, 0 deletions

diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PciExpress31.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PciExpress31.h
new file mode 100644
index 0000000000..72a3ccda81
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PciExpress31.h
@@ -0,0 +1,78 @@
+/** @file
+Support for the PCI Express 3.1 standard.
+
+This header file may not define all structures.  Please extend as required.
+
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCIEXPRESS31_H_
+#define _PCIEXPRESS31_H_
+
+#include <IndustryStandard/PciExpress30.h>
+
+#pragma pack(1)
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_ID    0x001E
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_VER1  0x1
+
+typedef union {
+  struct {
+    UINT32 PciPmL12 : 1;
+    UINT32 PciPmL11 : 1;
+    UINT32 AspmL12 : 1;
+    UINT32 AspmL11 : 1;
+    UINT32 L1PmSubstates : 1;
+    UINT32 Reserved : 3;
+    UINT32 CommonModeRestoreTime : 8;
+    UINT32 TPowerOnScale : 2;
+    UINT32 Reserved2 : 1;
+    UINT32 TPowerOnValue : 5;
+    UINT32 Reserved3 : 8;
+  } Bits;
+  UINT32   Uint32;
+} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY;
+
+typedef union {
+  struct {
+    UINT32 PciPmL12 : 1;
+    UINT32 PciPmL11 : 1;
+    UINT32 AspmL12 : 1;
+    UINT32 AspmL11 : 1;
+    UINT32 Reserved : 4;
+    UINT32 CommonModeRestoreTime : 8;
+    UINT32 LtrL12ThresholdValue : 10;
+    UINT32 Reserved2 : 3;
+    UINT32 LtrL12ThresholdScale : 3;
+  } Bits;
+  UINT32   Uint32;
+} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1;
+
+typedef union {
+  struct {
+    UINT32 TPowerOnScale : 2;
+    UINT32 Reserved : 1;
+    UINT32 TPowerOnValue : 5;
+    UINT32 Reserved2 : 24;
+  } Bits;
+  UINT32   Uint32;
+} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2;
+
+typedef struct {
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER   Header;
+  PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY Capability;
+  PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1   Control1;
+  PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2   Control2;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_L1_PM_SUBSTATES;
+
+#pragma pack()
+
+#endif