diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-12 15:23:25 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-28 08:59:11 +0000 |
| commit | ae7ac8a72372e4099bcf0667b5f97b4a223da48d (patch) | |
| tree | ae4d809a4cfa01711a76da4a5b5ca234f80ff778 /src/vendorcode/google/chromeos | |
| parent | fa5f9b5aff2279d6304a8b197e12714934025575 (diff) | |
ACPI: Separate ChromeOS NVS in ASL
For builds with MAINBOARD_HAS_CHROMEOS=y but CHROMEOS=n, there
is reduced dsdt.aml size and reduced GNVS allocation from cbmem.
More importantly, it's less error-prone when the OperationRegion
size is not hard-coded inside the .asl files.
Change-Id: I54b0d63a41561f9a5d9ebde77967e6d21ee014cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49477
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/google/chromeos')
| -rw-r--r-- | src/vendorcode/google/chromeos/acpi/gnvs.asl | 41 |
1 files changed, 22 insertions, 19 deletions
diff --git a/src/vendorcode/google/chromeos/acpi/gnvs.asl b/src/vendorcode/google/chromeos/acpi/gnvs.asl index 3f7681db87..89e7055f89 100644 --- a/src/vendorcode/google/chromeos/acpi/gnvs.asl +++ b/src/vendorcode/google/chromeos/acpi/gnvs.asl @@ -4,23 +4,26 @@ * the mainboard's chromeos.asl */ -VBT0, 32, // 0x000 - Boot Reason -VBT1, 32, // 0x004 - Active Main Firmware -VBT2, 32, // 0x008 - Active EC Firmware -VBT3, 16, // 0x00c - CHSW -VBT4, 2048, // 0x00e - HWID -VBT5, 512, // 0x10e - FWID -VBT6, 512, // 0x14e - FRID -VBT7, 32, // 0x18e - active main firmware type -VBT8, 32, // 0x192 - Recovery Reason -VBT9, 32, // 0x196 - FMAP base address -CHVD, 24576, // 0x19a - VDAT space filled by verified boot -VBTA, 32, // 0xd9a - pointer to smbios FWID -MEHH, 256, // 0xd9e - Management Engine Hash -RMOB, 32, // 0xdbe - RAM oops base address -RMOL, 32, // 0xdc2 - RAM oops length -ROVP, 32, // 0xdc6 - pointer to RO_VPD -ROVL, 32, // 0xdca - size of RO_VPD -RWVP, 32, // 0xdce - pointer to RW_VPD -RWVL, 32, // 0xdd2 - size of RW_VPD +Field (CNVS, ByteAcc, NoLock, Preserve) +{ + VBT0, 32, // 0x000 - Boot Reason + VBT1, 32, // 0x004 - Active Main Firmware + VBT2, 32, // 0x008 - Active EC Firmware + VBT3, 16, // 0x00c - CHSW + VBT4, 2048, // 0x00e - HWID + VBT5, 512, // 0x10e - FWID + VBT6, 512, // 0x14e - FRID + VBT7, 32, // 0x18e - active main firmware type + VBT8, 32, // 0x192 - Recovery Reason + VBT9, 32, // 0x196 - FMAP base address + CHVD, 24576, // 0x19a - VDAT space filled by verified boot + VBTA, 32, // 0xd9a - pointer to smbios FWID + MEHH, 256, // 0xd9e - Management Engine Hash + RMOB, 32, // 0xdbe - RAM oops base address + RMOL, 32, // 0xdc2 - RAM oops length + ROVP, 32, // 0xdc6 - pointer to RO_VPD + ROVL, 32, // 0xdca - size of RO_VPD + RWVP, 32, // 0xdce - pointer to RW_VPD + RWVL, 32, // 0xdd2 - size of RW_VPD // 0xdd6 +} |