ACPI: Separate ChromeOS NVS in ASL

For builds with MAINBOARD_HAS_CHROMEOS=y but CHROMEOS=n, there
is reduced dsdt.aml size and reduced GNVS allocation from cbmem.

More importantly, it's less error-prone when the OperationRegion
size is not hard-coded inside the .asl files.

Change-Id: I54b0d63a41561f9a5d9ebde77967e6d21ee014cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49477
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

14 files changed, 41 insertions, 59 deletions

diff --git a/src/acpi/acpigen_extern.asl b/src/acpi/acpigen_extern.asl
index 73d626fbea..5e380b5039 100644
--- a/src/acpi/acpigen_extern.asl
+++ b/src/acpi/acpigen_extern.asl
@@ -18,3 +18,9 @@ External (NVB1, IntObj)
 External (NVS1, IntObj)
 OperationRegion (DNVS, SystemMemory, NVB1, NVS1)
 #endif
+
+#if CONFIG(CHROMEOS)
+External (NVB2, IntObj)
+External (NVS2, IntObj)
+OperationRegion (CNVS, SystemMemory, NVB2, NVS2)
+#endif
diff --git a/src/acpi/dsdt_top.asl b/src/acpi/dsdt_top.asl
index 761c1b541d..8dceb6ae27 100644
--- a/src/acpi/dsdt_top.asl
+++ b/src/acpi/dsdt_top.asl
@@ -1,3 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpigen_extern.asl>
+
+#if CONFIG(CHROMEOS)
+#include <vendorcode/google/chromeos/acpi/gnvs.asl>
+#endif
diff --git a/src/acpi/gnvs.c b/src/acpi/gnvs.c
index 010b0e0149..4da830a5ad 100644
--- a/src/acpi/gnvs.c
+++ b/src/acpi/gnvs.c
@@ -41,7 +41,7 @@ void acpi_create_gnvs(void)
 		gnvs_size = 0x100;
 	if (CONFIG(ACPI_HAS_DEVICE_NVS))
 		gnvs_size = 0x2000;
-	else if (CONFIG(MAINBOARD_HAS_CHROMEOS))
+	else if (CONFIG(CHROMEOS))
 		gnvs_size = 0x1000;
 
 	gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, gnvs_size);
@@ -72,9 +72,16 @@ void acpi_fill_gnvs(void)
 
 	acpigen_write_scope("\\");
 	acpigen_write_name_dword("NVB0", (uintptr_t)gnvs);
-	acpigen_write_name_dword("NVS0", CONFIG(MAINBOARD_HAS_CHROMEOS) ? 0x1000 : 0x100);
+	acpigen_write_name_dword("NVS0", 0x100);
 	acpigen_pop_len();
 
+	if (CONFIG(CHROMEOS)) {
+		acpigen_write_scope("\\");
+		acpigen_write_name_dword("NVB2", (uintptr_t)gnvs + GNVS_CHROMEOS_ACPI_OFFSET);
+		acpigen_write_name_dword("NVS2", 0xf00);
+		acpigen_pop_len();
+	}
+
 	if (CONFIG(ACPI_HAS_DEVICE_NVS)) {
 		acpigen_write_scope("\\");
 		acpigen_write_name_dword("NVB1", (uintptr_t)gnvs + GNVS_DEVICE_NVS_OFFSET);
diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl
index 4b0e774755..9d3f381f97 100644
--- a/src/soc/amd/picasso/acpi/globalnvs.asl
+++ b/src/soc/amd/picasso/acpi/globalnvs.asl
@@ -21,7 +21,4 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	TMPS,	8,	// 0x17 - Temperature Sensor ID
 	TCRT,	8,	// 0x18 - Critical Threshold
 	TPSV,	8,	// 0x19 - Passive Threshold
-	/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
-	Offset (0x100),
-	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
 }
diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl
index 252ceda911..7a48dd57f8 100644
--- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl
+++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl
@@ -42,7 +42,4 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	FW01,	32,	// 0x28 - xHCI FW RAM addr, boot RAM
 	FW03,	32,	// 0x2c - xHCI FW RAM addr, Instruction RAM
 	EH10,	32,	// 0x30 - EHCI BAR
-	/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
-	Offset (0x100),
-	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
 }
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index 07853defe3..b79a446297 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -28,8 +28,4 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	ELNG,   64,     // 0x35 - 0x3C EPC Length
 	A4GB,	64,	// 0x3D - 0x44 Base of above 4GB MMIO Resource
 	A4GS,	64,	// 0x45 - 0x4C Length of above 4GB MMIO Resource
-
-	/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
-	Offset (0x100),
-	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
 }
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl
index eb51cada51..97530cb14c 100644
--- a/src/soc/intel/baytrail/acpi/globalnvs.asl
+++ b/src/soc/intel/baytrail/acpi/globalnvs.asl
@@ -42,10 +42,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	CMEM,	 32,	/* 0x30 - CBMEM TOC */
 	TOLM,	 32,	/* 0x34 - Top of Low Memory */
 	CBMC,	 32,	/* 0x38 - coreboot mem console pointer */
-
-	/* ChromeOS specific */
-	Offset (0x100),
-	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
 }
 
 /* Set flag to enable USB charging in S3 */
diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl
index 628a79190a..0714f23e39 100644
--- a/src/soc/intel/braswell/acpi/globalnvs.asl
+++ b/src/soc/intel/braswell/acpi/globalnvs.asl
@@ -44,10 +44,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	CMEM,	 32,	/* 0x30 - CBMEM TOC */
 	TOLM,	 32,	/* 0x34 - Top of Low Memory */
 	CBMC,	 32,	/* 0x38 - coreboot mem console pointer */
-
-	/* ChromeOS specific */
-	Offset (0x100),
-	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
 }
 
 /* Set flag to enable USB charging in S3 */
diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl
index 60d5737165..1911636f8d 100644
--- a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl
+++ b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl
@@ -34,10 +34,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	CBMC,	32,	// 0x1c - 0x1f - coreboot Memory Console
 	PM1I,	64,	// 0x20 - 0x27 - PM1 wake status bit
 	GPEI,	64,	// 0x28 - 0x2f - GPE wake status bit
-
-	/* ChromeOS specific */
-	Offset (0x100),
-	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
 }
 
 /* Set flag to enable USB charging in S3 */
diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
index d508544cb0..18852d4bd1 100644
--- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
+++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
@@ -26,8 +26,4 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	UIOR,	8,	// 0x2f - UART debug controller init on S3 resume
 	A4GB,	64,	// 0x30 - 0x37 Base of above 4GB MMIO Resource
 	A4GS,	64,	// 0x38 - 0x3f Length of above 4GB MMIO Resource
-
-	/* ChromeOS specific */
-	Offset (0x100),
-	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
 }
diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index 45c784e18d..cc7cc9c990 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -46,10 +46,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	ELNG,	64,	// 0x4C - 0x53 EPC Length
 	A4GB,	64,	// 0x54 - 0x5B Base of above 4GB MMIO Resource
 	A4GS,	64,	// 0x5C - 0x63 Length of above 4GB MMIO Resource
-
-	/* ChromeOS specific */
-	Offset (0x100),
-	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
 }
 
 /* Set flag to enable USB charging in S3 */
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
index eafa3adacc..f64a845238 100644
--- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
@@ -103,10 +103,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	Offset (0xf5),
 	TPIQ,	 8,	// 0xf5 - trackpad IRQ value
 	CBMC,	32,
-
-	/* ChromeOS specific */
-	Offset (0x100),
-	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
 }
 
 /* Set flag to enable USB charging in S3 */
diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
index 179a9912cc..f4071f1144 100644
--- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
@@ -93,10 +93,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 
 	Offset (0xa0),
 	CBMC, 32,	// 0xa0 - coreboot mem console pointer
-
-	/* ChromeOS specific */
-	Offset (0x100),
-	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
 }
 
 /* Set flag to enable USB charging in S3 */
diff --git a/src/vendorcode/google/chromeos/acpi/gnvs.asl b/src/vendorcode/google/chromeos/acpi/gnvs.asl
index 3f7681db87..89e7055f89 100644
--- a/src/vendorcode/google/chromeos/acpi/gnvs.asl
+++ b/src/vendorcode/google/chromeos/acpi/gnvs.asl
@@ -4,23 +4,26 @@
  * the mainboard's chromeos.asl
  */
 
-VBT0,   32,	// 0x000 - Boot Reason
-VBT1,   32,	// 0x004 - Active Main Firmware
-VBT2,   32,	// 0x008 - Active EC Firmware
-VBT3,   16,	// 0x00c - CHSW
-VBT4, 2048,	// 0x00e - HWID
-VBT5,  512,	// 0x10e - FWID
-VBT6,  512,	// 0x14e - FRID
-VBT7,   32,	// 0x18e - active main firmware type
-VBT8,   32,	// 0x192 - Recovery Reason
-VBT9,   32,	// 0x196 - FMAP base address
-CHVD, 24576,	// 0x19a - VDAT space filled by verified boot
-VBTA,	32,	// 0xd9a - pointer to smbios FWID
-MEHH,  256,	// 0xd9e - Management Engine Hash
-RMOB,   32,	// 0xdbe - RAM oops base address
-RMOL,   32,	// 0xdc2 - RAM oops length
-ROVP,	32,	// 0xdc6 - pointer to RO_VPD
-ROVL,	32,	// 0xdca - size of RO_VPD
-RWVP,	32,	// 0xdce - pointer to RW_VPD
-RWVL,	32,	// 0xdd2 - size of RW_VPD
+Field (CNVS, ByteAcc, NoLock, Preserve)
+{
+	VBT0,   32,	// 0x000 - Boot Reason
+	VBT1,   32,	// 0x004 - Active Main Firmware
+	VBT2,   32,	// 0x008 - Active EC Firmware
+	VBT3,   16,	// 0x00c - CHSW
+	VBT4, 2048,	// 0x00e - HWID
+	VBT5,  512,	// 0x10e - FWID
+	VBT6,  512,	// 0x14e - FRID
+	VBT7,   32,	// 0x18e - active main firmware type
+	VBT8,   32,	// 0x192 - Recovery Reason
+	VBT9,   32,	// 0x196 - FMAP base address
+	CHVD, 24576,	// 0x19a - VDAT space filled by verified boot
+	VBTA,	32,	// 0xd9a - pointer to smbios FWID
+	MEHH,  256,	// 0xd9e - Management Engine Hash
+	RMOB,   32,	// 0xdbe - RAM oops base address
+	RMOL,   32,	// 0xdc2 - RAM oops length
+	ROVP,	32,	// 0xdc6 - pointer to RO_VPD
+	ROVL,	32,	// 0xdca - size of RO_VPD
+	RWVP,	32,	// 0xdce - pointer to RW_VPD
+	RWVL,	32,	// 0xdd2 - size of RW_VPD
 		// 0xdd6
+}