diff options
| author | Peter Lemenkov <lemenkov@gmail.com> | 2018-10-19 16:57:27 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2018-10-23 06:15:43 +0000 |
| commit | 5797b2eb05ec46d877a2ae6b5e0c517ae54a6fe8 (patch) | |
| tree | 1b23efeb6e987f4886ffd5afa12418234eb988b4 /src/vendorcode/amd/agesa/f15tn/Proc | |
| parent | 39315985e89e6ef3e7c01e697faf439280045157 (diff) | |
src: Typo fix (cosmetic)
Change-Id: I81985bd2836bdeb369587f170504a8a048ee496b
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29196
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/agesa/f15tn/Proc')
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c | 2 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c index c7efe43532..6d28bfe5cb 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c @@ -113,7 +113,7 @@ F15TnIsCpbSupported ( /*---------------------------------------------------------------------------------------*/ /** - * BSC entry point for for enabling Core Performance Boost. + * BSC entry point for enabling Core Performance Boost. * * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG. * diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c index 77f0b65ea1..1660c493ee 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c @@ -85,7 +85,7 @@ STATIC CONST UINT16 ROMDATA MmioBaseLimitHiRegOffset[MMIO_REG_PAIR_NUM] = {0x180 /*---------------------------------------------------------------------------------------*/ /** - * BSC entry point for for adding MMIO map + * BSC entry point for adding MMIO map * * program MMIO base/limit registers * |