diff options
| author | Mike Banon <mikebdp2@gmail.com> | 2018-08-23 00:50:08 +0300 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-05-20 15:15:22 +0000 |
| commit | 334e8360efb03644488ce4ac8a9a9e75ef6fa6c0 (patch) | |
| tree | 375720660e6bab2f3480e8e495facbd5857454a6 /src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h | |
| parent | cf041d8c8375d07434908a8bd1028d4bd0d54070 (diff) | |
src/vendorcode/amd/agesa/f15tn: Update microcode to version 0x600111F 2018-03-05
This microcode update for CPU IDs 0x610F01/0x610F31 improves system stability:
in particular, fixes Xen hardware virtualization freezes. Also it attempts to
patch some Spectre-related security vulnerabilities. This new microcode has been
tested by multiple coreboot community members and found working perfectly.
Old version: 0x600110F [2012-01-11]
replaced by
New version: 0x600111F [2018-03-05]
Change-Id: Ied5da0ff85abb63c2db2eeafd051b8e00916d961
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28273
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: <awokd@danwin1210.me>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h')
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h index f0d9194018..bd00756c43 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h @@ -808,9 +808,9 @@ extern F_IS_NB_PSTATE_ENABLED F15IsNbPstateEnabled; #define F15_TN_UCODE_0E #if AGESA_ENTRY_INIT_EARLY == TRUE - extern CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600110F_Enc []; + extern CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600111F_Enc []; #undef F15_TN_UCODE_10F - #define F15_TN_UCODE_10F CpuF15TnMicrocodePatch0600110F_Enc, + #define F15_TN_UCODE_10F CpuF15TnMicrocodePatch0600111F_Enc, #endif |