diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2015-07-30 11:17:40 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-10-30 18:24:07 +0100 |
| commit | d91ddc8d3181b8ab23726c8e744093f39473c202 (patch) | |
| tree | 9214b34758be7bb547f7168fc838abeb00e05c7d /src/vendorcode/amd/agesa/f15/Legacy | |
| parent | 772029fe7321e0ddea11711b6756a32f19572db4 (diff) | |
vendorcode/amd: 64bit fixes
Change-Id: I6a0752cf0c0e484e670acca97c4991b5578845fb
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11081
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/vendorcode/amd/agesa/f15/Legacy')
| -rw-r--r-- | src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c | 4 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c | 12 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c index ae25a49dd9..4353c41c3e 100644 --- a/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c +++ b/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c @@ -83,8 +83,8 @@ AmdAgesaDispatcher ( IMAGE_ENTRY ImageEntry; MODULE_ENTRY ModuleEntry; DISPATCH_TABLE *Entry; - UINT32 ImageStart; - UINT32 ImageEnd; + UINTN ImageStart; + UINTN ImageEnd; AMD_IMAGE_HEADER* AltImagePtr; Status = AGESA_UNSUPPORTED; diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c index b2accb2aaf..aa7c1b87b7 100644 --- a/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c +++ b/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c @@ -148,7 +148,7 @@ CopyHeapToTempRamAtPost ( // // 0xC0000 ~ 0xFFFFF // - HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX4k_C0000 + (((AmdHeapRamAddress >> 16) & 0x3) * 2)); + HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX4k_C0000 + ((((UINTN)AmdHeapRamAddress >> 16) & 0x3) * 2)); MsrData = AMD_MTRR_FIX4K_UC_DRAM; LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader); LibAmdMsrWrite ((HeapRamFixMtrr + 1), &MsrData, StdHeader); @@ -156,7 +156,7 @@ CopyHeapToTempRamAtPost ( // // 0x80000~0xBFFFF // - HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX16k_80000 + ((AmdHeapRamAddress >> 17) & 0x1)); + HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX16k_80000 + (((UINTN)AmdHeapRamAddress >> 17) & 0x1)); MsrData = AMD_MTRR_FIX16K_UC_DRAM; LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader); } else { @@ -165,7 +165,7 @@ CopyHeapToTempRamAtPost ( // LibAmdMsrRead (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); MsrData = MsrData & (~(0xFF << (8 * ((AmdHeapRamAddress >> 16) & 0x7)))); - MsrData = MsrData | (AMD_MTRR_FIX64K_UC_DRAM << (8 * ((AmdHeapRamAddress >> 16) & 0x7))); + MsrData = MsrData | (AMD_MTRR_FIX64K_UC_DRAM << (8 * (((UINTN)AmdHeapRamAddress >> 16) & 0x7))); LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); } @@ -209,7 +209,7 @@ CopyHeapToTempRamAtPost ( TotalSize = sizeof (HEAP_MANAGER); SizeOfNodeData = 0; AlignTo16ByteInTempMem = 0; - BaseAddressInCache = (UINT8 *) (UINT32)StdHeader->HeapBasePtr; + BaseAddressInCache = (UINT8 *) (UINTN)StdHeader->HeapBasePtr; HeapManagerInCache = (HEAP_MANAGER *) BaseAddressInCache; HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset; HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset); @@ -308,8 +308,8 @@ CopyHeapToMainRamAtPost ( TotalSize = sizeof (HEAP_MANAGER); SizeOfNodeData = 0; AlignTo16ByteInMainMem = 0; - BaseAddressInTempMem = (UINT8 *)(UINT32) StdHeader->HeapBasePtr; - HeapManagerInTempMem = (HEAP_MANAGER *)(UINT32) StdHeader->HeapBasePtr; + BaseAddressInTempMem = (UINT8 *)(UINTN) StdHeader->HeapBasePtr; + HeapManagerInTempMem = (HEAP_MANAGER *)(UINTN) StdHeader->HeapBasePtr; HeapInTempMemOffset = HeapManagerInTempMem->FirstActiveBufferOffset; HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset); |