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authorStefan Reinauer <reinauer@chromium.org>2015-07-30 11:17:40 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-10-30 18:24:07 +0100
commitd91ddc8d3181b8ab23726c8e744093f39473c202 (patch)
tree9214b34758be7bb547f7168fc838abeb00e05c7d /src/vendorcode/amd/agesa
parent772029fe7321e0ddea11711b6756a32f19572db4 (diff)
vendorcode/amd: 64bit fixes
Change-Id: I6a0752cf0c0e484e670acca97c4991b5578845fb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11081 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/vendorcode/amd/agesa')
-rw-r--r--src/vendorcode/amd/agesa/f10/Include/Ids.h2
-rw-r--r--src/vendorcode/amd/agesa/f10/Include/gcc-intrin.h46
-rw-r--r--src/vendorcode/amd/agesa/f10/Makefile.inc6
-rw-r--r--src/vendorcode/amd/agesa/f10/gcccar.inc5
-rw-r--r--src/vendorcode/amd/agesa/f12/Include/Ids.h2
-rw-r--r--src/vendorcode/amd/agesa/f12/Include/gcc-intrin.h46
-rw-r--r--src/vendorcode/amd/agesa/f12/Makefile.inc13
-rw-r--r--src/vendorcode/amd/agesa/f12/cpcarmac.inc8
-rw-r--r--src/vendorcode/amd/agesa/f14/Include/Ids.h2
-rw-r--r--src/vendorcode/amd/agesa/f14/Legacy/Proc/Dispatcher.c4
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c10
-rw-r--r--src/vendorcode/amd/agesa/f15/Include/Ids.h2
-rw-r--r--src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h24
-rw-r--r--src/vendorcode/amd/agesa/f15/Include/gcc-intrin.h46
-rw-r--r--src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c4
-rw-r--r--src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c12
-rw-r--r--src/vendorcode/amd/agesa/f15/Makefile.inc7
-rw-r--r--src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c14
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Include/Ids.h2
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h24
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Include/gcc-intrin.h46
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Legacy/Proc/Dispatcher.c4
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c4
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c12
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Makefile.inc6
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c14
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3LateRestore.c2
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfx.h2
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h2
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c2
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c2
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c2
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Include/Ids.h2
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Include/OptionIdsInstall.h24
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Include/gcc-intrin.h46
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Legacy/Proc/Dispatcher.c10
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Legacy/Proc/agesaCallouts.c2
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c6
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Makefile.inc3
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatureLeveling.c2
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c4
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.c2
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c14
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3LateRestore.c2
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Gnb.h2
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c6
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.c12
47 files changed, 269 insertions, 245 deletions
diff --git a/src/vendorcode/amd/agesa/f10/Include/Ids.h b/src/vendorcode/amd/agesa/f10/Include/Ids.h
index 73a88564d2..2607b3dd43 100644
--- a/src/vendorcode/amd/agesa/f10/Include/Ids.h
+++ b/src/vendorcode/amd/agesa/f10/Include/Ids.h
@@ -447,7 +447,7 @@ typedef enum { //vv- for debug reference only
/// Function entry for HDT script to call
typedef struct _SCRIPT_FUNCTION {
- UINT32 FuncAddr; ///< Function address in ROM
+ UINTN FuncAddr; ///< Function address in ROM
CHAR8 FuncName[40]; ///< Function name
} SCRIPT_FUNCTION;
diff --git a/src/vendorcode/amd/agesa/f10/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f10/Include/gcc-intrin.h
index 7d90f8bb5a..9ae45c3ee2 100644
--- a/src/vendorcode/amd/agesa/f10/Include/gcc-intrin.h
+++ b/src/vendorcode/amd/agesa/f10/Include/gcc-intrin.h
@@ -27,11 +27,11 @@
*/
#if defined (__GNUC__)
-
+#include <stdint.h>
/* I/O intrin functions. */
-static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned short Port)
+static __inline__ __attribute__((always_inline)) uint8_t __inbyte(uint16_t Port)
{
- unsigned char value;
+ uint8_t value;
__asm__ __volatile__ (
"in %1, %0"
@@ -42,9 +42,9 @@ static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned
return value;
}
-static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigned short Port)
+static __inline__ __attribute__((always_inline)) uint16_t __inword(uint16_t Port)
{
- unsigned short value;
+ uint16_t value;
__asm__ __volatile__ (
"in %1, %0"
@@ -55,9 +55,9 @@ static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigne
return value;
}
-static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigned short Port)
+static __inline__ __attribute__((always_inline)) uint32_t __indword(uint16_t Port)
{
- unsigned long value;
+ uint32_t value;
__asm__ __volatile__ (
"in %1, %0"
@@ -68,7 +68,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigne
}
-static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short Port,unsigned char Data)
+static __inline__ __attribute__((always_inline)) void __outbyte(uint16_t Port,uint8_t Data)
{
__asm__ __volatile__ (
"out %0, %1"
@@ -77,7 +77,7 @@ static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short P
);
}
-static __inline__ __attribute__((always_inline)) void __outword(unsigned short Port,unsigned short Data)
+static __inline__ __attribute__((always_inline)) void __outword(uint16_t Port,uint16_t Data)
{
__asm__ __volatile__ (
"out %0, %1"
@@ -86,7 +86,7 @@ static __inline__ __attribute__((always_inline)) void __outword(unsigned short P
);
}
-static __inline__ __attribute__((always_inline)) void __outdword(unsigned short Port,unsigned long Data)
+static __inline__ __attribute__((always_inline)) void __outdword(uint16_t Port,uint32_t Data)
{
__asm__ __volatile__ (
"out %0, %1"
@@ -95,7 +95,7 @@ static __inline__ __attribute__((always_inline)) void __outdword(unsigned short
);
}
-static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __inbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; insb"
@@ -104,7 +104,7 @@ static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned sh
);
}
-static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __inwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; insw"
@@ -113,7 +113,7 @@ static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned sh
);
}
-static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __indwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; insl"
@@ -122,7 +122,7 @@ static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned s
);
}
-static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __outbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; outsb"
@@ -131,7 +131,7 @@ static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned s
);
}
-static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __outwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; outsw"
@@ -140,7 +140,7 @@ static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned s
);
}
-static __inline__ __attribute__((always_inline)) void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __outdwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; outsl"
@@ -525,7 +525,7 @@ static __inline__ __attribute__((always_inline)) void __lidt(void *Source)
}
static __inline__ __attribute__((always_inline)) void
-__writefsbyte(const unsigned long Offset, const unsigned char Data)
+__writefsbyte(const unsigned long Offset, const uint8_t Data)
{
__asm__ ("movb %[Data], %%fs:%a[Offset]"
:
@@ -533,7 +533,7 @@ __writefsbyte(const unsigned long Offset, const unsigned char Data)
}
static __inline__ __attribute__((always_inline)) void
-__writefsword(const unsigned long Offset, const unsigned short Data)
+__writefsword(const unsigned long Offset, const uint16_t Data)
{
__asm__ ("movw %[Data], %%fs:%a[Offset]"
:
@@ -541,14 +541,14 @@ __writefsword(const unsigned long Offset, const unsigned short Data)
}
static __inline__ __attribute__((always_inline)) void
-__writefsdword(const unsigned long Offset, const unsigned long Data)
+__writefsdword(const unsigned long Offset, const uint32_t Data)
{
__asm__ ("movl %[Data], %%fs:%a[Offset]"
:
: [Offset] "ir" (Offset), [Data] "ir" (Data));
}
-static __inline__ __attribute__((always_inline)) unsigned char
+static __inline__ __attribute__((always_inline)) uint8_t
__readfsbyte(const unsigned long Offset)
{
unsigned char value;
@@ -558,7 +558,7 @@ __readfsbyte(const unsigned long Offset)
return value;
}
-static __inline__ __attribute__((always_inline)) unsigned short
+static __inline__ __attribute__((always_inline)) uint16_t
__readfsword(const unsigned long Offset)
{
unsigned short value;
@@ -568,11 +568,11 @@ __readfsword(const unsigned long Offset)
return value;
}
-static __inline__ __attribute__((always_inline)) unsigned long
+static __inline__ __attribute__((always_inline)) uint32_t
__readfsdword(unsigned long Offset)
{
unsigned long value;
- __asm__ ("movl %%fs:%a[Offset], %[value]"
+ __asm__ ("mov %%fs:%a[Offset], %[value]"
: [value] "=r" (value)
: [Offset] "ir" (Offset));
return value;
diff --git a/src/vendorcode/amd/agesa/f10/Makefile.inc b/src/vendorcode/amd/agesa/f10/Makefile.inc
index fe4a797d5c..e0aa00dcd1 100644
--- a/src/vendorcode/amd/agesa/f10/Makefile.inc
+++ b/src/vendorcode/amd/agesa/f10/Makefile.inc
@@ -47,15 +47,21 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/Mem
## AGESA need sse feature ##
CFLAGS_x86_32 += -msse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
+CFLAGS_x86_64 += -msse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
export AGESA_ROOT := $(AGESA_ROOT)
export AGESA_INC := $(AGESA_INC)
CPPFLAGS_x86_32 += $(AGESA_INC)
+CPPFLAGS_x86_64 += $(AGESA_INC)
#######################################################################
classes-y += libagesa
+ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
$(eval $(call create_class_compiler,libagesa,x86_32))
+else
+$(eval $(call create_class_compiler,libagesa,x86_64))
+endif
#libagesa-y += Proc/CPU/Family/0x10/F10IoCstate.c
#libagesa-y += Proc/CPU/Feature/cpuIoCstate.c
diff --git a/src/vendorcode/amd/agesa/f10/gcccar.inc b/src/vendorcode/amd/agesa/f10/gcccar.inc
index 94d0ccc3fa..2f0e0836b0 100644
--- a/src/vendorcode/amd/agesa/f10/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f10/gcccar.inc
@@ -240,7 +240,7 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
jnz node_core_exit # Br if yes
mov $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue
-
+
mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B
_RDMSR
bt $APIC_BSC, %eax # Is this the BSC?
@@ -965,7 +965,7 @@ fam15_enable_stack_hook_exit:
btr $DIS_HW_PF, %eax # Turn on hardware prefetches
#.endif # End workaround for erratum 498
0:
- _WRMSR
+ _WRMSR
#--------------------------------------------------------------------------
# Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
#--------------------------------------------------------------------------
@@ -1609,4 +1609,3 @@ ClearTheStack: # Stack base is in SS, stack pointer is
xor %eax, %eax
.endm
-
diff --git a/src/vendorcode/amd/agesa/f12/Include/Ids.h b/src/vendorcode/amd/agesa/f12/Include/Ids.h
index 216c1b948f..3f1f37b72d 100644
--- a/src/vendorcode/amd/agesa/f12/Include/Ids.h
+++ b/src/vendorcode/amd/agesa/f12/Include/Ids.h
@@ -666,7 +666,7 @@ typedef enum { //vv- for debug reference only
#define IDS_CALLOUT_FCH_INIT_ENV 0x00 ///< The function data of IDS callout function of FchInitEnv.
/// Function entry for HDT script to call
typedef struct _SCRIPT_FUNCTION {
- UINT32 FuncAddr; ///< Function address in ROM
+ UINTN FuncAddr; ///< Function address in ROM
CHAR8 FuncName[40]; ///< Function name
} SCRIPT_FUNCTION;
diff --git a/src/vendorcode/amd/agesa/f12/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f12/Include/gcc-intrin.h
index 7d90f8bb5a..9ae45c3ee2 100644
--- a/src/vendorcode/amd/agesa/f12/Include/gcc-intrin.h
+++ b/src/vendorcode/amd/agesa/f12/Include/gcc-intrin.h
@@ -27,11 +27,11 @@
*/
#if defined (__GNUC__)
-
+#include <stdint.h>
/* I/O intrin functions. */
-static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned short Port)
+static __inline__ __attribute__((always_inline)) uint8_t __inbyte(uint16_t Port)
{
- unsigned char value;
+ uint8_t value;
__asm__ __volatile__ (
"in %1, %0"
@@ -42,9 +42,9 @@ static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned
return value;
}
-static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigned short Port)
+static __inline__ __attribute__((always_inline)) uint16_t __inword(uint16_t Port)
{
- unsigned short value;
+ uint16_t value;
__asm__ __volatile__ (
"in %1, %0"
@@ -55,9 +55,9 @@ static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigne
return value;
}
-static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigned short Port)
+static __inline__ __attribute__((always_inline)) uint32_t __indword(uint16_t Port)
{
- unsigned long value;
+ uint32_t value;
__asm__ __volatile__ (
"in %1, %0"
@@ -68,7 +68,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigne
}
-static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short Port,unsigned char Data)
+static __inline__ __attribute__((always_inline)) void __outbyte(uint16_t Port,uint8_t Data)
{
__asm__ __volatile__ (
"out %0, %1"
@@ -77,7 +77,7 @@ static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short P
);
}
-static __inline__ __attribute__((always_inline)) void __outword(unsigned short Port,unsigned short Data)
+static __inline__ __attribute__((always_inline)) void __outword(uint16_t Port,uint16_t Data)
{
__asm__ __volatile__ (
"out %0, %1"
@@ -86,7 +86,7 @@ static __inline__ __attribute__((always_inline)) void __outword(unsigned short P
);
}
-static __inline__ __attribute__((always_inline)) void __outdword(unsigned short Port,unsigned long Data)
+static __inline__ __attribute__((always_inline)) void __outdword(uint16_t Port,uint32_t Data)
{
__asm__ __volatile__ (
"out %0, %1"
@@ -95,7 +95,7 @@ static __inline__ __attribute__((always_inline)) void __outdword(unsigned short
);
}
-static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __inbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; insb"
@@ -104,7 +104,7 @@ static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned sh
);
}
-static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __inwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; insw"
@@ -113,7 +113,7 @@ static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned sh
);
}
-static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __indwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; insl"
@@ -122,7 +122,7 @@ static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned s
);
}
-static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __outbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; outsb"
@@ -131,7 +131,7 @@ static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned s
);
}
-static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __outwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; outsw"
@@ -140,7 +140,7 @@ static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned s
);
}
-static __inline__ __attribute__((always_inline)) void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __outdwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; outsl"
@@ -525,7 +525,7 @@ static __inline__ __attribute__((always_inline)) void __lidt(void *Source)
}
static __inline__ __attribute__((always_inline)) void
-__writefsbyte(const unsigned long Offset, const unsigned char Data)
+__writefsbyte(const unsigned long Offset, const uint8_t Data)
{
__asm__ ("movb %[Data], %%fs:%a[Offset]"
:
@@ -533,7 +533,7 @@ __writefsbyte(const unsigned long Offset, const unsigned char Data)
}
static __inline__ __attribute__((always_inline)) void
-__writefsword(const unsigned long Offset, const unsigned short Data)
+__writefsword(const unsigned long Offset, const uint16_t Data)
{
__asm__ ("movw %[Data], %%fs:%a[Offset]"
:
@@ -541,14 +541,14 @@ __writefsword(const unsigned long Offset, const unsigned short Data)
}
static __inline__ __attribute__((always_inline)) void
-__writefsdword(const unsigned long Offset, const unsigned long Data)
+__writefsdword(const unsigned long Offset, const uint32_t Data)
{
__asm__ ("movl %[Data], %%fs:%a[Offset]"
:
: [Offset] "ir" (Offset), [Data] "ir" (Data));
}
-static __inline__ __attribute__((always_inline)) unsigned char
+static __inline__ __attribute__((always_inline)) uint8_t
__readfsbyte(const unsigned long Offset)
{
unsigned char value;
@@ -558,7 +558,7 @@ __readfsbyte(const unsigned long Offset)
return value;
}
-static __inline__ __attribute__((always_inline)) unsigned short
+static __inline__ __attribute__((always_inline)) uint16_t
__readfsword(const unsigned long Offset)
{
unsigned short value;
@@ -568,11 +568,11 @@ __readfsword(const unsigned long Offset)
return value;
}
-static __inline__ __attribute__((always_inline)) unsigned long
+static __inline__ __attribute__((always_inline)) uint32_t
__readfsdword(unsigned long Offset)
{
unsigned long value;
- __asm__ ("movl %%fs:%a[Offset], %[value]"
+ __asm__ ("mov %%fs:%a[Offset], %[value]"
: [value] "=r" (value)
: [Offset] "ir" (Offset));
return value;
diff --git a/src/vendorcode/amd/agesa/f12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Makefile.inc
index 1e5bc703cb..e135e2ac44 100644
--- a/src/vendorcode/amd/agesa/f12/Makefile.inc
+++ b/src/vendorcode/amd/agesa/f12/Makefile.inc
@@ -2,7 +2,7 @@
#
# Copyright (c) 2011, Advanced Micro Devices, Inc.
# All rights reserved.
-#
+#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright
@@ -10,10 +10,10 @@
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
-# * Neither the name of Advanced Micro Devices, Inc. nor the names of
-# its contributors may be used to endorse or promote products derived
+# * Neither the name of Advanced Micro Devices, Inc. nor the names of
+# its contributors may be used to endorse or promote products derived
# from this software without specific prior written permission.
-#
+#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -24,7 +24,7 @@
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
+#
#*****************************************************************************
# AGESA V5 Files
@@ -80,7 +80,10 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Tech
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Tech/DDR3
CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
+CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
export AGESA_INC := $(AGESA_INC)
CPPFLAGS_x86_32 += $(AGESA_INC)
+CPPFLAGS_x86_64 += $(AGESA_INC)
+
#######################################################################
diff --git a/src/vendorcode/amd/agesa/f12/cpcarmac.inc b/src/vendorcode/amd/agesa/f12/cpcarmac.inc
index b4add85922..dce7d3f333 100644
--- a/src/vendorcode/amd/agesa/f12/cpcarmac.inc
+++ b/src/vendorcode/amd/agesa/f12/cpcarmac.inc
@@ -9,7 +9,7 @@
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
-;
+;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
@@ -17,10 +17,10 @@
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
+; * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
-;
+;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
diff --git a/src/vendorcode/amd/agesa/f14/Include/Ids.h b/src/vendorcode/amd/agesa/f14/Include/Ids.h
index 732f458f8f..451c4d6c8f 100644
--- a/src/vendorcode/amd/agesa/f14/Include/Ids.h
+++ b/src/vendorcode/amd/agesa/f14/Include/Ids.h
@@ -643,7 +643,7 @@ typedef enum { //vv- for debug reference only
/// Function entry for HDT script to call
typedef struct _SCRIPT_FUNCTION {
- UINT32 FuncAddr; ///< Function address in ROM
+ UINTN FuncAddr; ///< Function address in ROM
CHAR8 FuncName[40]; ///< Function name
} SCRIPT_FUNCTION;
diff --git a/src/vendorcode/amd/agesa/f14/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f14/Legacy/Proc/Dispatcher.c
index 68d9e6fcd9..d7c6f80dbb 100644
--- a/src/vendorcode/amd/agesa/f14/Legacy/Proc/Dispatcher.c
+++ b/src/vendorcode/amd/agesa/f14/Legacy/Proc/Dispatcher.c
@@ -85,8 +85,8 @@ AmdAgesaDispatcher (
IMAGE_ENTRY ImageEntry;
MODULE_ENTRY ModuleEntry;
DISPATCH_TABLE *Entry;
- UINT32 ImageStart;
- UINT32 ImageEnd;
+ UINTN ImageStart;
+ UINTN ImageEnd;
CONST AMD_IMAGE_HEADER* AltImagePtr;
Status = AGESA_UNSUPPORTED;
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c
index a8a6d46b60..4963b4b056 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c
@@ -259,30 +259,30 @@ MemFS3GetDeviceList (
(*DeviceBlockHdrPtr)->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize;
// Copy device list on the stack to the heap.
- BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) (UINT32) AllocHeapParams.BufferPtr;
+ BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINTN) AllocHeapParams.BufferPtr;
for (Die = 0; Die < DieCount; Die ++) {
for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
// Copy PCI device descriptor to the heap if it exists.
if (DeviceDescript[Die].PCIDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader);
+ LibAmdMemCopy ((VOID *)(UINTN) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader);
(*DeviceBlockHdrPtr)->NumDevices ++;
BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR);
}
// Copy conditional PCI device descriptor to the heap if it exists.
if (DeviceDescript[Die].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader);
+ LibAmdMemCopy ((VOID *)(UINTN) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader);
(*DeviceBlockHdrPtr)->NumDevices ++;
BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
}
// Copy MSR device descriptor to the heap if it exists.
if (DeviceDescript[Die].MSRDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader);
+ LibAmdMemCopy ((VOID *)(UINTN) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader);
(*DeviceBlockHdrPtr)->NumDevices ++;
BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR);
}
// Copy conditional MSR device descriptor to the heap if it exists.
if (DeviceDescript[Die].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader);
+ LibAmdMemCopy ((VOID *)(UINTN) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader);
(*DeviceBlockHdrPtr)->NumDevices ++;
BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
}
diff --git a/src/vendorcode/amd/agesa/f15/Include/Ids.h b/src/vendorcode/amd/agesa/f15/Include/Ids.h
index b8d50919be..07ceeaf603 100644
--- a/src/vendorcode/amd/agesa/f15/Include/Ids.h
+++ b/src/vendorcode/amd/agesa/f15/Include/Ids.h
@@ -615,7 +615,7 @@ typedef enum { //vv- for debug reference only
/// Function entry for HDT script to call
typedef struct _SCRIPT_FUNCTION {
- UINT32 FuncAddr; ///< Function address in ROM
+ UINTN FuncAddr; ///< Function address in ROM
CHAR8 FuncName[40]; ///< Function name
} SCRIPT_FUNCTION;
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h
index a2c0034bd8..6873370a55 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h
@@ -74,29 +74,29 @@ CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVE
#if (AGESA_ENTRY_INIT_POST == TRUE)
#include <mu.h>
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
- { (UINT32) /*(UINT64)*/ MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
- { (UINT32) /*(UINT64)*/ MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
- { (UINT32) /*(UINT64)*/ MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"}
+ { (UINTN) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
+ { (UINTN) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
+ { (UINTN) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"}
};
#elif (AGESA_ENTRY_INIT_RECOVERY == TRUE)
#include <mru.h>
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
- { (UINT32) (UINT64) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"},
- { (UINT32) (UINT64) MemRecURead1CL, "Read1Cl(BufferAddr,PhyAddrLo)"},
- { (UINT32) (UINT64) MemRecUFlushPattern, "Flush1Cl(PhyAddrLo)"}
+ { (UINTN) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"},
+ { (UINTN) MemRecURead1CL, "Read1Cl(BufferAddr,PhyAddrLo)"},
+ { (UINTN) MemRecUFlushPattern, "Flush1Cl(PhyAddrLo)"}
};
#else
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
- { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"},
- { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"},
- { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"}
+ { (UINTN) CommonReturnFalse, "DefRet()"},
+ { (UINTN) CommonReturnFalse, "DefRet()"},
+ { (UINTN) CommonReturnFalse, "DefRet()"}
};
#endif
#else
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
- { (UINT32) /*(UINT64)*/ CommonReturnFalse, "DefRet()"},
- { (UINT32) /*(UINT64)*/ CommonReturnFalse, "DefRet()"},
- { (UINT32) /*(UINT64)*/ CommonReturnFalse, "DefRet()"}
+ { (UINTN) CommonReturnFalse, "DefRet()"},
+ { (UINTN) CommonReturnFalse, "DefRet()"},
+ { (UINTN) CommonReturnFalse, "DefRet()"}
};
#endif
diff --git a/src/vendorcode/amd/agesa/f15/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f15/Include/gcc-intrin.h
index 7d90f8bb5a..9ae45c3ee2 100644
--- a/src/vendorcode/amd/agesa/f15/Include/gcc-intrin.h
+++ b/src/vendorcode/amd/agesa/f15/Include/gcc-intrin.h
@@ -27,11 +27,11 @@
*/
#if defined (__GNUC__)
-
+#include <stdint.h>
/* I/O intrin functions. */
-static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned short Port)
+static __inline__ __attribute__((always_inline)) uint8_t __inbyte(uint16_t Port)
{
- unsigned char value;
+ uint8_t value;
__asm__ __volatile__ (
"in %1, %0"
@@ -42,9 +42,9 @@ static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned
return value;
}
-static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigned short Port)
+static __inline__ __attribute__((always_inline)) uint16_t __inword(uint16_t Port)
{
- unsigned short value;
+ uint16_t value;
__asm__ __volatile__ (
"in %1, %0"
@@ -55,9 +55,9 @@ static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigne
return value;
}
-static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigned short Port)
+static __inline__ __attribute__((always_inline)) uint32_t __indword(uint16_t Port)
{
- unsigned long value;
+ uint32_t value;
__asm__ __volatile__ (
"in %1, %0"
@@ -68,7 +68,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigne
}
-static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short Port,unsigned char Data)
+static __inline__ __attribute__((always_inline)) void __outbyte(uint16_t Port,uint8_t Data)
{
__asm__ __volatile__ (
"out %0, %1"
@@ -77,7 +77,7 @@ static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short P
);
}
-static __inline__ __attribute__((always_inline)) void __outword(unsigned short Port,unsigned short Data)
+static __inline__ __attribute__((always_inline)) void __outword(uint16_t Port,uint16_t Data)
{
__asm__ __volatile__ (
"out %0, %1"
@@ -86,7 +86,7 @@ static __inline__ __attribute__((always_inline)) void __outword(unsigned short P
);
}
-static __inline__ __attribute__((always_inline)) void __outdword(unsigned short Port,unsigned long Data)
+static __inline__ __attribute__((always_inline)) void __outdword(uint16_t Port,uint32_t Data)
{
__asm__ __volatile__ (
"out %0, %1"
@@ -95,7 +95,7 @@ static __inline__ __attribute__((always_inline)) void __outdword(unsigned short
);
}
-static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __inbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; insb"
@@ -104,7 +104,7 @@ static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned sh
);
}
-static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __inwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; insw"
@@ -113,7 +113,7 @@ static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned sh
);
}
-static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __indwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; insl"
@@ -122,7 +122,7 @@ static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned s
);
}
-static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __outbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; outsb"
@@ -131,7 +131,7 @@ static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned s
);
}
-static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __outwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; outsw"
@@ -140,7 +140,7 @@ static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned s
);
}
-static __inline__ __attribute__((always_inline)) void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __outdwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; outsl"
@@ -525,7 +525,7 @@ static __inline__ __attribute__((always_inline)) void __lidt(void *Source)
}
static __inline__ __attribute__((always_inline)) void
-__writefsbyte(const unsigned long Offset, const unsigned char Data)
+__writefsbyte(const unsigned long Offset, const uint8_t Data)
{
__asm__ ("movb %[Data], %%fs:%a[Offset]"
:
@@ -533,7 +533,7 @@ __writefsbyte(const unsigned long Offset, const unsigned char Data)
}
static __inline__ __attribute__((always_inline)) void
-__writefsword(const unsigned long Offset, const unsigned short Data)
+__writefsword(const unsigned long Offset, const uint16_t Data)
{
__asm__ ("movw %[Data], %%fs:%a[Offset]"
:
@@ -541,14 +541,14 @@ __writefsword(const unsigned long Offset, const unsigned short Data)
}
static __inline__ __attribute__((always_inline)) void
-__writefsdword(const unsigned long Offset, const unsigned long Data)
+__writefsdword(const unsigned long Offset, const uint32_t Data)
{
__asm__ ("movl %[Data], %%fs:%a[Offset]"
:
: [Offset] "ir" (Offset), [Data] "ir" (Data));
}
-static __inline__ __attribute__((always_inline)) unsigned char
+static __inline__ __attribute__((always_inline)) uint8_t
__readfsbyte(const unsigned long Offset)
{
unsigned char value;
@@ -558,7 +558,7 @@ __readfsbyte(const unsigned long Offset)
return value;
}
-static __inline__ __attribute__((always_inline)) unsigned short
+static __inline__ __attribute__((always_inline)) uint16_t
__readfsword(const unsigned long Offset)
{
unsigned short value;
@@ -568,11 +568,11 @@ __readfsword(const unsigned long Offset)
return value;
}
-static __inline__ __attribute__((always_inline)) unsigned long
+static __inline__ __attribute__((always_inline)) uint32_t
__readfsdword(unsigned long Offset)
{
unsigned long value;
- __asm__ ("movl %%fs:%a[Offset], %[value]"
+ __asm__ ("mov %%fs:%a[Offset], %[value]"
: [value] "=r" (value)
: [Offset] "ir" (Offset));
return value;
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c
index ae25a49dd9..4353c41c3e 100644
--- a/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c
+++ b/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c
@@ -83,8 +83,8 @@ AmdAgesaDispatcher (
IMAGE_ENTRY ImageEntry;
MODULE_ENTRY ModuleEntry;
DISPATCH_TABLE *Entry;
- UINT32 ImageStart;
- UINT32 ImageEnd;
+ UINTN ImageStart;
+ UINTN ImageEnd;
AMD_IMAGE_HEADER* AltImagePtr;
Status = AGESA_UNSUPPORTED;
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c
index b2accb2aaf..aa7c1b87b7 100644
--- a/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c
@@ -148,7 +148,7 @@ CopyHeapToTempRamAtPost (
//
// 0xC0000 ~ 0xFFFFF
//
- HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX4k_C0000 + (((AmdHeapRamAddress >> 16) & 0x3) * 2));
+ HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX4k_C0000 + ((((UINTN)AmdHeapRamAddress >> 16) & 0x3) * 2));
MsrData = AMD_MTRR_FIX4K_UC_DRAM;
LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
LibAmdMsrWrite ((HeapRamFixMtrr + 1), &MsrData, StdHeader);
@@ -156,7 +156,7 @@ CopyHeapToTempRamAtPost (
//
// 0x80000~0xBFFFF
//
- HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX16k_80000 + ((AmdHeapRamAddress >> 17) & 0x1));
+ HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX16k_80000 + (((UINTN)AmdHeapRamAddress >> 17) & 0x1));
MsrData = AMD_MTRR_FIX16K_UC_DRAM;
LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
} else {
@@ -165,7 +165,7 @@ CopyHeapToTempRamAtPost (
//
LibAmdMsrRead (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
MsrData = MsrData & (~(0xFF << (8 * ((AmdHeapRamAddress >> 16) & 0x7))));
- MsrData = MsrData | (AMD_MTRR_FIX64K_UC_DRAM << (8 * ((AmdHeapRamAddress >> 16) & 0x7)));
+ MsrData = MsrData | (AMD_MTRR_FIX64K_UC_DRAM << (8 * (((UINTN)AmdHeapRamAddress >> 16) & 0x7)));
LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
}
@@ -209,7 +209,7 @@ CopyHeapToTempRamAtPost (
TotalSize = sizeof (HEAP_MANAGER);
SizeOfNodeData = 0;
AlignTo16ByteInTempMem = 0;
- BaseAddressInCache = (UINT8 *) (UINT32)StdHeader->HeapBasePtr;
+ BaseAddressInCache = (UINT8 *) (UINTN)StdHeader->HeapBasePtr;
HeapManagerInCache = (HEAP_MANAGER *) BaseAddressInCache;
HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset;
HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
@@ -308,8 +308,8 @@ CopyHeapToMainRamAtPost (
TotalSize = sizeof (HEAP_MANAGER);
SizeOfNodeData = 0;
AlignTo16ByteInMainMem = 0;
- BaseAddressInTempMem = (UINT8 *)(UINT32) StdHeader->HeapBasePtr;
- HeapManagerInTempMem = (HEAP_MANAGER *)(UINT32) StdHeader->HeapBasePtr;
+ BaseAddressInTempMem = (UINT8 *)(UINTN) StdHeader->HeapBasePtr;
+ HeapManagerInTempMem = (HEAP_MANAGER *)(UINTN) StdHeader->HeapBasePtr;
HeapInTempMemOffset = HeapManagerInTempMem->FirstActiveBufferOffset;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset);
diff --git a/src/vendorcode/amd/agesa/f15/Makefile.inc b/src/vendorcode/amd/agesa/f15/Makefile.inc
index 94e3e434c1..88870b9541 100644
--- a/src/vendorcode/amd/agesa/f15/Makefile.inc
+++ b/src/vendorcode/amd/agesa/f15/Makefile.inc
@@ -59,15 +59,22 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/Mem
## AGESA need sse feature ##
CFLAGS_x86_32 += -msse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
+CFLAGS_x86_64 += -msse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
export AGESA_ROOT := $(AGESA_ROOT)
export AGESA_INC := $(AGESA_INC)
CPPFLAGS_x86_32 += $(AGESA_INC)
+CPPFLAGS_x86_64 += $(AGESA_INC)
+
#######################################################################
classes-y += libagesa
+ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
$(eval $(call create_class_compiler,libagesa,x86_32))
+else
+$(eval $(call create_class_compiler,libagesa,x86_64))
+endif
libagesa-y += Legacy/Proc/agesaCallouts.c
libagesa-y += Legacy/Proc/Dispatcher.c
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c
index f42c35da08..5698fb36eb 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c
@@ -156,7 +156,7 @@ HeapManagerInit (
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader);
- HeapBufferPtr = (UINT8 *)(UINT32) StdHeader->HeapBasePtr;
+ HeapBufferPtr = (UINT8 *)(UINTN) StdHeader->HeapBasePtr;
// Check whether the heap manager is already initialized
LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrData, StdHeader);
@@ -326,14 +326,14 @@ HeapAllocateBuffer (
// Check Heap database is valid
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// The base address in StdHeader is incorrect, get base address by itself
- BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader);
+ BaseAddress = (UINT8 *)(UINTN) HeapGetBaseAddress (StdHeader);
HeapManager = (HEAP_MANAGER *) BaseAddress;
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// Heap is not available, ASSERT here
ASSERT (FALSE);
return AGESA_ERROR;
}
- StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress;
+ StdHeader->HeapBasePtr = (UINTN)BaseAddress;
}
// Allocate
@@ -471,14 +471,14 @@ HeapDeallocateBuffer (
// Check Heap database is valid
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// The base address in StdHeader is incorrect, get base address by itself
- BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader);
+ BaseAddress = (UINT8 *)(UINTN) HeapGetBaseAddress (StdHeader);
HeapManager = (HEAP_MANAGER *) BaseAddress;
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// Heap is not available, ASSERT here
ASSERT (FALSE);
return AGESA_ERROR;
}
- StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress;
+ StdHeader->HeapBasePtr = (UINTN)BaseAddress;
}
OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET;
@@ -600,14 +600,14 @@ HeapLocateBuffer (
// Check Heap database is valid
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// The base address in StdHeader is incorrect, get base address by itself
- BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader);
+ BaseAddress = (UINT8 *)(UINTN) HeapGetBaseAddress (StdHeader);
HeapManager = (HEAP_MANAGER *) BaseAddress;
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// Heap is not available, ASSERT here
ASSERT (FALSE);
return AGESA_ERROR;
}
- StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress;
+ StdHeader->HeapBasePtr = (UINTN)BaseAddress;
}
OffsetOfCurrentNode = HeapManager->FirstActiveBufferOffset;
CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/Ids.h b/src/vendorcode/amd/agesa/f15tn/Include/Ids.h
index abbb6d4ef9..b2cf9f35e5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/Ids.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/Ids.h
@@ -840,7 +840,7 @@ typedef enum { //vv- for debug reference only
#define IDS_CALLOUT_POWER_PLAN_INIT 0x8D ///< The function data of IDS callout function of Override Power Plan Init
/// Function entry for HDT script to call
typedef struct _SCRIPT_FUNCTION {
- UINT32 FuncAddr; ///< Function address in ROM
+ UINTN FuncAddr; ///< Function address in ROM
CHAR8 FuncName[40]; ///< Function name
} SCRIPT_FUNCTION;
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h
index a60667f293..5fe172c6e3 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h
@@ -74,29 +74,29 @@ CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVE
#if (AGESA_ENTRY_INIT_POST == TRUE)
#include <mu.h>
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
- { (UINT32) /*(UINT64)*/ MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
- { (UINT32) /*(UINT64)*/ MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
- { (UINT32) /*(UINT64)*/ MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"}
+ { (UINTN) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
+ { (UINTN) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
+ { (UINTN) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"}
};
#elif (AGESA_ENTRY_INIT_RECOVERY == TRUE)
#include <mru.h>
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
- { (UINT32) (UINT64) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"},
- { (UINT32) (UINT64) MemRecURead1CL, "Read1Cl(BufferAddr,PhyAddrLo)"},
- { (UINT32) (UINT64) MemRecUFlushPattern, "Flush1Cl(PhyAddrLo)"}
+ { (UINTN) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"},
+ { (UINTN) MemRecURead1CL, "Read1Cl(BufferAddr,PhyAddrLo)"},
+ { (UINTN) MemRecUFlushPattern, "Flush1Cl(PhyAddrLo)"}
};
#else
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
- { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"},
- { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"},
- { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"}
+ { (UINTN) CommonReturnFalse, "DefRet()"},
+ { (UINTN) CommonReturnFalse, "DefRet()"},
+ { (UINTN) CommonReturnFalse, "DefRet()"}
};
#endif
#else
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
- { (UINT32) /*(UINT64)*/ CommonReturnFalse, "DefRet()"},
- { (UINT32) /*(UINT64)*/ CommonReturnFalse, "DefRet()"},
- { (UINT32) /*(UINT64)*/ CommonReturnFalse, "DefRet()"}
+ { (UINTN) CommonReturnFalse, "DefRet()"},
+ { (UINTN) CommonReturnFalse, "DefRet()"},
+ { (UINTN) CommonReturnFalse, "DefRet()"}
};
#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f15tn/Include/gcc-intrin.h
index 7d90f8bb5a..9ae45c3ee2 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/gcc-intrin.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/gcc-intrin.h
@@ -27,11 +27,11 @@
*/
#if defined (__GNUC__)
-
+#include <stdint.h>
/* I/O intrin functions. */
-static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned short Port)
+static __inline__ __attribute__((always_inline)) uint8_t __inbyte(uint16_t Port)
{
- unsigned char value;
+ uint8_t value;
__asm__ __volatile__ (
"in %1, %0"
@@ -42,9 +42,9 @@ static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned
return value;
}
-static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigned short Port)
+static __inline__ __attribute__((always_inline)) uint16_t __inword(uint16_t Port)
{
- unsigned short value;
+ uint16_t value;
__asm__ __volatile__ (
"in %1, %0"
@@ -55,9 +55,9 @@ static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigne
return value;
}
-static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigned short Port)
+static __inline__ __attribute__((always_inline)) uint32_t __indword(uint16_t Port)
{
- unsigned long value;
+ uint32_t value;
__asm__ __volatile__ (
"in %1, %0"
@@ -68,7 +68,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigne
}
-static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short Port,unsigned char Data)
+static __inline__ __attribute__((always_inline)) void __outbyte(uint16_t Port,uint8_t Data)
{
__asm__ __volatile__ (
"out %0, %1"
@@ -77,7 +77,7 @@ static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short P
);
}
-static __inline__ __attribute__((always_inline)) void __outword(unsigned short Port,unsigned short Data)
+static __inline__ __attribute__((always_inline)) void __outword(uint16_t Port,uint16_t Data)
{
__asm__ __volatile__ (
"out %0, %1"
@@ -86,7 +86,7 @@ static __inline__ __attribute__((always_inline)) void __outword(unsigned short P
);
}
-static __inline__ __attribute__((always_inline)) void __outdword(unsigned short Port,unsigned long Data)
+static __inline__ __attribute__((always_inline)) void __outdword(uint16_t Port,uint32_t Data)
{
__asm__ __volatile__ (
"out %0, %1"
@@ -95,7 +95,7 @@ static __inline__ __attribute__((always_inline)) void __outdword(unsigned short
);
}
-static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __inbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; insb"
@@ -104,7 +104,7 @@ static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned sh
);
}
-static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __inwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; insw"
@@ -113,7 +113,7 @@ static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned sh
);
}
-static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __indwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; insl"
@@ -122,7 +122,7 @@ static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned s
);
}
-static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __outbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; outsb"
@@ -131,7 +131,7 @@ static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned s
);
}
-static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __outwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; outsw"
@@ -140,7 +140,7 @@ static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned s
);
}
-static __inline__ __attribute__((always_inline)) void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __outdwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; outsl"
@@ -525,7 +525,7 @@ static __inline__ __attribute__((always_inline)) void __lidt(void *Source)
}
static __inline__ __attribute__((always_inline)) void
-__writefsbyte(const unsigned long Offset, const unsigned char Data)
+__writefsbyte(const unsigned long Offset, const uint8_t Data)
{
__asm__ ("movb %[Data], %%fs:%a[Offset]"
:
@@ -533,7 +533,7 @@ __writefsbyte(const unsigned long Offset, const unsigned char Data)
}
static __inline__ __attribute__((always_inline)) void
-__writefsword(const unsigned long Offset, const unsigned short Data)
+__writefsword(const unsigned long Offset, const uint16_t Data)
{
__asm__ ("movw %[Data], %%fs:%a[Offset]"
:
@@ -541,14 +541,14 @@ __writefsword(const unsigned long Offset, const unsigned short Data)
}
static __inline__ __attribute__((always_inline)) void
-__writefsdword(const unsigned long Offset, const unsigned long Data)
+__writefsdword(const unsigned long Offset, const uint32_t Data)
{
__asm__ ("movl %[Data], %%fs:%a[Offset]"
:
: [Offset] "ir" (Offset), [Data] "ir" (Data));
}
-static __inline__ __attribute__((always_inline)) unsigned char
+static __inline__ __attribute__((always_inline)) uint8_t
__readfsbyte(const unsigned long Offset)
{
unsigned char value;
@@ -558,7 +558,7 @@ __readfsbyte(const unsigned long Offset)
return value;
}
-static __inline__ __attribute__((always_inline)) unsigned short
+static __inline__ __attribute__((always_inline)) uint16_t
__readfsword(const unsigned long Offset)
{
unsigned short value;
@@ -568,11 +568,11 @@ __readfsword(const unsigned long Offset)
return value;
}
-static __inline__ __attribute__((always_inline)) unsigned long
+static __inline__ __attribute__((always_inline)) uint32_t
__readfsdword(unsigned long Offset)
{
unsigned long value;
- __asm__ ("movl %%fs:%a[Offset], %[value]"
+ __asm__ ("mov %%fs:%a[Offset], %[value]"
: [value] "=r" (value)
: [Offset] "ir" (Offset));
return value;
diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/Dispatcher.c
index b30770642d..4188f1b7be 100644
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/Dispatcher.c
+++ b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/Dispatcher.c
@@ -82,8 +82,8 @@ AmdAgesaDispatcher (
IMAGE_ENTRY ImageEntry;
MODULE_ENTRY ModuleEntry;
DISPATCH_TABLE *Entry;
- UINT32 ImageStart;
- UINT32 ImageEnd;
+ UINTN ImageStart;
+ UINTN ImageEnd;
CONST AMD_IMAGE_HEADER* AltImagePtr;
Status = AGESA_UNSUPPORTED;
diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c
index 1df58aa4c9..198b404f0f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c
+++ b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c
@@ -434,7 +434,7 @@ AgesaFchOemCallout (
IN VOID *FchData
)
{
- AGESA_STATUS Status; Status = AmdAgesaCallout(AGESA_FCH_OEM_CALLOUT, (UINT32)FchData, ((FCH_DATA_BLOCK *)FchData)->StdHeader); return Status; //return AGESA_UNSUPPORTED;
+ AGESA_STATUS Status; Status = AmdAgesaCallout(AGESA_FCH_OEM_CALLOUT, (UINTN)FchData, ((FCH_DATA_BLOCK *)FchData)->StdHeader); return Status; //return AGESA_UNSUPPORTED;
}
/*---------------------------------------------------------------------------------------*/
@@ -454,7 +454,7 @@ excel331 (
{
AGESA_STATUS Status;
- Status = AmdAgesaCallout (0x00028146ul , (UINT32)SocketIdModuleId, MemData);
+ Status = AmdAgesaCallout (0x00028146ul , SocketIdModuleId, MemData);
return Status;
}
diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c
index 7ed5f16b5c..ec17b95504 100644
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c
@@ -147,7 +147,7 @@ CopyHeapToTempRamAtPost (
//
// 0xC0000 ~ 0xFFFFF
//
- HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX4k_C0000 + (((AmdHeapRamAddress >> 16) & 0x3) * 2));
+ HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX4k_C0000 + ((((UINTN)AmdHeapRamAddress >> 16) & 0x3) * 2));
MsrData = AMD_MTRR_FIX4K_UC_DRAM;
LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
LibAmdMsrWrite ((HeapRamFixMtrr + 1), &MsrData, StdHeader);
@@ -155,7 +155,7 @@ CopyHeapToTempRamAtPost (
//
// 0x80000~0xBFFFF
//
- HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX16k_80000 + ((AmdHeapRamAddress >> 17) & 0x1));
+ HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX16k_80000 + (((UINTN)AmdHeapRamAddress >> 17) & 0x1));
MsrData = AMD_MTRR_FIX16K_UC_DRAM;
LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
} else {
@@ -164,7 +164,7 @@ CopyHeapToTempRamAtPost (
//
LibAmdMsrRead (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
MsrData = MsrData & (~(0xFF << (8 * ((AmdHeapRamAddress >> 16) & 0x7))));
- MsrData = MsrData | (AMD_MTRR_FIX64K_UC_DRAM << (8 * ((AmdHeapRamAddress >> 16) & 0x7)));
+ MsrData = MsrData | (AMD_MTRR_FIX64K_UC_DRAM << (8 * (((UINTN)AmdHeapRamAddress >> 16) & 0x7)));
LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
}
@@ -208,7 +208,7 @@ CopyHeapToTempRamAtPost (
TotalSize = sizeof (HEAP_MANAGER);
SizeOfNodeData = 0;
AlignTo16ByteInTempMem = 0;
- BaseAddressInCache = (UINT8 *) (UINT32)StdHeader->HeapBasePtr;
+ BaseAddressInCache = (UINT8 *) (UINTN)StdHeader->HeapBasePtr;
HeapManagerInCache = (HEAP_MANAGER *) BaseAddressInCache;
HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset;
HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
@@ -307,8 +307,8 @@ CopyHeapToMainRamAtPost (
TotalSize = sizeof (HEAP_MANAGER);
SizeOfNodeData = 0;
AlignTo16ByteInMainMem = 0;
- BaseAddressInTempMem = (UINT8 *)(UINT32) StdHeader->HeapBasePtr;
- HeapManagerInTempMem = (HEAP_MANAGER *)(UINT32) StdHeader->HeapBasePtr;
+ BaseAddressInTempMem = (UINT8 *)(UINTN) StdHeader->HeapBasePtr;
+ HeapManagerInTempMem = (HEAP_MANAGER *)(UINTN) StdHeader->HeapBasePtr;
HeapInTempMemOffset = HeapManagerInTempMem->FirstActiveBufferOffset;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset);
diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc
index 0de46b01d3..986fbc5a15 100644
--- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc
+++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc
@@ -77,15 +77,21 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Include/Library
AGESA_INC += -I$(src)/southbridge/amd/agesa/hudson
CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
+CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
export AGESA_ROOT := $(AGESA_ROOT)
export AGESA_INC := $(AGESA_INC)
CPPFLAGS_x86_32 += $(AGESA_INC)
+CPPFLAGS_x86_64 += $(AGESA_INC)
#######################################################################
classes-y += libagesa
+ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
$(eval $(call create_class_compiler,libagesa,x86_32))
+else
+$(eval $(call create_class_compiler,libagesa,x86_64))
+endif
libagesa-y += Legacy/Proc/Dispatcher.c
libagesa-y += Legacy/Proc/agesaCallouts.c
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c
index 2e454714d6..f28159363b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c
@@ -155,7 +155,7 @@ HeapManagerInit (
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader);
- HeapBufferPtr = (UINT8 *)(UINT32) StdHeader->HeapBasePtr;
+ HeapBufferPtr = (UINT8 *)(UINTN) StdHeader->HeapBasePtr;
// Check whether the heap manager is already initialized
LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrData, StdHeader);
@@ -325,14 +325,14 @@ HeapAllocateBuffer (
// Check Heap database is valid
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// The base address in StdHeader is incorrect, get base address by itself
- BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader);
+ BaseAddress = (UINT8 *)(UINTN) HeapGetBaseAddress (StdHeader);
HeapManager = (HEAP_MANAGER *) BaseAddress;
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// Heap is not available, ASSERT here
ASSERT (FALSE);
return AGESA_ERROR;
}
- StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress;
+ StdHeader->HeapBasePtr = (UINTN)BaseAddress;
}
// Allocate
@@ -470,14 +470,14 @@ HeapDeallocateBuffer (
// Check Heap database is valid
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// The base address in StdHeader is incorrect, get base address by itself
- BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader);
+ BaseAddress = (UINT8 *)(UINTN) HeapGetBaseAddress (StdHeader);
HeapManager = (HEAP_MANAGER *) BaseAddress;
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// Heap is not available, ASSERT here
ASSERT (FALSE);
return AGESA_ERROR;
}
- StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress;
+ StdHeader->HeapBasePtr = (UINTN)BaseAddress;
}
OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET;
@@ -599,14 +599,14 @@ HeapLocateBuffer (
// Check Heap database is valid
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// The base address in StdHeader is incorrect, get base address by itself
- BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader);
+ BaseAddress = (UINT8 *)(UINTN) HeapGetBaseAddress (StdHeader);
HeapManager = (HEAP_MANAGER *) BaseAddress;
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// Heap is not available, ASSERT here
ASSERT (FALSE);
return AGESA_ERROR;
}
- StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress;
+ StdHeader->HeapBasePtr = (UINTN)BaseAddress;
}
OffsetOfCurrentNode = HeapManager->FirstActiveBufferOffset;
CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3LateRestore.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3LateRestore.c
index fb8edd9835..2f23a7ab7e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3LateRestore.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3LateRestore.c
@@ -119,7 +119,7 @@ AmdS3LateRestore (
ASSERT (S3LateParams != NULL);
BufferPointer = (UINT8 *) S3LateParams->S3DataBlock.VolatileStorage;
- S3LateParams->StdHeader.HeapBasePtr = (UINT32) &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset];
+ S3LateParams->StdHeader.HeapBasePtr = (UINTN) &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset];
ASSERT (S3LateParams->StdHeader.HeapBasePtr != 0);
IDS_HDT_CONSOLE_INIT (&S3LateParams->StdHeader);
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfx.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfx.h
index 1a934eb916..ac3318ab95 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfx.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfx.h
@@ -125,7 +125,7 @@ typedef enum {
/// Graphics Platform Configuration
typedef struct {
- UINT32 StdHeader; ///< Standard Header TODO: Used to be PVOID
+ UINTN StdHeader; ///< Standard Header TODO: Used to be PVOID
PCI_ADDR GfxPciAddress; ///< Graphics PCI Address
UMA_INFO UmaInfo; ///< UMA Information
UINT32 GmmBase; ///< GMM Base
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h
index b25c50c7b3..e8194f8202 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h
@@ -355,7 +355,7 @@ typedef struct {
/// PCIe platform configuration info
typedef struct {
PCIe_DESCRIPTOR_HEADER Header; ///< Descrptor Header
- UINT32 StdHeader; ///< Standard configuration header TODO:Used to be PVOID
+ UINTN StdHeader; ///< Standard configuration header TODO:Used to be PVOID
UINT32 LinkReceiverDetectionPooling; ///< Receiver pooling detection time in us.
UINT32 LinkL0Pooling; ///< Pooling for link to get to L0 in us
UINT32 LinkGpioResetAssertionTime; ///< Gpio reset assertion time in us
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
index b822294573..8befb2cd5e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
@@ -183,7 +183,7 @@ GfxLocateConfigData (
IDS_ERROR_TRAP;
return AGESA_FATAL;
}
- (*Gfx)->StdHeader = /* (PVOID) */(UINT32) StdHeader;
+ (*Gfx)->StdHeader = /* (PVOID) */(UINTN)StdHeader;
return AGESA_SUCCESS;
}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
index 49fd4cb7de..f0fe7f86a5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
@@ -113,7 +113,7 @@ GfxConfigPostInterface (
Gfx->GfxControllerMode = GfxControllerLegacyBridgeMode;
Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 1, 5, 0, 0);
}
- Gfx->StdHeader = /* (PVOID) */(UINT32) StdHeader;
+ Gfx->StdHeader = /* (PVOID) */(UINTN) StdHeader;
Gfx->GnbHdAudio = PostParamsPtr->PlatformConfig.GnbHdAudio;
Gfx->AbmSupport = PostParamsPtr->PlatformConfig.AbmSupport;
Gfx->DynamicRefreshRate = PostParamsPtr->PlatformConfig.DynamicRefreshRate;
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
index 0719e5256e..f66fd9b419 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
@@ -432,7 +432,7 @@ PcieLocateConfigurationData (
IDS_ERROR_TRAP;
return AGESA_FATAL;
}
- (*Pcie)->StdHeader = /* (PVOID) */ (UINT32)StdHeader;
+ (*Pcie)->StdHeader = /* (PVOID) */ (UINTN)StdHeader;
PcieUpdateConfigurationData (*Pcie);
return AGESA_SUCCESS;
}
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/Ids.h b/src/vendorcode/amd/agesa/f16kb/Include/Ids.h
index 69bb6da0ff..53477cb866 100644
--- a/src/vendorcode/amd/agesa/f16kb/Include/Ids.h
+++ b/src/vendorcode/amd/agesa/f16kb/Include/Ids.h
@@ -888,7 +888,7 @@ typedef enum { //vv- for debug reference only
/// Function entry for HDT script to call
typedef struct _SCRIPT_FUNCTION {
- UINT32 FuncAddr; ///< Function address in ROM
+ UINTN FuncAddr; ///< Function address in ROM
CHAR8 FuncName[40]; ///< Function name
} SCRIPT_FUNCTION;
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionIdsInstall.h
index b5a566f522..fe875004a2 100644
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionIdsInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionIdsInstall.h
@@ -74,29 +74,29 @@ CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVE
#if (AGESA_ENTRY_INIT_POST == TRUE)
#include <mu.h>
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
- { (UINT32) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
- { (UINT32) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
- { (UINT32) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"}
+ { (UINTN) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
+ { (UINTN) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
+ { (UINTN) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"}
};
#elif (AGESA_ENTRY_INIT_RECOVERY == TRUE)
#include <mru.h>
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
- { (UINT32) (UINT64) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"},
- { (UINT32) (UINT64) MemRecURead1CL, "Read1Cl(BufferAddr,PhyAddrLo)"},
- { (UINT32) (UINT64) MemRecUFlushPattern, "Flush1Cl(PhyAddrLo)"}
+ { (UINTN) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"},
+ { (UINTN) MemRecURead1CL, "Read1Cl(BufferAddr,PhyAddrLo)"},
+ { (UINTN) MemRecUFlushPattern, "Flush1Cl(PhyAddrLo)"}
};
#else
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
- { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"},
- { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"},
- { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"}
+ { (UINTN) CommonReturnFalse, "DefRet()"},
+ { (UINTN) CommonReturnFalse, "DefRet()"},
+ { (UINTN) CommonReturnFalse, "DefRet()"}
};
#endif
#else
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
- { (UINT32) CommonReturnFalse, "DefRet()"},
- { (UINT32) CommonReturnFalse, "DefRet()"},
- { (UINT32) CommonReturnFalse, "DefRet()"}
+ { (UINTN) CommonReturnFalse, "DefRet()"},
+ { (UINTN) CommonReturnFalse, "DefRet()"},
+ { (UINTN) CommonReturnFalse, "DefRet()"}
};
#endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f16kb/Include/gcc-intrin.h
index 7d90f8bb5a..9ae45c3ee2 100644
--- a/src/vendorcode/amd/agesa/f16kb/Include/gcc-intrin.h
+++ b/src/vendorcode/amd/agesa/f16kb/Include/gcc-intrin.h
@@ -27,11 +27,11 @@
*/
#if defined (__GNUC__)
-
+#include <stdint.h>
/* I/O intrin functions. */
-static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned short Port)
+static __inline__ __attribute__((always_inline)) uint8_t __inbyte(uint16_t Port)
{
- unsigned char value;
+ uint8_t value;
__asm__ __volatile__ (
"in %1, %0"
@@ -42,9 +42,9 @@ static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned
return value;
}
-static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigned short Port)
+static __inline__ __attribute__((always_inline)) uint16_t __inword(uint16_t Port)
{
- unsigned short value;
+ uint16_t value;
__asm__ __volatile__ (
"in %1, %0"
@@ -55,9 +55,9 @@ static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigne
return value;
}
-static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigned short Port)
+static __inline__ __attribute__((always_inline)) uint32_t __indword(uint16_t Port)
{
- unsigned long value;
+ uint32_t value;
__asm__ __volatile__ (
"in %1, %0"
@@ -68,7 +68,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigne
}
-static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short Port,unsigned char Data)
+static __inline__ __attribute__((always_inline)) void __outbyte(uint16_t Port,uint8_t Data)
{
__asm__ __volatile__ (
"out %0, %1"
@@ -77,7 +77,7 @@ static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short P
);
}
-static __inline__ __attribute__((always_inline)) void __outword(unsigned short Port,unsigned short Data)
+static __inline__ __attribute__((always_inline)) void __outword(uint16_t Port,uint16_t Data)
{
__asm__ __volatile__ (
"out %0, %1"
@@ -86,7 +86,7 @@ static __inline__ __attribute__((always_inline)) void __outword(unsigned short P
);
}
-static __inline__ __attribute__((always_inline)) void __outdword(unsigned short Port,unsigned long Data)
+static __inline__ __attribute__((always_inline)) void __outdword(uint16_t Port,uint32_t Data)
{
__asm__ __volatile__ (
"out %0, %1"
@@ -95,7 +95,7 @@ static __inline__ __attribute__((always_inline)) void __outdword(unsigned short
);
}
-static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __inbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; insb"
@@ -104,7 +104,7 @@ static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned sh
);
}
-static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __inwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; insw"
@@ -113,7 +113,7 @@ static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned sh
);
}
-static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __indwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; insl"
@@ -122,7 +122,7 @@ static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned s
);
}
-static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __outbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; outsb"
@@ -131,7 +131,7 @@ static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned s
);
}
-static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __outwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; outsw"
@@ -140,7 +140,7 @@ static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned s
);
}
-static __inline__ __attribute__((always_inline)) void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __outdwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"rep ; outsl"
@@ -525,7 +525,7 @@ static __inline__ __attribute__((always_inline)) void __lidt(void *Source)
}
static __inline__ __attribute__((always_inline)) void
-__writefsbyte(const unsigned long Offset, const unsigned char Data)
+__writefsbyte(const unsigned long Offset, const uint8_t Data)
{
__asm__ ("movb %[Data], %%fs:%a[Offset]"
:
@@ -533,7 +533,7 @@ __writefsbyte(const unsigned long Offset, const unsigned char Data)
}
static __inline__ __attribute__((always_inline)) void
-__writefsword(const unsigned long Offset, const unsigned short Data)
+__writefsword(const unsigned long Offset, const uint16_t Data)
{
__asm__ ("movw %[Data], %%fs:%a[Offset]"
:
@@ -541,14 +541,14 @@ __writefsword(const unsigned long Offset, const unsigned short Data)
}
static __inline__ __attribute__((always_inline)) void
-__writefsdword(const unsigned long Offset, const unsigned long Data)
+__writefsdword(const unsigned long Offset, const uint32_t Data)
{
__asm__ ("movl %[Data], %%fs:%a[Offset]"
:
: [Offset] "ir" (Offset), [Data] "ir" (Data));
}
-static __inline__ __attribute__((always_inline)) unsigned char
+static __inline__ __attribute__((always_inline)) uint8_t
__readfsbyte(const unsigned long Offset)
{
unsigned char value;
@@ -558,7 +558,7 @@ __readfsbyte(const unsigned long Offset)
return value;
}
-static __inline__ __attribute__((always_inline)) unsigned short
+static __inline__ __attribute__((always_inline)) uint16_t
__readfsword(const unsigned long Offset)
{
unsigned short value;
@@ -568,11 +568,11 @@ __readfsword(const unsigned long Offset)
return value;
}
-static __inline__ __attribute__((always_inline)) unsigned long
+static __inline__ __attribute__((always_inline)) uint32_t
__readfsdword(unsigned long Offset)
{
unsigned long value;
- __asm__ ("movl %%fs:%a[Offset], %[value]"
+ __asm__ ("mov %%fs:%a[Offset], %[value]"
: [value] "=r" (value)
: [Offset] "ir" (Offset));
return value;
diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/Dispatcher.c
index 782a52376a..f41deda1d0 100644
--- a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/Dispatcher.c
+++ b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/Dispatcher.c
@@ -82,8 +82,8 @@ AmdAgesaDispatcher (
IMAGE_ENTRY ImageEntry;
MODULE_ENTRY ModuleEntry;
DISPATCH_TABLE *Entry;
- UINT32 ImageStart;
- UINT32 ImageEnd;
+ UINTN ImageStart;
+ UINTN ImageEnd;
CONST AMD_IMAGE_HEADER* AltImagePtr;
Status = AGESA_UNSUPPORTED;
@@ -104,7 +104,7 @@ AmdAgesaDispatcher (
// 2. Try next dispatcher if possible, and we have not already got status back
if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) {
- ModuleEntry = (MODULE_ENTRY) (UINT32) mCpuModuleID.NextBlock->ModuleDispatcher;
+ ModuleEntry = (MODULE_ENTRY) mCpuModuleID.NextBlock->ModuleDispatcher;
if (ModuleEntry != NULL) {
Status = (*ModuleEntry) (ConfigPtr);
}
@@ -116,10 +116,10 @@ AmdAgesaDispatcher (
ImageStart = ((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr;
ImageEnd = ImageStart + 4;
// Locate/test image base that matches this component
- AltImagePtr = LibAmdLocateImage ((VOID *) (UINT32)ImageStart, (VOID *) (UINT32)ImageEnd, 4096, (CHAR8 *) AGESA_ID);
+ AltImagePtr = LibAmdLocateImage ((VOID *)ImageStart, (VOID *)ImageEnd, 4096, (CHAR8 *) AGESA_ID);
if (AltImagePtr != NULL) {
//Invoke alternative Image
- ImageEntry = (IMAGE_ENTRY) ((UINT32) AltImagePtr + AltImagePtr->EntryPointAddress);
+ ImageEntry = (IMAGE_ENTRY) ((UINTN) AltImagePtr + AltImagePtr->EntryPointAddress);
Status = (*ImageEntry) (ConfigPtr);
}
}
diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/agesaCallouts.c b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/agesaCallouts.c
index 990c0a7894..c00619f06e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/agesaCallouts.c
+++ b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/agesaCallouts.c
@@ -436,7 +436,7 @@ AgesaFchOemCallout (
)
{
AGESA_STATUS Status;
- Status = AmdAgesaCallout(AGESA_FCH_OEM_CALLOUT, (UINT32)FchData, ((FCH_DATA_BLOCK *)FchData)->StdHeader);
+ Status = AmdAgesaCallout(AGESA_FCH_OEM_CALLOUT, (UINTN)FchData, ((FCH_DATA_BLOCK *)FchData)->StdHeader);
return Status;
}
diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c
index 7f03e13e7e..d282bdb48a 100644
--- a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c
@@ -212,7 +212,7 @@ CopyHeapToTempRamAtPost (
TotalSize = sizeof (HEAP_MANAGER);
SizeOfNodeData = 0;
AlignTo16ByteInTempMem = 0;
- BaseAddressInCache = (UINT8 *)(UINT32) StdHeader->HeapBasePtr;
+ BaseAddressInCache = (UINT8 *)(UINTN) StdHeader->HeapBasePtr;
HeapManagerInCache = (HEAP_MANAGER *) BaseAddressInCache;
HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset;
HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
@@ -315,8 +315,8 @@ CopyHeapToMainRamAtPost (
TotalSize = sizeof (HEAP_MANAGER);
SizeOfNodeData = 0;
AlignTo16ByteInMainMem = 0;
- BaseAddressInTempMem = (UINT8 *)(UINT32) StdHeader->HeapBasePtr;
- HeapManagerInTempMem = (HEAP_MANAGER *)(UINT32) StdHeader->HeapBasePtr;
+ BaseAddressInTempMem = (UINT8 *)(UINTN) StdHeader->HeapBasePtr;
+ HeapManagerInTempMem = (HEAP_MANAGER *)(UINTN) StdHeader->HeapBasePtr;
HeapInTempMemOffset = HeapManagerInTempMem->FirstActiveBufferOffset;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset);
diff --git a/src/vendorcode/amd/agesa/f16kb/Makefile.inc b/src/vendorcode/amd/agesa/f16kb/Makefile.inc
index 5ce7aee583..e2338026a4 100644
--- a/src/vendorcode/amd/agesa/f16kb/Makefile.inc
+++ b/src/vendorcode/amd/agesa/f16kb/Makefile.inc
@@ -79,8 +79,11 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Feat/RDWR2DTRAINING
AGESA_INC += -I$(src)/southbridge/amd/agesa/hudson
CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
+CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
+
export AGESA_ROOT := $(AGESA_ROOT)
export AGESA_INC := $(AGESA_INC)
CPPFLAGS_x86_32 += $(AGESA_INC)
+CPPFLAGS_x86_64 += $(AGESA_INC)
#######################################################################
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatureLeveling.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatureLeveling.c
index 6494c69407..60b1bddf36 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatureLeveling.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatureLeveling.c
@@ -261,5 +261,5 @@ GetGlobalCpuFeatureListAddress (
AddressValue = GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR;
- *Address = (UINT64 *)(UINT32)(AddressValue);
+ *Address = (UINT64 *)(UINTN)(AddressValue);
}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c
index 7feb3faee2..4b6128e245 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c
@@ -215,7 +215,7 @@ SaveDeviceContext (
UINT64 EndAddress;
VOID *OrMask;
- StartAddress = (UINT64)(UINT32) DeviceList;
+ StartAddress = (UINTN) DeviceList;
Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset;
@@ -279,7 +279,7 @@ SaveDeviceContext (
break;
}
}
- EndAddress = (UINT64)(UINT32) OrMask;
+ EndAddress = (UINTN) OrMask;
*ActualBufferSize = (UINT32) (EndAddress - StartAddress);
}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.c
index 605e0c4325..f1217a32c8 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.c
@@ -202,7 +202,7 @@ GetPstateGatherDataAddressAtPost (
AddressValue = P_STATE_DATA_GATHER_TEMP_ADDR;
- *Ptr = (UINT64 *)(UINT32)(AddressValue);
+ *Ptr = (UINT64 *)(UINTN)(AddressValue);
return AGESA_SUCCESS;
}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c
index 42a6afa10f..24ee886c98 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c
@@ -158,7 +158,7 @@ HeapManagerInit (
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader);
- HeapBufferPtr = (UINT8 *)(UINT32) StdHeader->HeapBasePtr;
+ HeapBufferPtr = (UINT8 *)(UINTN) StdHeader->HeapBasePtr;
// Check whether the heap manager is already initialized
LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrData, StdHeader);
@@ -328,14 +328,14 @@ HeapAllocateBuffer (
// Check Heap database is valid
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// The base address in StdHeader is incorrect, get base address by itself
- BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader);
+ BaseAddress = (UINT8 *)(UINTN) HeapGetBaseAddress (StdHeader);
HeapManager = (HEAP_MANAGER *) BaseAddress;
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// Heap is not available, ASSERT here
ASSERT (FALSE);
return AGESA_ERROR;
}
- StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress;
+ StdHeader->HeapBasePtr = (UINTN)BaseAddress;
}
// Allocate
@@ -473,14 +473,14 @@ HeapDeallocateBuffer (
// Check Heap database is valid
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// The base address in StdHeader is incorrect, get base address by itself
- BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader);
+ BaseAddress = (UINT8 *)(UINTN) HeapGetBaseAddress (StdHeader);
HeapManager = (HEAP_MANAGER *) BaseAddress;
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// Heap is not available, ASSERT here
ASSERT (FALSE);
return AGESA_ERROR;
}
- StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress;
+ StdHeader->HeapBasePtr = (UINTN)BaseAddress;
}
OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET;
@@ -602,14 +602,14 @@ HeapLocateBuffer (
// Check Heap database is valid
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// The base address in StdHeader is incorrect, get base address by itself
- BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader);
+ BaseAddress = (UINT8 *)(UINTN) HeapGetBaseAddress (StdHeader);
HeapManager = (HEAP_MANAGER *) BaseAddress;
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// Heap is not available, ASSERT here
ASSERT (FALSE);
return AGESA_ERROR;
}
- StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress;
+ StdHeader->HeapBasePtr = (UINTN)BaseAddress;
}
OffsetOfCurrentNode = HeapManager->FirstActiveBufferOffset;
CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3LateRestore.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3LateRestore.c
index 5b30e55e20..093ab970b3 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3LateRestore.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3LateRestore.c
@@ -119,7 +119,7 @@ AmdS3LateRestore (
ASSERT (S3LateParams != NULL);
BufferPointer = (UINT8 *) S3LateParams->S3DataBlock.VolatileStorage;
- S3LateParams->StdHeader.HeapBasePtr = (UINT32) &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset];
+ S3LateParams->StdHeader.HeapBasePtr = (UINTN) &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset];
ASSERT (S3LateParams->StdHeader.HeapBasePtr != 0);
IDS_HDT_CONSOLE_INIT (&S3LateParams->StdHeader);
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Gnb.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Gnb.h
index c01fd5ef98..8261a3d924 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Gnb.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Gnb.h
@@ -75,7 +75,7 @@
#define OFF 0
-#define PVOID UINT32
+#define PVOID UINTN
#define STRING_TO_UINT32(a, b, c, d) ((UINT32) ((d << 24) | (c << 16) | (b << 8) | a))
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c
index 66cf992243..aee94676e9 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c
@@ -189,8 +189,8 @@ GfxSamuInit (
// Load boot control structure
SamuBootControl = (SAMU_BOOT_CONTROL *)AlignedControlXBuffer;
SamuBootControl->BootControl = 0x3;
- SamuBootControl->KernelAddrLo = (UINT32) (AlignedPatchYBuffer);
- SamuBootControl->KernelAddrHi = 0; //(UINT32) ((((UINT64) AlignedPatchYBuffer) >> 32) & 0xFF);
+ SamuBootControl->KernelAddrLo = (UINTN)AlignedPatchYBuffer;
+ SamuBootControl->KernelAddrHi = ((((UINT64)(UINTN)AlignedPatchYBuffer) >> 32) & 0xFF);
if (SamuUseF1dPatch == TRUE) {
SamuBootControl->TweakSelect = 0xBB027E1F;
SamuBootControl->KeySelect = 0x8E174F83;
@@ -209,7 +209,7 @@ GfxSamuInit (
// Write (physical address of boot control structure)>>8 into SAM_SAB_INIT_TLB_CONFIG (Location X >> 8)
GMMx22008 = 0x4;
GnbRegisterWriteKB (GnbHandle, 0x12, 0x22008, &GMMx22008, 0, GnbLibGetHeader (Gfx));
- GMMx2200C = ((UINT32) ((UINT32) AlignedControlXBuffer)) >> 8;
+ GMMx2200C = ((UINTN) AlignedControlXBuffer) >> 8;
GnbRegisterWriteKB (GnbHandle, 0x12, 0x2200C, &GMMx2200C, 0, GnbLibGetHeader (Gfx));
// Write 0x0 to SAM_RST_HOST_SOFT_RESET
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.c b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.c
index bde0514528..d4d2685750 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.c
@@ -252,14 +252,14 @@ AmdIdsHdtOutInit (
HdtoutHeader.DataIndex = 0;
HdtoutHeader.PrintCtrl = HDTOUT_PRINTCTRL_ON;
HdtoutHeader.NumBreakpointUnit = 0;
- HdtoutHeader.FuncListAddr = (UINT32) IDS_FUNCLIST_ADDR;
+ HdtoutHeader.FuncListAddr = (UINTN)IDS_FUNCLIST_ADDR;
HdtoutHeader.StatusStr[0] = 0;
HdtoutHeader.OutBufferMode = HDTOUT_BUFFER_MODE_ON;
HdtoutHeader.EnableMask = 0;
HdtoutHeader.ConsoleFilter = IDS_DEBUG_PRINT_MASK;
// Trigger HDTOUT breakpoint to get inputs from script
- IdsOutPort (HDTOUT_INIT, (UINT32) &HdtoutHeader, 0);
+ IdsOutPort (HDTOUT_INIT, (UINTN) &HdtoutHeader, 0);
// Disable AP HDTOUT if set BspOnlyFlag
if (HdtoutHeader.BspOnlyFlag == HDTOUT_BSP_ONLY) {
if (!IsBsp (StdHeader, &IgnoreSts)) {
@@ -299,7 +299,7 @@ AmdIdsHdtOutInit (
} while ((HdtoutHeader.BufferSize & 0x8000) == 0);
// If the buffer have been successfully allocated?
if ((HdtoutHeader.BufferSize & 0x8000) == 0) {
- LibAmdWriteCpuReg (DR3_REG, (UINT32) AllocHeapParams.BufferPtr);
+ LibAmdWriteCpuReg (DR3_REG, (UINTN)AllocHeapParams.BufferPtr);
LibAmdMemCopy (AllocHeapParams.BufferPtr, &HdtoutHeader, sizeof (HdtoutHeader) - 2, StdHeader);
} else {
/// Clear DR3_REG
@@ -327,7 +327,7 @@ AmdIdsHdtOutBufferFlush (
if (AmdIdsHdtoutGetHeader (&HdtoutHeaderPtr, StdHeader)) {
if ((HdtoutHeaderPtr->PrintCtrl == HDTOUT_PRINTCTRL_ON) &&
(HdtoutHeaderPtr->OutBufferMode == HDTOUT_BUFFER_MODE_ON)) {
- IdsOutPort (HDTOUT_PRINT, (UINT32) HdtoutHeaderPtr->Data, HdtoutHeaderPtr->DataIndex);
+ IdsOutPort (HDTOUT_PRINT, (UINTN)HdtoutHeaderPtr->Data, HdtoutHeaderPtr->DataIndex);
HdtoutHeaderPtr->DataIndex = 0;
}
}
@@ -355,10 +355,10 @@ AmdIdsHdtOutExitCoreTask (
if (AmdIdsHdtoutGetHeader (&HdtoutHeaderPtr, StdHeader)) {
if ((HdtoutHeaderPtr->PrintCtrl == HDTOUT_PRINTCTRL_ON) &&
(HdtoutHeaderPtr->OutBufferMode == HDTOUT_BUFFER_MODE_ON)) {
- IdsOutPort (HDTOUT_PRINT, (UINT32) HdtoutHeaderPtr->Data, HdtoutHeaderPtr->DataIndex);
+ IdsOutPort (HDTOUT_PRINT, (UINTN)HdtoutHeaderPtr->Data, HdtoutHeaderPtr->DataIndex);
}
}
- IdsOutPort (HDTOUT_EXIT, (UINT32) HdtoutHeaderPtr, 0);
+ IdsOutPort (HDTOUT_EXIT, (UINTN)HdtoutHeaderPtr, 0);
AmdIdsHdtOutRegisterRestore (StdHeader);