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| author | Rui Zhou <zhourui@huaqin.corp-partner.google.com> | 2024-11-05 14:42:02 +0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-11-07 04:15:06 +0000 |
| commit | 77f6682b95f45716f7ccf8ac8f1fa569a118b6e7 (patch) | |
| tree | ed84d0d8015310262c4cfb1abb1d66323015d91d /src/superio/nuvoton/nct5104d | |
| parent | 7d8e105420c3d8fc7385cd9ad634fd4e130030b7 (diff) | |
mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
The previous GPIO config will cause the SSD device to not be recognized. Based on schematics NB7559_MB_SCH_V1_2024_1010.pdf. So we adjust the position of the enable and reset pins.
BUG=b:374629673
BRANCH=None
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. power on proto board successfully
Change-Id: Idb36f67206450612655cb3efd3cce240475ef3ab
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/superio/nuvoton/nct5104d')
0 files changed, 0 insertions, 0 deletions