diff options
| author | Rui Zhou <zhourui@huaqin.corp-partner.google.com> | 2024-11-05 14:42:02 +0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-11-07 04:15:06 +0000 |
| commit | 77f6682b95f45716f7ccf8ac8f1fa569a118b6e7 (patch) | |
| tree | ed84d0d8015310262c4cfb1abb1d66323015d91d | |
| parent | 7d8e105420c3d8fc7385cd9ad634fd4e130030b7 (diff) | |
mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
The previous GPIO config will cause the SSD device to not be recognized. Based on schematics NB7559_MB_SCH_V1_2024_1010.pdf. So we adjust the position of the enable and reset pins.
BUG=b:374629673
BRANCH=None
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. power on proto board successfully
Change-Id: Idb36f67206450612655cb3efd3cce240475ef3ab
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
| -rw-r--r-- | src/mainboard/google/brya/variants/rull/gpio.c | 15 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/rull/overridetree.cb | 11 |
2 files changed, 17 insertions, 9 deletions
diff --git a/src/mainboard/google/brya/variants/rull/gpio.c b/src/mainboard/google/brya/variants/rull/gpio.c index 13d64690d8..c78ad40a63 100644 --- a/src/mainboard/google/brya/variants/rull/gpio.c +++ b/src/mainboard/google/brya/variants/rull/gpio.c @@ -23,8 +23,6 @@ static const struct pad_config override_gpio_table[] = { /* A22 : GPP_A22 ==> NC */ PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG), - /* B4 : I2C2_SDA ==> SSD1_RST_L */ - PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), /* B5 : I2C2_SDA ==> NA */ PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG), /* B6 : I2C2_SCL ==> NA */ @@ -32,14 +30,18 @@ static const struct pad_config override_gpio_table[] = { /* B11 : NC ==> EN_PP3300_WLAN_X*/ PAD_CFG_GPO(GPP_B11, 0, DEEP), + /* D11 : EN_PP1800_WCAM_X ==> EN_PP3300_SSD_X */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* B4 : SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* D3 : ISH_GP3 ==> NA */ PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), /* D6 : WWAN_PWR_ENABLE ==> PCIE_REFCLK_SSD1_REQ_N */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* D8 : SRCCLKREQ3# ==> NC */ PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG), - /* D11 : EN_PP1800_WCAM_X ==> EN_PP3300_SSD_X */ - PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* D13 : EN_PP1800_WCAM_X ==> NA */ PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), /* D15 : EN_PP2800_WCAM_X ==> NA */ @@ -105,6 +107,11 @@ static const struct pad_config override_gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* B4 : I2C2_SDA ==> SSD1_RST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* D11 : EN_PP1800_WCAM_X ==> EN_PP3300_SSD_X */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), diff --git a/src/mainboard/google/brya/variants/rull/overridetree.cb b/src/mainboard/google/brya/variants/rull/overridetree.cb index d91a7aaaae..1896d94638 100644 --- a/src/mainboard/google/brya/variants/rull/overridetree.cb +++ b/src/mainboard/google/brya/variants/rull/overridetree.cb @@ -405,13 +405,14 @@ chip soc/intel/alderlake }" chip soc/intel/common/block/pcie/rtd3 # enable_gpio is EN_PP3300_SSD - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D11)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" register "srcclk_pin" = "1" - device generic 0 on end + device generic 0 on + probe STORAGE STORAGE_NVME + probe unprovisioned + end end - probe STORAGE STORAGE_NVME - probe unprovisioned end device ref emmc on probe STORAGE STORAGE_EMMC |