summaryrefslogtreecommitdiff
path: root/src/southbridge
diff options
context:
space:
mode:
authorJohnny Lin <johnny_lin@wiwynn.com>2023-01-16 11:42:35 +0800
committerDavid Hendricks <david.hendricks@gmail.com>2023-01-23 01:00:12 +0000
commit337f8a173321a397011465644feaa613891e8478 (patch)
tree280c7f0d7f7fa29535d8dcf0fbb3f22cef361886 /src/southbridge
parent80b1fa3332a8022a45bfeacb129a2b171cc30135 (diff)
soc/intel/xeon_sp: Remove NO_FSP_TEMP_RAM_EXIT from common config
For SPR-SP FSP MRC cache, NO_FSP_TEMP_RAM_EXIT should not be selected. Change-Id: I63101f286809d6cebb9a7d74443446cb3fe650c4 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71928 Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions