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authorKyösti Mälkki <kyosti.malkki@gmail.com>2021-06-06 08:28:16 +0300
committerFelix Held <felix-coreboot@felixheld.de>2021-10-22 14:18:45 +0000
commitc25ecb54436ab1b20f99db363f71fa13fd3e9831 (patch)
tree03413e23f58c0dcfcabdcd31b66287c95e78551e /src/southbridge/intel/i82801jx/Kconfig
parent4bab5691cc9369ea3dd8427d1f54a7ae470a35f8 (diff)
arch/x86/ioapic: Select IOAPIC with SMP
For coreboot proper, I/O APIC programming is not really required, except for the APIC ID field. We generally do not guard the related set_ioapic_id() or setup_ioapic() calls with CONFIG(IOAPIC). In practice it's something one cannot leave unselected, but maintain the Kconfig for the time being. Change-Id: I6e83efafcf6e81d1dfd433fab1e89024d984cc1f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/southbridge/intel/i82801jx/Kconfig')
-rw-r--r--src/southbridge/intel/i82801jx/Kconfig1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig
index fa469ce0ae..197ed523f6 100644
--- a/src/southbridge/intel/i82801jx/Kconfig
+++ b/src/southbridge/intel/i82801jx/Kconfig
@@ -9,7 +9,6 @@ config SOUTHBRIDGE_INTEL_I82801JX
select HAVE_SMI_HANDLER
select HAVE_USBDEBUG_OPTIONS
select INTEL_DESCRIPTOR_MODE_CAPABLE
- select IOAPIC
select SOUTHBRIDGE_INTEL_COMMON_GPIO
select SOUTHBRIDGE_INTEL_COMMON_PMBASE
select SOUTHBRIDGE_INTEL_COMMON_PMCLIB