From c25ecb54436ab1b20f99db363f71fa13fd3e9831 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 6 Jun 2021 08:28:16 +0300 Subject: arch/x86/ioapic: Select IOAPIC with SMP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For coreboot proper, I/O APIC programming is not really required, except for the APIC ID field. We generally do not guard the related set_ioapic_id() or setup_ioapic() calls with CONFIG(IOAPIC). In practice it's something one cannot leave unselected, but maintain the Kconfig for the time being. Change-Id: I6e83efafcf6e81d1dfd433fab1e89024d984cc1f Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/55291 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Raul Rangel --- src/southbridge/intel/i82801jx/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'src/southbridge/intel/i82801jx/Kconfig') diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index fa469ce0ae..197ed523f6 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -9,7 +9,6 @@ config SOUTHBRIDGE_INTEL_I82801JX select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS select INTEL_DESCRIPTOR_MODE_CAPABLE - select IOAPIC select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_PMCLIB -- cgit v1.2.3