diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-27 09:41:02 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-12 09:22:18 +0000 |
| commit | d2b9ec13622d34714b4ecf8b9daf53b32665d3d7 (patch) | |
| tree | 205a6f66c9ece4b05010b0c33a8c174bc954249c /src/southbridge/intel/fsp_rangeley | |
| parent | a9a1913d4d3f27f681b6ef980f064b57da8c1a68 (diff) | |
src: Remove unneeded include "{arch,cpu}/cpu.h"
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley')
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/lpc.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/romstage.c | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/romstage.h | 1 |
3 files changed, 1 insertions, 3 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 88cc73fa82..726fd3b9ef 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -25,7 +25,7 @@ #include <arch/io.h> #include <arch/ioapic.h> #include <arch/acpi.h> -#include <cpu/cpu.h> +#include <arch/cpu.h> #include <elog.h> #include <string.h> #include <cbmem.h> diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 2f598d88d5..270e7ce3db 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -31,7 +31,6 @@ #include "southbridge/intel/fsp_rangeley/soc.h" #include "southbridge/intel/fsp_rangeley/gpio.h" #include "southbridge/intel/fsp_rangeley/romstage.h" -#include <arch/cpu.h> #include <cpu/x86/msr.h> #include "gpio.h" diff --git a/src/southbridge/intel/fsp_rangeley/romstage.h b/src/southbridge/intel/fsp_rangeley/romstage.h index 57f1899367..261357746f 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.h +++ b/src/southbridge/intel/fsp_rangeley/romstage.h @@ -22,7 +22,6 @@ #endif #include <stdint.h> -#include <arch/cpu.h> #include <drivers/intel/fsp1_0/fsp_util.h> void main(FSP_INFO_HEADER *fsp_info_header); |