diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2018-10-01 19:17:11 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-22 08:35:25 +0000 |
| commit | 45022ae056cdbf58429b77daf2da176306312801 (patch) | |
| tree | 4218666e3c14e41232778c4ceff301292b3c61d9 /src/southbridge/intel/fsp_i89xx/romstage.c | |
| parent | 33fcaf91ff825ad0adf0a2a483e6a296ed4e0e31 (diff) | |
intel: Use CF9 reset (part 1)
Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to
perform a "system reset" in their hard_reset() implementation. Replace
all duplicate CF9 reset implementations for these platforms.
Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel/fsp_i89xx/romstage.c')
| -rw-r--r-- | src/southbridge/intel/fsp_i89xx/romstage.c | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c index afe00bd6aa..268ea668ba 100644 --- a/src/southbridge/intel/fsp_i89xx/romstage.c +++ b/src/southbridge/intel/fsp_i89xx/romstage.c @@ -31,7 +31,7 @@ #include <console/usb.h> #include <halt.h> #include <program_loading.h> -#include <reset.h> +#include <cf9_reset.h> #include <drivers/intel/fsp1_0/fsp_util.h> #include <northbridge/intel/fsp_sandybridge/northbridge.h> #include <northbridge/intel/fsp_sandybridge/raminit.h> @@ -42,12 +42,6 @@ #include "pch.h" #include "romstage.h" -static inline void reset_system(void) -{ - hard_reset(); - halt(); -} - static void pch_enable_lpc(void) { pci_devfn_t dev = PCH_LPC_DEV; @@ -202,7 +196,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { cbmem_was_initted = !cbmem_recovery(0); if (cbmem_was_initted) { - reset_system(); + system_reset(); } /* Save the HOB pointer in CBMEM to be used in ramstage. */ |