diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2015-05-31 20:28:17 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-20 16:35:47 +0100 |
| commit | d2e8f6ad33c750853844c5674d1a1a926ad7d93a (patch) | |
| tree | fde712f291c184ad279f9c1f4634b49d07eac867 /src/southbridge/amd/agesa/hudson/pci_devs.h | |
| parent | e536a4d91697fc49d865dfa5065d2cbb31cbc03f (diff) | |
southbridge/amd: add support for Bolton FCH
The Bolton FCH needs different firmware files than the Hudson FCH.
A small patch to vendorcode is probably needed to make the XHCI controller work.
XHCI_DEVID in pci_devs.h is probably wrong for Hudson.
Change-Id: Ib81c0881979edcde717217dc89d8af415520d7e5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/9623
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/agesa/hudson/pci_devs.h')
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/pci_devs.h | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/southbridge/amd/agesa/hudson/pci_devs.h b/src/southbridge/amd/agesa/hudson/pci_devs.h index b365c74bb0..d335fc2ec5 100644 --- a/src/southbridge/amd/agesa/hudson/pci_devs.h +++ b/src/southbridge/amd/agesa/hudson/pci_devs.h @@ -24,6 +24,13 @@ #define XHCI_DEVID 0x7814 #define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) +#define XHCI2_DEV 0x10 +#define XHCI2_FUNC 1 +#define XHCI2_DEVID 0x7814 +#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC) +#endif + /* SATA */ #define SATA_DEV 0x11 #define SATA_FUNC 0 @@ -66,7 +73,7 @@ #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) /* IDE */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #define IDE_DEV 0x14 #define IDE_FUNC 1 # define IDE_DEVID 0x780C @@ -99,7 +106,7 @@ #define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC) /* PCIe Ports */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #define SB_PCIE_DEV 0x15 #define SB_PCIE_PORT1_FUNC 0 #define SB_PCIE_PORT2_FUNC 1 |