diff options
| author | Kevin Paul Herbert <kph@meraki.net> | 2014-12-24 18:43:20 -0800 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-15 08:50:22 +0100 |
| commit | bde6d309dfafe58732ec46314a2d4c08974b62d4 (patch) | |
| tree | 17ba00565487ddfbb5759c96adfbb3fffe2a4550 /src/southbridge/amd/agesa/hudson/imc.c | |
| parent | 4b10dec1a66122b515b2191f823d7fd379ec655f (diff) | |
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/amd/agesa/hudson/imc.c')
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/imc.c | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c index d706292ab7..65b31fd828 100644 --- a/src/southbridge/amd/agesa/hudson/imc.c +++ b/src/southbridge/amd/agesa/hudson/imc.c @@ -27,22 +27,24 @@ #include <Proc/Fch/Common/FchCommonCfg.h> #include <Proc/Fch/FchPlatform.h> +#define VACPI_MMIO_VBASE ((u8 *)ACPI_MMIO_BASE) + void imc_reg_init(void) { /* Init Power Management Block 2 (PM2) Registers. * Check BKDG for AMD Family 16h for details. */ - write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x00, 0x06); - write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x01, 0x06); - write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x02, 0xf7); - write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x03, 0xff); - write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x04, 0xff); + write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x00, 0x06); + write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x01, 0x06); + write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x02, 0xf7); + write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x03, 0xff); + write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x04, 0xff); #if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE - write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x10, 0x06); - write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x11, 0x06); - write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x12, 0xf7); - write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x13, 0xff); - write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x14, 0xff); + write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x10, 0x06); + write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x11, 0x06); + write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x12, 0xf7); + write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x13, 0xff); + write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x14, 0xff); #endif #if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE |