x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer

On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.

Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)

6 files changed, 25 insertions, 23 deletions

diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
index 258267ed04..5463d2bb90 100644
--- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
+++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
@@ -40,7 +40,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
 
 void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
 {
-	u32 base_regs = pci_ehci_base_regs(dev);
+	u8 *base_regs = pci_ehci_base_regs(dev);
 	u32 reg32;
 
 	/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
@@ -48,7 +48,7 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
 	reg32 &= ~(0xf << 28);
 	reg32 |= (port << 28);
 	reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
-	write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
+	write32(base_regs + (DEBUGPORT_MISC_CONTROL / sizeof(u32)), reg32);
 }
 
 
diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c
index fd2c268a23..4ddfea2b8e 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.c
+++ b/src/southbridge/amd/agesa/hudson/hudson.c
@@ -40,22 +40,22 @@
 
 void pm_write8(u8 reg, u8 value)
 {
-	write8(PM_MMIO_BASE + reg, value);
+	write8((void *)(PM_MMIO_BASE + reg), value);
 }
 
 u8 pm_read8(u8 reg)
 {
-	return read8(PM_MMIO_BASE + reg);
+	return read8((void *)(PM_MMIO_BASE + reg));
 }
 
 void pm_write16(u8 reg, u16 value)
 {
-	write16(PM_MMIO_BASE + reg, value);
+	write16((void *)(PM_MMIO_BASE + reg), value);
 }
 
 u16 pm_read16(u16 reg)
 {
-	return read16(PM_MMIO_BASE + reg);
+	return read16((void *)(PM_MMIO_BASE + reg));
 }
 
 #define PM_REG_USB_ENABLE	0xef
diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c
index d706292ab7..65b31fd828 100644
--- a/src/southbridge/amd/agesa/hudson/imc.c
+++ b/src/southbridge/amd/agesa/hudson/imc.c
@@ -27,22 +27,24 @@
 #include <Proc/Fch/Common/FchCommonCfg.h>
 #include <Proc/Fch/FchPlatform.h>
 
+#define VACPI_MMIO_VBASE ((u8 *)ACPI_MMIO_BASE)
+
 void imc_reg_init(void)
 {
 	/* Init Power Management Block 2 (PM2) Registers.
 	 * Check BKDG for AMD Family 16h for details. */
-	write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x00, 0x06);
-	write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x01, 0x06);
-	write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x02, 0xf7);
-	write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x03, 0xff);
-	write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x04, 0xff);
+	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x00, 0x06);
+	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x01, 0x06);
+	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x02, 0xf7);
+	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x03, 0xff);
+	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x04, 0xff);
 
 #if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
-	write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x10, 0x06);
-	write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x11, 0x06);
-	write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x12, 0xf7);
-	write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x13, 0xff);
-	write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x14, 0xff);
+	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x10, 0x06);
+	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x11, 0x06);
+	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x12, 0xf7);
+	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x13, 0xff);
+	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x14, 0xff);
 #endif
 
 #if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c
index d6ca215a6a..bc6564d1ec 100644
--- a/src/southbridge/amd/agesa/hudson/sm.c
+++ b/src/southbridge/amd/agesa/hudson/sm.c
@@ -82,7 +82,7 @@
 
 static void sm_init(device_t dev)
 {
-	setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS);
+	setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
 }
 
 static int lsmbus_recv_byte(device_t dev)
diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h
index 53da00adfa..520c65fe51 100644
--- a/src/southbridge/amd/agesa/hudson/smi.h
+++ b/src/southbridge/amd/agesa/hudson/smi.h
@@ -36,22 +36,22 @@ enum smi_lvl {
 
 static inline uint32_t smi_read32(uint8_t offset)
 {
-	return read32(SMI_BASE + offset);
+	return read32((void *)(SMI_BASE + offset));
 }
 
 static inline void smi_write32(uint8_t offset, uint32_t value)
 {
-	write32(SMI_BASE + offset, value);
+	write32((void *)(SMI_BASE + offset), value);
 }
 
 static inline uint16_t smi_read16(uint8_t offset)
 {
-	return read16(SMI_BASE + offset);
+	return read16((void *)(SMI_BASE + offset));
 }
 
 static inline void smi_write16(uint8_t offset, uint16_t value)
 {
-	write16(SMI_BASE + offset, value);
+	write16((void *)(SMI_BASE + offset), value);
 }
 
 void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);
diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c
index 735ab7ed16..fe6ea507e3 100644
--- a/src/southbridge/amd/agesa/hudson/spi.c
+++ b/src/southbridge/amd/agesa/hudson/spi.c
@@ -53,12 +53,12 @@ static u32 spibar;
 
 static inline uint8_t spi_read(uint8_t reg)
 {
-	return read8(spibar + reg);
+	return read8((void *)(spibar + reg));
 }
 
 static inline void spi_write(uint8_t reg, uint8_t val)
 {
-	write8(spibar + reg, val);
+	write8((void *)(spibar + reg), val);
 }
 
 static void reset_internal_fifo_pointer(void)