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authorFelix Held <felix-coreboot@felixheld.de>2024-02-01 20:50:11 +0100
committerFelix Held <felix-coreboot@felixheld.de>2024-02-02 20:37:50 +0000
commit953d7d979b9d358636df0504d18f1ed5d6fdc265 (patch)
tree79ec084d2515cef6add57fb03beee0646e00ca7f /src/soc
parent5dc83818b8d14950bf10451f75901b52108b0697 (diff)
soc/amd/phoenix/fch: only init ACPI IO ports in FSP case
Since openSIL configures the APCI IO port addresses, coreboot should not overwrite them. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If10e5a9f52ab313ad1afebd7f9e722994d48b0a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80297 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/phoenix/fch.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/src/soc/amd/phoenix/fch.c b/src/soc/amd/phoenix/fch.c
index e9bc80a505..1e03cda105 100644
--- a/src/soc/amd/phoenix/fch.c
+++ b/src/soc/amd/phoenix/fch.c
@@ -89,10 +89,12 @@ static void fch_init_acpi_ports(void)
* ACPI tables are generated. Enable these ports indiscriminately.
*/
- pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK);
- pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK);
- pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
- pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
+ if (CONFIG(PLATFORM_USES_FSP2_0)) {
+ pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK);
+ pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK);
+ pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
+ pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
+ }
if (CONFIG(HAVE_SMI_HANDLER)) {
/* APMC - SMI Command Port */