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authorSubrata Banik <subrata.banik@intel.com>2017-08-10 14:22:43 +0530
committerAaron Durbin <adurbin@chromium.org>2017-08-16 23:30:12 +0000
commit3e550446452a8dad886e02d708aa325266b65663 (patch)
treeba652cb68ad54c762cb0b4723ab755dc0b880a93 /src/soc
parentb27aa82a50cde46d43ea0dd6ad797eb9c248e6c8 (diff)
soc/intel/cannonlake: Add proper support to enable UART2 in 16550 mode
Need to perform a dummy read in order to activate LPSS UART's 16550 8-bit compatibility mode. TEST=Able to get serial log in both 32 bit and 8 bit mode through LPSS UART2 based on CONFIG_DRIVERS_UART_8250MEM_32 and CONFIG_DRIVERS_UART_8250MEM selection. Change-Id: Ief58fdcb8a91f9951a48c3bd7490b1c7fee17e48 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/cannonlake/uart.c17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c
index cb1273d399..af224eb9ce 100644
--- a/src/soc/intel/cannonlake/uart.c
+++ b/src/soc/intel/cannonlake/uart.c
@@ -27,6 +27,10 @@
#include <soc/pcr_ids.h>
#include <soc/iomap.h>
+/* Serial IO UART controller legacy mode */
+#define PCR_SERIAL_IO_GPPRVRW7 0x618
+#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx))
+
static const struct port {
struct pad_config pads[2]; /* just TX and RX */
device_t dev;
@@ -55,6 +59,19 @@ void pch_uart_init(void)
base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
uart_common_init(p->dev, base);
+
+ /* Put UART2 in byte access mode for 16550 compatibility */
+ if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) {
+ pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
+ PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));
+
+ /*
+ * Dummy read after setting any of GPPRVRW7.
+ * Required for UART 16550 8-bit Legacy mode to become active
+ */
+ lpss_clk_read(base);
+ }
+
gpio_configure_pads(p->pads, ARRAY_SIZE(p->pads));
}