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authorSridhar Siricilla <sridhar.siricilla@intel.com>2022-12-08 11:40:02 +0530
committerSridhar Siricilla <sridhar.siricilla@intel.com>2022-12-21 09:35:42 +0000
commit1e638ba27ca3ef6d9ddf204af036744ab90873df (patch)
tree0be4147725ae67c1756dcd775f6fd0bff0f007fc /src/soc/ucb
parent1542d16173b4ac0eed414f135a2f61b073386271 (diff)
soc/intel/meteorlake/romstage: Rewrite the if condition
The patch rewrites `if` condition by connecting two different conditions using the logical and(&&) operator without changing the semantics to improve the code readability. TEST=Build the code for Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I8c912f694d801768b1553f33de78f01215be7f0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/70479 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Diffstat (limited to 'src/soc/ucb')
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