diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2022-12-08 11:40:02 +0530 |
|---|---|---|
| committer | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2022-12-21 09:35:42 +0000 |
| commit | 1e638ba27ca3ef6d9ddf204af036744ab90873df (patch) | |
| tree | 0be4147725ae67c1756dcd775f6fd0bff0f007fc /src | |
| parent | 1542d16173b4ac0eed414f135a2f61b073386271 (diff) | |
soc/intel/meteorlake/romstage: Rewrite the if condition
The patch rewrites `if` condition by connecting two different conditions
using the logical and(&&) operator without changing the semantics to
improve the code readability.
TEST=Build the code for Rex
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I8c912f694d801768b1553f33de78f01215be7f0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70479
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/meteorlake/romstage/romstage.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c index ba0079ca09..35f9368b5a 100644 --- a/src/soc/intel/meteorlake/romstage/romstage.c +++ b/src/soc/intel/meteorlake/romstage/romstage.c @@ -130,12 +130,10 @@ void mainboard_romstage_entry(void) cse_init(HECI1_BASE_ADDRESS); s3wake = pmc_fill_power_state(ps) == ACPI_S3; - if (!s3wake) { - if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) { - timestamp_add_now(TS_CSE_FW_SYNC_START); - cse_fw_sync(); - timestamp_add_now(TS_CSE_FW_SYNC_END); - } + if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) { + timestamp_add_now(TS_CSE_FW_SYNC_START); + cse_fw_sync(); + timestamp_add_now(TS_CSE_FW_SYNC_END); } /* |