arm(64): Globally replace writel(v, a) with write32(a, v)

This patch is a raw application of the following spatch to src/:

@@
expression A, V;
@@
- writel(V, A)
+ write32(A, V)
@@
expression A, V;
@@
- writew(V, A)
+ write16(A, V)
@@
expression A, V;
@@
- writeb(V, A)
+ write8(A, V)
@@
expression A;
@@
- readl(A)
+ read32(A)
@@
expression A;
@@
- readb(A)
+ read8(A)

BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)

Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6
Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254864
Reviewed-on: http://review.coreboot.org/9836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

17 files changed, 424 insertions, 418 deletions

diff --git a/src/soc/nvidia/tegra132/addressmap.c b/src/soc/nvidia/tegra132/addressmap.c
index 377d083e02..5940db7067 100644
--- a/src/soc/nvidia/tegra132/addressmap.c
+++ b/src/soc/nvidia/tegra132/addressmap.c
@@ -187,9 +187,9 @@ void trustzone_region_init(void)
 		return;
 
 	/* Set the carveout region. */
-	writel(tz_base_mib << 20, &mc->security_cfg0);
-	writel(tz_size_mib, &mc->security_cfg1);
+	write32(&mc->security_cfg0, tz_base_mib << 20);
+	write32(&mc->security_cfg1, tz_size_mib);
 
 	/* Enable SMMU translations */
-	writel(MC_SMMU_CONFIG_ENABLE, &mc->smmu_config);
+	write32(&mc->smmu_config, MC_SMMU_CONFIG_ENABLE);
 }
diff --git a/src/soc/nvidia/tegra132/bootblock.c b/src/soc/nvidia/tegra132/bootblock.c
index 6fd36eb2bd..317ab4a1f6 100644
--- a/src/soc/nvidia/tegra132/bootblock.c
+++ b/src/soc/nvidia/tegra132/bootblock.c
@@ -46,7 +46,7 @@ static void save_odmdata(void)
 	bct_offset = read32((void *)(TEGRA_SRAM_BASE + BCT_OFFSET_IN_BIT));
 	if (bct_offset > TEGRA_SRAM_BASE && bct_offset < TEGRA_SRAM_MAX) {
 		odmdata = read32((void *)(bct_offset + ODMDATA_OFFSET_IN_BCT));
-		writel(odmdata, &pmc->odmdata);
+		write32(&pmc->odmdata, odmdata);
 	}
 }
 
diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c
index 1cc59add84..f9356a91bc 100644
--- a/src/soc/nvidia/tegra132/ccplex.c
+++ b/src/soc/nvidia/tegra132/ccplex.c
@@ -46,12 +46,12 @@ static int ccplex_start(void)
 	struct tegra_pmc_regs * const pmc = PMC_REGS;
 
 	/* Set the handshake bit to be knocked down. */
-	writel(handshake_mask, &pmc->scratch118);
+	write32(&pmc->scratch118, handshake_mask);
 
 	/* Assert nCXRSET[1] */
 	reg = read32(CLK_RST_REG(rst_cpu_cmplx_set));
 	reg |= cxreset1_mask;
-	writel(reg, CLK_RST_REG(rst_cpu_cmplx_set));
+	write32(CLK_RST_REG(rst_cpu_cmplx_set), reg);
 
 	stopwatch_init_msecs_expire(&sw, timeout_ms);
 	while (1) {
@@ -140,14 +140,14 @@ static void request_ram_repair(void)
 	/* Perform cluster 0 ram repair */
 	reg = read32(&flow->ram_repair);
 	reg |= req;
-	writel(reg, &flow->ram_repair);
+	write32(&flow->ram_repair, reg);
 	while ((read32(&flow->ram_repair) & sts) != sts)
 		;
 
 	/* Perform cluster 1 ram repair */
 	reg = read32(&flow->ram_repair_cluster1);
 	reg |= req;
-	writel(reg, &flow->ram_repair_cluster1);
+	write32(&flow->ram_repair_cluster1, reg);
 	while ((read32(&flow->ram_repair_cluster1) & sts) != sts)
 		;
 
@@ -169,11 +169,11 @@ void ccplex_cpu_prepare(void)
 static void start_common_clocks(void)
 {
 	/* Clear fast CPU partition reset. */
-	writel(CRC_RST_CPUG_CLR_NONCPU, CLK_RST_REG(rst_cpug_cmplx_clr));
+	write32(CLK_RST_REG(rst_cpug_cmplx_clr), CRC_RST_CPUG_CLR_NONCPU);
 
 	/* Clear reset of L2 and CoreSight components. */
-	writel(CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG,
-	       CLK_RST_REG(rst_cpug_cmplx_clr));
+	write32(CLK_RST_REG(rst_cpug_cmplx_clr),
+		CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG);
 }
 
 void ccplex_cpu_start(void *entry_addr)
diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c
index 4cd8a5886d..c13a086501 100644
--- a/src/soc/nvidia/tegra132/clock.c
+++ b/src/soc/nvidia/tegra132/clock.c
@@ -163,7 +163,7 @@ struct {
  */
 static u32 clock_get_osc_bits(void)
 {
-	return (readl(CLK_RST_REG(osc_ctrl)) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
+	return (read32(CLK_RST_REG(osc_ctrl)) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
 }
 
 int clock_get_osc_khz(void)
@@ -173,7 +173,7 @@ int clock_get_osc_khz(void)
 
 int clock_get_pll_input_khz(void)
 {
-	u32 osc_ctrl = readl(CLK_RST_REG(osc_ctrl));
+	u32 osc_ctrl = read32(CLK_RST_REG(osc_ctrl));
 	u32 osc_bits = (osc_ctrl & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
 	u32 pll_ref_div = (osc_ctrl & OSC_PREDIV_MASK) >> OSC_PREDIV_SHIFT;
 	return osc_table[osc_bits].khz >> pll_ref_div;
@@ -186,11 +186,11 @@ void clock_init_arm_generic_timer(void)
 	set_cntfrq(freq);
 
 	/* Record the system timer frequency. */
-	writel(freq, &sysctr->cntfid0);
+	write32(&sysctr->cntfid0, freq);
 	/* Enable the system counter. */
 	uint32_t cntcr = read32(&sysctr->cntcr);
 	cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG;
-	writel(cntcr, &sysctr->cntcr);
+	write32(&sysctr->cntcr, cntcr);
 }
 
 #define SOR0_CLK_SEL0			(1 << 14)
@@ -221,18 +221,18 @@ static void init_pll(u32 *base, u32 *misc, const union pll_fields pll, u32 lock)
 		       pll.div.lfcon << PLL_MISC_LFCON_SHIFT;
 
 	/* Write dividers but BYPASS the PLL while we're messing with it. */
-	writel(dividers | PLL_BASE_BYPASS, base);
+	write32(base, dividers | PLL_BASE_BYPASS);
 	/*
 	 * Set Lock bit, CPCON and LFCON fields (default to 0 if it doesn't
 	 * exist for this PLL)
 	 */
-	writel(lock | misc_con, misc);
+	write32(misc, lock | misc_con);
 
 	/* Enable PLL and take it back out of BYPASS */
-	writel(dividers | PLL_BASE_ENABLE, base);
+	write32(base, dividers | PLL_BASE_ENABLE);
 
 	/* Wait for lock ready */
-	while (!(readl(base) & PLL_BASE_LOCK));
+	while (!(read32(base) & PLL_BASE_LOCK));
 }
 
 static void init_utmip_pll(void)
@@ -243,14 +243,14 @@ static void init_utmip_pll(void)
 	clrbits_le32(CLK_RST_REG(utmip_pll_cfg2), 1 << 30); /* PHY_XTAL_CLKEN */
 	udelay(1);
 
-	writel(80 << 16 | 1 << 8 | 0, CLK_RST_REG(utmip_pll_cfg0));/* 960MHz * 1 / 80 == 12 MHz */
+	write32(CLK_RST_REG(utmip_pll_cfg0), 80 << 16 | 1 << 8 | 0);/* 960MHz * 1 / 80 == 12 MHz */
 
-	writel(div_round_up(khz, 8000) << 27 | 0 << 16 | 0 << 14 | 0 << 12 | div_round_up(khz, 102) << 0 | 0,
-	       CLK_RST_REG(utmip_pll_cfg1));
+	write32(CLK_RST_REG(utmip_pll_cfg1),
+		div_round_up(khz, 8000) << 27 | 0 << 16 | 0 << 14 | 0 << 12 | div_round_up(khz, 102) << 0 | 0);
 
 	/* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */
-	writel(0 << 24 | div_round_up(khz, 3200) << 18 | div_round_up(khz, 256) << 6 | 0 << 4 | 0 << 2 | 0 << 0 | 0,
-	       CLK_RST_REG(utmip_pll_cfg2));
+	write32(CLK_RST_REG(utmip_pll_cfg2),
+		0 << 24 | div_round_up(khz, 3200) << 18 | div_round_up(khz, 256) << 6 | 0 << 4 | 0 << 2 | 0 << 0 | 0);
 
 	setbits_le32(CLK_RST_REG(utmip_pll_cfg2), 1 << 30); /* PHY_XTAL_CLKEN */
 }
@@ -274,12 +274,12 @@ static void graphics_pll(void)
 	 * that it is needed.
 	 */
 	u32 scfg = (1 << 28) | (1 << 24) | (1 << 22);
-	writel(scfg, cfg);
+	write32(cfg, scfg);
 	init_pll(CLK_RST_REG(plldp_base), CLK_RST_REG(plldp_misc),
 		osc_table[osc].plldp, PLLDPD2_MISC_LOCK_ENABLE);
 	/* leave dither and undoc bits set, release clamp */
 	scfg = (1<<28) | (1<<24);
-	writel(scfg, cfg);
+	write32(cfg, scfg);
 }
 
 /*
@@ -387,8 +387,8 @@ u32 clock_configure_plld(u32 frequency)
  * been determined through trial and error (must lead to div 13 at 24MHz). */
 void clock_early_uart(void)
 {
-	writel(CLK_SRC_DEV_ID(UARTA, CLK_M) << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900),
-	       CLK_RST_REG(clk_src_uarta));
+	write32(CLK_RST_REG(clk_src_uarta),
+		CLK_SRC_DEV_ID(UARTA, CLK_M) << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900));
 
 	clock_enable_clear_reset_l(CLK_L_UARTA);
 }
@@ -437,22 +437,22 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,
 	 * values after coldboot reset).
 	 */
 
-	writel(misc1, CLK_RST_REG(pllm_misc1));
-	writel(misc2, CLK_RST_REG(pllm_misc2));
+	write32(CLK_RST_REG(pllm_misc1), misc1);
+	write32(CLK_RST_REG(pllm_misc2), misc2);
 
 	/* PLLM.BASE needs BYPASS=0, different from general init_pll */
-	base = readl(CLK_RST_REG(pllm_base));
+	base = read32(CLK_RST_REG(pllm_base));
 	base &= ~(PLLCMX_BASE_DIVN_MASK | PLLCMX_BASE_DIVM_MASK |
 		  PLLM_BASE_DIVP_MASK | PLL_BASE_BYPASS);
 	base |= ((m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT) |
 		 (p << PLL_BASE_DIVP_SHIFT));
-	writel(base, CLK_RST_REG(pllm_base));
+	write32(CLK_RST_REG(pllm_base), base);
 
 	setbits_le32(CLK_RST_REG(pllm_base), PLL_BASE_ENABLE);
 	/* stable_time is required, before we can start to check lock. */
 	udelay(stable_time);
 
-	while (!(readl(CLK_RST_REG(pllm_base)) & PLL_BASE_LOCK))
+	while (!(read32(CLK_RST_REG(pllm_base)) & PLL_BASE_LOCK))
 		udelay(1);
 
 	/*
@@ -466,7 +466,7 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,
 
 	/* Enable and start MEM(MC) and EMC. */
 	clock_enable_clear_reset(0, CLK_H_MEM | CLK_H_EMC, 0, 0, 0, 0);
-	writel(emc_source, CLK_RST_REG(clk_src_emc));
+	write32(CLK_RST_REG(clk_src_emc), emc_source);
 	udelay(IO_STABILIZATION_DELAY);
 }
 
@@ -477,9 +477,9 @@ void clock_cpu0_config(void)
 	u32 timeout = 0;
 
 	/* disable IDDQ */
-	reg = readl(&clst_clk->pllx_misc3);
+	reg = read32(&clst_clk->pllx_misc3);
 	reg &= ~PLLX_IDDQ;
-	writel(reg, &clst_clk->pllx_misc3);
+	write32(&clst_clk->pllx_misc3, reg);
 
 	/* init pllx */
 	init_pll(&clst_clk->pllx_base, &clst_clk->pllx_misc,
@@ -490,9 +490,9 @@ void clock_cpu0_config(void)
 	 * when above pllx programming has taken effect.
 	 */
 	do {
-		if (readl(&clst_clk->misc_ctrl) & CLK_SWITCH_MATCH) {
-			writel((CC_CCLK_BRST_POL_PLLX_OUT0_LJ << 28),
-			       &clst_clk->cclk_brst_pol);
+		if (read32(&clst_clk->misc_ctrl) & CLK_SWITCH_MATCH) {
+			write32(&clst_clk->cclk_brst_pol,
+				(CC_CCLK_BRST_POL_PLLX_OUT0_LJ << 28));
 			break;
 		}
 
@@ -512,8 +512,8 @@ void clock_cpu0_config(void)
 void clock_halt_avp(void)
 {
 	for (;;)
-		writel(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT,
-		       &flow->halt_cop_events);
+		write32(&flow->halt_cop_events,
+		        FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT);
 }
 
 void clock_init(void)
@@ -521,7 +521,7 @@ void clock_init(void)
 	u32 osc = clock_get_osc_bits();
 
 	/* Set PLLC dynramp_step A to 0x2b and B to 0xb (from U-Boot -- why? */
-	writel(0x2b << 17 | 0xb << 9, CLK_RST_REG(pllc_misc2));
+	write32(CLK_RST_REG(pllc_misc2), 0x2b << 17 | 0xb << 9);
 
 	/* Max out the AVP clock before everything else (need PLLC for that). */
 	init_pll(CLK_RST_REG(pllc_base), CLK_RST_REG(pllc_misc),
@@ -529,12 +529,12 @@ void clock_init(void)
 
 	/* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA
 	 * features section in the TRM). */
-	writel(1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT,
-	       CLK_RST_REG(clk_sys_rate));	/* pclk = hclk = sclk/2 */
-	writel(CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN,
-	       CLK_RST_REG(pllc_out));
-	writel(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT,
-	       CLK_RST_REG(sclk_brst_pol));		/* sclk = 300 MHz */
+	write32(CLK_RST_REG(clk_sys_rate),
+		1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT);	/* pclk = hclk = sclk/2 */
+	write32(CLK_RST_REG(pllc_out),
+		CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN);
+	write32(CLK_RST_REG(sclk_brst_pol),
+		SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT);		/* sclk = 300 MHz */
 
 	/* Change the oscillator drive strength (from U-Boot -- why?) */
 	clrsetbits_le32(CLK_RST_REG(osc_ctrl), OSC_XOFS_MASK,
@@ -549,10 +549,10 @@ void clock_init(void)
 			OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT);
 
 	/* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */
-	writel((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT,
-	       CLK_RST_REG(pllp_outa));
-	writel((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT,
-	       CLK_RST_REG(pllp_outb));
+	write32(CLK_RST_REG(pllp_outa),
+		(CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT);
+	write32(CLK_RST_REG(pllp_outb),
+		(CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT);
 
 	/* init pllu */
 	init_pll(CLK_RST_REG(pllu_base), CLK_RST_REG(pllu_misc),
@@ -565,9 +565,9 @@ void clock_init(void)
 void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg,
 				  u32 *rst_dev_clr_reg)
 {
-	writel(val, clk_enb_set_reg);
+	write32(clk_enb_set_reg, val);
 	udelay(IO_STABILIZATION_DELAY);
-	writel(val, rst_dev_clr_reg);
+	write32(rst_dev_clr_reg, val);
 }
 
 static u32 * const clk_enb_set_arr[DEV_CONFIG_BLOCKS] = {
@@ -613,7 +613,7 @@ static void clock_write_regs(u32 * const regs[DEV_CONFIG_BLOCKS],
 
 	for (; i < DEV_CONFIG_BLOCKS; i++)
 		if (bits[i])
-			writel(bits[i], regs[i]);
+			write32(regs[i], bits[i]);
 }
 
 void clock_enable_regs(u32 bits[DEV_CONFIG_BLOCKS])
@@ -648,9 +648,9 @@ void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x)
 
 static void clock_reset_dev(u32 *setaddr, u32 *clraddr, u32 bit)
 {
-	writel(bit, setaddr);
+	write32(setaddr, bit);
 	udelay(LOGIC_STABILIZATION_DELAY);
-	writel(bit, clraddr);
+	write32(clraddr, bit);
 }
 
 void clock_reset_l(u32 bit)
diff --git a/src/soc/nvidia/tegra132/cpu.c b/src/soc/nvidia/tegra132/cpu.c
index 8cd2c0faea..b6f0cfec11 100644
--- a/src/soc/nvidia/tegra132/cpu.c
+++ b/src/soc/nvidia/tegra132/cpu.c
@@ -40,15 +40,15 @@ static void enable_core_clocks(int cpu)
 
 	/* Clear reset of CPU components. */
 	if (cpu == 0)
-		writel(cpu0_clocks, CLK_RST_REG(rst_cpug_cmplx_clr));
+		write32(CLK_RST_REG(rst_cpug_cmplx_clr), cpu0_clocks);
 	else
-		writel(cpu1_clocks, CLK_RST_REG(rst_cpug_cmplx_clr));
+		write32(CLK_RST_REG(rst_cpug_cmplx_clr), cpu1_clocks);
 }
 
 static void set_armv8_32bit_reset_vector(uintptr_t entry)
 {
 	void * const evp_cpu_reset_vector = EVP_CPU_RESET_VECTOR;
-	writel(entry, evp_cpu_reset_vector);
+	write32(evp_cpu_reset_vector, entry);
 }
 
 static void set_armv8_64bit_reset_vector(uintptr_t entry)
@@ -56,8 +56,8 @@ static void set_armv8_64bit_reset_vector(uintptr_t entry)
 	struct tegra_pmc_regs * const pmc = PMC_REGS;
 
 	/* Currently assume 32-bit addresses only. */
-	writel(entry, &pmc->secure_scratch34);
-	writel(0, &pmc->secure_scratch35);
+	write32(&pmc->secure_scratch34, entry);
+	write32(&pmc->secure_scratch35, 0);
 }
 
 void cpu_prepare_startup(void *entry_64)
diff --git a/src/soc/nvidia/tegra132/dc.c b/src/soc/nvidia/tegra132/dc.c
index a3ba9e6fe7..07eac2e687 100644
--- a/src/soc/nvidia/tegra132/dc.c
+++ b/src/soc/nvidia/tegra132/dc.c
@@ -38,7 +38,7 @@ unsigned long READL(void * p)
         if (dump > 1)
 		printk(BIOS_SPEW, "readl %p\n", p);
 
-        value = readl(p);
+        value = read32(p);
         if (dump)
 		printk(BIOS_SPEW, "readl %p %08lx\n", p, value);
         return value;
@@ -48,7 +48,7 @@ void WRITEL(unsigned long value, void * p)
 {
         if (dump)
 		printk(BIOS_SPEW, "writel %p %08lx\n", p, value);
-        writel(value, p);
+        write32(p, value);
 }
 
 /* return in 1000ths of a Hertz */
diff --git a/src/soc/nvidia/tegra132/dsi.c b/src/soc/nvidia/tegra132/dsi.c
index 8508b6666d..1af24e140c 100644
--- a/src/soc/nvidia/tegra132/dsi.c
+++ b/src/soc/nvidia/tegra132/dsi.c
@@ -869,7 +869,7 @@ static int dsi_enable(struct soc_nvidia_tegra132_config *config)
 	tegra_output_dsi_setup_clock(dsi_a, config);
 
 	/* configure APB_MISC_GP_MIPI_PAD_CTRL_0 */
-	writel(DSIB_MODE_DSI, (unsigned int *)APB_MISC_GP_MIPI_PAD_CTRL_0);
+	write32((unsigned int *)APB_MISC_GP_MIPI_PAD_CTRL_0, DSIB_MODE_DSI);
 
 	/* configure phy interface timing registers */
 	tegra_dsi_set_phy_timing(dsi_a);
diff --git a/src/soc/nvidia/tegra132/flow_ctrl.c b/src/soc/nvidia/tegra132/flow_ctrl.c
index 6d7d11590c..213dca2779 100644
--- a/src/soc/nvidia/tegra132/flow_ctrl.c
+++ b/src/soc/nvidia/tegra132/flow_ctrl.c
@@ -62,14 +62,14 @@ static uint32_t flowctrl_read_cpu_csr(int cpu)
 
 static void flowctrl_write_cpu_csr(int cpu, uint32_t val)
 {
-	writel(val, tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]);
-	val = readl(tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]);
+	write32(tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu], val);
+	val = read32(tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]);
 }
 
 void flowctrl_write_cpu_halt(int cpu, uint32_t val)
 {
-	writel(val, tegra_flowctrl_base + flowctrl_offset_halt_cpu[cpu]);
-	val = readl(tegra_flowctrl_base + flowctrl_offset_halt_cpu[cpu]);
+	write32(tegra_flowctrl_base + flowctrl_offset_halt_cpu[cpu], val);
+	val = read32(tegra_flowctrl_base + flowctrl_offset_halt_cpu[cpu]);
 }
 
 static void flowctrl_prepare_cpu_off(int cpu)
diff --git a/src/soc/nvidia/tegra132/i2c6.c b/src/soc/nvidia/tegra132/i2c6.c
index ef86126935..1ae8db3075 100644
--- a/src/soc/nvidia/tegra132/i2c6.c
+++ b/src/soc/nvidia/tegra132/i2c6.c
@@ -43,7 +43,7 @@ static void remove_clamps(int id)
 		return;
 
 	/* Remove clamp */
-	writel((1 << id), &pmc->remove_clamping_cmd);
+	write32(&pmc->remove_clamping_cmd, (1 << id));
 
 	/* Wait for clamp off */
 	while (partition_clamp_on(id))
@@ -86,7 +86,7 @@ void soc_configure_i2c6pad(void)
 	soc_configure_host1x();
 
 	/* Now we can write the I2C6 mux in DPAUX */
-	writel(I2C6_PADCTL, (void *)DPAUX_HYBRID_PADCTL);
+	write32((void *)DPAUX_HYBRID_PADCTL, I2C6_PADCTL);
 
 	/*
 	 * Delay before turning off Host1X/DPAUX clocks.
diff --git a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c
index 29fb9dedd6..8392a58228 100644
--- a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c
@@ -261,17 +261,17 @@ inline static void write32(uint32_t val, void *addr)
 
 inline static void setbits32(uint32_t bits, void *addr)
 {
-	writel(read32(addr) | bits, addr);
+	write32(addr, read32(addr) | bits);
 }
 
 inline static void clrbits32(uint32_t bits, void *addr)
 {
-	writel(read32(addr) & ~bits, addr);
+	write32(addr, read32(addr) & ~bits);
 }
 
 static void __attribute__((noreturn)) reset(void)
 {
-	writel(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr);
+	write32(clk_rst_rst_devices_l_ptr, SWR_TRIG_SYS_RST);
 	halt();
 }
 
@@ -370,18 +370,18 @@ static void enable_uart(void)
 	clrbits32(uart_mask, uart_rst_reg);
 
 	/* Program UART clock source: PLLP (408000000) */
-	writel(0, uart_clk_source);
+	write32(uart_clk_source, 0);
 
 	/* Program 115200n8 to the uart port */
 	/* baud-rate of 115200 */
-	writel(LCR_DLAB, (uart_base + UART_LCR));
-	writel((UART_RATE_115200 & 0xff), (uart_base + UART_THR_DLAB));
-	writel((UART_RATE_115200 >> 8), (uart_base + UART_IER_DLAB));
+	write32((uart_base + UART_LCR), LCR_DLAB);
+	write32((uart_base + UART_THR_DLAB), (UART_RATE_115200 & 0xff));
+	write32((uart_base + UART_IER_DLAB), (UART_RATE_115200 >> 8));
 	/* 8-bit and no parity */
-	writel(LCR_WD_SIZE_8, (uart_base + UART_LCR));
+	write32((uart_base + UART_LCR), LCR_WD_SIZE_8);
 	/* enable and clear RX/TX FIFO */
-	writel((FCR_TX_CLR + FCR_RX_CLR + FCR_EN_FIFO),
-	       (uart_base + UART_IIR_FCR));
+	write32((uart_base + UART_IIR_FCR),
+		(FCR_TX_CLR + FCR_RX_CLR + FCR_EN_FIFO));
 }
 
 /* Accessors. */
@@ -401,7 +401,7 @@ static unsigned get_osc_freq(void)
 
 static void enable_jtag(void)
 {
-	writel(PP_CONFIG_CTL_JTAG, misc_pp_config_ctl_ptr);
+	write32(misc_pp_config_ctl_ptr, PP_CONFIG_CTL_JTAG);
 }
 
 /* Clock configuration. */
@@ -417,7 +417,7 @@ static void config_oscillator(void)
 	osc_ctrl &= ~OSC_XOFS_MASK;
 	osc_ctrl |= (xofs << OSC_XOFS_SHIFT);
 	osc_ctrl |= OSC_XOE;
-	writel(osc_ctrl, clk_rst_osc_ctrl_ptr);
+	write32(clk_rst_osc_ctrl_ptr, osc_ctrl);
 }
 
 static void config_pllu(void)
@@ -462,24 +462,24 @@ static void config_pllu(void)
 	// Configure PLLU.
 	uint32_t base = PLLU_BYPASS | PLLU_OVERRIDE |
 			(divn << PLLU_DIVN_SHIFT) | (divm << PLLU_DIVM_SHIFT);
-	writel(base, clk_rst_pllu_base_ptr);
+	write32(clk_rst_pllu_base_ptr, base);
 	uint32_t misc = (cpcon << PLLU_CPCON_SHIFT) |
 			(lfcon << PLLU_LFCON_SHIFT);
-	writel(misc, clk_rst_pllu_misc_ptr);
+	write32(clk_rst_pllu_misc_ptr, misc);
 
 	// Enable PLLU.
 	base &= ~PLLU_BYPASS;
 	base |= PLLU_ENABLE;
-	writel(base, clk_rst_pllu_base_ptr);
+	write32(clk_rst_pllu_base_ptr, base);
 	misc |= PLLU_LOCK_ENABLE;
-	writel(misc, clk_rst_pllu_misc_ptr);
+	write32(clk_rst_pllu_misc_ptr, misc);
 }
 
 static void enable_cpu_clocks(void)
 {
 	// Enable the CPU complex clock.
-	writel(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr);
-	writel(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr);
+	write32(clk_rst_clk_enb_l_set_ptr, CLK_ENB_CPU);
+	write32(clk_rst_clk_enb_v_set_ptr, CLK_ENB_CPUG | CLK_ENB_CPULP);
 }
 
 
@@ -489,7 +489,7 @@ static void enable_cpu_clocks(void)
 static void config_core_sight(void)
 {
 	// Enable the CoreSight clock.
-	writel(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr);
+	write32(clk_rst_clk_out_enb_u_set_ptr, CLK_ENB_CSITE);
 
 	/*
 	 * De-assert CoreSight reset.
@@ -497,7 +497,7 @@ static void config_core_sight(void)
 	 *       now. It will be restored to its original clock source
 	 *       when the CPU-side restoration code runs.
 	 */
-	writel(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr);
+	write32(clk_rst_rst_dev_u_clr_ptr, SWR_CSITE_RST);
 }
 
 
@@ -508,11 +508,11 @@ static void clear_cpu_resets(void)
 	/* Hold CPU1 in reset */
 	setbits32(SET_CXRESET1, clk_rst_rst_cpulp_cmplx_set_ptr);
 
-	writel(CLR_NONCPURESET | CLR_L2RESET | CLR_PRESETDBG,
-	       clk_rst_rst_cpug_cmplx_clr_ptr);
+	write32(clk_rst_rst_cpug_cmplx_clr_ptr,
+		CLR_NONCPURESET | CLR_L2RESET | CLR_PRESETDBG);
 
-	writel(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0,
-	       clk_rst_rst_cpug_cmplx_clr_ptr);
+	write32(clk_rst_rst_cpug_cmplx_clr_ptr,
+		CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0);
 }
 
 
@@ -542,7 +542,8 @@ static void power_on_partition(unsigned id)
 	uint32_t bit = 0x1 << id;
 	if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) {
 		// Partition is not on. Turn it on.
-		writel(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr);
+		write32(pmc_ctlr_pwrgate_toggle_ptr,
+			id | PWRGATE_TOGGLE_START);
 
 		// Wait until the partition is powerd on.
 		while (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit))
@@ -572,15 +573,15 @@ static void power_on_main_cpu(void)
 	 */
 	uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr);
 
-	writel(orig_timer * (204000000 / 32768),
-	       pmc_ctlr_cpupwrgood_timer_ptr);
+	write32(pmc_ctlr_cpupwrgood_timer_ptr,
+		orig_timer * (204000000 / 32768));
 
 	power_on_partition(PARTID_CRAIL);
 	power_on_partition(PARTID_C0NC);
 	power_on_partition(PARTID_CE0);
 
 	// Restore the original PMC_CPUPWRGOOD_TIMER.
-	writel(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr);
+	write32(pmc_ctlr_cpupwrgood_timer_ptr, orig_timer);
 }
 
 
@@ -609,7 +610,7 @@ void lp0_resume(void)
 	config_oscillator();
 
 	// Program SUPER_CCLK_DIVIDER.
-	writel(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr);
+	write32(clk_rst_super_cclk_div_ptr, SUPER_CDIV_ENB);
 
 	config_core_sight();
 
@@ -623,12 +624,12 @@ void lp0_resume(void)
 	 * T132 always resets to AARCH32 and SW needs to write RMR_EL3
 	 * to bootstrap into AARCH64.
 	 */
-	writel(get_wakeup_vector(), pmc_ctlr_secure_scratch34_ptr);
-	writel(0, pmc_ctlr_secure_scratch35_ptr);
-	writel((uint32_t)aarch64_trampoline, evp_cpu_reset_ptr);
+	write32(pmc_ctlr_secure_scratch34_ptr, get_wakeup_vector());
+	write32(pmc_ctlr_secure_scratch35_ptr, 0);
+	write32(evp_cpu_reset_ptr, (uint32_t)aarch64_trampoline);
 
 	// Select CPU complex clock source.
-	writel(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr);
+	write32(clk_rst_cclk_burst_policy_ptr, CCLK_PLLP_BURST_POLICY);
 
 	// Disable PLLX since it isn't used as CPU clock source.
 	clrbits32(PLLX_ENABLE, clk_rst_pllx_base_ptr);
@@ -637,12 +638,12 @@ void lp0_resume(void)
 	uint32_t ack_width = read32(clk_rst_cpu_softrst_ctrl2_ptr);
 	ack_width &= ~CAR2PMC_CPU_ACK_WIDTH_MASK;
 	ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT;
-	writel(ack_width, clk_rst_cpu_softrst_ctrl2_ptr);
+	write32(clk_rst_cpu_softrst_ctrl2_ptr, ack_width);
 
 	// Disable VPR.
-	writel(0, mc_video_protect_size_mb_ptr);
-	writel(VIDEO_PROTECT_WRITE_ACCESS_DISABLE,
-               mc_video_protect_reg_ctrl_ptr);
+	write32(mc_video_protect_size_mb_ptr, 0);
+	write32(mc_video_protect_reg_ctrl_ptr,
+		VIDEO_PROTECT_WRITE_ACCESS_DISABLE);
 
 	enable_cpu_clocks();
 
@@ -655,8 +656,8 @@ void lp0_resume(void)
 
 	// Halt the AVP.
 	while (1)
-		writel(FLOW_MODE_STOP | EVENT_JTAG,
-		       flow_ctlr_halt_cop_events_ptr);
+		write32(flow_ctlr_halt_cop_events_ptr,
+		        FLOW_MODE_STOP | EVENT_JTAG);
 }
 
 
diff --git a/src/soc/nvidia/tegra132/mipi.c b/src/soc/nvidia/tegra132/mipi.c
index abd2230378..1768fa0fd3 100644
--- a/src/soc/nvidia/tegra132/mipi.c
+++ b/src/soc/nvidia/tegra132/mipi.c
@@ -43,13 +43,13 @@ static struct tegra_mipi mipi_data = {
 static inline unsigned long tegra_mipi_readl(struct tegra_mipi *mipi,
 					     unsigned long reg)
 {
-	return readl(mipi->regs + (reg << 2));
+	return read32(mipi->regs + (reg << 2));
 }
 
 static inline void tegra_mipi_writel(struct tegra_mipi *mipi,
 				     unsigned long value, unsigned long reg)
 {
-	writel(value, mipi->regs + (reg << 2));
+	write32(mipi->regs + (reg << 2), value);
 }
 
 static const struct calibration_regs tegra124_mipi_calibration_regs[] = {
diff --git a/src/soc/nvidia/tegra132/padconfig.c b/src/soc/nvidia/tegra132/padconfig.c
index 790f10f9c0..46cf944441 100644
--- a/src/soc/nvidia/tegra132/padconfig.c
+++ b/src/soc/nvidia/tegra132/padconfig.c
@@ -36,7 +36,7 @@ static inline uint32_t pad_get_pinmux(int index)
 
 static inline void pad_set_pinmux(int index, uint32_t reg)
 {
-	return writel(reg, &pinmux_regs[index]);
+	return write32(&pinmux_regs[index], reg);
 }
 
 static inline void pad_set_gpio_out(int gpio_index, int val)
@@ -45,10 +45,10 @@ static inline void pad_set_gpio_out(int gpio_index, int val)
 	int port = gpio_index_to_port(gpio_index);
 	int bit = gpio_to_bit(gpio_index);
 
-	writel((1 << (bit + GPIO_GPIOS_PER_PORT)) | (val << bit),
-	       &regs->out_value_mask[port]);
-	writel((1 << (bit + GPIO_GPIOS_PER_PORT)) | (1 << bit),
-	       &regs->out_enable_mask[port]);
+	write32(&regs->out_value_mask[port],
+		(1 << (bit + GPIO_GPIOS_PER_PORT)) | (val << bit));
+	write32(&regs->out_enable_mask[port],
+		(1 << (bit + GPIO_GPIOS_PER_PORT)) | (1 << bit));
 }
 
 static inline void pad_set_mode(int gpio_index, int sfio_or_gpio)
@@ -57,8 +57,8 @@ static inline void pad_set_mode(int gpio_index, int sfio_or_gpio)
 	int port = gpio_index_to_port(gpio_index);
 	int bit = gpio_to_bit(gpio_index);
 
-	writel((1 << (bit + GPIO_GPIOS_PER_PORT)) | (sfio_or_gpio << bit),
-	       &regs->config_mask[port]);
+	write32(&regs->config_mask[port],
+		(1 << (bit + GPIO_GPIOS_PER_PORT)) | (sfio_or_gpio << bit));
 }
 
 static inline void pad_set_gpio_mode(int gpio_index)
diff --git a/src/soc/nvidia/tegra132/power.c b/src/soc/nvidia/tegra132/power.c
index 0ebfd7c53e..b9ac90acf8 100644
--- a/src/soc/nvidia/tegra132/power.c
+++ b/src/soc/nvidia/tegra132/power.c
@@ -41,7 +41,7 @@ void power_ungate_partition(uint32_t id)
 		pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK);
 		pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT);
 		pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START;
-		writel(pwrgate_toggle, &pmc->pwrgate_toggle);
+		write32(&pmc->pwrgate_toggle, pwrgate_toggle);
 
 		/* Wait for the request to be accepted. */
 		while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START)
diff --git a/src/soc/nvidia/tegra132/sdram.c b/src/soc/nvidia/tegra132/sdram.c
index 14d2b50fe1..65dce9b4cd 100644
--- a/src/soc/nvidia/tegra132/sdram.c
+++ b/src/soc/nvidia/tegra132/sdram.c
@@ -31,7 +31,7 @@
 static void sdram_patch(uintptr_t addr, uint32_t value)
 {
 	if (addr)
-		writel(value, (uint32_t*)addr);
+		write32((uint32_t *)addr, value);
 }
 
 static void writebits(uint32_t value, uint32_t *addr, uint32_t mask)
@@ -44,7 +44,7 @@ static void sdram_configure_pmc(const struct sdram_params *param,
 				struct tegra_pmc_regs *regs)
 {
 	/* VDDP Select */
-	writel(param->PmcVddpSel, &regs->vddp_sel);
+	write32(&regs->vddp_sel, param->PmcVddpSel);
 	udelay(param->PmcVddpSelWait);
 
 	/* Set DDR pad voltage */
@@ -60,7 +60,7 @@ static void sdram_configure_pmc(const struct sdram_params *param,
 	writebits(param->PmcNoIoPower, &regs->no_iopower,
 		  (PMC_NO_IOPOWER_MEM_MASK | PMC_NO_IOPOWER_MEM_COMP_MASK));
 
-	writel(param->PmcRegShort, &regs->reg_short);
+	write32(&regs->reg_short, param->PmcRegShort);
 }
 
 static void sdram_start_clocks(const struct sdram_params *param)
@@ -100,148 +100,151 @@ static void sdram_deassert_sel_dpd(const struct sdram_params *param,
 static void sdram_set_swizzle(const struct sdram_params *param,
 			      struct tegra_emc_regs *regs)
 {
-	writel(param->EmcSwizzleRank0ByteCfg, &regs->swizzle_rank0_byte_cfg);
-	writel(param->EmcSwizzleRank0Byte0, &regs->swizzle_rank0_byte0);
-	writel(param->EmcSwizzleRank0Byte1, &regs->swizzle_rank0_byte1);
-	writel(param->EmcSwizzleRank0Byte2, &regs->swizzle_rank0_byte2);
-	writel(param->EmcSwizzleRank0Byte3, &regs->swizzle_rank0_byte3);
-	writel(param->EmcSwizzleRank1ByteCfg, &regs->swizzle_rank1_byte_cfg);
-	writel(param->EmcSwizzleRank1Byte0, &regs->swizzle_rank1_byte0);
-	writel(param->EmcSwizzleRank1Byte1, &regs->swizzle_rank1_byte1);
-	writel(param->EmcSwizzleRank1Byte2, &regs->swizzle_rank1_byte2);
-	writel(param->EmcSwizzleRank1Byte3, &regs->swizzle_rank1_byte3);
+	write32(&regs->swizzle_rank0_byte_cfg, param->EmcSwizzleRank0ByteCfg);
+	write32(&regs->swizzle_rank0_byte0, param->EmcSwizzleRank0Byte0);
+	write32(&regs->swizzle_rank0_byte1, param->EmcSwizzleRank0Byte1);
+	write32(&regs->swizzle_rank0_byte2, param->EmcSwizzleRank0Byte2);
+	write32(&regs->swizzle_rank0_byte3, param->EmcSwizzleRank0Byte3);
+	write32(&regs->swizzle_rank1_byte_cfg, param->EmcSwizzleRank1ByteCfg);
+	write32(&regs->swizzle_rank1_byte0, param->EmcSwizzleRank1Byte0);
+	write32(&regs->swizzle_rank1_byte1, param->EmcSwizzleRank1Byte1);
+	write32(&regs->swizzle_rank1_byte2, param->EmcSwizzleRank1Byte2);
+	write32(&regs->swizzle_rank1_byte3, param->EmcSwizzleRank1Byte3);
 }
 
 static void sdram_set_pad_controls(const struct sdram_params *param,
 				   struct tegra_emc_regs *regs)
 {
 	/* Program the pad controls */
-	writel(param->EmcXm2CmdPadCtrl, &regs->xm2cmdpadctrl);
-	writel(param->EmcXm2CmdPadCtrl2, &regs->xm2cmdpadctrl2);
-	writel(param->EmcXm2CmdPadCtrl3, &regs->xm2cmdpadctrl3);
-	writel(param->EmcXm2CmdPadCtrl4, &regs->xm2cmdpadctrl4);
-	writel(param->EmcXm2CmdPadCtrl5, &regs->xm2cmdpadctrl5);
+	write32(&regs->xm2cmdpadctrl, param->EmcXm2CmdPadCtrl);
+	write32(&regs->xm2cmdpadctrl2, param->EmcXm2CmdPadCtrl2);
+	write32(&regs->xm2cmdpadctrl3, param->EmcXm2CmdPadCtrl3);
+	write32(&regs->xm2cmdpadctrl4, param->EmcXm2CmdPadCtrl4);
+	write32(&regs->xm2cmdpadctrl5, param->EmcXm2CmdPadCtrl5);
 
-	writel(param->EmcXm2DqsPadCtrl, &regs->xm2dqspadctrl);
-	writel(param->EmcXm2DqsPadCtrl2, &regs->xm2dqspadctrl2);
-	writel(param->EmcXm2DqsPadCtrl3, &regs->xm2dqspadctrl3);
-	writel(param->EmcXm2DqsPadCtrl4, &regs->xm2dqspadctrl4);
-	writel(param->EmcXm2DqsPadCtrl5, &regs->xm2dqspadctrl5);
-	writel(param->EmcXm2DqsPadCtrl6, &regs->xm2dqspadctrl6);
+	write32(&regs->xm2dqspadctrl, param->EmcXm2DqsPadCtrl);
+	write32(&regs->xm2dqspadctrl2, param->EmcXm2DqsPadCtrl2);
+	write32(&regs->xm2dqspadctrl3, param->EmcXm2DqsPadCtrl3);
+	write32(&regs->xm2dqspadctrl4, param->EmcXm2DqsPadCtrl4);
+	write32(&regs->xm2dqspadctrl5, param->EmcXm2DqsPadCtrl5);
+	write32(&regs->xm2dqspadctrl6, param->EmcXm2DqsPadCtrl6);
 
-	writel(param->EmcXm2DqPadCtrl, &regs->xm2dqpadctrl);
-	writel(param->EmcXm2DqPadCtrl2, &regs->xm2dqpadctrl2);
-	writel(param->EmcXm2DqPadCtrl3, &regs->xm2dqpadctrl3);
+	write32(&regs->xm2dqpadctrl, param->EmcXm2DqPadCtrl);
+	write32(&regs->xm2dqpadctrl2, param->EmcXm2DqPadCtrl2);
+	write32(&regs->xm2dqpadctrl3, param->EmcXm2DqPadCtrl3);
 
-	writel(param->EmcXm2ClkPadCtrl, &regs->xm2clkpadctrl);
-	writel(param->EmcXm2ClkPadCtrl2, &regs->xm2clkpadctrl2);
+	write32(&regs->xm2clkpadctrl, param->EmcXm2ClkPadCtrl);
+	write32(&regs->xm2clkpadctrl2, param->EmcXm2ClkPadCtrl2);
 
-	writel(param->EmcXm2CompPadCtrl, &regs->xm2comppadctrl);
+	write32(&regs->xm2comppadctrl, param->EmcXm2CompPadCtrl);
 
-	writel(param->EmcXm2VttGenPadCtrl, &regs->xm2vttgenpadctrl);
-	writel(param->EmcXm2VttGenPadCtrl2, &regs->xm2vttgenpadctrl2);
-	writel(param->EmcXm2VttGenPadCtrl3, &regs->xm2vttgenpadctrl3);
+	write32(&regs->xm2vttgenpadctrl, param->EmcXm2VttGenPadCtrl);
+	write32(&regs->xm2vttgenpadctrl2, param->EmcXm2VttGenPadCtrl2);
+	write32(&regs->xm2vttgenpadctrl3, param->EmcXm2VttGenPadCtrl3);
 
-	writel(param->EmcCttTermCtrl, &regs->ctt_term_ctrl);
+	write32(&regs->ctt_term_ctrl, param->EmcCttTermCtrl);
 }
 
 static void sdram_trigger_emc_timing_update(struct tegra_emc_regs *regs)
 {
-	writel(EMC_TIMING_CONTROL_TIMING_UPDATE, &regs->timing_control);
+	write32(&regs->timing_control, EMC_TIMING_CONTROL_TIMING_UPDATE);
 }
 
 static void sdram_init_mc(const struct sdram_params *param,
 			  struct tegra_mc_regs *regs)
 {
 	/* Initialize MC VPR settings */
-	writel(param->McDisplaySnapRing, &regs->display_snap_ring);
-	writel(param->McVideoProtectBom, &regs->video_protect_bom);
-	writel(param->McVideoProtectBomAdrHi, &regs->video_protect_bom_adr_hi);
-	writel(param->McVideoProtectSizeMb, &regs->video_protect_size_mb);
-	writel(param->McVideoProtectVprOverride,
-	       &regs->video_protect_vpr_override);
-	writel(param->McVideoProtectVprOverride1,
-	       &regs->video_protect_vpr_override1);
-	writel(param->McVideoProtectGpuOverride0,
-	       &regs->video_protect_gpu_override_0);
-	writel(param->McVideoProtectGpuOverride1,
-	       &regs->video_protect_gpu_override_1);
+	write32(&regs->display_snap_ring, param->McDisplaySnapRing);
+	write32(&regs->video_protect_bom, param->McVideoProtectBom);
+	write32(&regs->video_protect_bom_adr_hi,
+		param->McVideoProtectBomAdrHi);
+	write32(&regs->video_protect_size_mb, param->McVideoProtectSizeMb);
+	write32(&regs->video_protect_vpr_override,
+		param->McVideoProtectVprOverride);
+	write32(&regs->video_protect_vpr_override1,
+		param->McVideoProtectVprOverride1);
+	write32(&regs->video_protect_gpu_override_0,
+		param->McVideoProtectGpuOverride0);
+	write32(&regs->video_protect_gpu_override_1,
+		param->McVideoProtectGpuOverride1);
 
 	/* Program SDRAM geometry paarameters */
-	writel(param->McEmemAdrCfg, &regs->emem_adr_cfg);
-	writel(param->McEmemAdrCfgDev0, &regs->emem_adr_cfg_dev0);
-	writel(param->McEmemAdrCfgDev1, &regs->emem_adr_cfg_dev1);
+	write32(&regs->emem_adr_cfg, param->McEmemAdrCfg);
+	write32(&regs->emem_adr_cfg_dev0, param->McEmemAdrCfgDev0);
+	write32(&regs->emem_adr_cfg_dev1, param->McEmemAdrCfgDev1);
 
 	/* Program bank swizzling */
-	writel(param->McEmemAdrCfgBankMask0, &regs->emem_bank_swizzle_cfg0);
-	writel(param->McEmemAdrCfgBankMask1, &regs->emem_bank_swizzle_cfg1);
-	writel(param->McEmemAdrCfgBankMask2, &regs->emem_bank_swizzle_cfg2);
-	writel(param->McEmemAdrCfgBankSwizzle3, &regs->emem_bank_swizzle_cfg3);
+	write32(&regs->emem_bank_swizzle_cfg0, param->McEmemAdrCfgBankMask0);
+	write32(&regs->emem_bank_swizzle_cfg1, param->McEmemAdrCfgBankMask1);
+	write32(&regs->emem_bank_swizzle_cfg2, param->McEmemAdrCfgBankMask2);
+	write32(&regs->emem_bank_swizzle_cfg3,
+		param->McEmemAdrCfgBankSwizzle3);
 
 	/* Program external memory aperature (base and size) */
-	writel(param->McEmemCfg, &regs->emem_cfg);
+	write32(&regs->emem_cfg, param->McEmemCfg);
 
 	/* Program SEC carveout (base and size) */
-	writel(param->McSecCarveoutBom, &regs->sec_carveout_bom);
-	writel(param->McSecCarveoutAdrHi, &regs->sec_carveout_adr_hi);
-	writel(param->McSecCarveoutSizeMb, &regs->sec_carveout_size_mb);
+	write32(&regs->sec_carveout_bom, param->McSecCarveoutBom);
+	write32(&regs->sec_carveout_adr_hi, param->McSecCarveoutAdrHi);
+	write32(&regs->sec_carveout_size_mb, param->McSecCarveoutSizeMb);
 
 	/* Program MTS carveout (base and size) */
-	writel(param->McMtsCarveoutBom, &regs->mts_carveout_bom);
-	writel(param->McMtsCarveoutAdrHi, &regs->mts_carveout_adr_hi);
-	writel(param->McMtsCarveoutSizeMb, &regs->mts_carveout_size_mb);
+	write32(&regs->mts_carveout_bom, param->McMtsCarveoutBom);
+	write32(&regs->mts_carveout_adr_hi, param->McMtsCarveoutAdrHi);
+	write32(&regs->mts_carveout_size_mb, param->McMtsCarveoutSizeMb);
 
 	/* Program the memory arbiter */
-	writel(param->McEmemArbCfg, &regs->emem_arb_cfg);
-	writel(param->McEmemArbOutstandingReq, &regs->emem_arb_outstanding_req);
-	writel(param->McEmemArbTimingRcd, &regs->emem_arb_timing_rcd);
-	writel(param->McEmemArbTimingRp, &regs->emem_arb_timing_rp);
-	writel(param->McEmemArbTimingRc, &regs->emem_arb_timing_rc);
-	writel(param->McEmemArbTimingRas, &regs->emem_arb_timing_ras);
-	writel(param->McEmemArbTimingFaw, &regs->emem_arb_timing_faw);
-	writel(param->McEmemArbTimingRrd, &regs->emem_arb_timing_rrd);
-	writel(param->McEmemArbTimingRap2Pre, &regs->emem_arb_timing_rap2pre);
-	writel(param->McEmemArbTimingWap2Pre, &regs->emem_arb_timing_wap2pre);
-	writel(param->McEmemArbTimingR2R, &regs->emem_arb_timing_r2r);
-	writel(param->McEmemArbTimingW2W, &regs->emem_arb_timing_w2w);
-	writel(param->McEmemArbTimingR2W, &regs->emem_arb_timing_r2w);
-	writel(param->McEmemArbTimingW2R, &regs->emem_arb_timing_w2r);
-	writel(param->McEmemArbDaTurns, &regs->emem_arb_da_turns);
-	writel(param->McEmemArbDaCovers, &regs->emem_arb_da_covers);
-	writel(param->McEmemArbMisc0, &regs->emem_arb_misc0);
-	writel(param->McEmemArbMisc1, &regs->emem_arb_misc1);
-	writel(param->McEmemArbRing1Throttle, &regs->emem_arb_ring1_throttle);
-	writel(param->McEmemArbOverride, &regs->emem_arb_override);
-	writel(param->McEmemArbOverride1, &regs->emem_arb_override_1);
-	writel(param->McEmemArbRsv, &regs->emem_arb_rsv);
+	write32(&regs->emem_arb_cfg, param->McEmemArbCfg);
+	write32(&regs->emem_arb_outstanding_req,
+		param->McEmemArbOutstandingReq);
+	write32(&regs->emem_arb_timing_rcd, param->McEmemArbTimingRcd);
+	write32(&regs->emem_arb_timing_rp, param->McEmemArbTimingRp);
+	write32(&regs->emem_arb_timing_rc, param->McEmemArbTimingRc);
+	write32(&regs->emem_arb_timing_ras, param->McEmemArbTimingRas);
+	write32(&regs->emem_arb_timing_faw, param->McEmemArbTimingFaw);
+	write32(&regs->emem_arb_timing_rrd, param->McEmemArbTimingRrd);
+	write32(&regs->emem_arb_timing_rap2pre, param->McEmemArbTimingRap2Pre);
+	write32(&regs->emem_arb_timing_wap2pre, param->McEmemArbTimingWap2Pre);
+	write32(&regs->emem_arb_timing_r2r, param->McEmemArbTimingR2R);
+	write32(&regs->emem_arb_timing_w2w, param->McEmemArbTimingW2W);
+	write32(&regs->emem_arb_timing_r2w, param->McEmemArbTimingR2W);
+	write32(&regs->emem_arb_timing_w2r, param->McEmemArbTimingW2R);
+	write32(&regs->emem_arb_da_turns, param->McEmemArbDaTurns);
+	write32(&regs->emem_arb_da_covers, param->McEmemArbDaCovers);
+	write32(&regs->emem_arb_misc0, param->McEmemArbMisc0);
+	write32(&regs->emem_arb_misc1, param->McEmemArbMisc1);
+	write32(&regs->emem_arb_ring1_throttle, param->McEmemArbRing1Throttle);
+	write32(&regs->emem_arb_override, param->McEmemArbOverride);
+	write32(&regs->emem_arb_override_1, param->McEmemArbOverride1);
+	write32(&regs->emem_arb_rsv, param->McEmemArbRsv);
 
 	/* Program extra snap levels for display client */
-	writel(param->McDisExtraSnapLevels, &regs->dis_extra_snap_levels);
+	write32(&regs->dis_extra_snap_levels, param->McDisExtraSnapLevels);
 
 	/* Trigger MC timing update */
-	writel(MC_TIMING_CONTROL_TIMING_UPDATE, &regs->timing_control);
+	write32(&regs->timing_control, MC_TIMING_CONTROL_TIMING_UPDATE);
 
 	/* Program second-level clock enable overrides */
-	writel(param->McClkenOverride, &regs->clken_override);
+	write32(&regs->clken_override, param->McClkenOverride);
 
 	/* Program statistics gathering */
-	writel(param->McStatControl, &regs->stat_control);
+	write32(&regs->stat_control, param->McStatControl);
 }
 
 static void sdram_init_emc(const struct sdram_params *param,
 			   struct tegra_emc_regs *regs)
 {
 	/* Program SDRAM geometry parameters */
-	writel(param->EmcAdrCfg, &regs->adr_cfg);
+	write32(&regs->adr_cfg, param->EmcAdrCfg);
 
 	/* Program second-level clock enable overrides */
-	writel(param->EmcClkenOverride, &regs->clken_override);
+	write32(&regs->clken_override, param->EmcClkenOverride);
 
 	/* Program EMC pad auto calibration */
-	writel(param->EmcAutoCalInterval, &regs->auto_cal_interval);
-	writel(param->EmcAutoCalConfig2, &regs->auto_cal_config2);
-	writel(param->EmcAutoCalConfig3, &regs->auto_cal_config3);
-	writel(param->EmcAutoCalConfig, &regs->auto_cal_config);
+	write32(&regs->auto_cal_interval, param->EmcAutoCalInterval);
+	write32(&regs->auto_cal_config2, param->EmcAutoCalConfig2);
+	write32(&regs->auto_cal_config3, param->EmcAutoCalConfig3);
+	write32(&regs->auto_cal_config, param->EmcAutoCalConfig);
 	udelay(param->EmcAutoCalWait);
 }
 
@@ -249,129 +252,129 @@ static void sdram_set_emc_timing(const struct sdram_params *param,
 				 struct tegra_emc_regs *regs)
 {
 	/* Program EMC timing configuration */
-	writel(param->EmcCfg2, &regs->cfg_2);
-	writel(param->EmcCfgPipe, &regs->cfg_pipe);
-	writel(param->EmcDbg, &regs->dbg);
-	writel(param->EmcCmdQ, &regs->cmdq);
-	writel(param->EmcMc2EmcQ, &regs->mc2emcq);
-	writel(param->EmcMrsWaitCnt, &regs->mrs_wait_cnt);
-	writel(param->EmcMrsWaitCnt2, &regs->mrs_wait_cnt2);
-	writel(param->EmcFbioCfg5, &regs->fbio_cfg5);
-	writel(param->EmcRc, &regs->rc);
-	writel(param->EmcRfc, &regs->rfc);
-	writel(param->EmcRfcSlr, &regs->rfc_slr);
-	writel(param->EmcRas, &regs->ras);
-	writel(param->EmcRp, &regs->rp);
-	writel(param->EmcR2r, &regs->r2r);
-	writel(param->EmcW2w, &regs->w2w);
-	writel(param->EmcR2w, &regs->r2w);
-	writel(param->EmcW2r, &regs->w2r);
-	writel(param->EmcR2p, &regs->r2p);
-	writel(param->EmcW2p, &regs->w2p);
-	writel(param->EmcRdRcd, &regs->rd_rcd);
-	writel(param->EmcWrRcd, &regs->wr_rcd);
-	writel(param->EmcRrd, &regs->rrd);
-	writel(param->EmcRext, &regs->rext);
-	writel(param->EmcWext, &regs->wext);
-	writel(param->EmcWdv, &regs->wdv);
-	writel(param->EmcWdvMask, &regs->wdv_mask);
-	writel(param->EmcQUse, &regs->quse);
-	writel(param->EmcQuseWidth, &regs->quse_width);
-	writel(param->EmcIbdly, &regs->ibdly);
-	writel(param->EmcEInput, &regs->einput);
-	writel(param->EmcEInputDuration, &regs->einput_duration);
-	writel(param->EmcPutermExtra, &regs->puterm_extra);
-	writel(param->EmcPutermWidth, &regs->puterm_width);
-	writel(param->EmcPutermAdj, &regs->puterm_adj);
-	writel(param->EmcCdbCntl1, &regs->cdb_cntl_1);
-	writel(param->EmcCdbCntl2, &regs->cdb_cntl_2);
-	writel(param->EmcCdbCntl3, &regs->cdb_cntl_3);
-	writel(param->EmcQRst, &regs->qrst);
-	writel(param->EmcQSafe, &regs->qsafe);
-	writel(param->EmcRdv, &regs->rdv);
-	writel(param->EmcRdvMask, &regs->rdv_mask);
-	writel(param->EmcQpop, &regs->qpop);
-	writel(param->EmcCtt, &regs->ctt);
-	writel(param->EmcCttDuration, &regs->ctt_duration);
-	writel(param->EmcRefresh, &regs->refresh);
-	writel(param->EmcBurstRefreshNum, &regs->burst_refresh_num);
-	writel(param->EmcPreRefreshReqCnt, &regs->pre_refresh_req_cnt);
-	writel(param->EmcPdEx2Wr, &regs->pdex2wr);
-	writel(param->EmcPdEx2Rd, &regs->pdex2rd);
-	writel(param->EmcPChg2Pden, &regs->pchg2pden);
-	writel(param->EmcAct2Pden, &regs->act2pden);
-	writel(param->EmcAr2Pden, &regs->ar2pden);
-	writel(param->EmcRw2Pden, &regs->rw2pden);
-	writel(param->EmcTxsr, &regs->txsr);
-	writel(param->EmcTxsrDll, &regs->txsrdll);
-	writel(param->EmcTcke, &regs->tcke);
-	writel(param->EmcTckesr, &regs->tckesr);
-	writel(param->EmcTpd, &regs->tpd);
-	writel(param->EmcTfaw, &regs->tfaw);
-	writel(param->EmcTrpab, &regs->trpab);
-	writel(param->EmcTClkStable, &regs->tclkstable);
-	writel(param->EmcTClkStop, &regs->tclkstop);
-	writel(param->EmcTRefBw, &regs->trefbw);
-	writel(param->EmcOdtWrite, &regs->odt_write);
-	writel(param->EmcOdtRead, &regs->odt_read);
-	writel(param->EmcFbioCfg6, &regs->fbio_cfg6);
-	writel(param->EmcCfgDigDll, &regs->cfg_dig_dll);
-	writel(param->EmcCfgDigDllPeriod, &regs->cfg_dig_dll_period);
+	write32(&regs->cfg_2, param->EmcCfg2);
+	write32(&regs->cfg_pipe, param->EmcCfgPipe);
+	write32(&regs->dbg, param->EmcDbg);
+	write32(&regs->cmdq, param->EmcCmdQ);
+	write32(&regs->mc2emcq, param->EmcMc2EmcQ);
+	write32(&regs->mrs_wait_cnt, param->EmcMrsWaitCnt);
+	write32(&regs->mrs_wait_cnt2, param->EmcMrsWaitCnt2);
+	write32(&regs->fbio_cfg5, param->EmcFbioCfg5);
+	write32(&regs->rc, param->EmcRc);
+	write32(&regs->rfc, param->EmcRfc);
+	write32(&regs->rfc_slr, param->EmcRfcSlr);
+	write32(&regs->ras, param->EmcRas);
+	write32(&regs->rp, param->EmcRp);
+	write32(&regs->r2r, param->EmcR2r);
+	write32(&regs->w2w, param->EmcW2w);
+	write32(&regs->r2w, param->EmcR2w);
+	write32(&regs->w2r, param->EmcW2r);
+	write32(&regs->r2p, param->EmcR2p);
+	write32(&regs->w2p, param->EmcW2p);
+	write32(&regs->rd_rcd, param->EmcRdRcd);
+	write32(&regs->wr_rcd, param->EmcWrRcd);
+	write32(&regs->rrd, param->EmcRrd);
+	write32(&regs->rext, param->EmcRext);
+	write32(&regs->wext, param->EmcWext);
+	write32(&regs->wdv, param->EmcWdv);
+	write32(&regs->wdv_mask, param->EmcWdvMask);
+	write32(&regs->quse, param->EmcQUse);
+	write32(&regs->quse_width, param->EmcQuseWidth);
+	write32(&regs->ibdly, param->EmcIbdly);
+	write32(&regs->einput, param->EmcEInput);
+	write32(&regs->einput_duration, param->EmcEInputDuration);
+	write32(&regs->puterm_extra, param->EmcPutermExtra);
+	write32(&regs->puterm_width, param->EmcPutermWidth);
+	write32(&regs->puterm_adj, param->EmcPutermAdj);
+	write32(&regs->cdb_cntl_1, param->EmcCdbCntl1);
+	write32(&regs->cdb_cntl_2, param->EmcCdbCntl2);
+	write32(&regs->cdb_cntl_3, param->EmcCdbCntl3);
+	write32(&regs->qrst, param->EmcQRst);
+	write32(&regs->qsafe, param->EmcQSafe);
+	write32(&regs->rdv, param->EmcRdv);
+	write32(&regs->rdv_mask, param->EmcRdvMask);
+	write32(&regs->qpop, param->EmcQpop);
+	write32(&regs->ctt, param->EmcCtt);
+	write32(&regs->ctt_duration, param->EmcCttDuration);
+	write32(&regs->refresh, param->EmcRefresh);
+	write32(&regs->burst_refresh_num, param->EmcBurstRefreshNum);
+	write32(&regs->pre_refresh_req_cnt, param->EmcPreRefreshReqCnt);
+	write32(&regs->pdex2wr, param->EmcPdEx2Wr);
+	write32(&regs->pdex2rd, param->EmcPdEx2Rd);
+	write32(&regs->pchg2pden, param->EmcPChg2Pden);
+	write32(&regs->act2pden, param->EmcAct2Pden);
+	write32(&regs->ar2pden, param->EmcAr2Pden);
+	write32(&regs->rw2pden, param->EmcRw2Pden);
+	write32(&regs->txsr, param->EmcTxsr);
+	write32(&regs->txsrdll, param->EmcTxsrDll);
+	write32(&regs->tcke, param->EmcTcke);
+	write32(&regs->tckesr, param->EmcTckesr);
+	write32(&regs->tpd, param->EmcTpd);
+	write32(&regs->tfaw, param->EmcTfaw);
+	write32(&regs->trpab, param->EmcTrpab);
+	write32(&regs->tclkstable, param->EmcTClkStable);
+	write32(&regs->tclkstop, param->EmcTClkStop);
+	write32(&regs->trefbw, param->EmcTRefBw);
+	write32(&regs->odt_write, param->EmcOdtWrite);
+	write32(&regs->odt_read, param->EmcOdtRead);
+	write32(&regs->fbio_cfg6, param->EmcFbioCfg6);
+	write32(&regs->cfg_dig_dll, param->EmcCfgDigDll);
+	write32(&regs->cfg_dig_dll_period, param->EmcCfgDigDllPeriod);
 
 	/* Don't write bit 1: addr swizzle lock bit. Written at end of sequence. */
-	writel(param->EmcFbioSpare & 0xfffffffd, &regs->fbio_spare);
-
-	writel(param->EmcCfgRsv, &regs->cfg_rsv);
-	writel(param->EmcDllXformDqs0, &regs->dll_xform_dqs0);
-	writel(param->EmcDllXformDqs1, &regs->dll_xform_dqs1);
-	writel(param->EmcDllXformDqs2, &regs->dll_xform_dqs2);
-	writel(param->EmcDllXformDqs3, &regs->dll_xform_dqs3);
-	writel(param->EmcDllXformDqs4, &regs->dll_xform_dqs4);
-	writel(param->EmcDllXformDqs5, &regs->dll_xform_dqs5);
-	writel(param->EmcDllXformDqs6, &regs->dll_xform_dqs6);
-	writel(param->EmcDllXformDqs7, &regs->dll_xform_dqs7);
-	writel(param->EmcDllXformDqs8, &regs->dll_xform_dqs8);
-	writel(param->EmcDllXformDqs9, &regs->dll_xform_dqs9);
-	writel(param->EmcDllXformDqs10, &regs->dll_xform_dqs10);
-	writel(param->EmcDllXformDqs11, &regs->dll_xform_dqs11);
-	writel(param->EmcDllXformDqs12, &regs->dll_xform_dqs12);
-	writel(param->EmcDllXformDqs13, &regs->dll_xform_dqs13);
-	writel(param->EmcDllXformDqs14, &regs->dll_xform_dqs14);
-	writel(param->EmcDllXformDqs15, &regs->dll_xform_dqs15);
-	writel(param->EmcDllXformQUse0, &regs->dll_xform_quse0);
-	writel(param->EmcDllXformQUse1, &regs->dll_xform_quse1);
-	writel(param->EmcDllXformQUse2, &regs->dll_xform_quse2);
-	writel(param->EmcDllXformQUse3, &regs->dll_xform_quse3);
-	writel(param->EmcDllXformQUse4, &regs->dll_xform_quse4);
-	writel(param->EmcDllXformQUse5, &regs->dll_xform_quse5);
-	writel(param->EmcDllXformQUse6, &regs->dll_xform_quse6);
-	writel(param->EmcDllXformQUse7, &regs->dll_xform_quse7);
-	writel(param->EmcDllXformQUse8, &regs->dll_xform_quse8);
-	writel(param->EmcDllXformQUse9, &regs->dll_xform_quse9);
-	writel(param->EmcDllXformQUse10, &regs->dll_xform_quse10);
-	writel(param->EmcDllXformQUse11, &regs->dll_xform_quse11);
-	writel(param->EmcDllXformQUse12, &regs->dll_xform_quse12);
-	writel(param->EmcDllXformQUse13, &regs->dll_xform_quse13);
-	writel(param->EmcDllXformQUse14, &regs->dll_xform_quse14);
-	writel(param->EmcDllXformQUse15, &regs->dll_xform_quse15);
-	writel(param->EmcDllXformDq0, &regs->dll_xform_dq0);
-	writel(param->EmcDllXformDq1, &regs->dll_xform_dq1);
-	writel(param->EmcDllXformDq2, &regs->dll_xform_dq2);
-	writel(param->EmcDllXformDq3, &regs->dll_xform_dq3);
-	writel(param->EmcDllXformDq4, &regs->dll_xform_dq4);
-	writel(param->EmcDllXformDq5, &regs->dll_xform_dq5);
-	writel(param->EmcDllXformDq6, &regs->dll_xform_dq6);
-	writel(param->EmcDllXformDq7, &regs->dll_xform_dq7);
-	writel(param->EmcDllXformAddr0, &regs->dll_xform_addr0);
-	writel(param->EmcDllXformAddr1, &regs->dll_xform_addr1);
-	writel(param->EmcDllXformAddr2, &regs->dll_xform_addr2);
-	writel(param->EmcDllXformAddr3, &regs->dll_xform_addr3);
-	writel(param->EmcDllXformAddr4, &regs->dll_xform_addr4);
-	writel(param->EmcDllXformAddr5, &regs->dll_xform_addr5);
-	writel(param->EmcAcpdControl, &regs->acpd_control);
-	writel(param->EmcDsrVttgenDrv, &regs->dsr_vttgen_drv);
-	writel(param->EmcTxdsrvttgen, &regs->txdsrvttgen);
-	writel(param->EmcBgbiasCtl0, &regs->bgbias_ctl0);
+	write32(&regs->fbio_spare, param->EmcFbioSpare & 0xfffffffd);
+
+	write32(&regs->cfg_rsv, param->EmcCfgRsv);
+	write32(&regs->dll_xform_dqs0, param->EmcDllXformDqs0);
+	write32(&regs->dll_xform_dqs1, param->EmcDllXformDqs1);
+	write32(&regs->dll_xform_dqs2, param->EmcDllXformDqs2);
+	write32(&regs->dll_xform_dqs3, param->EmcDllXformDqs3);
+	write32(&regs->dll_xform_dqs4, param->EmcDllXformDqs4);
+	write32(&regs->dll_xform_dqs5, param->EmcDllXformDqs5);
+	write32(&regs->dll_xform_dqs6, param->EmcDllXformDqs6);
+	write32(&regs->dll_xform_dqs7, param->EmcDllXformDqs7);
+	write32(&regs->dll_xform_dqs8, param->EmcDllXformDqs8);
+	write32(&regs->dll_xform_dqs9, param->EmcDllXformDqs9);
+	write32(&regs->dll_xform_dqs10, param->EmcDllXformDqs10);
+	write32(&regs->dll_xform_dqs11, param->EmcDllXformDqs11);
+	write32(&regs->dll_xform_dqs12, param->EmcDllXformDqs12);
+	write32(&regs->dll_xform_dqs13, param->EmcDllXformDqs13);
+	write32(&regs->dll_xform_dqs14, param->EmcDllXformDqs14);
+	write32(&regs->dll_xform_dqs15, param->EmcDllXformDqs15);
+	write32(&regs->dll_xform_quse0, param->EmcDllXformQUse0);
+	write32(&regs->dll_xform_quse1, param->EmcDllXformQUse1);
+	write32(&regs->dll_xform_quse2, param->EmcDllXformQUse2);
+	write32(&regs->dll_xform_quse3, param->EmcDllXformQUse3);
+	write32(&regs->dll_xform_quse4, param->EmcDllXformQUse4);
+	write32(&regs->dll_xform_quse5, param->EmcDllXformQUse5);
+	write32(&regs->dll_xform_quse6, param->EmcDllXformQUse6);
+	write32(&regs->dll_xform_quse7, param->EmcDllXformQUse7);
+	write32(&regs->dll_xform_quse8, param->EmcDllXformQUse8);
+	write32(&regs->dll_xform_quse9, param->EmcDllXformQUse9);
+	write32(&regs->dll_xform_quse10, param->EmcDllXformQUse10);
+	write32(&regs->dll_xform_quse11, param->EmcDllXformQUse11);
+	write32(&regs->dll_xform_quse12, param->EmcDllXformQUse12);
+	write32(&regs->dll_xform_quse13, param->EmcDllXformQUse13);
+	write32(&regs->dll_xform_quse14, param->EmcDllXformQUse14);
+	write32(&regs->dll_xform_quse15, param->EmcDllXformQUse15);
+	write32(&regs->dll_xform_dq0, param->EmcDllXformDq0);
+	write32(&regs->dll_xform_dq1, param->EmcDllXformDq1);
+	write32(&regs->dll_xform_dq2, param->EmcDllXformDq2);
+	write32(&regs->dll_xform_dq3, param->EmcDllXformDq3);
+	write32(&regs->dll_xform_dq4, param->EmcDllXformDq4);
+	write32(&regs->dll_xform_dq5, param->EmcDllXformDq5);
+	write32(&regs->dll_xform_dq6, param->EmcDllXformDq6);
+	write32(&regs->dll_xform_dq7, param->EmcDllXformDq7);
+	write32(&regs->dll_xform_addr0, param->EmcDllXformAddr0);
+	write32(&regs->dll_xform_addr1, param->EmcDllXformAddr1);
+	write32(&regs->dll_xform_addr2, param->EmcDllXformAddr2);
+	write32(&regs->dll_xform_addr3, param->EmcDllXformAddr3);
+	write32(&regs->dll_xform_addr4, param->EmcDllXformAddr4);
+	write32(&regs->dll_xform_addr5, param->EmcDllXformAddr5);
+	write32(&regs->acpd_control, param->EmcAcpdControl);
+	write32(&regs->dsr_vttgen_drv, param->EmcDsrVttgenDrv);
+	write32(&regs->txdsrvttgen, param->EmcTxdsrvttgen);
+	write32(&regs->bgbias_ctl0, param->EmcBgbiasCtl0);
 
 	/*
 	 * Set pipe bypass enable bits before sending any DRAM commands.
@@ -391,8 +394,8 @@ static void sdram_patch_bootrom(const struct sdram_params *param,
 				  BOOT_ROM_PATCH_CONTROL_OFFSET_MASK) >>
 				  BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT);
 		addr = BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS + (addr << 2);
-		writel(param->BootRomPatchData, (uint32_t *)addr);
-		writel(1, &regs->timing_control);
+		write32((uint32_t *)addr, param->BootRomPatchData);
+		write32(&regs->timing_control, 1);
 	}
 }
 
@@ -400,7 +403,7 @@ static void sdram_set_dpd3(const struct sdram_params *param,
 			   struct tegra_pmc_regs *regs)
 {
 	/* Program DPD request */
-	writel(param->PmcIoDpd3Req, &regs->io_dpd3_req);
+	write32(&regs->io_dpd3_req, param->PmcIoDpd3Req);
 	udelay(param->PmcIoDpd3ReqWait);
 }
 
@@ -408,27 +411,27 @@ static void sdram_set_dli_trims(const struct sdram_params *param,
 				struct tegra_emc_regs *regs)
 {
 	/* Program DLI trims */
-	writel(param->EmcDliTrimTxDqs0, &regs->dli_trim_txdqs0);
-	writel(param->EmcDliTrimTxDqs1, &regs->dli_trim_txdqs1);
-	writel(param->EmcDliTrimTxDqs2, &regs->dli_trim_txdqs2);
-	writel(param->EmcDliTrimTxDqs3, &regs->dli_trim_txdqs3);
-	writel(param->EmcDliTrimTxDqs4, &regs->dli_trim_txdqs4);
-	writel(param->EmcDliTrimTxDqs5, &regs->dli_trim_txdqs5);
-	writel(param->EmcDliTrimTxDqs6, &regs->dli_trim_txdqs6);
-	writel(param->EmcDliTrimTxDqs7, &regs->dli_trim_txdqs7);
-	writel(param->EmcDliTrimTxDqs8, &regs->dli_trim_txdqs8);
-	writel(param->EmcDliTrimTxDqs9, &regs->dli_trim_txdqs9);
-	writel(param->EmcDliTrimTxDqs10, &regs->dli_trim_txdqs10);
-	writel(param->EmcDliTrimTxDqs11, &regs->dli_trim_txdqs11);
-	writel(param->EmcDliTrimTxDqs12, &regs->dli_trim_txdqs12);
-	writel(param->EmcDliTrimTxDqs13, &regs->dli_trim_txdqs13);
-	writel(param->EmcDliTrimTxDqs14, &regs->dli_trim_txdqs14);
-	writel(param->EmcDliTrimTxDqs15, &regs->dli_trim_txdqs15);
-
-	writel(param->EmcCaTrainingTimingCntl1,
-	       &regs->ca_training_timing_cntl1);
-	writel(param->EmcCaTrainingTimingCntl2,
-	       &regs->ca_training_timing_cntl2);
+	write32(&regs->dli_trim_txdqs0, param->EmcDliTrimTxDqs0);
+	write32(&regs->dli_trim_txdqs1, param->EmcDliTrimTxDqs1);
+	write32(&regs->dli_trim_txdqs2, param->EmcDliTrimTxDqs2);
+	write32(&regs->dli_trim_txdqs3, param->EmcDliTrimTxDqs3);
+	write32(&regs->dli_trim_txdqs4, param->EmcDliTrimTxDqs4);
+	write32(&regs->dli_trim_txdqs5, param->EmcDliTrimTxDqs5);
+	write32(&regs->dli_trim_txdqs6, param->EmcDliTrimTxDqs6);
+	write32(&regs->dli_trim_txdqs7, param->EmcDliTrimTxDqs7);
+	write32(&regs->dli_trim_txdqs8, param->EmcDliTrimTxDqs8);
+	write32(&regs->dli_trim_txdqs9, param->EmcDliTrimTxDqs9);
+	write32(&regs->dli_trim_txdqs10, param->EmcDliTrimTxDqs10);
+	write32(&regs->dli_trim_txdqs11, param->EmcDliTrimTxDqs11);
+	write32(&regs->dli_trim_txdqs12, param->EmcDliTrimTxDqs12);
+	write32(&regs->dli_trim_txdqs13, param->EmcDliTrimTxDqs13);
+	write32(&regs->dli_trim_txdqs14, param->EmcDliTrimTxDqs14);
+	write32(&regs->dli_trim_txdqs15, param->EmcDliTrimTxDqs15);
+
+	write32(&regs->ca_training_timing_cntl1,
+		param->EmcCaTrainingTimingCntl1);
+	write32(&regs->ca_training_timing_cntl2,
+		param->EmcCaTrainingTimingCntl2);
 
 	sdram_trigger_emc_timing_update(regs);
 	udelay(param->EmcTimingControlWait);
@@ -444,7 +447,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param,
 	 * Assert dummy read of PIN register to ensure above write to PIN
 	 * register went through. 200 is the recommended value by NVIDIA.
 	 */
-	dummy |= readl(&regs->pin);
+	dummy |= read32(&regs->pin);
 	udelay(200 + param->EmcPinExtraWait);
 
 	/* Deassert reset */
@@ -453,7 +456,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param,
 	 * Assert dummy read of PIN register to ensure above write to PIN
 	 * register went through. 200 is the recommended value by NVIDIA.
 	 */
-	dummy |= readl(&regs->pin);
+	dummy |= read32(&regs->pin);
 	udelay(500 + param->EmcPinExtraWait);
 
 	/* Enable clock enable signal */
@@ -462,7 +465,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param,
 	 * Assert dummy read of PIN register to ensure above write to PIN
 	 * register went through. 200 is the recommended value by NVIDIA.
 	 */
-	dummy |= readl(&regs->pin);
+	dummy |= read32(&regs->pin);
 	udelay(param->EmcPinProgramWait);
 
 	if (!dummy) {
@@ -479,20 +482,20 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param,
 static void sdram_init_ddr3(const struct sdram_params *param, struct tegra_emc_regs *regs)
 {
 	/* Write mode registers */
-	writel(param->EmcEmrs2, &regs->emrs2);
-	writel(param->EmcEmrs3, &regs->emrs3);
-	writel(param->EmcEmrs, &regs->emrs);
-	writel(param->EmcMrs, &regs->mrs);
+	write32(&regs->emrs2, param->EmcEmrs2);
+	write32(&regs->emrs3, param->EmcEmrs3);
+	write32(&regs->emrs, param->EmcEmrs);
+	write32(&regs->mrs, param->EmcMrs);
 
 	if (param->EmcExtraModeRegWriteEnable) {
-		writel(param->EmcMrsExtra, &regs->mrs);
+		write32(&regs->mrs, param->EmcMrsExtra);
 	}
 
-	writel(param->EmcZcalInitDev0, &regs->zq_cal);
+	write32(&regs->zq_cal, param->EmcZcalInitDev0);
 	udelay(param->EmcZcalInitWait);
 
 	if ((param->EmcDevSelect & 2) == 0) {
-		writel(param->EmcZcalInitDev1, &regs->zq_cal);
+		write32(&regs->zq_cal, param->EmcZcalInitDev1);
 		udelay(param->EmcZcalInitWait);
 	}
 }
@@ -500,29 +503,30 @@ static void sdram_init_ddr3(const struct sdram_params *param, struct tegra_emc_r
 static void sdram_init_lpddr3(const struct sdram_params *param, struct tegra_emc_regs *regs)
 {
 	/* Precharge all banks. DEV_SELECTN = 0 => Select all devices */
-	writel(((param->EmcDevSelect << EMC_REF_DEV_SELECTN_SHIFT) | 1), &regs->pre);
+	write32(&regs->pre,
+		((param->EmcDevSelect << EMC_REF_DEV_SELECTN_SHIFT) | 1));
 
 	/* Send Reset MRW command */
-	writel(param->EmcMrwResetCommand, &regs->mrw);
+	write32(&regs->mrw, param->EmcMrwResetCommand);
 	udelay(param->EmcMrwResetNInitWait);
 
-	writel(param->EmcZcalInitDev0, &regs->mrw);
+	write32(&regs->mrw, param->EmcZcalInitDev0);
 	udelay(param->EmcZcalInitWait);
 
 	if ((param->EmcDevSelect & 2) == 0)
 	{
-		writel(param->EmcZcalInitDev1, &regs->mrw);
+		write32(&regs->mrw, param->EmcZcalInitDev1);
 		udelay(param->EmcZcalInitWait);
 	}
 
 	/* Write mode registers */
-	writel(param->EmcMrw2, &regs->mrw2);
-	writel(param->EmcMrw1, &regs->mrw);
-	writel(param->EmcMrw3, &regs->mrw3);
-	writel(param->EmcMrw4, &regs->mrw4);
+	write32(&regs->mrw2, param->EmcMrw2);
+	write32(&regs->mrw, param->EmcMrw1);
+	write32(&regs->mrw3, param->EmcMrw3);
+	write32(&regs->mrw4, param->EmcMrw4);
 
 	if (param->EmcExtraModeRegWriteEnable) {
-		writel(param->EmcMrwExtra, &regs->mrw);
+		write32(&regs->mrw, param->EmcMrwExtra);
 	}
 }
 
@@ -546,9 +550,9 @@ static void sdram_set_zq_calibration(const struct sdram_params *param,
 				     struct tegra_emc_regs *regs)
 {
 	/* Start periodic ZQ calibration */
-	writel(param->EmcZcalInterval, &regs->zcal_interval);
-	writel(param->EmcZcalWaitCnt, &regs->zcal_wait_cnt);
-	writel(param->EmcZcalMrwCmd, &regs->zcal_mrw_cmd);
+	write32(&regs->zcal_interval, param->EmcZcalInterval);
+	write32(&regs->zcal_wait_cnt, param->EmcZcalWaitCnt);
+	write32(&regs->zcal_mrw_cmd, param->EmcZcalMrwCmd);
 }
 
 static void sdram_set_refresh(const struct sdram_params *param,
@@ -566,15 +570,15 @@ static void sdram_set_refresh(const struct sdram_params *param,
 	}
 
 	/* Enable refresh */
-	writel((param->EmcDevSelect | EMC_REFCTRL_REF_VALID_ENABLED),
-	       &regs->refctrl);
+	write32(&regs->refctrl,
+		(param->EmcDevSelect | EMC_REFCTRL_REF_VALID_ENABLED));
 
-	writel(param->EmcDynSelfRefControl, &regs->dyn_self_ref_control);
-	writel(param->EmcCfg, &regs->cfg);
-	writel(param->EmcSelDpdCtrl, &regs->sel_dpd_ctrl);
+	write32(&regs->dyn_self_ref_control, param->EmcDynSelfRefControl);
+	write32(&regs->cfg, param->EmcCfg);
+	write32(&regs->sel_dpd_ctrl, param->EmcSelDpdCtrl);
 
 	/* Write addr swizzle lock bit */
-	writel(param->EmcFbioSpare, &regs->fbio_spare);
+	write32(&regs->fbio_spare, param->EmcFbioSpare);
 
 	/* Re-trigger timing to latch power saving functions */
 	sdram_trigger_emc_timing_update(regs);
@@ -592,12 +596,13 @@ static void sdram_lock_carveouts(const struct sdram_params *param,
 				 struct tegra_mc_regs *regs)
 {
 	/* Lock carveouts, and emem_cfg registers */
-	writel(param->McVideoProtectWriteAccess, &regs->video_protect_reg_ctrl);
-	writel(MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED,
-	       &regs->emem_cfg_access_ctrl);
-	writel(param->McSecCarveoutProtectWriteAccess,
-	       &regs->sec_carveout_reg_ctrl);
-	writel(param->McMtsCarveoutRegCtrl, &regs->mts_carveout_reg_ctrl);
+	write32(&regs->video_protect_reg_ctrl,
+		param->McVideoProtectWriteAccess);
+	write32(&regs->emem_cfg_access_ctrl,
+		MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED);
+	write32(&regs->sec_carveout_reg_ctrl,
+		param->McSecCarveoutProtectWriteAccess);
+	write32(&regs->mts_carveout_reg_ctrl, param->McMtsCarveoutRegCtrl);
 }
 
 void sdram_init(const struct sdram_params *param)
@@ -653,7 +658,7 @@ void sdram_init(const struct sdram_params *param)
 uint32_t sdram_get_ram_code(void)
 {
 	struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE;
-	return ((readl(&pmc->strapping_opt_a) &
+	return ((read32(&pmc->strapping_opt_a) &
 		 PMC_STRAPPING_OPT_A_RAM_CODE_MASK) >>
 		PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT);
 }
diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c
index 7923f7e3cd..1003ca53a8 100644
--- a/src/soc/nvidia/tegra132/soc.c
+++ b/src/soc/nvidia/tegra132/soc.c
@@ -83,9 +83,9 @@ static void lock_down_vpr(void)
 {
 	struct tegra_mc_regs *regs = (void *)(uintptr_t)TEGRA_MC_BASE;
 
-	writel(0, &regs->video_protect_bom);
-	writel(0, &regs->video_protect_size_mb);
-	writel(1, &regs->video_protect_reg_ctrl);
+	write32(&regs->video_protect_bom, 0);
+	write32(&regs->video_protect_size_mb, 0);
+	write32(&regs->video_protect_reg_ctrl, 1);
 }
 
 static void soc_init(device_t dev)
diff --git a/src/soc/nvidia/tegra132/spi.c b/src/soc/nvidia/tegra132/spi.c
index e240700f06..33620fb202 100644
--- a/src/soc/nvidia/tegra132/spi.c
+++ b/src/soc/nvidia/tegra132/spi.c
@@ -230,7 +230,7 @@ int spi_claim_bus(struct spi_slave *slave)
 	else
 		val |= SPI_CMD1_CS_SW_VAL;
 
-	writel(val, &regs->command1);
+	write32(&regs->command1, val);
 	return 0;
 }
 
@@ -246,7 +246,7 @@ void spi_release_bus(struct spi_slave *slave)
 	else
 		val &= ~SPI_CMD1_CS_SW_VAL;
 
-	writel(val, &regs->command1);
+	write32(&regs->command1, val);
 }
 
 static void dump_fifo_status(struct tegra_spi_channel *spi)
@@ -383,12 +383,12 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi,
 
 	/* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and
 	 * PIO transfers */
-	writel(todo - 1, &spi->regs->dma_blk);
+	write32(&spi->regs->dma_blk, todo - 1);
 
 	if (dir == SPI_SEND) {
 		unsigned int to_fifo = bytes;
 		while (to_fifo) {
-			writel(*p, &spi->regs->tx_fifo);
+			write32(&spi->regs->tx_fifo, *p);
 			p++;
 			to_fifo--;
 		}
@@ -493,12 +493,12 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
 		/* ensure bytes to send will be visible to DMA controller */
 		dcache_clean_by_mva(spi->out_buf, bytes);
 
-		writel((uintptr_t) & spi->regs->tx_fifo,
-		       &spi->dma_out->regs->apb_ptr);
-		writel((uintptr_t)spi->out_buf, &spi->dma_out->regs->ahb_ptr);
+		write32(&spi->dma_out->regs->apb_ptr,
+			(uintptr_t) & spi->regs->tx_fifo);
+		write32(&spi->dma_out->regs->ahb_ptr, (uintptr_t)spi->out_buf);
 		setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR);
 		setup_dma_params(spi, spi->dma_out);
-		writel(wcount, &spi->dma_out->regs->wcount);
+		write32(&spi->dma_out->regs->wcount, wcount);
 	} else {
 		spi->dma_in = dma_claim();
 		if (!spi->dma_in)
@@ -507,16 +507,16 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
 		/* avoid data collisions */
 		dcache_clean_invalidate_by_mva(spi->in_buf, bytes);
 
-		writel((uintptr_t)&spi->regs->rx_fifo,
-		       &spi->dma_in->regs->apb_ptr);
-		writel((uintptr_t)spi->in_buf, &spi->dma_in->regs->ahb_ptr);
+		write32(&spi->dma_in->regs->apb_ptr,
+			(uintptr_t)&spi->regs->rx_fifo);
+		write32(&spi->dma_in->regs->ahb_ptr, (uintptr_t)spi->in_buf);
 		clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR);
 		setup_dma_params(spi, spi->dma_in);
-		writel(wcount, &spi->dma_in->regs->wcount);
+		write32(&spi->dma_in->regs->wcount, wcount);
 	}
 
 	/* BLOCK_SIZE starts at n-1 */
-	writel(todo - 1, &spi->regs->dma_blk);
+	write32(&spi->regs->dma_blk, todo - 1);
 	return todo;
 }
 
diff --git a/src/soc/nvidia/tegra132/uart.c b/src/soc/nvidia/tegra132/uart.c
index 90765e1496..e7b7ca9f69 100644
--- a/src/soc/nvidia/tegra132/uart.c
+++ b/src/soc/nvidia/tegra132/uart.c
@@ -63,19 +63,19 @@ static void tegra132_uart_init(struct tegra132_uart *uart_ptr)
 	tegra132_uart_tx_flush(uart_ptr);
 
 	// Disable interrupts.
-	writeb(0, &uart_ptr->ier);
+	write8(&uart_ptr->ier, 0);
 	// Force DTR and RTS to high.
-	writeb(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr);
+	write8(&uart_ptr->mcr, UART8250_MCR_DTR | UART8250_MCR_RTS);
 	// Set line configuration, access divisor latches.
-	writeb(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr);
+	write8(&uart_ptr->lcr, UART8250_LCR_DLAB | line_config);
 	// Set the divisor.
-	writeb(divisor & 0xff, &uart_ptr->dll);
-	writeb((divisor >> 8) & 0xff, &uart_ptr->dlm);
+	write8(&uart_ptr->dll, divisor & 0xff);
+	write8(&uart_ptr->dlm, (divisor >> 8) & 0xff);
 	// Hide the divisor latches.
-	writeb(line_config, &uart_ptr->lcr);
+	write8(&uart_ptr->lcr, line_config);
 	// Enable FIFOs, and clear receive and transmit.
-	writeb(UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT,
-	       &uart_ptr->fcr);
+	write8(&uart_ptr->fcr,
+	       UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT);
 }
 
 static unsigned char tegra132_uart_rx_byte(struct tegra132_uart *uart_ptr)
@@ -88,7 +88,7 @@ static unsigned char tegra132_uart_rx_byte(struct tegra132_uart *uart_ptr)
 static void tegra132_uart_tx_byte(struct tegra132_uart *uart_ptr, unsigned char data)
 {
 	while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE));
-	writeb(data, &uart_ptr->thr);
+	write8(&uart_ptr->thr, data);
 }
 
 static void tegra132_uart_tx_flush(struct tegra132_uart *uart_ptr)