diff options
| author | Julius Werner <jwerner@chromium.org> | 2015-02-19 14:51:15 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-21 08:22:28 +0200 |
| commit | 2f37bd65518865688b9234afce0d467508d6f465 (patch) | |
| tree | eba5ed799de966299602b30c70d51dd40eaadd73 /src/soc | |
| parent | 1f60f971fc89ef841e81b978964b38278d597b1d (diff) | |
arm(64): Globally replace writel(v, a) with write32(a, v)
This patch is a raw application of the following spatch to src/:
@@
expression A, V;
@@
- writel(V, A)
+ write32(A, V)
@@
expression A, V;
@@
- writew(V, A)
+ write16(A, V)
@@
expression A, V;
@@
- writeb(V, A)
+ write8(A, V)
@@
expression A;
@@
- readl(A)
+ read32(A)
@@
expression A;
@@
- readb(A)
+ read8(A)
BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)
Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6
Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254864
Reviewed-on: http://review.coreboot.org/9836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc')
85 files changed, 2225 insertions, 2359 deletions
diff --git a/src/soc/broadcom/cygnus/timer.c b/src/soc/broadcom/cygnus/timer.c index 5116389778..bde1e3bfc7 100644 --- a/src/soc/broadcom/cygnus/timer.c +++ b/src/soc/broadcom/cygnus/timer.c @@ -49,9 +49,9 @@ static inline uint64_t timer_raw_value(void) uint32_t count_l; do { - count_h = readl(&timer_ptr->gtim_glob_hi); - count_l = readl(&timer_ptr->gtim_glob_low); - cur_tick = readl(&timer_ptr->gtim_glob_hi); + count_h = read32(&timer_ptr->gtim_glob_hi); + count_l = read32(&timer_ptr->gtim_glob_low); + cur_tick = read32(&timer_ptr->gtim_glob_hi); } while (cur_tick != count_h); return (cur_tick << 32) + count_l; @@ -64,8 +64,8 @@ void timer_monotonic_get(struct mono_time *mt) void init_timer(void) { - writel(TIMER_GLB_TIM_CTRL_PRESC, &timer_ptr->gtim_glob_ctrl); - writel(0, &timer_ptr->gtim_glob_low); - writel(0, &timer_ptr->gtim_glob_hi); - writel(TIMER_GLB_TIM_CTRL_TIM_EN, &timer_ptr->gtim_glob_ctrl); + write32(&timer_ptr->gtim_glob_ctrl, TIMER_GLB_TIM_CTRL_PRESC); + write32(&timer_ptr->gtim_glob_low, 0); + write32(&timer_ptr->gtim_glob_hi, 0); + write32(&timer_ptr->gtim_glob_ctrl, TIMER_GLB_TIM_CTRL_TIM_EN); } diff --git a/src/soc/nvidia/tegra/apbmisc.c b/src/soc/nvidia/tegra/apbmisc.c index 292d21d02f..3f7df5bd0e 100644 --- a/src/soc/nvidia/tegra/apbmisc.c +++ b/src/soc/nvidia/tegra/apbmisc.c @@ -26,12 +26,12 @@ static struct apbmisc *misc = (struct apbmisc *)TEGRA_APB_MISC_BASE; void enable_jtag(void) { - writel(PP_CONFIG_CTL_JTAG, &misc->pp_config_ctl); + write32(&misc->pp_config_ctl, PP_CONFIG_CTL_JTAG); } void clamp_tristate_inputs(void) { - writel(PP_PINMUX_CLAMP_INPUTS, &misc->pp_pinmux_global); + write32(&misc->pp_pinmux_global, PP_PINMUX_CLAMP_INPUTS); } void tegra_revision_info(struct tegra_revision *id) diff --git a/src/soc/nvidia/tegra/gpio.c b/src/soc/nvidia/tegra/gpio.c index 8179580add..e0561c057d 100644 --- a/src/soc/nvidia/tegra/gpio.c +++ b/src/soc/nvidia/tegra/gpio.c @@ -67,8 +67,8 @@ static void gpio_write_port(int index, size_t offset, u32 mask, u32 value) u32 new_reg = (reg & ~mask) | (value & mask); if (new_reg != reg) { - writel(new_reg, - (u8 *)&gpio_banks[bank] + offset + port * sizeof(u32)); + write32((u8 *)&gpio_banks[bank] + offset + port * sizeof(u32), + new_reg); } } diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c index b9a5f42a37..1d5df3c342 100644 --- a/src/soc/nvidia/tegra/i2c.c +++ b/src/soc/nvidia/tegra/i2c.c @@ -40,9 +40,9 @@ static void do_bus_clear(int bus) // 4. Set TERMINATE condition (1 = IMMEDIATE) bc = read32(®s->bus_clear_config); bc |= I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_IMMEDIATE; - writel(bc, ®s->bus_clear_config); + write32(®s->bus_clear_config, bc); // 4.1 Set MSTR_CONFIG_LOAD and wait for clear - writel(I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE, ®s->config_load); + write32(®s->config_load, I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE); for (i = 0; i < timeout_ms * 10 && (read32(®s->config_load) & I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE); i++) { printk(BIOS_DEBUG, "%s: wait for MSTR_CONFIG_LOAD to clear\n", @@ -50,7 +50,7 @@ static void do_bus_clear(int bus) udelay(100); } // 5. Set ENABLE to start the bus clear op - writel(bc | I2C_BUS_CLEAR_CONFIG_BC_ENABLE, ®s->bus_clear_config); + write32(®s->bus_clear_config, bc | I2C_BUS_CLEAR_CONFIG_BC_ENABLE); for (i = 0; i < timeout_ms * 10 && (read32(®s->bus_clear_config) & I2C_BUS_CLEAR_CONFIG_BC_ENABLE); i++) { printk(BIOS_DEBUG, "%s: wait for bus clear completion\n", @@ -74,7 +74,7 @@ static int tegra_i2c_send_recv(int bus, int read, rx_full >>= I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT; while (header_words && tx_empty) { - writel(*headers++, ®s->tx_packet_fifo); + write32(®s->tx_packet_fifo, *headers++); header_words--; tx_empty--; } @@ -96,7 +96,7 @@ static int tegra_i2c_send_recv(int bus, int read, int todo = MIN(data_len, sizeof(word)); memcpy(&word, data, todo); - writel(word, ®s->tx_packet_fifo); + write32(®s->tx_packet_fifo, word); data_len -= todo; data += sizeof(word); tx_empty--; @@ -208,5 +208,5 @@ void i2c_init(unsigned bus) { struct tegra_i2c_regs * const regs = tegra_i2c_info[bus].base; - writel(I2C_CNFG_PACKET_MODE_EN, ®s->cnfg); + write32(®s->cnfg, I2C_CNFG_PACKET_MODE_EN); } diff --git a/src/soc/nvidia/tegra/pingroup.c b/src/soc/nvidia/tegra/pingroup.c index c856c173ac..332e05aeaa 100644 --- a/src/soc/nvidia/tegra/pingroup.c +++ b/src/soc/nvidia/tegra/pingroup.c @@ -26,7 +26,7 @@ static uint32_t *pingroup_regs = (void *)TEGRA_APB_PINGROUP_BASE; void pingroup_set_config(int group_index, uint32_t config) { - writel(config, &pingroup_regs[group_index]); + write32(&pingroup_regs[group_index], config); } uint32_t pingroup_get_config(int group_index) diff --git a/src/soc/nvidia/tegra/pinmux.c b/src/soc/nvidia/tegra/pinmux.c index a88a063cac..f28b0266e7 100644 --- a/src/soc/nvidia/tegra/pinmux.c +++ b/src/soc/nvidia/tegra/pinmux.c @@ -26,7 +26,7 @@ static uint32_t *pinmux_regs = (void *)TEGRA_APB_PINMUX_BASE; void pinmux_set_config(int pin_index, uint32_t config) { - writel(config, &pinmux_regs[pin_index]); + write32(&pinmux_regs[pin_index], config); } uint32_t pinmux_get_config(int pin_index) diff --git a/src/soc/nvidia/tegra/usb.c b/src/soc/nvidia/tegra/usb.c index c666c40f3b..4a069fa02e 100644 --- a/src/soc/nvidia/tegra/usb.c +++ b/src/soc/nvidia/tegra/usb.c @@ -126,7 +126,7 @@ static void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type t { int timeout = 1000; - writel(1 << 1, &usb->ehci_usbcmd); /* Host Controller Reset */ + write32(&usb->ehci_usbcmd, 1 << 1); /* Host Controller Reset */ /* TODO: Resets are long, find way to parallelize... or just use XHCI */ while (--timeout && (read32(&usb->ehci_usbcmd) & 1 << 1)) /* wait for HC to reset */; @@ -137,11 +137,11 @@ static void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type t } /* Controller mode: HOST */ - writel(3 << 0, &usb->usb_mode); + write32(&usb->usb_mode, 3 << 0); /* Parallel transceiver selct */ - writel(type << 29, &usb->lpm_ctrl); + write32(&usb->lpm_ctrl, type << 29); /* Tx FIFO Burst thresh */ - writel(0x10 << 16, &usb->tx_fill_tuning); + write32(&usb->tx_fill_tuning, 0x10 << 16); } /* Assume USBx clocked, out of reset, UTMI+ PLL set up, SAMP_x out of pwrdn */ @@ -157,27 +157,27 @@ void usb_setup_utmip(void *usb_base) udelay(1); /* Take stuff out of pwrdn and add some magic numbers from U-Boot */ - writel(0x8 << 25 | 0x3 << 22 | 0 << 21 | 0 << 18 | 0 << 16 | 0 << 14 | 1 << 13 | 0x1 << 10 | 0x1 << 8 | 0x4 << 0 | 0, - &usb->utmip.xcvr0); - writel(0x7 << 18 | 0 << 4 | 0 << 2 | 0 << 0 | 0, &usb->utmip.xcvr1); - writel(1 << 19 | 1 << 16 | 1 << 9 | 0, &usb->utmip.tx); - writel(0x2 << 30 | 1 << 28 | 0x1 << 24 | 0x3 << 21 | 0x11 << 15 | 0x10 << 10 | 0, - &usb->utmip.hsrx0); + write32(&usb->utmip.xcvr0, + 0x8 << 25 | 0x3 << 22 | 0 << 21 | 0 << 18 | 0 << 16 | 0 << 14 | 1 << 13 | 0x1 << 10 | 0x1 << 8 | 0x4 << 0 | 0); + write32(&usb->utmip.xcvr1, 0x7 << 18 | 0 << 4 | 0 << 2 | 0 << 0 | 0); + write32(&usb->utmip.tx, 1 << 19 | 1 << 16 | 1 << 9 | 0); + write32(&usb->utmip.hsrx0, + 0x2 << 30 | 1 << 28 | 0x1 << 24 | 0x3 << 21 | 0x11 << 15 | 0x10 << 10 | 0); /* U-Boot claims the USBD values for these are used across all UTMI+ * PHYs. That sounds so horribly wrong that I'm not going to implement * it, but keep it in mind if we're ever not using the USBD port. */ - writel(0x1 << 24 | 1 << 23 | 1 << 22 | 1 << 11 | 0 << 10 | 0x1 << 2 | 0x2 << 0 | 0, - &usb->utmip.bias0); + write32(&usb->utmip.bias0, + 0x1 << 24 | 1 << 23 | 1 << 22 | 1 << 11 | 0 << 10 | 0x1 << 2 | 0x2 << 0 | 0); - writel(khz / 2200 << 3 | 1 << 2 | 0 << 0 | 0, &usb->utmip.bias1); + write32(&usb->utmip.bias1, khz / 2200 << 3 | 1 << 2 | 0 << 0 | 0); - writel(0xffff << 16 | 25 * khz / 10 << 0 | 0, &usb->utmip.debounce); + write32(&usb->utmip.debounce, 0xffff << 16 | 25 * khz / 10 << 0 | 0); udelay(1); setbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */ - writel(1 << 12 | 0 << 11 | 0, &usb->suspend_ctrl); + write32(&usb->suspend_ctrl, 1 << 12 | 0 << 11 | 0); usb_ehci_reset_and_prepare(usb, USB_PHY_UTMIP); printk(BIOS_DEBUG, "USB controller @ %p set up with UTMI+ PHY\n",usb_base); diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index dc1d1dbe8a..1d124b220f 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -163,7 +163,7 @@ struct { */ static u32 clock_get_osc_bits(void) { - return (readl(&clk_rst->osc_ctrl) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; + return (read32(&clk_rst->osc_ctrl) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; } int clock_get_osc_khz(void) @@ -173,7 +173,7 @@ int clock_get_osc_khz(void) int clock_get_pll_input_khz(void) { - u32 osc_ctrl = readl(&clk_rst->osc_ctrl); + u32 osc_ctrl = read32(&clk_rst->osc_ctrl); u32 osc_bits = (osc_ctrl & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; u32 pll_ref_div = (osc_ctrl & OSC_PREDIV_MASK) >> OSC_PREDIV_SHIFT; return osc_table[osc_bits].khz >> pll_ref_div; @@ -186,11 +186,11 @@ void clock_init_arm_generic_timer(void) set_cntfrq(freq); // Record the system timer frequency. - writel(freq, &sysctr->cntfid0); + write32(&sysctr->cntfid0, freq); // Enable the system counter. uint32_t cntcr = read32(&sysctr->cntcr); cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG; - writel(cntcr, &sysctr->cntcr); + write32(&sysctr->cntcr, cntcr); } #define SOR0_CLK_SEL0 (1 << 14) @@ -221,18 +221,18 @@ static void init_pll(u32 *base, u32 *misc, const union pll_fields pll, u32 lock) pll.div.lfcon << PLL_MISC_LFCON_SHIFT; /* Write dividers but BYPASS the PLL while we're messing with it. */ - writel(dividers | PLL_BASE_BYPASS, base); + write32(base, dividers | PLL_BASE_BYPASS); /* * Set Lock bit, CPCON and LFCON fields (default to 0 if it doesn't * exist for this PLL) */ - writel(lock | misc_con, misc); + write32(misc, lock | misc_con); /* Enable PLL and take it back out of BYPASS */ - writel(dividers | PLL_BASE_ENABLE, base); + write32(base, dividers | PLL_BASE_ENABLE); /* Wait for lock ready */ - while (!(readl(base) & PLL_BASE_LOCK)); + while (!(read32(base) & PLL_BASE_LOCK)); } static void init_utmip_pll(void) @@ -243,14 +243,14 @@ static void init_utmip_pll(void) clrbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ udelay(1); - writel(80 << 16 | 1 << 8 | 0, &clk_rst->utmip_pll_cfg0); /* 960MHz * 1 / 80 == 12 MHz */ + write32(&clk_rst->utmip_pll_cfg0, 80 << 16 | 1 << 8 | 0); /* 960MHz * 1 / 80 == 12 MHz */ - writel(CEIL_DIV(khz, 8000) << 27 | 0 << 16 | 0 << 14 | 0 << 12 | CEIL_DIV(khz, 102) << 0 | 0, - &clk_rst->utmip_pll_cfg1); + write32(&clk_rst->utmip_pll_cfg1, + CEIL_DIV(khz, 8000) << 27 | 0 << 16 | 0 << 14 | 0 << 12 | CEIL_DIV(khz, 102) << 0 | 0); /* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */ - writel(0 << 24 | CEIL_DIV(khz, 3200) << 18 | CEIL_DIV(khz, 256) << 6 | 0 << 4 | 0 << 2 | 0 << 0 | 0, - &clk_rst->utmip_pll_cfg2); + write32(&clk_rst->utmip_pll_cfg2, + 0 << 24 | CEIL_DIV(khz, 3200) << 18 | CEIL_DIV(khz, 256) << 6 | 0 << 4 | 0 << 2 | 0 << 0 | 0); setbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ } @@ -274,12 +274,12 @@ static void graphics_pll(void) * that it is needed. */ u32 scfg = (1<<28) | (1<<24) | (1<<22); - writel(scfg, cfg); + write32(cfg, scfg); init_pll(&clk_rst->plldp_base, &clk_rst->plldp_misc, osc_table[osc].plldp, PLLDPD2_MISC_LOCK_ENABLE); /* leave dither and undoc bits set, release clamp */ scfg = (1<<28) | (1<<24); - writel(scfg, cfg); + write32(cfg, scfg); /* disp1 will be set when panel information (pixel clock) is * retrieved (clock_display). @@ -387,8 +387,8 @@ clock_display(u32 frequency) * been determined through trial and error (must lead to div 13 at 24MHz). */ void clock_early_uart(void) { - writel(CLK_M << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900), - &clk_rst->clk_src_uarta); + write32(&clk_rst->clk_src_uarta, + CLK_M << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900)); setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_UARTA); udelay(2); clrbits_le32(&clk_rst->rst_dev_l, CLK_L_UARTA); @@ -438,22 +438,22 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, * values after coldboot reset). */ - writel(misc1, &clk_rst->pllm_misc1); - writel(misc2, &clk_rst->pllm_misc2); + write32(&clk_rst->pllm_misc1, misc1); + write32(&clk_rst->pllm_misc2, misc2); /* PLLM.BASE needs BYPASS=0, different from general init_pll */ - base = readl(&clk_rst->pllm_base); + base = read32(&clk_rst->pllm_base); base &= ~(PLLCMX_BASE_DIVN_MASK | PLLCMX_BASE_DIVM_MASK | PLLM_BASE_DIVP_MASK | PLL_BASE_BYPASS); base |= ((m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT) | (p << PLL_BASE_DIVP_SHIFT)); - writel(base, &clk_rst->pllm_base); + write32(&clk_rst->pllm_base, base); setbits_le32(&clk_rst->pllm_base, PLL_BASE_ENABLE); /* stable_time is required, before we can start to check lock. */ udelay(stable_time); - while (!(readl(&clk_rst->pllm_base) & PLL_BASE_LOCK)) { + while (!(read32(&clk_rst->pllm_base) & PLL_BASE_LOCK)) { udelay(1); } /* @@ -467,7 +467,7 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, /* Enable and start MEM(MC) and EMC. */ clock_enable_clear_reset(0, CLK_H_MEM | CLK_H_EMC, 0, 0, 0, 0); - writel(emc_source, &clk_rst->clk_src_emc); + write32(&clk_rst->clk_src_emc, emc_source); udelay(IO_STABILIZATION_DELAY); } @@ -475,24 +475,24 @@ void clock_cpu0_config(void *entry) { void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100; - writel((uintptr_t)_estack, &maincpu_stack_pointer); - writel((uintptr_t)entry, &maincpu_entry_point); - writel((uintptr_t)&maincpu_setup, evp_cpu_reset); + write32(&maincpu_stack_pointer, (uintptr_t)_estack); + write32(&maincpu_entry_point, (uintptr_t)entry); + write32(evp_cpu_reset, (uintptr_t)&maincpu_setup); /* Set active CPU cluster to G */ clrbits_le32(&flow->cluster_control, 1); // Set up cclk_brst and divider. - writel((CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) | (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28), - &clk_rst->cclk_brst_pol); - writel(CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB, - &clk_rst->super_cclk_div); + write32(&clk_rst->cclk_brst_pol, + (CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) | (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28)); + write32(&clk_rst->super_cclk_div, + CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB); // Enable the clocks for CPUs 0-3. uint32_t cpu_cmplx_clr = read32(&clk_rst->clk_cpu_cmplx_clr); cpu_cmplx_clr |= CRC_CLK_CLR_CPU0_STP | CRC_CLK_CLR_CPU1_STP | CRC_CLK_CLR_CPU2_STP | CRC_CLK_CLR_CPU3_STP; - writel(cpu_cmplx_clr, &clk_rst->clk_cpu_cmplx_clr); + write32(&clk_rst->clk_cpu_cmplx_clr, cpu_cmplx_clr); // Enable other CPU related clocks. setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU); @@ -503,23 +503,23 @@ void clock_cpu0_config(void *entry) void clock_cpu0_remove_reset(void) { // Disable the reset on the non-CPU parts of the fast cluster. - writel(CRC_RST_CPUG_CLR_NONCPU, &clk_rst->rst_cpug_cmplx_clr); + write32(&clk_rst->rst_cpug_cmplx_clr, CRC_RST_CPUG_CLR_NONCPU); // Disable the various resets on the CPUs. - writel(CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 | CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 | CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 | CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 | CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 | CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 | CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 | CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG, - &clk_rst->rst_cpug_cmplx_clr); + write32(&clk_rst->rst_cpug_cmplx_clr, + CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 | CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 | CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 | CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 | CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 | CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 | CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 | CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG); // Disable the reset on the non-CPU parts of the slow cluster. - writel(CRC_RST_CPULP_CLR_NONCPU, &clk_rst->rst_cpulp_cmplx_clr); + write32(&clk_rst->rst_cpulp_cmplx_clr, CRC_RST_CPULP_CLR_NONCPU); // Disable the various resets on the LP CPU. - writel(CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 | CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 | CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG, - &clk_rst->rst_cpulp_cmplx_clr); + write32(&clk_rst->rst_cpulp_cmplx_clr, + CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 | CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 | CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG); } void clock_halt_avp(void) { for (;;) { - writel(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT, - &flow->halt_cop_events); + write32(&flow->halt_cop_events, + FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT); } } @@ -528,7 +528,7 @@ void clock_init(void) u32 osc = clock_get_osc_bits(); /* Set PLLC dynramp_step A to 0x2b and B to 0xb (from U-Boot -- why? */ - writel(0x2b << 17 | 0xb << 9, &clk_rst->pllc_misc2); + write32(&clk_rst->pllc_misc2, 0x2b << 17 | 0xb << 9); /* Max out the AVP clock before everything else (need PLLC for that). */ init_pll(&clk_rst->pllc_base, &clk_rst->pllc_misc, @@ -536,12 +536,12 @@ void clock_init(void) /* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA * features section in the TRM). */ - writel(TEGRA_HCLK_RATIO << HCLK_DIVISOR_SHIFT | TEGRA_PCLK_RATIO << PCLK_DIVISOR_SHIFT, - &clk_rst->clk_sys_rate); - writel(CLK_DIVIDER(TEGRA_PLLC_KHZ, TEGRA_SCLK_KHZ) << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN, - &clk_rst->pllc_out); - writel(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT, - &clk_rst->sclk_brst_pol); /* sclk = 300 MHz */ + write32(&clk_rst->clk_sys_rate, + TEGRA_HCLK_RATIO << HCLK_DIVISOR_SHIFT | TEGRA_PCLK_RATIO << PCLK_DIVISOR_SHIFT); + write32(&clk_rst->pllc_out, + CLK_DIVIDER(TEGRA_PLLC_KHZ, TEGRA_SCLK_KHZ) << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN); + write32(&clk_rst->sclk_brst_pol, + SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT); /* sclk = 300 MHz */ /* Change the oscillator drive strength (from U-Boot -- why?) */ clrsetbits_le32(&clk_rst->osc_ctrl, OSC_XOFS_MASK, @@ -559,10 +559,10 @@ void clock_init(void) clrbits_le32(&clk_rst->pllx_misc3, PLLX_IDDQ_MASK); /* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */ - writel((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT, - &clk_rst->pllp_outa); - writel((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT, - &clk_rst->pllp_outb); + write32(&clk_rst->pllp_outa, + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT); + write32(&clk_rst->pllp_outb, + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT); /* init pllx */ init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc, @@ -578,62 +578,62 @@ void clock_init(void) void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x) { - if (l) writel(l, &clk_rst->clk_enb_l_set); - if (h) writel(h, &clk_rst->clk_enb_h_set); - if (u) writel(u, &clk_rst->clk_enb_u_set); - if (v) writel(v, &clk_rst->clk_enb_v_set); - if (w) writel(w, &clk_rst->clk_enb_w_set); - if (x) writel(x, &clk_rst->clk_enb_x_set); + if (l) write32(&clk_rst->clk_enb_l_set, l); + if (h) write32(&clk_rst->clk_enb_h_set, h); + if (u) write32(&clk_rst->clk_enb_u_set, u); + if (v) write32(&clk_rst->clk_enb_v_set, v); + if (w) write32(&clk_rst->clk_enb_w_set, w); + if (x) write32(&clk_rst->clk_enb_x_set, x); /* Give clocks time to stabilize. */ udelay(IO_STABILIZATION_DELAY); - if (l) writel(l, &clk_rst->rst_dev_l_clr); - if (h) writel(h, &clk_rst->rst_dev_h_clr); - if (u) writel(u, &clk_rst->rst_dev_u_clr); - if (v) writel(v, &clk_rst->rst_dev_v_clr); - if (w) writel(w, &clk_rst->rst_dev_w_clr); - if (x) writel(x, &clk_rst->rst_dev_x_clr); + if (l) write32(&clk_rst->rst_dev_l_clr, l); + if (h) write32(&clk_rst->rst_dev_h_clr, h); + if (u) write32(&clk_rst->rst_dev_u_clr, u); + if (v) write32(&clk_rst->rst_dev_v_clr, v); + if (w) write32(&clk_rst->rst_dev_w_clr, w); + if (x) write32(&clk_rst->rst_dev_x_clr, x); } void clock_reset_l(u32 bit) { - writel(bit, &clk_rst->rst_dev_l_set); + write32(&clk_rst->rst_dev_l_set, bit); udelay(1); - writel(bit, &clk_rst->rst_dev_l_clr); + write32(&clk_rst->rst_dev_l_clr, bit); } void clock_reset_h(u32 bit) { - writel(bit, &clk_rst->rst_dev_h_set); + write32(&clk_rst->rst_dev_h_set, bit); udelay(1); - writel(bit, &clk_rst->rst_dev_h_clr); + write32(&clk_rst->rst_dev_h_clr, bit); } void clock_reset_u(u32 bit) { - writel(bit, &clk_rst->rst_dev_u_set); + write32(&clk_rst->rst_dev_u_set, bit); udelay(1); - writel(bit, &clk_rst->rst_dev_u_clr); + write32(&clk_rst->rst_dev_u_clr, bit); } void clock_reset_v(u32 bit) { - writel(bit, &clk_rst->rst_dev_v_set); + write32(&clk_rst->rst_dev_v_set, bit); udelay(1); - writel(bit, &clk_rst->rst_dev_v_clr); + write32(&clk_rst->rst_dev_v_clr, bit); } void clock_reset_w(u32 bit) { - writel(bit, &clk_rst->rst_dev_w_set); + write32(&clk_rst->rst_dev_w_set, bit); udelay(1); - writel(bit, &clk_rst->rst_dev_w_clr); + write32(&clk_rst->rst_dev_w_clr, bit); } void clock_reset_x(u32 bit) { - writel(bit, &clk_rst->rst_dev_x_set); + write32(&clk_rst->rst_dev_x_set, bit); udelay(1); - writel(bit, &clk_rst->rst_dev_x_clr); + write32(&clk_rst->rst_dev_x_clr, bit); } diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 71fff1c93e..7273090eec 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -53,7 +53,7 @@ unsigned long READL(void * p) if (dump > 1) printk(BIOS_SPEW, "readl %p\n", p); - value = readl(p); + value = read32(p); if (dump) printk(BIOS_SPEW, "readl %p %08lx\n", p, value); return value; @@ -63,7 +63,7 @@ void WRITEL(unsigned long value, void * p) { if (dump) printk(BIOS_SPEW, "writel %p %08lx\n", p, value); - writel(value, p); + write32(p, value); } /* return in 1000ths of a Hertz */ diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 9418e152da..2ed2103d15 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -282,17 +282,17 @@ inline static void write32(uint32_t val, void *addr) inline static void setbits32(uint32_t bits, void *addr) { - writel(read32(addr) | bits, addr); + write32(addr, read32(addr) | bits); } inline static void clrbits32(uint32_t bits, void *addr) { - writel(read32(addr) & ~bits, addr); + write32(addr, read32(addr) & ~bits); } static void __attribute__((noreturn)) reset(void) { - writel(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr); + write32(clk_rst_rst_devices_l_ptr, SWR_TRIG_SYS_RST); halt(); } @@ -337,7 +337,7 @@ static void config_oscillator(void) osc_ctrl &= ~OSC_XOFS_MASK; osc_ctrl |= (xofs << OSC_XOFS_SHIFT); osc_ctrl |= OSC_XOE; - writel(osc_ctrl, clk_rst_osc_ctrl_ptr); + write32(clk_rst_osc_ctrl_ptr, osc_ctrl); } static void config_pllu(void) @@ -382,17 +382,17 @@ static void config_pllu(void) // Configure PLLU. uint32_t base = PLLU_BYPASS | PLLU_OVERRIDE | (divn << PLLU_DIVN_SHIFT) | (divm << PLLU_DIVM_SHIFT); - writel(base, clk_rst_pllu_base_ptr); + write32(clk_rst_pllu_base_ptr, base); uint32_t misc = (cpcon << PLLU_CPCON_SHIFT) | (lfcon << PLLU_LFCON_SHIFT); - writel(misc, clk_rst_pllu_misc_ptr); + write32(clk_rst_pllu_misc_ptr, misc); // Enable PLLU. base &= ~PLLU_BYPASS; base |= PLLU_ENABLE; - writel(base, clk_rst_pllu_base_ptr); + write32(clk_rst_pllu_base_ptr, base); misc |= PLLU_LOCK_ENABLE; - writel(misc, clk_rst_pllu_misc_ptr); + write32(clk_rst_pllu_misc_ptr, misc); } static void config_tsc(void) @@ -400,26 +400,26 @@ static void config_tsc(void) // Tell the TSC the oscillator frequency. switch (get_osc_freq()) { case OSC_FREQ_12: - writel(12000000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 12000000); break; case OSC_FREQ_48: - writel(48000000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 48000000); break; case OSC_FREQ_16P8: - writel(16800000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 16800000); break; case OSC_FREQ_19P2: - writel(19200000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 19200000); break; case OSC_FREQ_38P4: - writel(38400000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 38400000); break; case OSC_FREQ_26: - writel(26000000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 26000000); break; default: // Default to 13MHz. - writel(13000000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 13000000); break; } @@ -430,8 +430,8 @@ static void config_tsc(void) static void enable_cpu_clocks(void) { // Enable the CPU complex clock. - writel(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr); - writel(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr); + write32(clk_rst_clk_enb_l_set_ptr, CLK_ENB_CPU); + write32(clk_rst_clk_enb_v_set_ptr, CLK_ENB_CPUG | CLK_ENB_CPULP); } @@ -441,7 +441,7 @@ static void enable_cpu_clocks(void) static void config_core_sight(void) { // Enable the CoreSight clock. - writel(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr); + write32(clk_rst_clk_out_enb_u_set_ptr, CLK_ENB_CSITE); /* * De-assert CoreSight reset. @@ -449,22 +449,22 @@ static void config_core_sight(void) * now. It will be restored to its original clock source * when the CPU-side restoration code runs. */ - writel(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr); + write32(clk_rst_rst_dev_u_clr_ptr, SWR_CSITE_RST); } static void config_mselect(void) { // Set MSELECT clock source to PLLP with 1:4 divider. - writel((6 << MSELECT_CLK_DIV_SHIFT) | MSELECT_CLK_SRC_PLLP_OUT0, - clk_rst_clk_src_mselect_ptr); + write32(clk_rst_clk_src_mselect_ptr, + (6 << MSELECT_CLK_DIV_SHIFT) | MSELECT_CLK_SRC_PLLP_OUT0); // Enable clock to MSELECT. - writel(CLK_ENB_MSELECT, clk_rst_clk_enb_v_set_ptr); + write32(clk_rst_clk_enb_v_set_ptr, CLK_ENB_MSELECT); udelay(2); // Bring MSELECT out of reset. - writel(SWR_MSELECT_RST, clk_rst_rst_dev_v_clr_ptr); + write32(clk_rst_rst_dev_v_clr_ptr, SWR_MSELECT_RST); } @@ -474,16 +474,16 @@ static void config_mselect(void) static void clear_cpu_resets(void) { // Take the non-cpu of the G and LP clusters out of reset. - writel(CLR_NONCPURESET, clk_rst_rst_cpulp_cmplx_clr_ptr); - writel(CLR_NONCPURESET, clk_rst_rst_cpug_cmplx_clr_ptr); + write32(clk_rst_rst_cpulp_cmplx_clr_ptr, CLR_NONCPURESET); + write32(clk_rst_rst_cpug_cmplx_clr_ptr, CLR_NONCPURESET); // Clear software controlled reset of the slow cluster. - writel(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0, - clk_rst_rst_cpulp_cmplx_clr_ptr); + write32(clk_rst_rst_cpulp_cmplx_clr_ptr, + CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0); // Clear software controlled reset of the fast cluster. - writel(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 | CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 | CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3, - clk_rst_rst_cpug_cmplx_clr_ptr); + write32(clk_rst_rst_cpug_cmplx_clr_ptr, + CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 | CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 | CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3); } @@ -513,7 +513,8 @@ static void power_on_partition(unsigned id) uint32_t bit = 0x1 << id; if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) { // Partition is not on. Turn it on. - writel(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr); + write32(pmc_ctlr_pwrgate_toggle_ptr, + id | PWRGATE_TOGGLE_START); // Wait until the partition is powerd on. while (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) @@ -543,8 +544,8 @@ static void power_on_main_cpu(void) */ uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr); - writel(orig_timer * (204000000 / 32768), - pmc_ctlr_cpupwrgood_timer_ptr); + write32(pmc_ctlr_cpupwrgood_timer_ptr, + orig_timer * (204000000 / 32768)); if (wakeup_on_lp()) { power_on_partition(PARTID_C1NC); @@ -556,7 +557,7 @@ static void power_on_main_cpu(void) } // Restore the original PMC_CPUPWRGOOD_TIMER. - writel(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr); + write32(pmc_ctlr_cpupwrgood_timer_ptr, orig_timer); } @@ -578,17 +579,17 @@ void lp0_resume(void) flow_ctlr_cluster_control_ptr); // Program SUPER_CCLK_DIVIDER. - writel(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr); + write32(clk_rst_super_cclk_div_ptr, SUPER_CDIV_ENB); config_core_sight(); config_pllu(); // Set the CPU reset vector. - writel(get_wakeup_vector(), evp_cpu_reset_ptr); + write32(evp_cpu_reset_ptr, get_wakeup_vector()); // Select CPU complex clock source. - writel(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr); + write32(clk_rst_cclk_burst_policy_ptr, CCLK_PLLP_BURST_POLICY); config_mselect(); @@ -599,14 +600,14 @@ void lp0_resume(void) uint32_t ack_width = read32(clk_rst_cpu_softrst_ctrl2_ptr); ack_width &= ~CAR2PMC_CPU_ACK_WIDTH_MASK; ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT; - writel(ack_width, clk_rst_cpu_softrst_ctrl2_ptr); + write32(clk_rst_cpu_softrst_ctrl2_ptr, ack_width); config_tsc(); // Disable VPR. - writel(0, mc_video_protect_size_mb_ptr); - writel(VIDEO_PROTECT_WRITE_ACCESS_DISABLE, - mc_video_protect_reg_ctrl_ptr); + write32(mc_video_protect_size_mb_ptr, 0); + write32(mc_video_protect_reg_ctrl_ptr, + VIDEO_PROTECT_WRITE_ACCESS_DISABLE); enable_cpu_clocks(); @@ -619,8 +620,8 @@ void lp0_resume(void) // Halt the AVP. while (1) - writel(FLOW_MODE_STOP | EVENT_JTAG, - flow_ctlr_halt_cop_events_ptr); + write32(flow_ctlr_halt_cop_events_ptr, + FLOW_MODE_STOP | EVENT_JTAG); } diff --git a/src/soc/nvidia/tegra124/power.c b/src/soc/nvidia/tegra124/power.c index b31d3a7781..962a8e12e3 100644 --- a/src/soc/nvidia/tegra124/power.c +++ b/src/soc/nvidia/tegra124/power.c @@ -48,7 +48,7 @@ static void power_ungate_partition(uint32_t id) pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK); pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT); pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START; - writel(pwrgate_toggle, &pmc->pwrgate_toggle); + write32(&pmc->pwrgate_toggle, pwrgate_toggle); // Wait for the request to be accepted. while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START) @@ -73,12 +73,12 @@ void power_enable_and_ungate_cpu(void) * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (150MHz), * set it for 5ms as per SysEng (5ms * PCLK_KHZ * 1000 / 1s). */ - writel((TEGRA_PCLK_KHZ * 5), &pmc->cpupwrgood_timer); + write32(&pmc->cpupwrgood_timer, (TEGRA_PCLK_KHZ * 5)); uint32_t cntrl = read32(&pmc->cntrl); cntrl &= ~PMC_CNTRL_CPUPWRREQ_POLARITY; cntrl |= PMC_CNTRL_CPUPWRREQ_OE; - writel(cntrl, &pmc->cntrl); + write32(&pmc->cntrl, cntrl); power_ungate_partition(POWER_PARTID_CRAIL); diff --git a/src/soc/nvidia/tegra124/sdram.c b/src/soc/nvidia/tegra124/sdram.c index d094c18594..dc6fd92544 100644 --- a/src/soc/nvidia/tegra124/sdram.c +++ b/src/soc/nvidia/tegra124/sdram.c @@ -33,7 +33,7 @@ static void sdram_patch(uintptr_t addr, uint32_t value) { if (addr) - writel(value, (uint32_t*)addr); + write32((uint32_t *)addr, value); } static void writebits(uint32_t value, uint32_t *addr, uint32_t mask) @@ -46,7 +46,7 @@ static void sdram_configure_pmc(const struct sdram_params *param, struct tegra_pmc_regs *regs) { /* VDDP Select */ - writel(param->PmcVddpSel, ®s->vddp_sel); + write32(®s->vddp_sel, param->PmcVddpSel); udelay(param->PmcVddpSelWait); /* Set DDR pad voltage */ @@ -62,7 +62,7 @@ static void sdram_configure_pmc(const struct sdram_params *param, writebits(param->PmcNoIoPower, ®s->no_iopower, (PMC_NO_IOPOWER_MEM_MASK | PMC_NO_IOPOWER_MEM_COMP_MASK)); - writel(param->PmcRegShort, ®s->reg_short); + write32(®s->reg_short, param->PmcRegShort); } static void sdram_start_clocks(const struct sdram_params *param) @@ -102,148 +102,151 @@ static void sdram_deassert_sel_dpd(const struct sdram_params *param, static void sdram_set_swizzle(const struct sdram_params *param, struct tegra_emc_regs *regs) { - writel(param->EmcSwizzleRank0ByteCfg, ®s->swizzle_rank0_byte_cfg); - writel(param->EmcSwizzleRank0Byte0, ®s->swizzle_rank0_byte0); - writel(param->EmcSwizzleRank0Byte1, ®s->swizzle_rank0_byte1); - writel(param->EmcSwizzleRank0Byte2, ®s->swizzle_rank0_byte2); - writel(param->EmcSwizzleRank0Byte3, ®s->swizzle_rank0_byte3); - writel(param->EmcSwizzleRank1ByteCfg, ®s->swizzle_rank1_byte_cfg); - writel(param->EmcSwizzleRank1Byte0, ®s->swizzle_rank1_byte0); - writel(param->EmcSwizzleRank1Byte1, ®s->swizzle_rank1_byte1); - writel(param->EmcSwizzleRank1Byte2, ®s->swizzle_rank1_byte2); - writel(param->EmcSwizzleRank1Byte3, ®s->swizzle_rank1_byte3); + write32(®s->swizzle_rank0_byte_cfg, param->EmcSwizzleRank0ByteCfg); + write32(®s->swizzle_rank0_byte0, param->EmcSwizzleRank0Byte0); + write32(®s->swizzle_rank0_byte1, param->EmcSwizzleRank0Byte1); + write32(®s->swizzle_rank0_byte2, param->EmcSwizzleRank0Byte2); + write32(®s->swizzle_rank0_byte3, param->EmcSwizzleRank0Byte3); + write32(®s->swizzle_rank1_byte_cfg, param->EmcSwizzleRank1ByteCfg); + write32(®s->swizzle_rank1_byte0, param->EmcSwizzleRank1Byte0); + write32(®s->swizzle_rank1_byte1, param->EmcSwizzleRank1Byte1); + write32(®s->swizzle_rank1_byte2, param->EmcSwizzleRank1Byte2); + write32(®s->swizzle_rank1_byte3, param->EmcSwizzleRank1Byte3); } static void sdram_set_pad_controls(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Program the pad controls */ - writel(param->EmcXm2CmdPadCtrl, ®s->xm2cmdpadctrl); - writel(param->EmcXm2CmdPadCtrl2, ®s->xm2cmdpadctrl2); - writel(param->EmcXm2CmdPadCtrl3, ®s->xm2cmdpadctrl3); - writel(param->EmcXm2CmdPadCtrl4, ®s->xm2cmdpadctrl4); - writel(param->EmcXm2CmdPadCtrl5, ®s->xm2cmdpadctrl5); + write32(®s->xm2cmdpadctrl, param->EmcXm2CmdPadCtrl); + write32(®s->xm2cmdpadctrl2, param->EmcXm2CmdPadCtrl2); + write32(®s->xm2cmdpadctrl3, param->EmcXm2CmdPadCtrl3); + write32(®s->xm2cmdpadctrl4, param->EmcXm2CmdPadCtrl4); + write32(®s->xm2cmdpadctrl5, param->EmcXm2CmdPadCtrl5); - writel(param->EmcXm2DqsPadCtrl, ®s->xm2dqspadctrl); - writel(param->EmcXm2DqsPadCtrl2, ®s->xm2dqspadctrl2); - writel(param->EmcXm2DqsPadCtrl3, ®s->xm2dqspadctrl3); - writel(param->EmcXm2DqsPadCtrl4, ®s->xm2dqspadctrl4); - writel(param->EmcXm2DqsPadCtrl5, ®s->xm2dqspadctrl5); - writel(param->EmcXm2DqsPadCtrl6, ®s->xm2dqspadctrl6); + write32(®s->xm2dqspadctrl, param->EmcXm2DqsPadCtrl); + write32(®s->xm2dqspadctrl2, param->EmcXm2DqsPadCtrl2); + write32(®s->xm2dqspadctrl3, param->EmcXm2DqsPadCtrl3); + write32(®s->xm2dqspadctrl4, param->EmcXm2DqsPadCtrl4); + write32(®s->xm2dqspadctrl5, param->EmcXm2DqsPadCtrl5); + write32(®s->xm2dqspadctrl6, param->EmcXm2DqsPadCtrl6); - writel(param->EmcXm2DqPadCtrl, ®s->xm2dqpadctrl); - writel(param->EmcXm2DqPadCtrl2, ®s->xm2dqpadctrl2); - writel(param->EmcXm2DqPadCtrl3, ®s->xm2dqpadctrl3); + write32(®s->xm2dqpadctrl, param->EmcXm2DqPadCtrl); + write32(®s->xm2dqpadctrl2, param->EmcXm2DqPadCtrl2); + write32(®s->xm2dqpadctrl3, param->EmcXm2DqPadCtrl3); - writel(param->EmcXm2ClkPadCtrl, ®s->xm2clkpadctrl); - writel(param->EmcXm2ClkPadCtrl2, ®s->xm2clkpadctrl2); + write32(®s->xm2clkpadctrl, param->EmcXm2ClkPadCtrl); + write32(®s->xm2clkpadctrl2, param->EmcXm2ClkPadCtrl2); - writel(param->EmcXm2CompPadCtrl, ®s->xm2comppadctrl); + write32(®s->xm2comppadctrl, param->EmcXm2CompPadCtrl); - writel(param->EmcXm2VttGenPadCtrl, ®s->xm2vttgenpadctrl); - writel(param->EmcXm2VttGenPadCtrl2, ®s->xm2vttgenpadctrl2); - writel(param->EmcXm2VttGenPadCtrl3, ®s->xm2vttgenpadctrl3); + write32(®s->xm2vttgenpadctrl, param->EmcXm2VttGenPadCtrl); + write32(®s->xm2vttgenpadctrl2, param->EmcXm2VttGenPadCtrl2); + write32(®s->xm2vttgenpadctrl3, param->EmcXm2VttGenPadCtrl3); - writel(param->EmcCttTermCtrl, ®s->ctt_term_ctrl); + write32(®s->ctt_term_ctrl, param->EmcCttTermCtrl); } static void sdram_trigger_emc_timing_update(struct tegra_emc_regs *regs) { - writel(EMC_TIMING_CONTROL_TIMING_UPDATE, ®s->timing_control); + write32(®s->timing_control, EMC_TIMING_CONTROL_TIMING_UPDATE); } static void sdram_init_mc(const struct sdram_params *param, struct tegra_mc_regs *regs) { /* Initialize MC VPR settings */ - writel(param->McDisplaySnapRing, ®s->display_snap_ring); - writel(param->McVideoProtectBom, ®s->video_protect_bom); - writel(param->McVideoProtectBomAdrHi, ®s->video_protect_bom_adr_hi); - writel(param->McVideoProtectSizeMb, ®s->video_protect_size_mb); - writel(param->McVideoProtectVprOverride, - ®s->video_protect_vpr_override); - writel(param->McVideoProtectVprOverride1, - ®s->video_protect_vpr_override1); - writel(param->McVideoProtectGpuOverride0, - ®s->video_protect_gpu_override_0); - writel(param->McVideoProtectGpuOverride1, - ®s->video_protect_gpu_override_1); + write32(®s->display_snap_ring, param->McDisplaySnapRing); + write32(®s->video_protect_bom, param->McVideoProtectBom); + write32(®s->video_protect_bom_adr_hi, + param->McVideoProtectBomAdrHi); + write32(®s->video_protect_size_mb, param->McVideoProtectSizeMb); + write32(®s->video_protect_vpr_override, + param->McVideoProtectVprOverride); + write32(®s->video_protect_vpr_override1, + param->McVideoProtectVprOverride1); + write32(®s->video_protect_gpu_override_0, + param->McVideoProtectGpuOverride0); + write32(®s->video_protect_gpu_override_1, + param->McVideoProtectGpuOverride1); /* Program SDRAM geometry paarameters */ - writel(param->McEmemAdrCfg, ®s->emem_adr_cfg); - writel(param->McEmemAdrCfgDev0, ®s->emem_adr_cfg_dev0); - writel(param->McEmemAdrCfgDev1, ®s->emem_adr_cfg_dev1); + write32(®s->emem_adr_cfg, param->McEmemAdrCfg); + write32(®s->emem_adr_cfg_dev0, param->McEmemAdrCfgDev0); + write32(®s->emem_adr_cfg_dev1, param->McEmemAdrCfgDev1); /* Program bank swizzling */ - writel(param->McEmemAdrCfgBankMask0, ®s->emem_bank_swizzle_cfg0); - writel(param->McEmemAdrCfgBankMask1, ®s->emem_bank_swizzle_cfg1); - writel(param->McEmemAdrCfgBankMask2, ®s->emem_bank_swizzle_cfg2); - writel(param->McEmemAdrCfgBankSwizzle3, ®s->emem_bank_swizzle_cfg3); + write32(®s->emem_bank_swizzle_cfg0, param->McEmemAdrCfgBankMask0); + write32(®s->emem_bank_swizzle_cfg1, param->McEmemAdrCfgBankMask1); + write32(®s->emem_bank_swizzle_cfg2, param->McEmemAdrCfgBankMask2); + write32(®s->emem_bank_swizzle_cfg3, + param->McEmemAdrCfgBankSwizzle3); /* Program external memory aperature (base and size) */ - writel(param->McEmemCfg, ®s->emem_cfg); + write32(®s->emem_cfg, param->McEmemCfg); /* Program SEC carveout (base and size) */ - writel(param->McSecCarveoutBom, ®s->sec_carveout_bom); - writel(param->McSecCarveoutAdrHi, ®s->sec_carveout_adr_hi); - writel(param->McSecCarveoutSizeMb, ®s->sec_carveout_size_mb); + write32(®s->sec_carveout_bom, param->McSecCarveoutBom); + write32(®s->sec_carveout_adr_hi, param->McSecCarveoutAdrHi); + write32(®s->sec_carveout_size_mb, param->McSecCarveoutSizeMb); /* Program MTS carveout (base and size) */ - writel(param->McMtsCarveoutBom, ®s->mts_carveout_bom); - writel(param->McMtsCarveoutAdrHi, ®s->mts_carveout_adr_hi); - writel(param->McMtsCarveoutSizeMb, ®s->mts_carveout_size_mb); + write32(®s->mts_carveout_bom, param->McMtsCarveoutBom); + write32(®s->mts_carveout_adr_hi, param->McMtsCarveoutAdrHi); + write32(®s->mts_carveout_size_mb, param->McMtsCarveoutSizeMb); /* Program the memory arbiter */ - writel(param->McEmemArbCfg, ®s->emem_arb_cfg); - writel(param->McEmemArbOutstandingReq, ®s->emem_arb_outstanding_req); - writel(param->McEmemArbTimingRcd, ®s->emem_arb_timing_rcd); - writel(param->McEmemArbTimingRp, ®s->emem_arb_timing_rp); - writel(param->McEmemArbTimingRc, ®s->emem_arb_timing_rc); - writel(param->McEmemArbTimingRas, ®s->emem_arb_timing_ras); - writel(param->McEmemArbTimingFaw, ®s->emem_arb_timing_faw); - writel(param->McEmemArbTimingRrd, ®s->emem_arb_timing_rrd); - writel(param->McEmemArbTimingRap2Pre, ®s->emem_arb_timing_rap2pre); - writel(param->McEmemArbTimingWap2Pre, ®s->emem_arb_timing_wap2pre); - writel(param->McEmemArbTimingR2R, ®s->emem_arb_timing_r2r); - writel(param->McEmemArbTimingW2W, ®s->emem_arb_timing_w2w); - writel(param->McEmemArbTimingR2W, ®s->emem_arb_timing_r2w); - writel(param->McEmemArbTimingW2R, ®s->emem_arb_timing_w2r); - writel(param->McEmemArbDaTurns, ®s->emem_arb_da_turns); - writel(param->McEmemArbDaCovers, ®s->emem_arb_da_covers); - writel(param->McEmemArbMisc0, ®s->emem_arb_misc0); - writel(param->McEmemArbMisc1, ®s->emem_arb_misc1); - writel(param->McEmemArbRing1Throttle, ®s->emem_arb_ring1_throttle); - writel(param->McEmemArbOverride, ®s->emem_arb_override); - writel(param->McEmemArbOverride1, ®s->emem_arb_override_1); - writel(param->McEmemArbRsv, ®s->emem_arb_rsv); + write32(®s->emem_arb_cfg, param->McEmemArbCfg); + write32(®s->emem_arb_outstanding_req, + param->McEmemArbOutstandingReq); + write32(®s->emem_arb_timing_rcd, param->McEmemArbTimingRcd); + write32(®s->emem_arb_timing_rp, param->McEmemArbTimingRp); + write32(®s->emem_arb_timing_rc, param->McEmemArbTimingRc); + write32(®s->emem_arb_timing_ras, param->McEmemArbTimingRas); + write32(®s->emem_arb_timing_faw, param->McEmemArbTimingFaw); + write32(®s->emem_arb_timing_rrd, param->McEmemArbTimingRrd); + write32(®s->emem_arb_timing_rap2pre, param->McEmemArbTimingRap2Pre); + write32(®s->emem_arb_timing_wap2pre, param->McEmemArbTimingWap2Pre); + write32(®s->emem_arb_timing_r2r, param->McEmemArbTimingR2R); + write32(®s->emem_arb_timing_w2w, param->McEmemArbTimingW2W); + write32(®s->emem_arb_timing_r2w, param->McEmemArbTimingR2W); + write32(®s->emem_arb_timing_w2r, param->McEmemArbTimingW2R); + write32(®s->emem_arb_da_turns, param->McEmemArbDaTurns); + write32(®s->emem_arb_da_covers, param->McEmemArbDaCovers); + write32(®s->emem_arb_misc0, param->McEmemArbMisc0); + write32(®s->emem_arb_misc1, param->McEmemArbMisc1); + write32(®s->emem_arb_ring1_throttle, param->McEmemArbRing1Throttle); + write32(®s->emem_arb_override, param->McEmemArbOverride); + write32(®s->emem_arb_override_1, param->McEmemArbOverride1); + write32(®s->emem_arb_rsv, param->McEmemArbRsv); /* Program extra snap levels for display client */ - writel(param->McDisExtraSnapLevels, ®s->dis_extra_snap_levels); + write32(®s->dis_extra_snap_levels, param->McDisExtraSnapLevels); /* Trigger MC timing update */ - writel(MC_TIMING_CONTROL_TIMING_UPDATE, ®s->timing_control); + write32(®s->timing_control, MC_TIMING_CONTROL_TIMING_UPDATE); /* Program second-level clock enable overrides */ - writel(param->McClkenOverride, ®s->clken_override); + write32(®s->clken_override, param->McClkenOverride); /* Program statistics gathering */ - writel(param->McStatControl, ®s->stat_control); + write32(®s->stat_control, param->McStatControl); } static void sdram_init_emc(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Program SDRAM geometry parameters */ - writel(param->EmcAdrCfg, ®s->adr_cfg); + write32(®s->adr_cfg, param->EmcAdrCfg); /* Program second-level clock enable overrides */ - writel(param->EmcClkenOverride, ®s->clken_override); + write32(®s->clken_override, param->EmcClkenOverride); /* Program EMC pad auto calibration */ - writel(param->EmcAutoCalInterval, ®s->auto_cal_interval); - writel(param->EmcAutoCalConfig2, ®s->auto_cal_config2); - writel(param->EmcAutoCalConfig3, ®s->auto_cal_config3); - writel(param->EmcAutoCalConfig, ®s->auto_cal_config); + write32(®s->auto_cal_interval, param->EmcAutoCalInterval); + write32(®s->auto_cal_config2, param->EmcAutoCalConfig2); + write32(®s->auto_cal_config3, param->EmcAutoCalConfig3); + write32(®s->auto_cal_config, param->EmcAutoCalConfig); udelay(param->EmcAutoCalWait); } @@ -251,129 +254,129 @@ static void sdram_set_emc_timing(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Program EMC timing configuration */ - writel(param->EmcCfg2, ®s->cfg_2); - writel(param->EmcCfgPipe, ®s->cfg_pipe); - writel(param->EmcDbg, ®s->dbg); - writel(param->EmcCmdQ, ®s->cmdq); - writel(param->EmcMc2EmcQ, ®s->mc2emcq); - writel(param->EmcMrsWaitCnt, ®s->mrs_wait_cnt); - writel(param->EmcMrsWaitCnt2, ®s->mrs_wait_cnt2); - writel(param->EmcFbioCfg5, ®s->fbio_cfg5); - writel(param->EmcRc, ®s->rc); - writel(param->EmcRfc, ®s->rfc); - writel(param->EmcRfcSlr, ®s->rfc_slr); - writel(param->EmcRas, ®s->ras); - writel(param->EmcRp, ®s->rp); - writel(param->EmcR2r, ®s->r2r); - writel(param->EmcW2w, ®s->w2w); - writel(param->EmcR2w, ®s->r2w); - writel(param->EmcW2r, ®s->w2r); - writel(param->EmcR2p, ®s->r2p); - writel(param->EmcW2p, ®s->w2p); - writel(param->EmcRdRcd, ®s->rd_rcd); - writel(param->EmcWrRcd, ®s->wr_rcd); - writel(param->EmcRrd, ®s->rrd); - writel(param->EmcRext, ®s->rext); - writel(param->EmcWext, ®s->wext); - writel(param->EmcWdv, ®s->wdv); - writel(param->EmcWdvMask, ®s->wdv_mask); - writel(param->EmcQUse, ®s->quse); - writel(param->EmcQuseWidth, ®s->quse_width); - writel(param->EmcIbdly, ®s->ibdly); - writel(param->EmcEInput, ®s->einput); - writel(param->EmcEInputDuration, ®s->einput_duration); - writel(param->EmcPutermExtra, ®s->puterm_extra); - writel(param->EmcPutermWidth, ®s->puterm_width); - writel(param->EmcPutermAdj, ®s->puterm_adj); - writel(param->EmcCdbCntl1, ®s->cdb_cntl_1); - writel(param->EmcCdbCntl2, ®s->cdb_cntl_2); - writel(param->EmcCdbCntl3, ®s->cdb_cntl_3); - writel(param->EmcQRst, ®s->qrst); - writel(param->EmcQSafe, ®s->qsafe); - writel(param->EmcRdv, ®s->rdv); - writel(param->EmcRdvMask, ®s->rdv_mask); - writel(param->EmcQpop, ®s->qpop); - writel(param->EmcCtt, ®s->ctt); - writel(param->EmcCttDuration, ®s->ctt_duration); - writel(param->EmcRefresh, ®s->refresh); - writel(param->EmcBurstRefreshNum, ®s->burst_refresh_num); - writel(param->EmcPreRefreshReqCnt, ®s->pre_refresh_req_cnt); - writel(param->EmcPdEx2Wr, ®s->pdex2wr); - writel(param->EmcPdEx2Rd, ®s->pdex2rd); - writel(param->EmcPChg2Pden, ®s->pchg2pden); - writel(param->EmcAct2Pden, ®s->act2pden); - writel(param->EmcAr2Pden, ®s->ar2pden); - writel(param->EmcRw2Pden, ®s->rw2pden); - writel(param->EmcTxsr, ®s->txsr); - writel(param->EmcTxsrDll, ®s->txsrdll); - writel(param->EmcTcke, ®s->tcke); - writel(param->EmcTckesr, ®s->tckesr); - writel(param->EmcTpd, ®s->tpd); - writel(param->EmcTfaw, ®s->tfaw); - writel(param->EmcTrpab, ®s->trpab); - writel(param->EmcTClkStable, ®s->tclkstable); - writel(param->EmcTClkStop, ®s->tclkstop); - writel(param->EmcTRefBw, ®s->trefbw); - writel(param->EmcOdtWrite, ®s->odt_write); - writel(param->EmcOdtRead, ®s->odt_read); - writel(param->EmcFbioCfg6, ®s->fbio_cfg6); - writel(param->EmcCfgDigDll, ®s->cfg_dig_dll); - writel(param->EmcCfgDigDllPeriod, ®s->cfg_dig_dll_period); + write32(®s->cfg_2, param->EmcCfg2); + write32(®s->cfg_pipe, param->EmcCfgPipe); + write32(®s->dbg, param->EmcDbg); + write32(®s->cmdq, param->EmcCmdQ); + write32(®s->mc2emcq, param->EmcMc2EmcQ); + write32(®s->mrs_wait_cnt, param->EmcMrsWaitCnt); + write32(®s->mrs_wait_cnt2, param->EmcMrsWaitCnt2); + write32(®s->fbio_cfg5, param->EmcFbioCfg5); + write32(®s->rc, param->EmcRc); + write32(®s->rfc, param->EmcRfc); + write32(®s->rfc_slr, param->EmcRfcSlr); + write32(®s->ras, param->EmcRas); + write32(®s->rp, param->EmcRp); + write32(®s->r2r, param->EmcR2r); + write32(®s->w2w, param->EmcW2w); + write32(®s->r2w, param->EmcR2w); + write32(®s->w2r, param->EmcW2r); + write32(®s->r2p, param->EmcR2p); + write32(®s->w2p, param->EmcW2p); + write32(®s->rd_rcd, param->EmcRdRcd); + write32(®s->wr_rcd, param->EmcWrRcd); + write32(®s->rrd, param->EmcRrd); + write32(®s->rext, param->EmcRext); + write32(®s->wext, param->EmcWext); + write32(®s->wdv, param->EmcWdv); + write32(®s->wdv_mask, param->EmcWdvMask); + write32(®s->quse, param->EmcQUse); + write32(®s->quse_width, param->EmcQuseWidth); + write32(®s->ibdly, param->EmcIbdly); + write32(®s->einput, param->EmcEInput); + write32(®s->einput_duration, param->EmcEInputDuration); + write32(®s->puterm_extra, param->EmcPutermExtra); + write32(®s->puterm_width, param->EmcPutermWidth); + write32(®s->puterm_adj, param->EmcPutermAdj); + write32(®s->cdb_cntl_1, param->EmcCdbCntl1); + write32(®s->cdb_cntl_2, param->EmcCdbCntl2); + write32(®s->cdb_cntl_3, param->EmcCdbCntl3); + write32(®s->qrst, param->EmcQRst); + write32(®s->qsafe, param->EmcQSafe); + write32(®s->rdv, param->EmcRdv); + write32(®s->rdv_mask, param->EmcRdvMask); + write32(®s->qpop, param->EmcQpop); + write32(®s->ctt, param->EmcCtt); + write32(®s->ctt_duration, param->EmcCttDuration); + write32(®s->refresh, param->EmcRefresh); + write32(®s->burst_refresh_num, param->EmcBurstRefreshNum); + write32(®s->pre_refresh_req_cnt, param->EmcPreRefreshReqCnt); + write32(®s->pdex2wr, param->EmcPdEx2Wr); + write32(®s->pdex2rd, param->EmcPdEx2Rd); + write32(®s->pchg2pden, param->EmcPChg2Pden); + write32(®s->act2pden, param->EmcAct2Pden); + write32(®s->ar2pden, param->EmcAr2Pden); + write32(®s->rw2pden, param->EmcRw2Pden); + write32(®s->txsr, param->EmcTxsr); + write32(®s->txsrdll, param->EmcTxsrDll); + write32(®s->tcke, param->EmcTcke); + write32(®s->tckesr, param->EmcTckesr); + write32(®s->tpd, param->EmcTpd); + write32(®s->tfaw, param->EmcTfaw); + write32(®s->trpab, param->EmcTrpab); + write32(®s->tclkstable, param->EmcTClkStable); + write32(®s->tclkstop, param->EmcTClkStop); + write32(®s->trefbw, param->EmcTRefBw); + write32(®s->odt_write, param->EmcOdtWrite); + write32(®s->odt_read, param->EmcOdtRead); + write32(®s->fbio_cfg6, param->EmcFbioCfg6); + write32(®s->cfg_dig_dll, param->EmcCfgDigDll); + write32(®s->cfg_dig_dll_period, param->EmcCfgDigDllPeriod); /* Don't write bit 1: addr swizzle lock bit. Written at end of sequence. */ - writel(param->EmcFbioSpare & 0xfffffffd, ®s->fbio_spare); - - writel(param->EmcCfgRsv, ®s->cfg_rsv); - writel(param->EmcDllXformDqs0, ®s->dll_xform_dqs0); - writel(param->EmcDllXformDqs1, ®s->dll_xform_dqs1); - writel(param->EmcDllXformDqs2, ®s->dll_xform_dqs2); - writel(param->EmcDllXformDqs3, ®s->dll_xform_dqs3); - writel(param->EmcDllXformDqs4, ®s->dll_xform_dqs4); - writel(param->EmcDllXformDqs5, ®s->dll_xform_dqs5); - writel(param->EmcDllXformDqs6, ®s->dll_xform_dqs6); - writel(param->EmcDllXformDqs7, ®s->dll_xform_dqs7); - writel(param->EmcDllXformDqs8, ®s->dll_xform_dqs8); - writel(param->EmcDllXformDqs9, ®s->dll_xform_dqs9); - writel(param->EmcDllXformDqs10, ®s->dll_xform_dqs10); - writel(param->EmcDllXformDqs11, ®s->dll_xform_dqs11); - writel(param->EmcDllXformDqs12, ®s->dll_xform_dqs12); - writel(param->EmcDllXformDqs13, ®s->dll_xform_dqs13); - writel(param->EmcDllXformDqs14, ®s->dll_xform_dqs14); - writel(param->EmcDllXformDqs15, ®s->dll_xform_dqs15); - writel(param->EmcDllXformQUse0, ®s->dll_xform_quse0); - writel(param->EmcDllXformQUse1, ®s->dll_xform_quse1); - writel(param->EmcDllXformQUse2, ®s->dll_xform_quse2); - writel(param->EmcDllXformQUse3, ®s->dll_xform_quse3); - writel(param->EmcDllXformQUse4, ®s->dll_xform_quse4); - writel(param->EmcDllXformQUse5, ®s->dll_xform_quse5); - writel(param->EmcDllXformQUse6, ®s->dll_xform_quse6); - writel(param->EmcDllXformQUse7, ®s->dll_xform_quse7); - writel(param->EmcDllXformQUse8, ®s->dll_xform_quse8); - writel(param->EmcDllXformQUse9, ®s->dll_xform_quse9); - writel(param->EmcDllXformQUse10, ®s->dll_xform_quse10); - writel(param->EmcDllXformQUse11, ®s->dll_xform_quse11); - writel(param->EmcDllXformQUse12, ®s->dll_xform_quse12); - writel(param->EmcDllXformQUse13, ®s->dll_xform_quse13); - writel(param->EmcDllXformQUse14, ®s->dll_xform_quse14); - writel(param->EmcDllXformQUse15, ®s->dll_xform_quse15); - writel(param->EmcDllXformDq0, ®s->dll_xform_dq0); - writel(param->EmcDllXformDq1, ®s->dll_xform_dq1); - writel(param->EmcDllXformDq2, ®s->dll_xform_dq2); - writel(param->EmcDllXformDq3, ®s->dll_xform_dq3); - writel(param->EmcDllXformDq4, ®s->dll_xform_dq4); - writel(param->EmcDllXformDq5, ®s->dll_xform_dq5); - writel(param->EmcDllXformDq6, ®s->dll_xform_dq6); - writel(param->EmcDllXformDq7, ®s->dll_xform_dq7); - writel(param->EmcDllXformAddr0, ®s->dll_xform_addr0); - writel(param->EmcDllXformAddr1, ®s->dll_xform_addr1); - writel(param->EmcDllXformAddr2, ®s->dll_xform_addr2); - writel(param->EmcDllXformAddr3, ®s->dll_xform_addr3); - writel(param->EmcDllXformAddr4, ®s->dll_xform_addr4); - writel(param->EmcDllXformAddr5, ®s->dll_xform_addr5); - writel(param->EmcAcpdControl, ®s->acpd_control); - writel(param->EmcDsrVttgenDrv, ®s->dsr_vttgen_drv); - writel(param->EmcTxdsrvttgen, ®s->txdsrvttgen); - writel(param->EmcBgbiasCtl0, ®s->bgbias_ctl0); + write32(®s->fbio_spare, param->EmcFbioSpare & 0xfffffffd); + + write32(®s->cfg_rsv, param->EmcCfgRsv); + write32(®s->dll_xform_dqs0, param->EmcDllXformDqs0); + write32(®s->dll_xform_dqs1, param->EmcDllXformDqs1); + write32(®s->dll_xform_dqs2, param->EmcDllXformDqs2); + write32(®s->dll_xform_dqs3, param->EmcDllXformDqs3); + write32(®s->dll_xform_dqs4, param->EmcDllXformDqs4); + write32(®s->dll_xform_dqs5, param->EmcDllXformDqs5); + write32(®s->dll_xform_dqs6, param->EmcDllXformDqs6); + write32(®s->dll_xform_dqs7, param->EmcDllXformDqs7); + write32(®s->dll_xform_dqs8, param->EmcDllXformDqs8); + write32(®s->dll_xform_dqs9, param->EmcDllXformDqs9); + write32(®s->dll_xform_dqs10, param->EmcDllXformDqs10); + write32(®s->dll_xform_dqs11, param->EmcDllXformDqs11); + write32(®s->dll_xform_dqs12, param->EmcDllXformDqs12); + write32(®s->dll_xform_dqs13, param->EmcDllXformDqs13); + write32(®s->dll_xform_dqs14, param->EmcDllXformDqs14); + write32(®s->dll_xform_dqs15, param->EmcDllXformDqs15); + write32(®s->dll_xform_quse0, param->EmcDllXformQUse0); + write32(®s->dll_xform_quse1, param->EmcDllXformQUse1); + write32(®s->dll_xform_quse2, param->EmcDllXformQUse2); + write32(®s->dll_xform_quse3, param->EmcDllXformQUse3); + write32(®s->dll_xform_quse4, param->EmcDllXformQUse4); + write32(®s->dll_xform_quse5, param->EmcDllXformQUse5); + write32(®s->dll_xform_quse6, param->EmcDllXformQUse6); + write32(®s->dll_xform_quse7, param->EmcDllXformQUse7); + write32(®s->dll_xform_quse8, param->EmcDllXformQUse8); + write32(®s->dll_xform_quse9, param->EmcDllXformQUse9); + write32(®s->dll_xform_quse10, param->EmcDllXformQUse10); + write32(®s->dll_xform_quse11, param->EmcDllXformQUse11); + write32(®s->dll_xform_quse12, param->EmcDllXformQUse12); + write32(®s->dll_xform_quse13, param->EmcDllXformQUse13); + write32(®s->dll_xform_quse14, param->EmcDllXformQUse14); + write32(®s->dll_xform_quse15, param->EmcDllXformQUse15); + write32(®s->dll_xform_dq0, param->EmcDllXformDq0); + write32(®s->dll_xform_dq1, param->EmcDllXformDq1); + write32(®s->dll_xform_dq2, param->EmcDllXformDq2); + write32(®s->dll_xform_dq3, param->EmcDllXformDq3); + write32(®s->dll_xform_dq4, param->EmcDllXformDq4); + write32(®s->dll_xform_dq5, param->EmcDllXformDq5); + write32(®s->dll_xform_dq6, param->EmcDllXformDq6); + write32(®s->dll_xform_dq7, param->EmcDllXformDq7); + write32(®s->dll_xform_addr0, param->EmcDllXformAddr0); + write32(®s->dll_xform_addr1, param->EmcDllXformAddr1); + write32(®s->dll_xform_addr2, param->EmcDllXformAddr2); + write32(®s->dll_xform_addr3, param->EmcDllXformAddr3); + write32(®s->dll_xform_addr4, param->EmcDllXformAddr4); + write32(®s->dll_xform_addr5, param->EmcDllXformAddr5); + write32(®s->acpd_control, param->EmcAcpdControl); + write32(®s->dsr_vttgen_drv, param->EmcDsrVttgenDrv); + write32(®s->txdsrvttgen, param->EmcTxdsrvttgen); + write32(®s->bgbias_ctl0, param->EmcBgbiasCtl0); /* * Set pipe bypass enable bits before sending any DRAM commands. @@ -393,8 +396,8 @@ static void sdram_patch_bootrom(const struct sdram_params *param, BOOT_ROM_PATCH_CONTROL_OFFSET_MASK) >> BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT); addr = BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS + (addr << 2); - writel(param->BootRomPatchData, (uint32_t *)addr); - writel(1, ®s->timing_control); + write32((uint32_t *)addr, param->BootRomPatchData); + write32(®s->timing_control, 1); } } @@ -402,7 +405,7 @@ static void sdram_set_dpd3(const struct sdram_params *param, struct tegra_pmc_regs *regs) { /* Program DPD request */ - writel(param->PmcIoDpd3Req, ®s->io_dpd3_req); + write32(®s->io_dpd3_req, param->PmcIoDpd3Req); udelay(param->PmcIoDpd3ReqWait); } @@ -410,27 +413,27 @@ static void sdram_set_dli_trims(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Program DLI trims */ - writel(param->EmcDliTrimTxDqs0, ®s->dli_trim_txdqs0); - writel(param->EmcDliTrimTxDqs1, ®s->dli_trim_txdqs1); - writel(param->EmcDliTrimTxDqs2, ®s->dli_trim_txdqs2); - writel(param->EmcDliTrimTxDqs3, ®s->dli_trim_txdqs3); - writel(param->EmcDliTrimTxDqs4, ®s->dli_trim_txdqs4); - writel(param->EmcDliTrimTxDqs5, ®s->dli_trim_txdqs5); - writel(param->EmcDliTrimTxDqs6, ®s->dli_trim_txdqs6); - writel(param->EmcDliTrimTxDqs7, ®s->dli_trim_txdqs7); - writel(param->EmcDliTrimTxDqs8, ®s->dli_trim_txdqs8); - writel(param->EmcDliTrimTxDqs9, ®s->dli_trim_txdqs9); - writel(param->EmcDliTrimTxDqs10, ®s->dli_trim_txdqs10); - writel(param->EmcDliTrimTxDqs11, ®s->dli_trim_txdqs11); - writel(param->EmcDliTrimTxDqs12, ®s->dli_trim_txdqs12); - writel(param->EmcDliTrimTxDqs13, ®s->dli_trim_txdqs13); - writel(param->EmcDliTrimTxDqs14, ®s->dli_trim_txdqs14); - writel(param->EmcDliTrimTxDqs15, ®s->dli_trim_txdqs15); - - writel(param->EmcCaTrainingTimingCntl1, - ®s->ca_training_timing_cntl1); - writel(param->EmcCaTrainingTimingCntl2, - ®s->ca_training_timing_cntl2); + write32(®s->dli_trim_txdqs0, param->EmcDliTrimTxDqs0); + write32(®s->dli_trim_txdqs1, param->EmcDliTrimTxDqs1); + write32(®s->dli_trim_txdqs2, param->EmcDliTrimTxDqs2); + write32(®s->dli_trim_txdqs3, param->EmcDliTrimTxDqs3); + write32(®s->dli_trim_txdqs4, param->EmcDliTrimTxDqs4); + write32(®s->dli_trim_txdqs5, param->EmcDliTrimTxDqs5); + write32(®s->dli_trim_txdqs6, param->EmcDliTrimTxDqs6); + write32(®s->dli_trim_txdqs7, param->EmcDliTrimTxDqs7); + write32(®s->dli_trim_txdqs8, param->EmcDliTrimTxDqs8); + write32(®s->dli_trim_txdqs9, param->EmcDliTrimTxDqs9); + write32(®s->dli_trim_txdqs10, param->EmcDliTrimTxDqs10); + write32(®s->dli_trim_txdqs11, param->EmcDliTrimTxDqs11); + write32(®s->dli_trim_txdqs12, param->EmcDliTrimTxDqs12); + write32(®s->dli_trim_txdqs13, param->EmcDliTrimTxDqs13); + write32(®s->dli_trim_txdqs14, param->EmcDliTrimTxDqs14); + write32(®s->dli_trim_txdqs15, param->EmcDliTrimTxDqs15); + + write32(®s->ca_training_timing_cntl1, + param->EmcCaTrainingTimingCntl1); + write32(®s->ca_training_timing_cntl2, + param->EmcCaTrainingTimingCntl2); sdram_trigger_emc_timing_update(regs); udelay(param->EmcTimingControlWait); @@ -446,7 +449,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, * Assert dummy read of PIN register to ensure above write to PIN * register went through. 200 is the recommended value by NVIDIA. */ - dummy |= readl(®s->pin); + dummy |= read32(®s->pin); udelay(200 + param->EmcPinExtraWait); /* Deassert reset */ @@ -455,7 +458,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, * Assert dummy read of PIN register to ensure above write to PIN * register went through. 200 is the recommended value by NVIDIA. */ - dummy |= readl(®s->pin); + dummy |= read32(®s->pin); udelay(500 + param->EmcPinExtraWait); /* Enable clock enable signal */ @@ -464,7 +467,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, * Assert dummy read of PIN register to ensure above write to PIN * register went through. 200 is the recommended value by NVIDIA. */ - dummy |= readl(®s->pin); + dummy |= read32(®s->pin); udelay(param->EmcPinProgramWait); if (!dummy) { @@ -478,13 +481,13 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, EMC_NOP_NOP_CMD_MASK | EMC_NOP_NOP_DEV_SELECTN_MASK); /* Write mode registers */ - writel(param->EmcEmrs2, ®s->emrs2); - writel(param->EmcEmrs3, ®s->emrs3); - writel(param->EmcEmrs, ®s->emrs); - writel(param->EmcMrs, ®s->mrs); + write32(®s->emrs2, param->EmcEmrs2); + write32(®s->emrs3, param->EmcEmrs3); + write32(®s->emrs, param->EmcEmrs); + write32(®s->mrs, param->EmcMrs); if (param->EmcExtraModeRegWriteEnable) { - writel(param->EmcMrwExtra, ®s->mrs); + write32(®s->mrs, param->EmcMrwExtra); } } @@ -494,11 +497,11 @@ static void sdram_init_zq_calibration(const struct sdram_params *param, if ((param->EmcZcalWarmColdBootEnables & EMC_ZCAL_WARM_COLD_BOOT_ENABLES_COLDBOOT_MASK) == 1) { /* Need to initialize ZCAL on coldboot. */ - writel(param->EmcZcalInitDev0, ®s->zq_cal); + write32(®s->zq_cal, param->EmcZcalInitDev0); udelay(param->EmcZcalInitWait); if ((param->EmcDevSelect & 2) == 0) { - writel(param->EmcZcalInitDev1, ®s->zq_cal); + write32(®s->zq_cal, param->EmcZcalInitDev1); udelay(param->EmcZcalInitWait); } } else { @@ -510,9 +513,9 @@ static void sdram_set_zq_calibration(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Start periodic ZQ calibration */ - writel(param->EmcZcalInterval, ®s->zcal_interval); - writel(param->EmcZcalWaitCnt, ®s->zcal_wait_cnt); - writel(param->EmcZcalMrwCmd, ®s->zcal_mrw_cmd); + write32(®s->zcal_interval, param->EmcZcalInterval); + write32(®s->zcal_wait_cnt, param->EmcZcalWaitCnt); + write32(®s->zcal_mrw_cmd, param->EmcZcalMrwCmd); } static void sdram_set_refresh(const struct sdram_params *param, @@ -530,15 +533,15 @@ static void sdram_set_refresh(const struct sdram_params *param, } /* Enable refresh */ - writel((param->EmcDevSelect | EMC_REFCTRL_REF_VALID_ENABLED), - ®s->refctrl); + write32(®s->refctrl, + (param->EmcDevSelect | EMC_REFCTRL_REF_VALID_ENABLED)); - writel(param->EmcDynSelfRefControl, ®s->dyn_self_ref_control); - writel(param->EmcCfg, ®s->cfg); - writel(param->EmcSelDpdCtrl, ®s->sel_dpd_ctrl); + write32(®s->dyn_self_ref_control, param->EmcDynSelfRefControl); + write32(®s->cfg, param->EmcCfg); + write32(®s->sel_dpd_ctrl, param->EmcSelDpdCtrl); /* Write addr swizzle lock bit */ - writel(param->EmcFbioSpare, ®s->fbio_spare); + write32(®s->fbio_spare, param->EmcFbioSpare); /* Re-trigger timing to latch power saving functions */ sdram_trigger_emc_timing_update(regs); @@ -556,12 +559,13 @@ static void sdram_lock_carveouts(const struct sdram_params *param, struct tegra_mc_regs *regs) { /* Lock carveouts, and emem_cfg registers */ - writel(param->McVideoProtectWriteAccess, ®s->video_protect_reg_ctrl); - writel(MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED, - ®s->emem_cfg_access_ctrl); - writel(param->McSecCarveoutProtectWriteAccess, - ®s->sec_carveout_reg_ctrl); - writel(param->McMtsCarveoutRegCtrl, ®s->mts_carveout_reg_ctrl); + write32(®s->video_protect_reg_ctrl, + param->McVideoProtectWriteAccess); + write32(®s->emem_cfg_access_ctrl, + MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED); + write32(®s->sec_carveout_reg_ctrl, + param->McSecCarveoutProtectWriteAccess); + write32(®s->mts_carveout_reg_ctrl, param->McMtsCarveoutRegCtrl); } void sdram_init(const struct sdram_params *param) @@ -616,7 +620,7 @@ void sdram_init(const struct sdram_params *param) uint32_t sdram_get_ram_code(void) { struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE; - return ((readl(&pmc->strapping_opt_a) & + return ((read32(&pmc->strapping_opt_a) & PMC_STRAPPING_OPT_A_RAM_CODE_MASK) >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT); } diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 0584177d5e..e1d022a420 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -230,7 +230,7 @@ int spi_claim_bus(struct spi_slave *slave) else val |= SPI_CMD1_CS_SW_VAL; - writel(val, ®s->command1); + write32(®s->command1, val); return 0; } @@ -246,7 +246,7 @@ void spi_release_bus(struct spi_slave *slave) else val &= ~SPI_CMD1_CS_SW_VAL; - writel(val, ®s->command1); + write32(®s->command1, val); } static void dump_fifo_status(struct tegra_spi_channel *spi) @@ -383,12 +383,12 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi, /* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and * PIO transfers */ - writel(todo - 1, &spi->regs->dma_blk); + write32(&spi->regs->dma_blk, todo - 1); if (dir == SPI_SEND) { unsigned int to_fifo = bytes; while (to_fifo) { - writel(*p, &spi->regs->tx_fifo); + write32(&spi->regs->tx_fifo, *p); p++; to_fifo--; } @@ -493,11 +493,12 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, /* ensure bytes to send will be visible to DMA controller */ dcache_clean_by_mva(spi->out_buf, bytes); - writel((u32)&spi->regs->tx_fifo, &spi->dma_out->regs->apb_ptr); - writel((u32)spi->out_buf, &spi->dma_out->regs->ahb_ptr); + write32(&spi->dma_out->regs->apb_ptr, + (u32)&spi->regs->tx_fifo); + write32(&spi->dma_out->regs->ahb_ptr, (u32)spi->out_buf); setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_out); - writel(wcount, &spi->dma_out->regs->wcount); + write32(&spi->dma_out->regs->wcount, wcount); } else { spi->dma_in = dma_claim(); if (!spi->dma_in) @@ -506,15 +507,15 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, /* avoid data collisions */ dcache_clean_invalidate_by_mva(spi->in_buf, bytes); - writel((u32)&spi->regs->rx_fifo, &spi->dma_in->regs->apb_ptr); - writel((u32)spi->in_buf, &spi->dma_in->regs->ahb_ptr); + write32(&spi->dma_in->regs->apb_ptr, (u32)&spi->regs->rx_fifo); + write32(&spi->dma_in->regs->ahb_ptr, (u32)spi->in_buf); clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_in); - writel(wcount, &spi->dma_in->regs->wcount); + write32(&spi->dma_in->regs->wcount, wcount); } /* BLOCK_SIZE starts at n-1 */ - writel(todo - 1, &spi->regs->dma_blk); + write32(&spi->regs->dma_blk, todo - 1); return todo; } diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index 26aec20030..70fafee83e 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -56,19 +56,19 @@ static void tegra124_uart_init(struct tegra124_uart *uart_ptr) tegra124_uart_tx_flush(uart_ptr); // Disable interrupts. - writeb(0, &uart_ptr->ier); + write8(&uart_ptr->ier, 0); // Force DTR and RTS to high. - writeb(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr); + write8(&uart_ptr->mcr, UART8250_MCR_DTR | UART8250_MCR_RTS); // Set line configuration, access divisor latches. - writeb(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr); + write8(&uart_ptr->lcr, UART8250_LCR_DLAB | line_config); // Set the divisor. - writeb(divisor & 0xff, &uart_ptr->dll); - writeb((divisor >> 8) & 0xff, &uart_ptr->dlm); + write8(&uart_ptr->dll, divisor & 0xff); + write8(&uart_ptr->dlm, (divisor >> 8) & 0xff); // Hide the divisor latches. - writeb(line_config, &uart_ptr->lcr); + write8(&uart_ptr->lcr, line_config); // Enable FIFOs, and clear receive and transmit. - writeb(UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT, - &uart_ptr->fcr); + write8(&uart_ptr->fcr, + UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT); } static unsigned char tegra124_uart_rx_byte(struct tegra124_uart *uart_ptr) @@ -81,7 +81,7 @@ static unsigned char tegra124_uart_rx_byte(struct tegra124_uart *uart_ptr) static void tegra124_uart_tx_byte(struct tegra124_uart *uart_ptr, unsigned char data) { while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE)); - writeb(data, &uart_ptr->thr); + write8(&uart_ptr->thr, data); } static void tegra124_uart_tx_flush(struct tegra124_uart *uart_ptr) diff --git a/src/soc/nvidia/tegra132/addressmap.c b/src/soc/nvidia/tegra132/addressmap.c index 377d083e02..5940db7067 100644 --- a/src/soc/nvidia/tegra132/addressmap.c +++ b/src/soc/nvidia/tegra132/addressmap.c @@ -187,9 +187,9 @@ void trustzone_region_init(void) return; /* Set the carveout region. */ - writel(tz_base_mib << 20, &mc->security_cfg0); - writel(tz_size_mib, &mc->security_cfg1); + write32(&mc->security_cfg0, tz_base_mib << 20); + write32(&mc->security_cfg1, tz_size_mib); /* Enable SMMU translations */ - writel(MC_SMMU_CONFIG_ENABLE, &mc->smmu_config); + write32(&mc->smmu_config, MC_SMMU_CONFIG_ENABLE); } diff --git a/src/soc/nvidia/tegra132/bootblock.c b/src/soc/nvidia/tegra132/bootblock.c index 6fd36eb2bd..317ab4a1f6 100644 --- a/src/soc/nvidia/tegra132/bootblock.c +++ b/src/soc/nvidia/tegra132/bootblock.c @@ -46,7 +46,7 @@ static void save_odmdata(void) bct_offset = read32((void *)(TEGRA_SRAM_BASE + BCT_OFFSET_IN_BIT)); if (bct_offset > TEGRA_SRAM_BASE && bct_offset < TEGRA_SRAM_MAX) { odmdata = read32((void *)(bct_offset + ODMDATA_OFFSET_IN_BCT)); - writel(odmdata, &pmc->odmdata); + write32(&pmc->odmdata, odmdata); } } diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c index 1cc59add84..f9356a91bc 100644 --- a/src/soc/nvidia/tegra132/ccplex.c +++ b/src/soc/nvidia/tegra132/ccplex.c @@ -46,12 +46,12 @@ static int ccplex_start(void) struct tegra_pmc_regs * const pmc = PMC_REGS; /* Set the handshake bit to be knocked down. */ - writel(handshake_mask, &pmc->scratch118); + write32(&pmc->scratch118, handshake_mask); /* Assert nCXRSET[1] */ reg = read32(CLK_RST_REG(rst_cpu_cmplx_set)); reg |= cxreset1_mask; - writel(reg, CLK_RST_REG(rst_cpu_cmplx_set)); + write32(CLK_RST_REG(rst_cpu_cmplx_set), reg); stopwatch_init_msecs_expire(&sw, timeout_ms); while (1) { @@ -140,14 +140,14 @@ static void request_ram_repair(void) /* Perform cluster 0 ram repair */ reg = read32(&flow->ram_repair); reg |= req; - writel(reg, &flow->ram_repair); + write32(&flow->ram_repair, reg); while ((read32(&flow->ram_repair) & sts) != sts) ; /* Perform cluster 1 ram repair */ reg = read32(&flow->ram_repair_cluster1); reg |= req; - writel(reg, &flow->ram_repair_cluster1); + write32(&flow->ram_repair_cluster1, reg); while ((read32(&flow->ram_repair_cluster1) & sts) != sts) ; @@ -169,11 +169,11 @@ void ccplex_cpu_prepare(void) static void start_common_clocks(void) { /* Clear fast CPU partition reset. */ - writel(CRC_RST_CPUG_CLR_NONCPU, CLK_RST_REG(rst_cpug_cmplx_clr)); + write32(CLK_RST_REG(rst_cpug_cmplx_clr), CRC_RST_CPUG_CLR_NONCPU); /* Clear reset of L2 and CoreSight components. */ - writel(CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG, - CLK_RST_REG(rst_cpug_cmplx_clr)); + write32(CLK_RST_REG(rst_cpug_cmplx_clr), + CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG); } void ccplex_cpu_start(void *entry_addr) diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c index 4cd8a5886d..c13a086501 100644 --- a/src/soc/nvidia/tegra132/clock.c +++ b/src/soc/nvidia/tegra132/clock.c @@ -163,7 +163,7 @@ struct { */ static u32 clock_get_osc_bits(void) { - return (readl(CLK_RST_REG(osc_ctrl)) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; + return (read32(CLK_RST_REG(osc_ctrl)) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; } int clock_get_osc_khz(void) @@ -173,7 +173,7 @@ int clock_get_osc_khz(void) int clock_get_pll_input_khz(void) { - u32 osc_ctrl = readl(CLK_RST_REG(osc_ctrl)); + u32 osc_ctrl = read32(CLK_RST_REG(osc_ctrl)); u32 osc_bits = (osc_ctrl & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; u32 pll_ref_div = (osc_ctrl & OSC_PREDIV_MASK) >> OSC_PREDIV_SHIFT; return osc_table[osc_bits].khz >> pll_ref_div; @@ -186,11 +186,11 @@ void clock_init_arm_generic_timer(void) set_cntfrq(freq); /* Record the system timer frequency. */ - writel(freq, &sysctr->cntfid0); + write32(&sysctr->cntfid0, freq); /* Enable the system counter. */ uint32_t cntcr = read32(&sysctr->cntcr); cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG; - writel(cntcr, &sysctr->cntcr); + write32(&sysctr->cntcr, cntcr); } #define SOR0_CLK_SEL0 (1 << 14) @@ -221,18 +221,18 @@ static void init_pll(u32 *base, u32 *misc, const union pll_fields pll, u32 lock) pll.div.lfcon << PLL_MISC_LFCON_SHIFT; /* Write dividers but BYPASS the PLL while we're messing with it. */ - writel(dividers | PLL_BASE_BYPASS, base); + write32(base, dividers | PLL_BASE_BYPASS); /* * Set Lock bit, CPCON and LFCON fields (default to 0 if it doesn't * exist for this PLL) */ - writel(lock | misc_con, misc); + write32(misc, lock | misc_con); /* Enable PLL and take it back out of BYPASS */ - writel(dividers | PLL_BASE_ENABLE, base); + write32(base, dividers | PLL_BASE_ENABLE); /* Wait for lock ready */ - while (!(readl(base) & PLL_BASE_LOCK)); + while (!(read32(base) & PLL_BASE_LOCK)); } static void init_utmip_pll(void) @@ -243,14 +243,14 @@ static void init_utmip_pll(void) clrbits_le32(CLK_RST_REG(utmip_pll_cfg2), 1 << 30); /* PHY_XTAL_CLKEN */ udelay(1); - writel(80 << 16 | 1 << 8 | 0, CLK_RST_REG(utmip_pll_cfg0));/* 960MHz * 1 / 80 == 12 MHz */ + write32(CLK_RST_REG(utmip_pll_cfg0), 80 << 16 | 1 << 8 | 0);/* 960MHz * 1 / 80 == 12 MHz */ - writel(div_round_up(khz, 8000) << 27 | 0 << 16 | 0 << 14 | 0 << 12 | div_round_up(khz, 102) << 0 | 0, - CLK_RST_REG(utmip_pll_cfg1)); + write32(CLK_RST_REG(utmip_pll_cfg1), + div_round_up(khz, 8000) << 27 | 0 << 16 | 0 << 14 | 0 << 12 | div_round_up(khz, 102) << 0 | 0); /* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */ - writel(0 << 24 | div_round_up(khz, 3200) << 18 | div_round_up(khz, 256) << 6 | 0 << 4 | 0 << 2 | 0 << 0 | 0, - CLK_RST_REG(utmip_pll_cfg2)); + write32(CLK_RST_REG(utmip_pll_cfg2), + 0 << 24 | div_round_up(khz, 3200) << 18 | div_round_up(khz, 256) << 6 | 0 << 4 | 0 << 2 | 0 << 0 | 0); setbits_le32(CLK_RST_REG(utmip_pll_cfg2), 1 << 30); /* PHY_XTAL_CLKEN */ } @@ -274,12 +274,12 @@ static void graphics_pll(void) * that it is needed. */ u32 scfg = (1 << 28) | (1 << 24) | (1 << 22); - writel(scfg, cfg); + write32(cfg, scfg); init_pll(CLK_RST_REG(plldp_base), CLK_RST_REG(plldp_misc), osc_table[osc].plldp, PLLDPD2_MISC_LOCK_ENABLE); /* leave dither and undoc bits set, release clamp */ scfg = (1<<28) | (1<<24); - writel(scfg, cfg); + write32(cfg, scfg); } /* @@ -387,8 +387,8 @@ u32 clock_configure_plld(u32 frequency) * been determined through trial and error (must lead to div 13 at 24MHz). */ void clock_early_uart(void) { - writel(CLK_SRC_DEV_ID(UARTA, CLK_M) << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900), - CLK_RST_REG(clk_src_uarta)); + write32(CLK_RST_REG(clk_src_uarta), + CLK_SRC_DEV_ID(UARTA, CLK_M) << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900)); clock_enable_clear_reset_l(CLK_L_UARTA); } @@ -437,22 +437,22 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, * values after coldboot reset). */ - writel(misc1, CLK_RST_REG(pllm_misc1)); - writel(misc2, CLK_RST_REG(pllm_misc2)); + write32(CLK_RST_REG(pllm_misc1), misc1); + write32(CLK_RST_REG(pllm_misc2), misc2); /* PLLM.BASE needs BYPASS=0, different from general init_pll */ - base = readl(CLK_RST_REG(pllm_base)); + base = read32(CLK_RST_REG(pllm_base)); base &= ~(PLLCMX_BASE_DIVN_MASK | PLLCMX_BASE_DIVM_MASK | PLLM_BASE_DIVP_MASK | PLL_BASE_BYPASS); base |= ((m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT) | (p << PLL_BASE_DIVP_SHIFT)); - writel(base, CLK_RST_REG(pllm_base)); + write32(CLK_RST_REG(pllm_base), base); setbits_le32(CLK_RST_REG(pllm_base), PLL_BASE_ENABLE); /* stable_time is required, before we can start to check lock. */ udelay(stable_time); - while (!(readl(CLK_RST_REG(pllm_base)) & PLL_BASE_LOCK)) + while (!(read32(CLK_RST_REG(pllm_base)) & PLL_BASE_LOCK)) udelay(1); /* @@ -466,7 +466,7 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, /* Enable and start MEM(MC) and EMC. */ clock_enable_clear_reset(0, CLK_H_MEM | CLK_H_EMC, 0, 0, 0, 0); - writel(emc_source, CLK_RST_REG(clk_src_emc)); + write32(CLK_RST_REG(clk_src_emc), emc_source); udelay(IO_STABILIZATION_DELAY); } @@ -477,9 +477,9 @@ void clock_cpu0_config(void) u32 timeout = 0; /* disable IDDQ */ - reg = readl(&clst_clk->pllx_misc3); + reg = read32(&clst_clk->pllx_misc3); reg &= ~PLLX_IDDQ; - writel(reg, &clst_clk->pllx_misc3); + write32(&clst_clk->pllx_misc3, reg); /* init pllx */ init_pll(&clst_clk->pllx_base, &clst_clk->pllx_misc, @@ -490,9 +490,9 @@ void clock_cpu0_config(void) * when above pllx programming has taken effect. */ do { - if (readl(&clst_clk->misc_ctrl) & CLK_SWITCH_MATCH) { - writel((CC_CCLK_BRST_POL_PLLX_OUT0_LJ << 28), - &clst_clk->cclk_brst_pol); + if (read32(&clst_clk->misc_ctrl) & CLK_SWITCH_MATCH) { + write32(&clst_clk->cclk_brst_pol, + (CC_CCLK_BRST_POL_PLLX_OUT0_LJ << 28)); break; } @@ -512,8 +512,8 @@ void clock_cpu0_config(void) void clock_halt_avp(void) { for (;;) - writel(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT, - &flow->halt_cop_events); + write32(&flow->halt_cop_events, + FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT); } void clock_init(void) @@ -521,7 +521,7 @@ void clock_init(void) u32 osc = clock_get_osc_bits(); /* Set PLLC dynramp_step A to 0x2b and B to 0xb (from U-Boot -- why? */ - writel(0x2b << 17 | 0xb << 9, CLK_RST_REG(pllc_misc2)); + write32(CLK_RST_REG(pllc_misc2), 0x2b << 17 | 0xb << 9); /* Max out the AVP clock before everything else (need PLLC for that). */ init_pll(CLK_RST_REG(pllc_base), CLK_RST_REG(pllc_misc), @@ -529,12 +529,12 @@ void clock_init(void) /* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA * features section in the TRM). */ - writel(1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT, - CLK_RST_REG(clk_sys_rate)); /* pclk = hclk = sclk/2 */ - writel(CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN, - CLK_RST_REG(pllc_out)); - writel(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT, - CLK_RST_REG(sclk_brst_pol)); /* sclk = 300 MHz */ + write32(CLK_RST_REG(clk_sys_rate), + 1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT); /* pclk = hclk = sclk/2 */ + write32(CLK_RST_REG(pllc_out), + CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN); + write32(CLK_RST_REG(sclk_brst_pol), + SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT); /* sclk = 300 MHz */ /* Change the oscillator drive strength (from U-Boot -- why?) */ clrsetbits_le32(CLK_RST_REG(osc_ctrl), OSC_XOFS_MASK, @@ -549,10 +549,10 @@ void clock_init(void) OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT); /* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */ - writel((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT, - CLK_RST_REG(pllp_outa)); - writel((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT, - CLK_RST_REG(pllp_outb)); + write32(CLK_RST_REG(pllp_outa), + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT); + write32(CLK_RST_REG(pllp_outb), + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT); /* init pllu */ init_pll(CLK_RST_REG(pllu_base), CLK_RST_REG(pllu_misc), @@ -565,9 +565,9 @@ void clock_init(void) void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg, u32 *rst_dev_clr_reg) { - writel(val, clk_enb_set_reg); + write32(clk_enb_set_reg, val); udelay(IO_STABILIZATION_DELAY); - writel(val, rst_dev_clr_reg); + write32(rst_dev_clr_reg, val); } static u32 * const clk_enb_set_arr[DEV_CONFIG_BLOCKS] = { @@ -613,7 +613,7 @@ static void clock_write_regs(u32 * const regs[DEV_CONFIG_BLOCKS], for (; i < DEV_CONFIG_BLOCKS; i++) if (bits[i]) - writel(bits[i], regs[i]); + write32(regs[i], bits[i]); } void clock_enable_regs(u32 bits[DEV_CONFIG_BLOCKS]) @@ -648,9 +648,9 @@ void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x) static void clock_reset_dev(u32 *setaddr, u32 *clraddr, u32 bit) { - writel(bit, setaddr); + write32(setaddr, bit); udelay(LOGIC_STABILIZATION_DELAY); - writel(bit, clraddr); + write32(clraddr, bit); } void clock_reset_l(u32 bit) diff --git a/src/soc/nvidia/tegra132/cpu.c b/src/soc/nvidia/tegra132/cpu.c index 8cd2c0faea..b6f0cfec11 100644 --- a/src/soc/nvidia/tegra132/cpu.c +++ b/src/soc/nvidia/tegra132/cpu.c @@ -40,15 +40,15 @@ static void enable_core_clocks(int cpu) /* Clear reset of CPU components. */ if (cpu == 0) - writel(cpu0_clocks, CLK_RST_REG(rst_cpug_cmplx_clr)); + write32(CLK_RST_REG(rst_cpug_cmplx_clr), cpu0_clocks); else - writel(cpu1_clocks, CLK_RST_REG(rst_cpug_cmplx_clr)); + write32(CLK_RST_REG(rst_cpug_cmplx_clr), cpu1_clocks); } static void set_armv8_32bit_reset_vector(uintptr_t entry) { void * const evp_cpu_reset_vector = EVP_CPU_RESET_VECTOR; - writel(entry, evp_cpu_reset_vector); + write32(evp_cpu_reset_vector, entry); } static void set_armv8_64bit_reset_vector(uintptr_t entry) @@ -56,8 +56,8 @@ static void set_armv8_64bit_reset_vector(uintptr_t entry) struct tegra_pmc_regs * const pmc = PMC_REGS; /* Currently assume 32-bit addresses only. */ - writel(entry, &pmc->secure_scratch34); - writel(0, &pmc->secure_scratch35); + write32(&pmc->secure_scratch34, entry); + write32(&pmc->secure_scratch35, 0); } void cpu_prepare_startup(void *entry_64) diff --git a/src/soc/nvidia/tegra132/dc.c b/src/soc/nvidia/tegra132/dc.c index a3ba9e6fe7..07eac2e687 100644 --- a/src/soc/nvidia/tegra132/dc.c +++ b/src/soc/nvidia/tegra132/dc.c @@ -38,7 +38,7 @@ unsigned long READL(void * p) if (dump > 1) printk(BIOS_SPEW, "readl %p\n", p); - value = readl(p); + value = read32(p); if (dump) printk(BIOS_SPEW, "readl %p %08lx\n", p, value); return value; @@ -48,7 +48,7 @@ void WRITEL(unsigned long value, void * p) { if (dump) printk(BIOS_SPEW, "writel %p %08lx\n", p, value); - writel(value, p); + write32(p, value); } /* return in 1000ths of a Hertz */ diff --git a/src/soc/nvidia/tegra132/dsi.c b/src/soc/nvidia/tegra132/dsi.c index 8508b6666d..1af24e140c 100644 --- a/src/soc/nvidia/tegra132/dsi.c +++ b/src/soc/nvidia/tegra132/dsi.c @@ -869,7 +869,7 @@ static int dsi_enable(struct soc_nvidia_tegra132_config *config) tegra_output_dsi_setup_clock(dsi_a, config); /* configure APB_MISC_GP_MIPI_PAD_CTRL_0 */ - writel(DSIB_MODE_DSI, (unsigned int *)APB_MISC_GP_MIPI_PAD_CTRL_0); + write32((unsigned int *)APB_MISC_GP_MIPI_PAD_CTRL_0, DSIB_MODE_DSI); /* configure phy interface timing registers */ tegra_dsi_set_phy_timing(dsi_a); diff --git a/src/soc/nvidia/tegra132/flow_ctrl.c b/src/soc/nvidia/tegra132/flow_ctrl.c index 6d7d11590c..213dca2779 100644 --- a/src/soc/nvidia/tegra132/flow_ctrl.c +++ b/src/soc/nvidia/tegra132/flow_ctrl.c @@ -62,14 +62,14 @@ static uint32_t flowctrl_read_cpu_csr(int cpu) static void flowctrl_write_cpu_csr(int cpu, uint32_t val) { - writel(val, tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]); - val = readl(tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]); + write32(tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu], val); + val = read32(tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]); } void flowctrl_write_cpu_halt(int cpu, uint32_t val) { - writel(val, tegra_flowctrl_base + flowctrl_offset_halt_cpu[cpu]); - val = readl(tegra_flowctrl_base + flowctrl_offset_halt_cpu[cpu]); + write32(tegra_flowctrl_base + flowctrl_offset_halt_cpu[cpu], val); + val = read32(tegra_flowctrl_base + flowctrl_offset_halt_cpu[cpu]); } static void flowctrl_prepare_cpu_off(int cpu) diff --git a/src/soc/nvidia/tegra132/i2c6.c b/src/soc/nvidia/tegra132/i2c6.c index ef86126935..1ae8db3075 100644 --- a/src/soc/nvidia/tegra132/i2c6.c +++ b/src/soc/nvidia/tegra132/i2c6.c @@ -43,7 +43,7 @@ static void remove_clamps(int id) return; /* Remove clamp */ - writel((1 << id), &pmc->remove_clamping_cmd); + write32(&pmc->remove_clamping_cmd, (1 << id)); /* Wait for clamp off */ while (partition_clamp_on(id)) @@ -86,7 +86,7 @@ void soc_configure_i2c6pad(void) soc_configure_host1x(); /* Now we can write the I2C6 mux in DPAUX */ - writel(I2C6_PADCTL, (void *)DPAUX_HYBRID_PADCTL); + write32((void *)DPAUX_HYBRID_PADCTL, I2C6_PADCTL); /* * Delay before turning off Host1X/DPAUX clocks. diff --git a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c index 29fb9dedd6..8392a58228 100644 --- a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c @@ -261,17 +261,17 @@ inline static void write32(uint32_t val, void *addr) inline static void setbits32(uint32_t bits, void *addr) { - writel(read32(addr) | bits, addr); + write32(addr, read32(addr) | bits); } inline static void clrbits32(uint32_t bits, void *addr) { - writel(read32(addr) & ~bits, addr); + write32(addr, read32(addr) & ~bits); } static void __attribute__((noreturn)) reset(void) { - writel(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr); + write32(clk_rst_rst_devices_l_ptr, SWR_TRIG_SYS_RST); halt(); } @@ -370,18 +370,18 @@ static void enable_uart(void) clrbits32(uart_mask, uart_rst_reg); /* Program UART clock source: PLLP (408000000) */ - writel(0, uart_clk_source); + write32(uart_clk_source, 0); /* Program 115200n8 to the uart port */ /* baud-rate of 115200 */ - writel(LCR_DLAB, (uart_base + UART_LCR)); - writel((UART_RATE_115200 & 0xff), (uart_base + UART_THR_DLAB)); - writel((UART_RATE_115200 >> 8), (uart_base + UART_IER_DLAB)); + write32((uart_base + UART_LCR), LCR_DLAB); + write32((uart_base + UART_THR_DLAB), (UART_RATE_115200 & 0xff)); + write32((uart_base + UART_IER_DLAB), (UART_RATE_115200 >> 8)); /* 8-bit and no parity */ - writel(LCR_WD_SIZE_8, (uart_base + UART_LCR)); + write32((uart_base + UART_LCR), LCR_WD_SIZE_8); /* enable and clear RX/TX FIFO */ - writel((FCR_TX_CLR + FCR_RX_CLR + FCR_EN_FIFO), - (uart_base + UART_IIR_FCR)); + write32((uart_base + UART_IIR_FCR), + (FCR_TX_CLR + FCR_RX_CLR + FCR_EN_FIFO)); } /* Accessors. */ @@ -401,7 +401,7 @@ static unsigned get_osc_freq(void) static void enable_jtag(void) { - writel(PP_CONFIG_CTL_JTAG, misc_pp_config_ctl_ptr); + write32(misc_pp_config_ctl_ptr, PP_CONFIG_CTL_JTAG); } /* Clock configuration. */ @@ -417,7 +417,7 @@ static void config_oscillator(void) osc_ctrl &= ~OSC_XOFS_MASK; osc_ctrl |= (xofs << OSC_XOFS_SHIFT); osc_ctrl |= OSC_XOE; - writel(osc_ctrl, clk_rst_osc_ctrl_ptr); + write32(clk_rst_osc_ctrl_ptr, osc_ctrl); } static void config_pllu(void) @@ -462,24 +462,24 @@ static void config_pllu(void) // Configure PLLU. uint32_t base = PLLU_BYPASS | PLLU_OVERRIDE | (divn << PLLU_DIVN_SHIFT) | (divm << PLLU_DIVM_SHIFT); - writel(base, clk_rst_pllu_base_ptr); + write32(clk_rst_pllu_base_ptr, base); uint32_t misc = (cpcon << PLLU_CPCON_SHIFT) | (lfcon << PLLU_LFCON_SHIFT); - writel(misc, clk_rst_pllu_misc_ptr); + write32(clk_rst_pllu_misc_ptr, misc); // Enable PLLU. base &= ~PLLU_BYPASS; base |= PLLU_ENABLE; - writel(base, clk_rst_pllu_base_ptr); + write32(clk_rst_pllu_base_ptr, base); misc |= PLLU_LOCK_ENABLE; - writel(misc, clk_rst_pllu_misc_ptr); + write32(clk_rst_pllu_misc_ptr, misc); } static void enable_cpu_clocks(void) { // Enable the CPU complex clock. - writel(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr); - writel(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr); + write32(clk_rst_clk_enb_l_set_ptr, CLK_ENB_CPU); + write32(clk_rst_clk_enb_v_set_ptr, CLK_ENB_CPUG | CLK_ENB_CPULP); } @@ -489,7 +489,7 @@ static void enable_cpu_clocks(void) static void config_core_sight(void) { // Enable the CoreSight clock. - writel(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr); + write32(clk_rst_clk_out_enb_u_set_ptr, CLK_ENB_CSITE); /* * De-assert CoreSight reset. @@ -497,7 +497,7 @@ static void config_core_sight(void) * now. It will be restored to its original clock source * when the CPU-side restoration code runs. */ - writel(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr); + write32(clk_rst_rst_dev_u_clr_ptr, SWR_CSITE_RST); } @@ -508,11 +508,11 @@ static void clear_cpu_resets(void) /* Hold CPU1 in reset */ setbits32(SET_CXRESET1, clk_rst_rst_cpulp_cmplx_set_ptr); - writel(CLR_NONCPURESET | CLR_L2RESET | CLR_PRESETDBG, - clk_rst_rst_cpug_cmplx_clr_ptr); + write32(clk_rst_rst_cpug_cmplx_clr_ptr, + CLR_NONCPURESET | CLR_L2RESET | CLR_PRESETDBG); - writel(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0, - clk_rst_rst_cpug_cmplx_clr_ptr); + write32(clk_rst_rst_cpug_cmplx_clr_ptr, + CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0); } @@ -542,7 +542,8 @@ static void power_on_partition(unsigned id) uint32_t bit = 0x1 << id; if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) { // Partition is not on. Turn it on. - writel(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr); + write32(pmc_ctlr_pwrgate_toggle_ptr, + id | PWRGATE_TOGGLE_START); // Wait until the partition is powerd on. while (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) @@ -572,15 +573,15 @@ static void power_on_main_cpu(void) */ uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr); - writel(orig_timer * (204000000 / 32768), - pmc_ctlr_cpupwrgood_timer_ptr); + write32(pmc_ctlr_cpupwrgood_timer_ptr, + orig_timer * (204000000 / 32768)); power_on_partition(PARTID_CRAIL); power_on_partition(PARTID_C0NC); power_on_partition(PARTID_CE0); // Restore the original PMC_CPUPWRGOOD_TIMER. - writel(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr); + write32(pmc_ctlr_cpupwrgood_timer_ptr, orig_timer); } @@ -609,7 +610,7 @@ void lp0_resume(void) config_oscillator(); // Program SUPER_CCLK_DIVIDER. - writel(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr); + write32(clk_rst_super_cclk_div_ptr, SUPER_CDIV_ENB); config_core_sight(); @@ -623,12 +624,12 @@ void lp0_resume(void) * T132 always resets to AARCH32 and SW needs to write RMR_EL3 * to bootstrap into AARCH64. */ - writel(get_wakeup_vector(), pmc_ctlr_secure_scratch34_ptr); - writel(0, pmc_ctlr_secure_scratch35_ptr); - writel((uint32_t)aarch64_trampoline, evp_cpu_reset_ptr); + write32(pmc_ctlr_secure_scratch34_ptr, get_wakeup_vector()); + write32(pmc_ctlr_secure_scratch35_ptr, 0); + write32(evp_cpu_reset_ptr, (uint32_t)aarch64_trampoline); // Select CPU complex clock source. - writel(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr); + write32(clk_rst_cclk_burst_policy_ptr, CCLK_PLLP_BURST_POLICY); // Disable PLLX since it isn't used as CPU clock source. clrbits32(PLLX_ENABLE, clk_rst_pllx_base_ptr); @@ -637,12 +638,12 @@ void lp0_resume(void) uint32_t ack_width = read32(clk_rst_cpu_softrst_ctrl2_ptr); ack_width &= ~CAR2PMC_CPU_ACK_WIDTH_MASK; ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT; - writel(ack_width, clk_rst_cpu_softrst_ctrl2_ptr); + write32(clk_rst_cpu_softrst_ctrl2_ptr, ack_width); // Disable VPR. - writel(0, mc_video_protect_size_mb_ptr); - writel(VIDEO_PROTECT_WRITE_ACCESS_DISABLE, - mc_video_protect_reg_ctrl_ptr); + write32(mc_video_protect_size_mb_ptr, 0); + write32(mc_video_protect_reg_ctrl_ptr, + VIDEO_PROTECT_WRITE_ACCESS_DISABLE); enable_cpu_clocks(); @@ -655,8 +656,8 @@ void lp0_resume(void) // Halt the AVP. while (1) - writel(FLOW_MODE_STOP | EVENT_JTAG, - flow_ctlr_halt_cop_events_ptr); + write32(flow_ctlr_halt_cop_events_ptr, + FLOW_MODE_STOP | EVENT_JTAG); } diff --git a/src/soc/nvidia/tegra132/mipi.c b/src/soc/nvidia/tegra132/mipi.c index abd2230378..1768fa0fd3 100644 --- a/src/soc/nvidia/tegra132/mipi.c +++ b/src/soc/nvidia/tegra132/mipi.c @@ -43,13 +43,13 @@ static struct tegra_mipi mipi_data = { static inline unsigned long tegra_mipi_readl(struct tegra_mipi *mipi, unsigned long reg) { - return readl(mipi->regs + (reg << 2)); + return read32(mipi->regs + (reg << 2)); } static inline void tegra_mipi_writel(struct tegra_mipi *mipi, unsigned long value, unsigned long reg) { - writel(value, mipi->regs + (reg << 2)); + write32(mipi->regs + (reg << 2), value); } static const struct calibration_regs tegra124_mipi_calibration_regs[] = { diff --git a/src/soc/nvidia/tegra132/padconfig.c b/src/soc/nvidia/tegra132/padconfig.c index 790f10f9c0..46cf944441 100644 --- a/src/soc/nvidia/tegra132/padconfig.c +++ b/src/soc/nvidia/tegra132/padconfig.c @@ -36,7 +36,7 @@ static inline uint32_t pad_get_pinmux(int index) static inline void pad_set_pinmux(int index, uint32_t reg) { - return writel(reg, &pinmux_regs[index]); + return write32(&pinmux_regs[index], reg); } static inline void pad_set_gpio_out(int gpio_index, int val) @@ -45,10 +45,10 @@ static inline void pad_set_gpio_out(int gpio_index, int val) int port = gpio_index_to_port(gpio_index); int bit = gpio_to_bit(gpio_index); - writel((1 << (bit + GPIO_GPIOS_PER_PORT)) | (val << bit), - ®s->out_value_mask[port]); - writel((1 << (bit + GPIO_GPIOS_PER_PORT)) | (1 << bit), - ®s->out_enable_mask[port]); + write32(®s->out_value_mask[port], + (1 << (bit + GPIO_GPIOS_PER_PORT)) | (val << bit)); + write32(®s->out_enable_mask[port], + (1 << (bit + GPIO_GPIOS_PER_PORT)) | (1 << bit)); } static inline void pad_set_mode(int gpio_index, int sfio_or_gpio) @@ -57,8 +57,8 @@ static inline void pad_set_mode(int gpio_index, int sfio_or_gpio) int port = gpio_index_to_port(gpio_index); int bit = gpio_to_bit(gpio_index); - writel((1 << (bit + GPIO_GPIOS_PER_PORT)) | (sfio_or_gpio << bit), - ®s->config_mask[port]); + write32(®s->config_mask[port], + (1 << (bit + GPIO_GPIOS_PER_PORT)) | (sfio_or_gpio << bit)); } static inline void pad_set_gpio_mode(int gpio_index) diff --git a/src/soc/nvidia/tegra132/power.c b/src/soc/nvidia/tegra132/power.c index 0ebfd7c53e..b9ac90acf8 100644 --- a/src/soc/nvidia/tegra132/power.c +++ b/src/soc/nvidia/tegra132/power.c @@ -41,7 +41,7 @@ void power_ungate_partition(uint32_t id) pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK); pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT); pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START; - writel(pwrgate_toggle, &pmc->pwrgate_toggle); + write32(&pmc->pwrgate_toggle, pwrgate_toggle); /* Wait for the request to be accepted. */ while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START) diff --git a/src/soc/nvidia/tegra132/sdram.c b/src/soc/nvidia/tegra132/sdram.c index 14d2b50fe1..65dce9b4cd 100644 --- a/src/soc/nvidia/tegra132/sdram.c +++ b/src/soc/nvidia/tegra132/sdram.c @@ -31,7 +31,7 @@ static void sdram_patch(uintptr_t addr, uint32_t value) { if (addr) - writel(value, (uint32_t*)addr); + write32((uint32_t *)addr, value); } static void writebits(uint32_t value, uint32_t *addr, uint32_t mask) @@ -44,7 +44,7 @@ static void sdram_configure_pmc(const struct sdram_params *param, struct tegra_pmc_regs *regs) { /* VDDP Select */ - writel(param->PmcVddpSel, ®s->vddp_sel); + write32(®s->vddp_sel, param->PmcVddpSel); udelay(param->PmcVddpSelWait); /* Set DDR pad voltage */ @@ -60,7 +60,7 @@ static void sdram_configure_pmc(const struct sdram_params *param, writebits(param->PmcNoIoPower, ®s->no_iopower, (PMC_NO_IOPOWER_MEM_MASK | PMC_NO_IOPOWER_MEM_COMP_MASK)); - writel(param->PmcRegShort, ®s->reg_short); + write32(®s->reg_short, param->PmcRegShort); } static void sdram_start_clocks(const struct sdram_params *param) @@ -100,148 +100,151 @@ static void sdram_deassert_sel_dpd(const struct sdram_params *param, static void sdram_set_swizzle(const struct sdram_params *param, struct tegra_emc_regs *regs) { - writel(param->EmcSwizzleRank0ByteCfg, ®s->swizzle_rank0_byte_cfg); - writel(param->EmcSwizzleRank0Byte0, ®s->swizzle_rank0_byte0); - writel(param->EmcSwizzleRank0Byte1, ®s->swizzle_rank0_byte1); - writel(param->EmcSwizzleRank0Byte2, ®s->swizzle_rank0_byte2); - writel(param->EmcSwizzleRank0Byte3, ®s->swizzle_rank0_byte3); - writel(param->EmcSwizzleRank1ByteCfg, ®s->swizzle_rank1_byte_cfg); - writel(param->EmcSwizzleRank1Byte0, ®s->swizzle_rank1_byte0); - writel(param->EmcSwizzleRank1Byte1, ®s->swizzle_rank1_byte1); - writel(param->EmcSwizzleRank1Byte2, ®s->swizzle_rank1_byte2); - writel(param->EmcSwizzleRank1Byte3, ®s->swizzle_rank1_byte3); + write32(®s->swizzle_rank0_byte_cfg, param->EmcSwizzleRank0ByteCfg); + write32(®s->swizzle_rank0_byte0, param->EmcSwizzleRank0Byte0); + write32(®s->swizzle_rank0_byte1, param->EmcSwizzleRank0Byte1); + write32(®s->swizzle_rank0_byte2, param->EmcSwizzleRank0Byte2); + write32(®s->swizzle_rank0_byte3, param->EmcSwizzleRank0Byte3); + write32(®s->swizzle_rank1_byte_cfg, param->EmcSwizzleRank1ByteCfg); + write32(®s->swizzle_rank1_byte0, param->EmcSwizzleRank1Byte0); + write32(®s->swizzle_rank1_byte1, param->EmcSwizzleRank1Byte1); + write32(®s->swizzle_rank1_byte2, param->EmcSwizzleRank1Byte2); + write32(®s->swizzle_rank1_byte3, param->EmcSwizzleRank1Byte3); } static void sdram_set_pad_controls(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Program the pad controls */ - writel(param->EmcXm2CmdPadCtrl, ®s->xm2cmdpadctrl); - writel(param->EmcXm2CmdPadCtrl2, ®s->xm2cmdpadctrl2); - writel(param->EmcXm2CmdPadCtrl3, ®s->xm2cmdpadctrl3); - writel(param->EmcXm2CmdPadCtrl4, ®s->xm2cmdpadctrl4); - writel(param->EmcXm2CmdPadCtrl5, ®s->xm2cmdpadctrl5); + write32(®s->xm2cmdpadctrl, param->EmcXm2CmdPadCtrl); + write32(®s->xm2cmdpadctrl2, param->EmcXm2CmdPadCtrl2); + write32(®s->xm2cmdpadctrl3, param->EmcXm2CmdPadCtrl3); + write32(®s->xm2cmdpadctrl4, param->EmcXm2CmdPadCtrl4); + write32(®s->xm2cmdpadctrl5, param->EmcXm2CmdPadCtrl5); - writel(param->EmcXm2DqsPadCtrl, ®s->xm2dqspadctrl); - writel(param->EmcXm2DqsPadCtrl2, ®s->xm2dqspadctrl2); - writel(param->EmcXm2DqsPadCtrl3, ®s->xm2dqspadctrl3); - writel(param->EmcXm2DqsPadCtrl4, ®s->xm2dqspadctrl4); - writel(param->EmcXm2DqsPadCtrl5, ®s->xm2dqspadctrl5); - writel(param->EmcXm2DqsPadCtrl6, ®s->xm2dqspadctrl6); + write32(®s->xm2dqspadctrl, param->EmcXm2DqsPadCtrl); + write32(®s->xm2dqspadctrl2, param->EmcXm2DqsPadCtrl2); + write32(®s->xm2dqspadctrl3, param->EmcXm2DqsPadCtrl3); + write32(®s->xm2dqspadctrl4, param->EmcXm2DqsPadCtrl4); + write32(®s->xm2dqspadctrl5, param->EmcXm2DqsPadCtrl5); + write32(®s->xm2dqspadctrl6, param->EmcXm2DqsPadCtrl6); - writel(param->EmcXm2DqPadCtrl, ®s->xm2dqpadctrl); - writel(param->EmcXm2DqPadCtrl2, ®s->xm2dqpadctrl2); - writel(param->EmcXm2DqPadCtrl3, ®s->xm2dqpadctrl3); + write32(®s->xm2dqpadctrl, param->EmcXm2DqPadCtrl); + write32(®s->xm2dqpadctrl2, param->EmcXm2DqPadCtrl2); + write32(®s->xm2dqpadctrl3, param->EmcXm2DqPadCtrl3); - writel(param->EmcXm2ClkPadCtrl, ®s->xm2clkpadctrl); - writel(param->EmcXm2ClkPadCtrl2, ®s->xm2clkpadctrl2); + write32(®s->xm2clkpadctrl, param->EmcXm2ClkPadCtrl); + write32(®s->xm2clkpadctrl2, param->EmcXm2ClkPadCtrl2); - writel(param->EmcXm2CompPadCtrl, ®s->xm2comppadctrl); + write32(®s->xm2comppadctrl, param->EmcXm2CompPadCtrl); - writel(param->EmcXm2VttGenPadCtrl, ®s->xm2vttgenpadctrl); - writel(param->EmcXm2VttGenPadCtrl2, ®s->xm2vttgenpadctrl2); - writel(param->EmcXm2VttGenPadCtrl3, ®s->xm2vttgenpadctrl3); + write32(®s->xm2vttgenpadctrl, param->EmcXm2VttGenPadCtrl); + write32(®s->xm2vttgenpadctrl2, param->EmcXm2VttGenPadCtrl2); + write32(®s->xm2vttgenpadctrl3, param->EmcXm2VttGenPadCtrl3); - writel(param->EmcCttTermCtrl, ®s->ctt_term_ctrl); + write32(®s->ctt_term_ctrl, param->EmcCttTermCtrl); } static void sdram_trigger_emc_timing_update(struct tegra_emc_regs *regs) { - writel(EMC_TIMING_CONTROL_TIMING_UPDATE, ®s->timing_control); + write32(®s->timing_control, EMC_TIMING_CONTROL_TIMING_UPDATE); } static void sdram_init_mc(const struct sdram_params *param, struct tegra_mc_regs *regs) { /* Initialize MC VPR settings */ - writel(param->McDisplaySnapRing, ®s->display_snap_ring); - writel(param->McVideoProtectBom, ®s->video_protect_bom); - writel(param->McVideoProtectBomAdrHi, ®s->video_protect_bom_adr_hi); - writel(param->McVideoProtectSizeMb, ®s->video_protect_size_mb); - writel(param->McVideoProtectVprOverride, - ®s->video_protect_vpr_override); - writel(param->McVideoProtectVprOverride1, - ®s->video_protect_vpr_override1); - writel(param->McVideoProtectGpuOverride0, - ®s->video_protect_gpu_override_0); - writel(param->McVideoProtectGpuOverride1, - ®s->video_protect_gpu_override_1); + write32(®s->display_snap_ring, param->McDisplaySnapRing); + write32(®s->video_protect_bom, param->McVideoProtectBom); + write32(®s->video_protect_bom_adr_hi, + param->McVideoProtectBomAdrHi); + write32(®s->video_protect_size_mb, param->McVideoProtectSizeMb); + write32(®s->video_protect_vpr_override, + param->McVideoProtectVprOverride); + write32(®s->video_protect_vpr_override1, + param->McVideoProtectVprOverride1); + write32(®s->video_protect_gpu_override_0, + param->McVideoProtectGpuOverride0); + write32(®s->video_protect_gpu_override_1, + param->McVideoProtectGpuOverride1); /* Program SDRAM geometry paarameters */ - writel(param->McEmemAdrCfg, ®s->emem_adr_cfg); - writel(param->McEmemAdrCfgDev0, ®s->emem_adr_cfg_dev0); - writel(param->McEmemAdrCfgDev1, ®s->emem_adr_cfg_dev1); + write32(®s->emem_adr_cfg, param->McEmemAdrCfg); + write32(®s->emem_adr_cfg_dev0, param->McEmemAdrCfgDev0); + write32(®s->emem_adr_cfg_dev1, param->McEmemAdrCfgDev1); /* Program bank swizzling */ - writel(param->McEmemAdrCfgBankMask0, ®s->emem_bank_swizzle_cfg0); - writel(param->McEmemAdrCfgBankMask1, ®s->emem_bank_swizzle_cfg1); - writel(param->McEmemAdrCfgBankMask2, ®s->emem_bank_swizzle_cfg2); - writel(param->McEmemAdrCfgBankSwizzle3, ®s->emem_bank_swizzle_cfg3); + write32(®s->emem_bank_swizzle_cfg0, param->McEmemAdrCfgBankMask0); + write32(®s->emem_bank_swizzle_cfg1, param->McEmemAdrCfgBankMask1); + write32(®s->emem_bank_swizzle_cfg2, param->McEmemAdrCfgBankMask2); + write32(®s->emem_bank_swizzle_cfg3, + param->McEmemAdrCfgBankSwizzle3); /* Program external memory aperature (base and size) */ - writel(param->McEmemCfg, ®s->emem_cfg); + write32(®s->emem_cfg, param->McEmemCfg); /* Program SEC carveout (base and size) */ - writel(param->McSecCarveoutBom, ®s->sec_carveout_bom); - writel(param->McSecCarveoutAdrHi, ®s->sec_carveout_adr_hi); - writel(param->McSecCarveoutSizeMb, ®s->sec_carveout_size_mb); + write32(®s->sec_carveout_bom, param->McSecCarveoutBom); + write32(®s->sec_carveout_adr_hi, param->McSecCarveoutAdrHi); + write32(®s->sec_carveout_size_mb, param->McSecCarveoutSizeMb); /* Program MTS carveout (base and size) */ - writel(param->McMtsCarveoutBom, ®s->mts_carveout_bom); - writel(param->McMtsCarveoutAdrHi, ®s->mts_carveout_adr_hi); - writel(param->McMtsCarveoutSizeMb, ®s->mts_carveout_size_mb); + write32(®s->mts_carveout_bom, param->McMtsCarveoutBom); + write32(®s->mts_carveout_adr_hi, param->McMtsCarveoutAdrHi); + write32(®s->mts_carveout_size_mb, param->McMtsCarveoutSizeMb); /* Program the memory arbiter */ - writel(param->McEmemArbCfg, ®s->emem_arb_cfg); - writel(param->McEmemArbOutstandingReq, ®s->emem_arb_outstanding_req); - writel(param->McEmemArbTimingRcd, ®s->emem_arb_timing_rcd); - writel(param->McEmemArbTimingRp, ®s->emem_arb_timing_rp); - writel(param->McEmemArbTimingRc, ®s->emem_arb_timing_rc); - writel(param->McEmemArbTimingRas, ®s->emem_arb_timing_ras); - writel(param->McEmemArbTimingFaw, ®s->emem_arb_timing_faw); - writel(param->McEmemArbTimingRrd, ®s->emem_arb_timing_rrd); - writel(param->McEmemArbTimingRap2Pre, ®s->emem_arb_timing_rap2pre); - writel(param->McEmemArbTimingWap2Pre, ®s->emem_arb_timing_wap2pre); - writel(param->McEmemArbTimingR2R, ®s->emem_arb_timing_r2r); - writel(param->McEmemArbTimingW2W, ®s->emem_arb_timing_w2w); - writel(param->McEmemArbTimingR2W, ®s->emem_arb_timing_r2w); - writel(param->McEmemArbTimingW2R, ®s->emem_arb_timing_w2r); - writel(param->McEmemArbDaTurns, ®s->emem_arb_da_turns); - writel(param->McEmemArbDaCovers, ®s->emem_arb_da_covers); - writel(param->McEmemArbMisc0, ®s->emem_arb_misc0); - writel(param->McEmemArbMisc1, ®s->emem_arb_misc1); - writel(param->McEmemArbRing1Throttle, ®s->emem_arb_ring1_throttle); - writel(param->McEmemArbOverride, ®s->emem_arb_override); - writel(param->McEmemArbOverride1, ®s->emem_arb_override_1); - writel(param->McEmemArbRsv, ®s->emem_arb_rsv); + write32(®s->emem_arb_cfg, param->McEmemArbCfg); + write32(®s->emem_arb_outstanding_req, + param->McEmemArbOutstandingReq); + write32(®s->emem_arb_timing_rcd, param->McEmemArbTimingRcd); + write32(®s->emem_arb_timing_rp, param->McEmemArbTimingRp); + write32(®s->emem_arb_timing_rc, param->McEmemArbTimingRc); + write32(®s->emem_arb_timing_ras, param->McEmemArbTimingRas); + write32(®s->emem_arb_timing_faw, param->McEmemArbTimingFaw); + write32(®s->emem_arb_timing_rrd, param->McEmemArbTimingRrd); + write32(®s->emem_arb_timing_rap2pre, param->McEmemArbTimingRap2Pre); + write32(®s->emem_arb_timing_wap2pre, param->McEmemArbTimingWap2Pre); + write32(®s->emem_arb_timing_r2r, param->McEmemArbTimingR2R); + write32(®s->emem_arb_timing_w2w, param->McEmemArbTimingW2W); + write32(®s->emem_arb_timing_r2w, param->McEmemArbTimingR2W); + write32(®s->emem_arb_timing_w2r, param->McEmemArbTimingW2R); + write32(®s->emem_arb_da_turns, param->McEmemArbDaTurns); + write32(®s->emem_arb_da_covers, param->McEmemArbDaCovers); + write32(®s->emem_arb_misc0, param->McEmemArbMisc0); + write32(®s->emem_arb_misc1, param->McEmemArbMisc1); + write32(®s->emem_arb_ring1_throttle, param->McEmemArbRing1Throttle); + write32(®s->emem_arb_override, param->McEmemArbOverride); + write32(®s->emem_arb_override_1, param->McEmemArbOverride1); + write32(®s->emem_arb_rsv, param->McEmemArbRsv); /* Program extra snap levels for display client */ - writel(param->McDisExtraSnapLevels, ®s->dis_extra_snap_levels); + write32(®s->dis_extra_snap_levels, param->McDisExtraSnapLevels); /* Trigger MC timing update */ - writel(MC_TIMING_CONTROL_TIMING_UPDATE, ®s->timing_control); + write32(®s->timing_control, MC_TIMING_CONTROL_TIMING_UPDATE); /* Program second-level clock enable overrides */ - writel(param->McClkenOverride, ®s->clken_override); + write32(®s->clken_override, param->McClkenOverride); /* Program statistics gathering */ - writel(param->McStatControl, ®s->stat_control); + write32(®s->stat_control, param->McStatControl); } static void sdram_init_emc(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Program SDRAM geometry parameters */ - writel(param->EmcAdrCfg, ®s->adr_cfg); + write32(®s->adr_cfg, param->EmcAdrCfg); /* Program second-level clock enable overrides */ - writel(param->EmcClkenOverride, ®s->clken_override); + write32(®s->clken_override, param->EmcClkenOverride); /* Program EMC pad auto calibration */ - writel(param->EmcAutoCalInterval, ®s->auto_cal_interval); - writel(param->EmcAutoCalConfig2, ®s->auto_cal_config2); - writel(param->EmcAutoCalConfig3, ®s->auto_cal_config3); - writel(param->EmcAutoCalConfig, ®s->auto_cal_config); + write32(®s->auto_cal_interval, param->EmcAutoCalInterval); + write32(®s->auto_cal_config2, param->EmcAutoCalConfig2); + write32(®s->auto_cal_config3, param->EmcAutoCalConfig3); + write32(®s->auto_cal_config, param->EmcAutoCalConfig); udelay(param->EmcAutoCalWait); } @@ -249,129 +252,129 @@ static void sdram_set_emc_timing(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Program EMC timing configuration */ - writel(param->EmcCfg2, ®s->cfg_2); - writel(param->EmcCfgPipe, ®s->cfg_pipe); - writel(param->EmcDbg, ®s->dbg); - writel(param->EmcCmdQ, ®s->cmdq); - writel(param->EmcMc2EmcQ, ®s->mc2emcq); - writel(param->EmcMrsWaitCnt, ®s->mrs_wait_cnt); - writel(param->EmcMrsWaitCnt2, ®s->mrs_wait_cnt2); - writel(param->EmcFbioCfg5, ®s->fbio_cfg5); - writel(param->EmcRc, ®s->rc); - writel(param->EmcRfc, ®s->rfc); - writel(param->EmcRfcSlr, ®s->rfc_slr); - writel(param->EmcRas, ®s->ras); - writel(param->EmcRp, ®s->rp); - writel(param->EmcR2r, ®s->r2r); - writel(param->EmcW2w, ®s->w2w); - writel(param->EmcR2w, ®s->r2w); - writel(param->EmcW2r, ®s->w2r); - writel(param->EmcR2p, ®s->r2p); - writel(param->EmcW2p, ®s->w2p); - writel(param->EmcRdRcd, ®s->rd_rcd); - writel(param->EmcWrRcd, ®s->wr_rcd); - writel(param->EmcRrd, ®s->rrd); - writel(param->EmcRext, ®s->rext); - writel(param->EmcWext, ®s->wext); - writel(param->EmcWdv, ®s->wdv); - writel(param->EmcWdvMask, ®s->wdv_mask); - writel(param->EmcQUse, ®s->quse); - writel(param->EmcQuseWidth, ®s->quse_width); - writel(param->EmcIbdly, ®s->ibdly); - writel(param->EmcEInput, ®s->einput); - writel(param->EmcEInputDuration, ®s->einput_duration); - writel(param->EmcPutermExtra, ®s->puterm_extra); - writel(param->EmcPutermWidth, ®s->puterm_width); - writel(param->EmcPutermAdj, ®s->puterm_adj); - writel(param->EmcCdbCntl1, ®s->cdb_cntl_1); - writel(param->EmcCdbCntl2, ®s->cdb_cntl_2); - writel(param->EmcCdbCntl3, ®s->cdb_cntl_3); - writel(param->EmcQRst, ®s->qrst); - writel(param->EmcQSafe, ®s->qsafe); - writel(param->EmcRdv, ®s->rdv); - writel(param->EmcRdvMask, ®s->rdv_mask); - writel(param->EmcQpop, ®s->qpop); - writel(param->EmcCtt, ®s->ctt); - writel(param->EmcCttDuration, ®s->ctt_duration); - writel(param->EmcRefresh, ®s->refresh); - writel(param->EmcBurstRefreshNum, ®s->burst_refresh_num); - writel(param->EmcPreRefreshReqCnt, ®s->pre_refresh_req_cnt); - writel(param->EmcPdEx2Wr, ®s->pdex2wr); - writel(param->EmcPdEx2Rd, ®s->pdex2rd); - writel(param->EmcPChg2Pden, ®s->pchg2pden); - writel(param->EmcAct2Pden, ®s->act2pden); - writel(param->EmcAr2Pden, ®s->ar2pden); - writel(param->EmcRw2Pden, ®s->rw2pden); - writel(param->EmcTxsr, ®s->txsr); - writel(param->EmcTxsrDll, ®s->txsrdll); - writel(param->EmcTcke, ®s->tcke); - writel(param->EmcTckesr, ®s->tckesr); - writel(param->EmcTpd, ®s->tpd); - writel(param->EmcTfaw, ®s->tfaw); - writel(param->EmcTrpab, ®s->trpab); - writel(param->EmcTClkStable, ®s->tclkstable); - writel(param->EmcTClkStop, ®s->tclkstop); - writel(param->EmcTRefBw, ®s->trefbw); - writel(param->EmcOdtWrite, ®s->odt_write); - writel(param->EmcOdtRead, ®s->odt_read); - writel(param->EmcFbioCfg6, ®s->fbio_cfg6); - writel(param->EmcCfgDigDll, ®s->cfg_dig_dll); - writel(param->EmcCfgDigDllPeriod, ®s->cfg_dig_dll_period); + write32(®s->cfg_2, param->EmcCfg2); + write32(®s->cfg_pipe, param->EmcCfgPipe); + write32(®s->dbg, param->EmcDbg); + write32(®s->cmdq, param->EmcCmdQ); + write32(®s->mc2emcq, param->EmcMc2EmcQ); + write32(®s->mrs_wait_cnt, param->EmcMrsWaitCnt); + write32(®s->mrs_wait_cnt2, param->EmcMrsWaitCnt2); + write32(®s->fbio_cfg5, param->EmcFbioCfg5); + write32(®s->rc, param->EmcRc); + write32(®s->rfc, param->EmcRfc); + write32(®s->rfc_slr, param->EmcRfcSlr); + write32(®s->ras, param->EmcRas); + write32(®s->rp, param->EmcRp); + write32(®s->r2r, param->EmcR2r); + write32(®s->w2w, param->EmcW2w); + write32(®s->r2w, param->EmcR2w); + write32(®s->w2r, param->EmcW2r); + write32(®s->r2p, param->EmcR2p); + write32(®s->w2p, param->EmcW2p); + write32(®s->rd_rcd, param->EmcRdRcd); + write32(®s->wr_rcd, param->EmcWrRcd); + write32(®s->rrd, param->EmcRrd); + write32(®s->rext, param->EmcRext); + write32(®s->wext, param->EmcWext); + write32(®s->wdv, param->EmcWdv); + write32(®s->wdv_mask, param->EmcWdvMask); + write32(®s->quse, param->EmcQUse); + write32(®s->quse_width, param->EmcQuseWidth); + write32(®s->ibdly, param->EmcIbdly); + write32(®s->einput, param->EmcEInput); + write32(®s->einput_duration, param->EmcEInputDuration); + write32(®s->puterm_extra, param->EmcPutermExtra); + write32(®s->puterm_width, param->EmcPutermWidth); + write32(®s->puterm_adj, param->EmcPutermAdj); + write32(®s->cdb_cntl_1, param->EmcCdbCntl1); + write32(®s->cdb_cntl_2, param->EmcCdbCntl2); + write32(®s->cdb_cntl_3, param->EmcCdbCntl3); + write32(®s->qrst, param->EmcQRst); + write32(®s->qsafe, param->EmcQSafe); + write32(®s->rdv, param->EmcRdv); + write32(®s->rdv_mask, param->EmcRdvMask); + write32(®s->qpop, param->EmcQpop); + write32(®s->ctt, param->EmcCtt); + write32(®s->ctt_duration, param->EmcCttDuration); + write32(®s->refresh, param->EmcRefresh); + write32(®s->burst_refresh_num, param->EmcBurstRefreshNum); + write32(®s->pre_refresh_req_cnt, param->EmcPreRefreshReqCnt); + write32(®s->pdex2wr, param->EmcPdEx2Wr); + write32(®s->pdex2rd, param->EmcPdEx2Rd); + write32(®s->pchg2pden, param->EmcPChg2Pden); + write32(®s->act2pden, param->EmcAct2Pden); + write32(®s->ar2pden, param->EmcAr2Pden); + write32(®s->rw2pden, param->EmcRw2Pden); + write32(®s->txsr, param->EmcTxsr); + write32(®s->txsrdll, param->EmcTxsrDll); + write32(®s->tcke, param->EmcTcke); + write32(®s->tckesr, param->EmcTckesr); + write32(®s->tpd, param->EmcTpd); + write32(®s->tfaw, param->EmcTfaw); + write32(®s->trpab, param->EmcTrpab); + write32(®s->tclkstable, param->EmcTClkStable); + write32(®s->tclkstop, param->EmcTClkStop); + write32(®s->trefbw, param->EmcTRefBw); + write32(®s->odt_write, param->EmcOdtWrite); + write32(®s->odt_read, param->EmcOdtRead); + write32(®s->fbio_cfg6, param->EmcFbioCfg6); + write32(®s->cfg_dig_dll, param->EmcCfgDigDll); + write32(®s->cfg_dig_dll_period, param->EmcCfgDigDllPeriod); /* Don't write bit 1: addr swizzle lock bit. Written at end of sequence. */ - writel(param->EmcFbioSpare & 0xfffffffd, ®s->fbio_spare); - - writel(param->EmcCfgRsv, ®s->cfg_rsv); - writel(param->EmcDllXformDqs0, ®s->dll_xform_dqs0); - writel(param->EmcDllXformDqs1, ®s->dll_xform_dqs1); - writel(param->EmcDllXformDqs2, ®s->dll_xform_dqs2); - writel(param->EmcDllXformDqs3, ®s->dll_xform_dqs3); - writel(param->EmcDllXformDqs4, ®s->dll_xform_dqs4); - writel(param->EmcDllXformDqs5, ®s->dll_xform_dqs5); - writel(param->EmcDllXformDqs6, ®s->dll_xform_dqs6); - writel(param->EmcDllXformDqs7, ®s->dll_xform_dqs7); - writel(param->EmcDllXformDqs8, ®s->dll_xform_dqs8); - writel(param->EmcDllXformDqs9, ®s->dll_xform_dqs9); - writel(param->EmcDllXformDqs10, ®s->dll_xform_dqs10); - writel(param->EmcDllXformDqs11, ®s->dll_xform_dqs11); - writel(param->EmcDllXformDqs12, ®s->dll_xform_dqs12); - writel(param->EmcDllXformDqs13, ®s->dll_xform_dqs13); - writel(param->EmcDllXformDqs14, ®s->dll_xform_dqs14); - writel(param->EmcDllXformDqs15, ®s->dll_xform_dqs15); - writel(param->EmcDllXformQUse0, ®s->dll_xform_quse0); - writel(param->EmcDllXformQUse1, ®s->dll_xform_quse1); - writel(param->EmcDllXformQUse2, ®s->dll_xform_quse2); - writel(param->EmcDllXformQUse3, ®s->dll_xform_quse3); - writel(param->EmcDllXformQUse4, ®s->dll_xform_quse4); - writel(param->EmcDllXformQUse5, ®s->dll_xform_quse5); - writel(param->EmcDllXformQUse6, ®s->dll_xform_quse6); - writel(param->EmcDllXformQUse7, ®s->dll_xform_quse7); - writel(param->EmcDllXformQUse8, ®s->dll_xform_quse8); - writel(param->EmcDllXformQUse9, ®s->dll_xform_quse9); - writel(param->EmcDllXformQUse10, ®s->dll_xform_quse10); - writel(param->EmcDllXformQUse11, ®s->dll_xform_quse11); - writel(param->EmcDllXformQUse12, ®s->dll_xform_quse12); - writel(param->EmcDllXformQUse13, ®s->dll_xform_quse13); - writel(param->EmcDllXformQUse14, ®s->dll_xform_quse14); - writel(param->EmcDllXformQUse15, ®s->dll_xform_quse15); - writel(param->EmcDllXformDq0, ®s->dll_xform_dq0); - writel(param->EmcDllXformDq1, ®s->dll_xform_dq1); - writel(param->EmcDllXformDq2, ®s->dll_xform_dq2); - writel(param->EmcDllXformDq3, ®s->dll_xform_dq3); - writel(param->EmcDllXformDq4, ®s->dll_xform_dq4); - writel(param->EmcDllXformDq5, ®s->dll_xform_dq5); - writel(param->EmcDllXformDq6, ®s->dll_xform_dq6); - writel(param->EmcDllXformDq7, ®s->dll_xform_dq7); - writel(param->EmcDllXformAddr0, ®s->dll_xform_addr0); - writel(param->EmcDllXformAddr1, ®s->dll_xform_addr1); - writel(param->EmcDllXformAddr2, ®s->dll_xform_addr2); - writel(param->EmcDllXformAddr3, ®s->dll_xform_addr3); - writel(param->EmcDllXformAddr4, ®s->dll_xform_addr4); - writel(param->EmcDllXformAddr5, ®s->dll_xform_addr5); - writel(param->EmcAcpdControl, ®s->acpd_control); - writel(param->EmcDsrVttgenDrv, ®s->dsr_vttgen_drv); - writel(param->EmcTxdsrvttgen, ®s->txdsrvttgen); - writel(param->EmcBgbiasCtl0, ®s->bgbias_ctl0); + write32(®s->fbio_spare, param->EmcFbioSpare & 0xfffffffd); + + write32(®s->cfg_rsv, param->EmcCfgRsv); + write32(®s->dll_xform_dqs0, param->EmcDllXformDqs0); + write32(®s->dll_xform_dqs1, param->EmcDllXformDqs1); + write32(®s->dll_xform_dqs2, param->EmcDllXformDqs2); + write32(®s->dll_xform_dqs3, param->EmcDllXformDqs3); + write32(®s->dll_xform_dqs4, param->EmcDllXformDqs4); + write32(®s->dll_xform_dqs5, param->EmcDllXformDqs5); + write32(®s->dll_xform_dqs6, param->EmcDllXformDqs6); + write32(®s->dll_xform_dqs7, param->EmcDllXformDqs7); + write32(®s->dll_xform_dqs8, param->EmcDllXformDqs8); + write32(®s->dll_xform_dqs9, param->EmcDllXformDqs9); + write32(®s->dll_xform_dqs10, param->EmcDllXformDqs10); + write32(®s->dll_xform_dqs11, param->EmcDllXformDqs11); + write32(®s->dll_xform_dqs12, param->EmcDllXformDqs12); + write32(®s->dll_xform_dqs13, param->EmcDllXformDqs13); + write32(®s->dll_xform_dqs14, param->EmcDllXformDqs14); + write32(®s->dll_xform_dqs15, param->EmcDllXformDqs15); + write32(®s->dll_xform_quse0, param->EmcDllXformQUse0); + write32(®s->dll_xform_quse1, param->EmcDllXformQUse1); + write32(®s->dll_xform_quse2, param->EmcDllXformQUse2); + write32(®s->dll_xform_quse3, param->EmcDllXformQUse3); + write32(®s->dll_xform_quse4, param->EmcDllXformQUse4); + write32(®s->dll_xform_quse5, param->EmcDllXformQUse5); + write32(®s->dll_xform_quse6, param->EmcDllXformQUse6); + write32(®s->dll_xform_quse7, param->EmcDllXformQUse7); + write32(®s->dll_xform_quse8, param->EmcDllXformQUse8); + write32(®s->dll_xform_quse9, param->EmcDllXformQUse9); + write32(®s->dll_xform_quse10, param->EmcDllXformQUse10); + write32(®s->dll_xform_quse11, param->EmcDllXformQUse11); + write32(®s->dll_xform_quse12, param->EmcDllXformQUse12); + write32(®s->dll_xform_quse13, param->EmcDllXformQUse13); + write32(®s->dll_xform_quse14, param->EmcDllXformQUse14); + write32(®s->dll_xform_quse15, param->EmcDllXformQUse15); + write32(®s->dll_xform_dq0, param->EmcDllXformDq0); + write32(®s->dll_xform_dq1, param->EmcDllXformDq1); + write32(®s->dll_xform_dq2, param->EmcDllXformDq2); + write32(®s->dll_xform_dq3, param->EmcDllXformDq3); + write32(®s->dll_xform_dq4, param->EmcDllXformDq4); + write32(®s->dll_xform_dq5, param->EmcDllXformDq5); + write32(®s->dll_xform_dq6, param->EmcDllXformDq6); + write32(®s->dll_xform_dq7, param->EmcDllXformDq7); + write32(®s->dll_xform_addr0, param->EmcDllXformAddr0); + write32(®s->dll_xform_addr1, param->EmcDllXformAddr1); + write32(®s->dll_xform_addr2, param->EmcDllXformAddr2); + write32(®s->dll_xform_addr3, param->EmcDllXformAddr3); + write32(®s->dll_xform_addr4, param->EmcDllXformAddr4); + write32(®s->dll_xform_addr5, param->EmcDllXformAddr5); + write32(®s->acpd_control, param->EmcAcpdControl); + write32(®s->dsr_vttgen_drv, param->EmcDsrVttgenDrv); + write32(®s->txdsrvttgen, param->EmcTxdsrvttgen); + write32(®s->bgbias_ctl0, param->EmcBgbiasCtl0); /* * Set pipe bypass enable bits before sending any DRAM commands. @@ -391,8 +394,8 @@ static void sdram_patch_bootrom(const struct sdram_params *param, BOOT_ROM_PATCH_CONTROL_OFFSET_MASK) >> BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT); addr = BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS + (addr << 2); - writel(param->BootRomPatchData, (uint32_t *)addr); - writel(1, ®s->timing_control); + write32((uint32_t *)addr, param->BootRomPatchData); + write32(®s->timing_control, 1); } } @@ -400,7 +403,7 @@ static void sdram_set_dpd3(const struct sdram_params *param, struct tegra_pmc_regs *regs) { /* Program DPD request */ - writel(param->PmcIoDpd3Req, ®s->io_dpd3_req); + write32(®s->io_dpd3_req, param->PmcIoDpd3Req); udelay(param->PmcIoDpd3ReqWait); } @@ -408,27 +411,27 @@ static void sdram_set_dli_trims(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Program DLI trims */ - writel(param->EmcDliTrimTxDqs0, ®s->dli_trim_txdqs0); - writel(param->EmcDliTrimTxDqs1, ®s->dli_trim_txdqs1); - writel(param->EmcDliTrimTxDqs2, ®s->dli_trim_txdqs2); - writel(param->EmcDliTrimTxDqs3, ®s->dli_trim_txdqs3); - writel(param->EmcDliTrimTxDqs4, ®s->dli_trim_txdqs4); - writel(param->EmcDliTrimTxDqs5, ®s->dli_trim_txdqs5); - writel(param->EmcDliTrimTxDqs6, ®s->dli_trim_txdqs6); - writel(param->EmcDliTrimTxDqs7, ®s->dli_trim_txdqs7); - writel(param->EmcDliTrimTxDqs8, ®s->dli_trim_txdqs8); - writel(param->EmcDliTrimTxDqs9, ®s->dli_trim_txdqs9); - writel(param->EmcDliTrimTxDqs10, ®s->dli_trim_txdqs10); - writel(param->EmcDliTrimTxDqs11, ®s->dli_trim_txdqs11); - writel(param->EmcDliTrimTxDqs12, ®s->dli_trim_txdqs12); - writel(param->EmcDliTrimTxDqs13, ®s->dli_trim_txdqs13); - writel(param->EmcDliTrimTxDqs14, ®s->dli_trim_txdqs14); - writel(param->EmcDliTrimTxDqs15, ®s->dli_trim_txdqs15); - - writel(param->EmcCaTrainingTimingCntl1, - ®s->ca_training_timing_cntl1); - writel(param->EmcCaTrainingTimingCntl2, - ®s->ca_training_timing_cntl2); + write32(®s->dli_trim_txdqs0, param->EmcDliTrimTxDqs0); + write32(®s->dli_trim_txdqs1, param->EmcDliTrimTxDqs1); + write32(®s->dli_trim_txdqs2, param->EmcDliTrimTxDqs2); + write32(®s->dli_trim_txdqs3, param->EmcDliTrimTxDqs3); + write32(®s->dli_trim_txdqs4, param->EmcDliTrimTxDqs4); + write32(®s->dli_trim_txdqs5, param->EmcDliTrimTxDqs5); + write32(®s->dli_trim_txdqs6, param->EmcDliTrimTxDqs6); + write32(®s->dli_trim_txdqs7, param->EmcDliTrimTxDqs7); + write32(®s->dli_trim_txdqs8, param->EmcDliTrimTxDqs8); + write32(®s->dli_trim_txdqs9, param->EmcDliTrimTxDqs9); + write32(®s->dli_trim_txdqs10, param->EmcDliTrimTxDqs10); + write32(®s->dli_trim_txdqs11, param->EmcDliTrimTxDqs11); + write32(®s->dli_trim_txdqs12, param->EmcDliTrimTxDqs12); + write32(®s->dli_trim_txdqs13, param->EmcDliTrimTxDqs13); + write32(®s->dli_trim_txdqs14, param->EmcDliTrimTxDqs14); + write32(®s->dli_trim_txdqs15, param->EmcDliTrimTxDqs15); + + write32(®s->ca_training_timing_cntl1, + param->EmcCaTrainingTimingCntl1); + write32(®s->ca_training_timing_cntl2, + param->EmcCaTrainingTimingCntl2); sdram_trigger_emc_timing_update(regs); udelay(param->EmcTimingControlWait); @@ -444,7 +447,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, * Assert dummy read of PIN register to ensure above write to PIN * register went through. 200 is the recommended value by NVIDIA. */ - dummy |= readl(®s->pin); + dummy |= read32(®s->pin); udelay(200 + param->EmcPinExtraWait); /* Deassert reset */ @@ -453,7 +456,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, * Assert dummy read of PIN register to ensure above write to PIN * register went through. 200 is the recommended value by NVIDIA. */ - dummy |= readl(®s->pin); + dummy |= read32(®s->pin); udelay(500 + param->EmcPinExtraWait); /* Enable clock enable signal */ @@ -462,7 +465,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, * Assert dummy read of PIN register to ensure above write to PIN * register went through. 200 is the recommended value by NVIDIA. */ - dummy |= readl(®s->pin); + dummy |= read32(®s->pin); udelay(param->EmcPinProgramWait); if (!dummy) { @@ -479,20 +482,20 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, static void sdram_init_ddr3(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Write mode registers */ - writel(param->EmcEmrs2, ®s->emrs2); - writel(param->EmcEmrs3, ®s->emrs3); - writel(param->EmcEmrs, ®s->emrs); - writel(param->EmcMrs, ®s->mrs); + write32(®s->emrs2, param->EmcEmrs2); + write32(®s->emrs3, param->EmcEmrs3); + write32(®s->emrs, param->EmcEmrs); + write32(®s->mrs, param->EmcMrs); if (param->EmcExtraModeRegWriteEnable) { - writel(param->EmcMrsExtra, ®s->mrs); + write32(®s->mrs, param->EmcMrsExtra); } - writel(param->EmcZcalInitDev0, ®s->zq_cal); + write32(®s->zq_cal, param->EmcZcalInitDev0); udelay(param->EmcZcalInitWait); if ((param->EmcDevSelect & 2) == 0) { - writel(param->EmcZcalInitDev1, ®s->zq_cal); + write32(®s->zq_cal, param->EmcZcalInitDev1); udelay(param->EmcZcalInitWait); } } @@ -500,29 +503,30 @@ static void sdram_init_ddr3(const struct sdram_params *param, struct tegra_emc_r static void sdram_init_lpddr3(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Precharge all banks. DEV_SELECTN = 0 => Select all devices */ - writel(((param->EmcDevSelect << EMC_REF_DEV_SELECTN_SHIFT) | 1), ®s->pre); + write32(®s->pre, + ((param->EmcDevSelect << EMC_REF_DEV_SELECTN_SHIFT) | 1)); /* Send Reset MRW command */ - writel(param->EmcMrwResetCommand, ®s->mrw); + write32(®s->mrw, param->EmcMrwResetCommand); udelay(param->EmcMrwResetNInitWait); - writel(param->EmcZcalInitDev0, ®s->mrw); + write32(®s->mrw, param->EmcZcalInitDev0); udelay(param->EmcZcalInitWait); if ((param->EmcDevSelect & 2) == 0) { - writel(param->EmcZcalInitDev1, ®s->mrw); + write32(®s->mrw, param->EmcZcalInitDev1); udelay(param->EmcZcalInitWait); } /* Write mode registers */ - writel(param->EmcMrw2, ®s->mrw2); - writel(param->EmcMrw1, ®s->mrw); - writel(param->EmcMrw3, ®s->mrw3); - writel(param->EmcMrw4, ®s->mrw4); + write32(®s->mrw2, param->EmcMrw2); + write32(®s->mrw, param->EmcMrw1); + write32(®s->mrw3, param->EmcMrw3); + write32(®s->mrw4, param->EmcMrw4); if (param->EmcExtraModeRegWriteEnable) { - writel(param->EmcMrwExtra, ®s->mrw); + write32(®s->mrw, param->EmcMrwExtra); } } @@ -546,9 +550,9 @@ static void sdram_set_zq_calibration(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Start periodic ZQ calibration */ - writel(param->EmcZcalInterval, ®s->zcal_interval); - writel(param->EmcZcalWaitCnt, ®s->zcal_wait_cnt); - writel(param->EmcZcalMrwCmd, ®s->zcal_mrw_cmd); + write32(®s->zcal_interval, param->EmcZcalInterval); + write32(®s->zcal_wait_cnt, param->EmcZcalWaitCnt); + write32(®s->zcal_mrw_cmd, param->EmcZcalMrwCmd); } static void sdram_set_refresh(const struct sdram_params *param, @@ -566,15 +570,15 @@ static void sdram_set_refresh(const struct sdram_params *param, } /* Enable refresh */ - writel((param->EmcDevSelect | EMC_REFCTRL_REF_VALID_ENABLED), - ®s->refctrl); + write32(®s->refctrl, + (param->EmcDevSelect | EMC_REFCTRL_REF_VALID_ENABLED)); - writel(param->EmcDynSelfRefControl, ®s->dyn_self_ref_control); - writel(param->EmcCfg, ®s->cfg); - writel(param->EmcSelDpdCtrl, ®s->sel_dpd_ctrl); + write32(®s->dyn_self_ref_control, param->EmcDynSelfRefControl); + write32(®s->cfg, param->EmcCfg); + write32(®s->sel_dpd_ctrl, param->EmcSelDpdCtrl); /* Write addr swizzle lock bit */ - writel(param->EmcFbioSpare, ®s->fbio_spare); + write32(®s->fbio_spare, param->EmcFbioSpare); /* Re-trigger timing to latch power saving functions */ sdram_trigger_emc_timing_update(regs); @@ -592,12 +596,13 @@ static void sdram_lock_carveouts(const struct sdram_params *param, struct tegra_mc_regs *regs) { /* Lock carveouts, and emem_cfg registers */ - writel(param->McVideoProtectWriteAccess, ®s->video_protect_reg_ctrl); - writel(MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED, - ®s->emem_cfg_access_ctrl); - writel(param->McSecCarveoutProtectWriteAccess, - ®s->sec_carveout_reg_ctrl); - writel(param->McMtsCarveoutRegCtrl, ®s->mts_carveout_reg_ctrl); + write32(®s->video_protect_reg_ctrl, + param->McVideoProtectWriteAccess); + write32(®s->emem_cfg_access_ctrl, + MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED); + write32(®s->sec_carveout_reg_ctrl, + param->McSecCarveoutProtectWriteAccess); + write32(®s->mts_carveout_reg_ctrl, param->McMtsCarveoutRegCtrl); } void sdram_init(const struct sdram_params *param) @@ -653,7 +658,7 @@ void sdram_init(const struct sdram_params *param) uint32_t sdram_get_ram_code(void) { struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE; - return ((readl(&pmc->strapping_opt_a) & + return ((read32(&pmc->strapping_opt_a) & PMC_STRAPPING_OPT_A_RAM_CODE_MASK) >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT); } diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c index 7923f7e3cd..1003ca53a8 100644 --- a/src/soc/nvidia/tegra132/soc.c +++ b/src/soc/nvidia/tegra132/soc.c @@ -83,9 +83,9 @@ static void lock_down_vpr(void) { struct tegra_mc_regs *regs = (void *)(uintptr_t)TEGRA_MC_BASE; - writel(0, ®s->video_protect_bom); - writel(0, ®s->video_protect_size_mb); - writel(1, ®s->video_protect_reg_ctrl); + write32(®s->video_protect_bom, 0); + write32(®s->video_protect_size_mb, 0); + write32(®s->video_protect_reg_ctrl, 1); } static void soc_init(device_t dev) diff --git a/src/soc/nvidia/tegra132/spi.c b/src/soc/nvidia/tegra132/spi.c index e240700f06..33620fb202 100644 --- a/src/soc/nvidia/tegra132/spi.c +++ b/src/soc/nvidia/tegra132/spi.c @@ -230,7 +230,7 @@ int spi_claim_bus(struct spi_slave *slave) else val |= SPI_CMD1_CS_SW_VAL; - writel(val, ®s->command1); + write32(®s->command1, val); return 0; } @@ -246,7 +246,7 @@ void spi_release_bus(struct spi_slave *slave) else val &= ~SPI_CMD1_CS_SW_VAL; - writel(val, ®s->command1); + write32(®s->command1, val); } static void dump_fifo_status(struct tegra_spi_channel *spi) @@ -383,12 +383,12 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi, /* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and * PIO transfers */ - writel(todo - 1, &spi->regs->dma_blk); + write32(&spi->regs->dma_blk, todo - 1); if (dir == SPI_SEND) { unsigned int to_fifo = bytes; while (to_fifo) { - writel(*p, &spi->regs->tx_fifo); + write32(&spi->regs->tx_fifo, *p); p++; to_fifo--; } @@ -493,12 +493,12 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, /* ensure bytes to send will be visible to DMA controller */ dcache_clean_by_mva(spi->out_buf, bytes); - writel((uintptr_t) & spi->regs->tx_fifo, - &spi->dma_out->regs->apb_ptr); - writel((uintptr_t)spi->out_buf, &spi->dma_out->regs->ahb_ptr); + write32(&spi->dma_out->regs->apb_ptr, + (uintptr_t) & spi->regs->tx_fifo); + write32(&spi->dma_out->regs->ahb_ptr, (uintptr_t)spi->out_buf); setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_out); - writel(wcount, &spi->dma_out->regs->wcount); + write32(&spi->dma_out->regs->wcount, wcount); } else { spi->dma_in = dma_claim(); if (!spi->dma_in) @@ -507,16 +507,16 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, /* avoid data collisions */ dcache_clean_invalidate_by_mva(spi->in_buf, bytes); - writel((uintptr_t)&spi->regs->rx_fifo, - &spi->dma_in->regs->apb_ptr); - writel((uintptr_t)spi->in_buf, &spi->dma_in->regs->ahb_ptr); + write32(&spi->dma_in->regs->apb_ptr, + (uintptr_t)&spi->regs->rx_fifo); + write32(&spi->dma_in->regs->ahb_ptr, (uintptr_t)spi->in_buf); clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_in); - writel(wcount, &spi->dma_in->regs->wcount); + write32(&spi->dma_in->regs->wcount, wcount); } /* BLOCK_SIZE starts at n-1 */ - writel(todo - 1, &spi->regs->dma_blk); + write32(&spi->regs->dma_blk, todo - 1); return todo; } diff --git a/src/soc/nvidia/tegra132/uart.c b/src/soc/nvidia/tegra132/uart.c index 90765e1496..e7b7ca9f69 100644 --- a/src/soc/nvidia/tegra132/uart.c +++ b/src/soc/nvidia/tegra132/uart.c @@ -63,19 +63,19 @@ static void tegra132_uart_init(struct tegra132_uart *uart_ptr) tegra132_uart_tx_flush(uart_ptr); // Disable interrupts. - writeb(0, &uart_ptr->ier); + write8(&uart_ptr->ier, 0); // Force DTR and RTS to high. - writeb(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr); + write8(&uart_ptr->mcr, UART8250_MCR_DTR | UART8250_MCR_RTS); // Set line configuration, access divisor latches. - writeb(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr); + write8(&uart_ptr->lcr, UART8250_LCR_DLAB | line_config); // Set the divisor. - writeb(divisor & 0xff, &uart_ptr->dll); - writeb((divisor >> 8) & 0xff, &uart_ptr->dlm); + write8(&uart_ptr->dll, divisor & 0xff); + write8(&uart_ptr->dlm, (divisor >> 8) & 0xff); // Hide the divisor latches. - writeb(line_config, &uart_ptr->lcr); + write8(&uart_ptr->lcr, line_config); // Enable FIFOs, and clear receive and transmit. - writeb(UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT, - &uart_ptr->fcr); + write8(&uart_ptr->fcr, + UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT); } static unsigned char tegra132_uart_rx_byte(struct tegra132_uart *uart_ptr) @@ -88,7 +88,7 @@ static unsigned char tegra132_uart_rx_byte(struct tegra132_uart *uart_ptr) static void tegra132_uart_tx_byte(struct tegra132_uart *uart_ptr, unsigned char data) { while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE)); - writeb(data, &uart_ptr->thr); + write8(&uart_ptr->thr, data); } static void tegra132_uart_tx_flush(struct tegra132_uart *uart_ptr) diff --git a/src/soc/qualcomm/ipq806x/blobs_init.c b/src/soc/qualcomm/ipq806x/blobs_init.c index a3c0cfa28e..d513d2545a 100644 --- a/src/soc/qualcomm/ipq806x/blobs_init.c +++ b/src/soc/qualcomm/ipq806x/blobs_init.c @@ -107,7 +107,7 @@ void start_rpm(void) u32 ready_mask = 1 << 10; struct stopwatch sw; - if (readl(RPM_SIGNAL_COOKIE) == RPM_FW_MAGIC_NUM) { + if (read32(RPM_SIGNAL_COOKIE) == RPM_FW_MAGIC_NUM) { printk(BIOS_INFO, "RPM appears to have already started\n"); return; } @@ -119,20 +119,20 @@ void start_rpm(void) printk(BIOS_INFO, "Starting RPM\n"); /* Clear 'ready' indication. */ - writel(readl(RPM_INT_ACK) & ~ready_mask, RPM_INT_ACK); + write32(RPM_INT_ACK, read32(RPM_INT_ACK) & ~ready_mask); /* Set RPM entry address */ - writel(load_addr, RPM_SIGNAL_ENTRY); + write32(RPM_SIGNAL_ENTRY, load_addr); /* Set cookie */ - writel(RPM_FW_MAGIC_NUM, RPM_SIGNAL_COOKIE); + write32(RPM_SIGNAL_COOKIE, RPM_FW_MAGIC_NUM); /* Wait for RPM start indication, up to 100ms. */ stopwatch_init_usecs_expire(&sw, 100000); - while (!(readl(RPM_INT) & ready_mask)) + while (!(read32(RPM_INT) & ready_mask)) if (stopwatch_expired(&sw)) die("RPM Initialization failed\n"); /* Acknowledge RPM initialization */ - writel(ready_mask, RPM_INT_ACK); + write32(RPM_INT_ACK, ready_mask); } #endif /* !__PRE_RAM__ */ diff --git a/src/soc/qualcomm/ipq806x/clock.c b/src/soc/qualcomm/ipq806x/clock.c index 0b770da94f..0ffd83f032 100644 --- a/src/soc/qualcomm/ipq806x/clock.c +++ b/src/soc/qualcomm/ipq806x/clock.c @@ -14,7 +14,7 @@ void uart_pll_vote_clk_enable(unsigned int clk_dummy) setbits_le32(BB_PLL_ENA_SC0_REG, BIT(8)); if (!clk_dummy) - while((readl(PLL_LOCK_DET_STATUS_REG) & BIT(8)) == 0); + while((read32(PLL_LOCK_DET_STATUS_REG) & BIT(8)) == 0); } /** @@ -29,7 +29,7 @@ static void uart_set_rate_mnd(unsigned int gsbi_port, unsigned int m, /* Assert MND reset. */ setbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7)); /* Program M and D values. */ - writel(MD16(m, n), GSBIn_UART_APPS_MD_REG(gsbi_port)); + write32(GSBIn_UART_APPS_MD_REG(gsbi_port), MD16(m, n)); /* Deassert MND reset. */ clrbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7)); } @@ -61,25 +61,25 @@ static void uart_local_clock_enable(unsigned int gsbi_port, unsigned int n, * set in the set_rate path because power can be saved by deferring * the selection of a clocked source until the clock is enabled. */ - reg_val = readl(reg); // REG(0x29D4+(0x20*((n)-1))) + reg_val = read32(reg); // REG(0x29D4+(0x20*((n)-1))) reg_val &= ~(Uart_clk_ns_mask); uart_ns_val = NS(BIT_POS_31,BIT_POS_16,n,m, 5, 4, 3, 1, 2, 0,3); reg_val |= (uart_ns_val & Uart_clk_ns_mask); - writel(reg_val,reg); + write32(reg, reg_val); /* enable MNCNTR_EN */ - reg_val = readl(reg); + reg_val = read32(reg); reg_val |= BIT(8); - writel(reg_val, reg); + write32(reg, reg_val); /* set source to PLL8 running @384MHz */ - reg_val = readl(reg); + reg_val = read32(reg); reg_val |= 0x3; - writel(reg_val, reg); + write32(reg, reg_val); /* Enable root. */ reg_val |= Uart_en_mask; - writel(reg_val, reg); + write32(reg, reg_val); uart_branch_clk_enable_reg(gsbi_port); } @@ -113,8 +113,8 @@ void uart_clock_config(unsigned int gsbi_port, unsigned int m, */ void nand_clock_config(void) { - writel(CLK_BRANCH_ENA(1) | ALWAYS_ON_CLK_BRANCH_ENA(1), - EBI2_CLK_CTL_REG); + write32(EBI2_CLK_CTL_REG, + CLK_BRANCH_ENA(1) | ALWAYS_ON_CLK_BRANCH_ENA(1)); /* Wait for clock to stabilize. */ udelay(10); @@ -126,17 +126,17 @@ void nand_clock_config(void) void usb_clock_config(void) { /* Magic clock initialization numbers, nobody knows how they work... */ - writel(0x10, USB30_MASTER_CLK_CTL_REG); - writel(0x10, USB30_1_MASTER_CLK_CTL_REG); - writel(0x500DF, USB30_MASTER_CLK_MD); - writel(0xE40942, USB30_MASTER_CLK_NS); - writel(0x100D7, USB30_MOC_UTMI_CLK_MD); - writel(0xD80942, USB30_MOC_UTMI_CLK_NS); - writel(0x10, USB30_MOC_UTMI_CLK_CTL); - writel(0x10, USB30_1_MOC_UTMI_CLK_CTL); - - writel(1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0 | 0, - USB30_RESET); + write32(USB30_MASTER_CLK_CTL_REG, 0x10); + write32(USB30_1_MASTER_CLK_CTL_REG, 0x10); + write32(USB30_MASTER_CLK_MD, 0x500DF); + write32(USB30_MASTER_CLK_NS, 0xE40942); + write32(USB30_MOC_UTMI_CLK_MD, 0x100D7); + write32(USB30_MOC_UTMI_CLK_NS, 0xD80942); + write32(USB30_MOC_UTMI_CLK_CTL, 0x10); + write32(USB30_1_MOC_UTMI_CLK_CTL, 0x10); + + write32(USB30_RESET, + 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0 | 0); udelay(5); - writel(0, USB30_RESET); /* deassert all USB resets again */ + write32(USB30_RESET, 0); /* deassert all USB resets again */ } diff --git a/src/soc/qualcomm/ipq806x/gpio.c b/src/soc/qualcomm/ipq806x/gpio.c index a0a3df9495..c40b521101 100644 --- a/src/soc/qualcomm/ipq806x/gpio.c +++ b/src/soc/qualcomm/ipq806x/gpio.c @@ -73,7 +73,7 @@ void gpio_tlmm_config_set(gpio_t gpio, unsigned func, val |= (drvstr & GPIO_CFG_DRV_MASK) << GPIO_CFG_DRV_SHIFT; val |= (enable & GPIO_CFG_OE_MASK) << GPIO_CFG_OE_SHIFT; - writel(val, GPIO_CONFIG_ADDR(gpio)); + write32(GPIO_CONFIG_ADDR(gpio), val); } /******************************************************* @@ -99,7 +99,7 @@ void gpio_tlmm_config_get(gpio_t gpio, unsigned *func, if (gpio_not_valid(gpio)) return; - val = readl(addr); + val = read32(addr); *pull = (val >> GPIO_CFG_PULL_SHIFT) & GPIO_CFG_PULL_MASK; *func = (val >> GPIO_CFG_FUNC_SHIFT) & GPIO_CFG_FUNC_MASK; @@ -122,7 +122,7 @@ int gpio_get(gpio_t gpio) return -1; - return (readl(GPIO_IN_OUT_ADDR(gpio)) >> GPIO_IO_IN_SHIFT) & + return (read32(GPIO_IN_OUT_ADDR(gpio)) >> GPIO_IO_IN_SHIFT) & GPIO_IO_IN_MASK; } @@ -131,7 +131,7 @@ void gpio_set(gpio_t gpio, int value) if (gpio_not_valid(gpio)) return; - writel((value & 1) << GPIO_IO_OUT_SHIFT, GPIO_IN_OUT_ADDR(gpio)); + write32(GPIO_IN_OUT_ADDR(gpio), (value & 1) << GPIO_IO_OUT_SHIFT); } void gpio_input_pulldown(gpio_t gpio) diff --git a/src/soc/qualcomm/ipq806x/gsbi.c b/src/soc/qualcomm/ipq806x/gsbi.c index 54adbe8db7..93270958a9 100644 --- a/src/soc/qualcomm/ipq806x/gsbi.c +++ b/src/soc/qualcomm/ipq806x/gsbi.c @@ -68,18 +68,18 @@ gsbi_return_t gsbi_init(gsbi_id_t gsbi_id, gsbi_protocol_t protocol) if (!gsbi_ctl) return GSBI_ID_ERROR; - writel((1 << GSBI_HCLK_CTL_GATE_ENA) | (1 << GSBI_HCLK_CTL_BRANCH_ENA), - GSBI_HCLK_CTL(gsbi_id)); + write32(GSBI_HCLK_CTL(gsbi_id), + (1 << GSBI_HCLK_CTL_GATE_ENA) | (1 << GSBI_HCLK_CTL_BRANCH_ENA)); if (gsbi_init_board(gsbi_id)) return GSBI_UNSUPPORTED; - writel(0, GSBI_QUP_APSS_NS_REG(gsbi_id)); - writel(0, GSBI_QUP_APSS_MD_REG(gsbi_id)); + write32(GSBI_QUP_APSS_NS_REG(gsbi_id), 0); + write32(GSBI_QUP_APSS_MD_REG(gsbi_id), 0); reg_val = ((m & GSBI_QUP_APPS_M_MASK) << GSBI_QUP_APPS_M_SHFT) | ((~n & GSBI_QUP_APPS_D_MASK) << GSBI_QUP_APPS_D_SHFT); - writel(reg_val, GSBI_QUP_APSS_MD_REG(gsbi_id)); + write32(GSBI_QUP_APSS_MD_REG(gsbi_id), reg_val); reg_val = (((~(n - m)) & GSBI_QUP_APPS_N_MASK) << GSBI_QUP_APPS_N_SHFT) | @@ -88,18 +88,18 @@ gsbi_return_t gsbi_init(gsbi_id_t gsbi_id, gsbi_protocol_t protocol) (((pre_div - 1) & GSBI_QUP_APPS_PRE_DIV_MSK) << GSBI_QUP_APPS_PRE_DIV_SFT) | (src & GSBI_QUP_APPS_SRC_SEL_MSK); - writel(reg_val, GSBI_QUP_APSS_NS_REG(gsbi_id)); + write32(GSBI_QUP_APSS_NS_REG(gsbi_id), reg_val); reg_val |= (1 << GSBI_QUP_APPS_ROOT_ENA_SFT) | (1 << GSBI_QUP_APPS_MNCTR_EN_SFT); - writel(reg_val, GSBI_QUP_APSS_NS_REG(gsbi_id)); + write32(GSBI_QUP_APSS_NS_REG(gsbi_id), reg_val); reg_val |= (1 << GSBI_QUP_APPS_BRANCH_ENA_SFT); - writel(reg_val, GSBI_QUP_APSS_NS_REG(gsbi_id)); + write32(GSBI_QUP_APSS_NS_REG(gsbi_id), reg_val); /*Select i2c protocol*/ - writel(((GSBI_CTL_PROTO_I2C & GSBI_CTL_PROTO_CODE_MSK) << - GSBI_CTL_PROTO_CODE_SFT), gsbi_ctl); + write32(gsbi_ctl, + ((GSBI_CTL_PROTO_I2C & GSBI_CTL_PROTO_CODE_MSK) << GSBI_CTL_PROTO_CODE_SFT)); return GSBI_SUCCESS; } diff --git a/src/soc/qualcomm/ipq806x/lcc.c b/src/soc/qualcomm/ipq806x/lcc.c index 978526d8e7..d577487618 100644 --- a/src/soc/qualcomm/ipq806x/lcc.c +++ b/src/soc/qualcomm/ipq806x/lcc.c @@ -129,43 +129,43 @@ static int lcc_init_enable_pll0(Ipq806xLccClocks *bus) regval = 0; regval = 15 << LCC_PLL0_L_SHIFT & LCC_PLL0_L_MASK; - writel(regval, &pll0_regs->l_val); + write32(&pll0_regs->l_val, regval); regval = 0; regval = 145 << LCC_PLL0_M_SHIFT & LCC_PLL0_M_MASK; - writel(regval, &pll0_regs->m_val); + write32(&pll0_regs->m_val, regval); regval = 0; regval = 199 << LCC_PLL0_N_SHIFT & LCC_PLL0_N_MASK; - writel(regval, &pll0_regs->n_val); + write32(&pll0_regs->n_val, regval); regval = 0; regval |= LCC_PLL0_CFG_LV_MAIN_ENABLE; regval |= LCC_PLL0_CFG_FRAC_ENABLE; - writel(regval, &pll0_regs->config); + write32(&pll0_regs->config, regval); regval = 0; regval |= LCC_PLL_PCLK_SRC_PRI; - writel(regval, &pll_regs->pri); + write32(&pll_regs->pri, regval); regval = 0; regval |= 1 << LCC_PLL0_MODE_BIAS_CNT_SHIFT & LCC_PLL0_MODE_BIAS_CNT_MASK; regval |= 8 << LCC_PLL0_MODE_LOCK_CNT_SHIFT & LCC_PLL0_MODE_LOCK_CNT_MASK; - writel(regval, &pll0_regs->mode); + write32(&pll0_regs->mode, regval); - regval = readl(&gcc_regs->apcs); + regval = read32(&gcc_regs->apcs); regval |= GCC_PLL_APCS_PLL4_ENABLE; - writel(regval, &gcc_regs->apcs); + write32(&gcc_regs->apcs, regval); - regval = readl(&pll0_regs->mode); + regval = read32(&pll0_regs->mode); regval |= LCC_PLL0_MODE_FSM_VOTE_ENABLE; - writel(regval, &pll0_regs->mode); + write32(&pll0_regs->mode, regval); mdelay(1); - regval = readl(&pll0_regs->status); + regval = read32(&pll0_regs->status); if (regval & LCC_PLL0_STAT_ACTIVE_MASK) return 0; @@ -182,7 +182,7 @@ static int lcc_init_enable_ahbix(Ipq806xLccClocks *bus) regval |= 1 << LCC_AHBIX_MD_M_VAL_SHIFT & LCC_AHBIX_MD_M_VAL_MASK; regval |= 252 << LCC_AHBIX_MD_NOT_2D_VAL_SHIFT & LCC_AHBIX_MD_NOT_2D_VAL_MASK; - writel(regval, &ahbix_regs->md); + write32(&ahbix_regs->md, regval); regval = 0; regval |= 253 << LCC_AHBIX_NS_N_VAL_SHIFT & LCC_AHBIX_NS_N_VAL_MASK; @@ -193,11 +193,11 @@ static int lcc_init_enable_ahbix(Ipq806xLccClocks *bus) regval |= LCC_AHBIX_NS_MNC_MODE_DUAL; regval |= LCC_AHBIX_NS_PREDIV_BYPASS; regval |= LCC_AHBIX_NS_MN_SRC_LPA; - writel(regval, &ahbix_regs->ns); + write32(&ahbix_regs->ns, regval); mdelay(1); - regval = readl(&ahbix_regs->status); + regval = read32(&ahbix_regs->status); if (regval & LCC_AHBIX_STAT_AIF_CLK_MASK) return 0; @@ -248,7 +248,7 @@ static int lcc_init_mi2s(Ipq806xLccClocks *bus, unsigned freq) regval |= m << LCC_MI2S_MD_M_VAL_SHIFT & LCC_MI2S_MD_M_VAL_MASK; regval |= d << LCC_MI2S_MD_NOT_2D_VAL_SHIFT & LCC_MI2S_MD_NOT_2D_VAL_MASK; - writel(regval, &mi2s_regs->md); + write32(&mi2s_regs->md, regval); regval = 0; regval |= n << LCC_MI2S_NS_N_VAL_SHIFT & LCC_MI2S_NS_N_VAL_MASK; @@ -258,7 +258,7 @@ static int lcc_init_mi2s(Ipq806xLccClocks *bus, unsigned freq) regval |= LCC_MI2S_NS_MNC_MODE_DUAL; regval |= pd; regval |= LCC_MI2S_NS_MN_SRC_LPA; - writel(regval, &mi2s_regs->ns); + write32(&mi2s_regs->ns, regval); return 0; } @@ -268,14 +268,14 @@ static int lcc_enable_mi2s(Ipq806xLccClocks *bus) Ipq806xLccMi2sRegs *mi2s_regs = bus->lcc_mi2s_regs; uint32_t regval; - regval = readl(&mi2s_regs->ns); + regval = read32(&mi2s_regs->ns); regval |= LCC_MI2S_NS_OSR_CXC_ENABLE; regval |= LCC_MI2S_NS_BIT_CXC_ENABLE; - writel(regval, &mi2s_regs->ns); + write32(&mi2s_regs->ns, regval); udelay(10); - regval = readl(&mi2s_regs->status); + regval = read32(&mi2s_regs->status); if (regval & LCC_MI2S_STAT_OSR_CLK_MASK) if (regval & LCC_MI2S_STAT_BIT_CLK_MASK) return 0; diff --git a/src/soc/qualcomm/ipq806x/qup.c b/src/soc/qualcomm/ipq806x/qup.c index 25adfc18db..bc78e7c67a 100644 --- a/src/soc/qualcomm/ipq806x/qup.c +++ b/src/soc/qualcomm/ipq806x/qup.c @@ -51,9 +51,9 @@ static unsigned gsbi_qup_base[] = { static qup_return_t qup_i2c_master_status(gsbi_id_t gsbi_id) { - uint32_t reg_val = readl(QUP_ADDR(gsbi_id, QUP_I2C_MASTER_STATUS)); + uint32_t reg_val = read32(QUP_ADDR(gsbi_id, QUP_I2C_MASTER_STATUS)); - if (readl(QUP_ADDR(gsbi_id, QUP_ERROR_FLAGS))) + if (read32(QUP_ADDR(gsbi_id, QUP_ERROR_FLAGS))) return QUP_ERR_XFER_FAIL; if (reg_val & QUP_I2C_INVALID_READ_ADDR) return QUP_ERR_I2C_INVALID_SLAVE_ADDR; @@ -77,7 +77,7 @@ static int check_bit_state(uint32_t *reg, int wait_for) { unsigned int count = TIMEOUT_CNT; - while ((readl(reg) & (QUP_STATE_VALID_MASK | QUP_STATE_MASK)) != + while ((read32(reg) & (QUP_STATE_VALID_MASK | QUP_STATE_MASK)) != (QUP_STATE_VALID | wait_for)) { if (count == 0) return QUP_ERR_TIMEOUT; @@ -103,14 +103,14 @@ qup_return_t qup_reset_i2c_master_status(gsbi_id_t gsbi_id) * Bit31-25, Bit1 and Bit0 are reserved. */ //TODO: Define each status bit. OR all status bits in a single macro. - writel(0x3FFFFFC, QUP_ADDR(gsbi_id, QUP_I2C_MASTER_STATUS)); + write32(QUP_ADDR(gsbi_id, QUP_I2C_MASTER_STATUS), 0x3FFFFFC); return QUP_SUCCESS; } static qup_return_t qup_reset_master_status(gsbi_id_t gsbi_id) { - writel(0x7C, QUP_ADDR(gsbi_id, QUP_ERROR_FLAGS)); - writel(0x7C, QUP_ADDR(gsbi_id, QUP_ERROR_FLAGS_EN)); + write32(QUP_ADDR(gsbi_id, QUP_ERROR_FLAGS), 0x7C); + write32(QUP_ADDR(gsbi_id, QUP_ERROR_FLAGS_EN), 0x7C); qup_reset_i2c_master_status(gsbi_id); return QUP_SUCCESS; } @@ -120,7 +120,7 @@ static qup_return_t qup_fifo_wait_for(gsbi_id_t gsbi_id, uint32_t status) qup_return_t ret = QUP_ERR_UNDEFINED; unsigned int count = TIMEOUT_CNT; - while (!(readl(QUP_ADDR(gsbi_id, QUP_OPERATIONAL)) & status)) { + while (!(read32(QUP_ADDR(gsbi_id, QUP_OPERATIONAL)) & status)) { ret = qup_i2c_master_status(gsbi_id); if (ret) return ret; @@ -137,7 +137,7 @@ static qup_return_t qup_fifo_wait_while(gsbi_id_t gsbi_id, uint32_t status) qup_return_t ret = QUP_ERR_UNDEFINED; unsigned int count = TIMEOUT_CNT; - while (readl(QUP_ADDR(gsbi_id, QUP_OPERATIONAL)) & status) { + while (read32(QUP_ADDR(gsbi_id, QUP_OPERATIONAL)) & status) { ret = qup_i2c_master_status(gsbi_id); if (ret) return ret; @@ -161,16 +161,16 @@ static qup_return_t qup_i2c_write_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj, qup_reset_master_status(gsbi_id); qup_set_state(gsbi_id, QUP_STATE_RUN); - writel((QUP_I2C_START_SEQ | QUP_I2C_ADDR(addr)), - QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO)); + write32(QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO), + (QUP_I2C_START_SEQ | QUP_I2C_ADDR(addr))); while (data_len) { if (data_len == 1 && stop_seq) { - writel((QUP_I2C_STOP_SEQ | QUP_I2C_DATA(data_ptr[idx])), - QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO)); + write32(QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO), + (QUP_I2C_STOP_SEQ | QUP_I2C_DATA(data_ptr[idx]))); } else { - writel((QUP_I2C_DATA_SEQ | QUP_I2C_DATA(data_ptr[idx])), - QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO)); + write32(QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO), + (QUP_I2C_DATA_SEQ | QUP_I2C_DATA(data_ptr[idx]))); } data_len--; idx++; @@ -187,10 +187,10 @@ static qup_return_t qup_i2c_write_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj, means that software knows to return to fill the output FIFO with data. */ - if (readl(QUP_ADDR(gsbi_id, QUP_OPERATIONAL)) & + if (read32(QUP_ADDR(gsbi_id, QUP_OPERATIONAL)) & OUTPUT_SERVICE_FLAG) { - writel(OUTPUT_SERVICE_FLAG, - QUP_ADDR(gsbi_id, QUP_OPERATIONAL)); + write32(QUP_ADDR(gsbi_id, QUP_OPERATIONAL), + OUTPUT_SERVICE_FLAG); } } @@ -234,17 +234,17 @@ static qup_return_t qup_i2c_read_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj) qup_reset_master_status(gsbi_id); qup_set_state(gsbi_id, QUP_STATE_RUN); - writel((QUP_I2C_START_SEQ | (QUP_I2C_ADDR(addr) | QUP_I2C_SLAVE_READ)), - QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO)); + write32(QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO), + (QUP_I2C_START_SEQ | (QUP_I2C_ADDR(addr) | QUP_I2C_SLAVE_READ))); - writel((QUP_I2C_RECV_SEQ | data_len), - QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO)); + write32(QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO), + (QUP_I2C_RECV_SEQ | data_len)); ret = qup_fifo_wait_while(gsbi_id, OUTPUT_FIFO_NOT_EMPTY); if (ret) return ret; - writel(OUTPUT_SERVICE_FLAG, QUP_ADDR(gsbi_id, QUP_OPERATIONAL)); + write32(QUP_ADDR(gsbi_id, QUP_OPERATIONAL), OUTPUT_SERVICE_FLAG); while (data_len) { uint32_t data; @@ -253,7 +253,7 @@ static qup_return_t qup_i2c_read_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj) if (ret) return ret; - data = readl(QUP_ADDR(gsbi_id, QUP_INPUT_FIFO)); + data = read32(QUP_ADDR(gsbi_id, QUP_INPUT_FIFO)); /* * Process tag and corresponding data value. For I2C master @@ -268,8 +268,8 @@ static qup_return_t qup_i2c_read_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj) data_ptr[idx] = QUP_I2C_DATA(data); idx++; data_len--; - writel(INPUT_SERVICE_FLAG, - QUP_ADDR(gsbi_id, QUP_OPERATIONAL)); + write32(QUP_ADDR(gsbi_id, QUP_OPERATIONAL), + INPUT_SERVICE_FLAG); } else if (QUP_I2C_MI_TAG(data) == QUP_I2C_MISTOP_SEQ) { /* Tag: MISTOP: Last byte of master input. */ data_ptr[idx] = QUP_I2C_DATA(data); @@ -282,7 +282,7 @@ static qup_return_t qup_i2c_read_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj) } } - writel(INPUT_SERVICE_FLAG, QUP_ADDR(gsbi_id, QUP_OPERATIONAL)); + write32(QUP_ADDR(gsbi_id, QUP_OPERATIONAL), INPUT_SERVICE_FLAG); p_tx_obj->p.iic.data_len = idx; qup_set_state(gsbi_id, QUP_STATE_PAUSE); @@ -316,7 +316,7 @@ qup_return_t qup_init(gsbi_id_t gsbi_id, const qup_config_t *config_ptr) uint32_t reg_val; /* Reset the QUP core.*/ - writel(0x1, QUP_ADDR(gsbi_id, QUP_SW_RESET)); + write32(QUP_ADDR(gsbi_id, QUP_SW_RESET), 0x1); /*Wait till the reset takes effect */ ret = qup_wait_for_state(gsbi_id, QUP_STATE_RESET); @@ -324,7 +324,7 @@ qup_return_t qup_init(gsbi_id_t gsbi_id, const qup_config_t *config_ptr) goto bailout; /* Reset the config */ - writel(0, QUP_ADDR(gsbi_id, QUP_CONFIG)); + write32(QUP_ADDR(gsbi_id, QUP_CONFIG), 0); /*Program the config register*/ /*Set N value*/ @@ -340,10 +340,10 @@ qup_return_t qup_init(gsbi_id_t gsbi_id, const qup_config_t *config_ptr) ret = QUP_ERR_UNSUPPORTED; goto bailout; } - writel(reg_val, QUP_ADDR(gsbi_id, QUP_CONFIG)); + write32(QUP_ADDR(gsbi_id, QUP_CONFIG), reg_val); /*Reset i2c clk cntl register*/ - writel(0, QUP_ADDR(gsbi_id, QUP_I2C_MASTER_CLK_CTL)); + write32(QUP_ADDR(gsbi_id, QUP_I2C_MASTER_CLK_CTL), 0); /*Set QUP IO Mode*/ switch (config_ptr->mode) { @@ -358,14 +358,14 @@ qup_return_t qup_init(gsbi_id_t gsbi_id, const qup_config_t *config_ptr) ret = QUP_ERR_UNSUPPORTED; goto bailout; } - writel(reg_val, QUP_ADDR(gsbi_id, QUP_IO_MODES)); + write32(QUP_ADDR(gsbi_id, QUP_IO_MODES), reg_val); /*Set i2c clk cntl*/ reg_val = (QUP_DIVIDER_MIN_VAL << QUP_HS_DIVIDER_SHFT); reg_val |= ((((config_ptr->src_frequency / config_ptr->clk_frequency) / 2) - QUP_DIVIDER_MIN_VAL) & QUP_FS_DIVIDER_MASK); - writel(reg_val, QUP_ADDR(gsbi_id, QUP_I2C_MASTER_CLK_CTL)); + write32(QUP_ADDR(gsbi_id, QUP_I2C_MASTER_CLK_CTL), reg_val); bailout: if (ret) @@ -377,7 +377,7 @@ bailout: qup_return_t qup_set_state(gsbi_id_t gsbi_id, uint32_t state) { qup_return_t ret = QUP_ERR_UNDEFINED; - unsigned curr_state = readl(QUP_ADDR(gsbi_id, QUP_STATE)); + unsigned curr_state = read32(QUP_ADDR(gsbi_id, QUP_STATE)); if ((state >= QUP_STATE_RESET && state <= QUP_STATE_PAUSE) && (curr_state & QUP_STATE_VALID_MASK)) { @@ -387,10 +387,10 @@ qup_return_t qup_set_state(gsbi_id_t gsbi_id, uint32_t state) * transition to complete. */ if (QUP_STATE_PAUSE == curr_state && QUP_STATE_RESET == state) { - writel(0x2, QUP_ADDR(gsbi_id, QUP_STATE)); - writel(0x2, QUP_ADDR(gsbi_id, QUP_STATE)); + write32(QUP_ADDR(gsbi_id, QUP_STATE), 0x2); + write32(QUP_ADDR(gsbi_id, QUP_STATE), 0x2); } else { - writel(state, QUP_ADDR(gsbi_id, QUP_STATE)); + write32(QUP_ADDR(gsbi_id, QUP_STATE), state); } ret = qup_wait_for_state(gsbi_id, state); } @@ -402,7 +402,7 @@ static qup_return_t qup_i2c_send_data(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj, uint8_t stop_seq) { qup_return_t ret = QUP_ERR_UNDEFINED; - uint8_t mode = (readl(QUP_ADDR(gsbi_id, QUP_IO_MODES)) >> + uint8_t mode = (read32(QUP_ADDR(gsbi_id, QUP_IO_MODES)) >> QUP_OUTPUT_MODE_SHFT) & QUP_MODE_MASK; ret = qup_i2c_write(gsbi_id, mode, p_tx_obj, stop_seq); @@ -423,7 +423,7 @@ qup_return_t qup_send_data(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj, { qup_return_t ret = QUP_ERR_UNDEFINED; - if (p_tx_obj->protocol == ((readl(QUP_ADDR(gsbi_id, QUP_CONFIG)) >> + if (p_tx_obj->protocol == ((read32(QUP_ADDR(gsbi_id, QUP_CONFIG)) >> QUP_MINI_CORE_PROTO_SHFT) & QUP_MINI_CORE_PROTO_MASK)) { switch (p_tx_obj->protocol) { case QUP_MINICORE_I2C_MASTER: @@ -440,7 +440,7 @@ qup_return_t qup_send_data(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj, static qup_return_t qup_i2c_recv_data(gsbi_id_t gsbi_id, qup_data_t *p_rx_obj) { qup_return_t ret = QUP_ERR_UNDEFINED; - uint8_t mode = (readl(QUP_ADDR(gsbi_id, QUP_IO_MODES)) >> + uint8_t mode = (read32(QUP_ADDR(gsbi_id, QUP_IO_MODES)) >> QUP_INPUT_MODE_SHFT) & QUP_MODE_MASK; ret = qup_i2c_read(gsbi_id, mode, p_rx_obj); @@ -460,7 +460,7 @@ qup_return_t qup_recv_data(gsbi_id_t gsbi_id, qup_data_t *p_rx_obj) { qup_return_t ret = QUP_ERR_UNDEFINED; - if (p_rx_obj->protocol == ((readl(QUP_ADDR(gsbi_id, QUP_CONFIG)) >> + if (p_rx_obj->protocol == ((read32(QUP_ADDR(gsbi_id, QUP_CONFIG)) >> QUP_MINI_CORE_PROTO_SHFT) & QUP_MINI_CORE_PROTO_MASK)) { switch (p_rx_obj->protocol) { case QUP_MINICORE_I2C_MASTER: diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index b374f17537..4a353130e1 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -285,7 +285,7 @@ static void CS_change(int port_num, int cs_num, int enable) val &= (~(1 << GPIO_OUTPUT)); if (!enable) val |= (1 << GPIO_OUTPUT); - writel(val, addr); + write32(addr, val); } /* diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index ebe1913734..c9ef77014c 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -89,22 +89,22 @@ static const uart_params_t uart_board_param = { static unsigned int msm_boot_uart_dm_init_rx_transfer(void *uart_dm_base) { /* Reset receiver */ - writel(MSM_BOOT_UART_DM_CMD_RESET_RX, - MSM_BOOT_UART_DM_CR(uart_dm_base)); + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CMD_RESET_RX); /* Enable receiver */ - writel(MSM_BOOT_UART_DM_CR_RX_ENABLE, - MSM_BOOT_UART_DM_CR(uart_dm_base)); - writel(MSM_BOOT_UART_DM_DMRX_DEF_VALUE, - MSM_BOOT_UART_DM_DMRX(uart_dm_base)); + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CR_RX_ENABLE); + write32(MSM_BOOT_UART_DM_DMRX(uart_dm_base), + MSM_BOOT_UART_DM_DMRX_DEF_VALUE); /* Clear stale event */ - writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, - MSM_BOOT_UART_DM_CR(uart_dm_base)); + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CMD_RES_STALE_INT); /* Enable stale event */ - writel(MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT, - MSM_BOOT_UART_DM_CR(uart_dm_base)); + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT); return MSM_BOOT_UART_DM_E_SUCCESS; } @@ -200,17 +200,17 @@ void uart_tx_byte(int idx, unsigned char data) void *base = uart_board_param.uart_dm_base; /* Wait until transmit FIFO is empty. */ - while (!(readl(MSM_BOOT_UART_DM_SR(base)) & + while (!(read32(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_TXEMT)) udelay(1); /* * TX FIFO is ready to accept new character(s). First write number of * characters to be transmitted. */ - writel(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base)); + write32(MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base), num_of_chars); /* And now write the character(s) */ - writel(tx_data, MSM_BOOT_UART_DM_TF(base, 0)); + write32(MSM_BOOT_UART_DM_TF(base, 0), tx_data); } #endif /* CONFIG_SERIAL_UART */ @@ -220,12 +220,12 @@ void uart_tx_byte(int idx, unsigned char data) */ static unsigned int msm_boot_uart_dm_reset(void *base) { - writel(MSM_BOOT_UART_DM_CMD_RESET_RX, MSM_BOOT_UART_DM_CR(base)); - writel(MSM_BOOT_UART_DM_CMD_RESET_TX, MSM_BOOT_UART_DM_CR(base)); - writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, - MSM_BOOT_UART_DM_CR(base)); - writel(MSM_BOOT_UART_DM_CMD_RES_TX_ERR, MSM_BOOT_UART_DM_CR(base)); - writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(base)); + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_RX); + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_TX); + write32(MSM_BOOT_UART_DM_CR(base), + MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT); + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_TX_ERR); + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_STALE_INT); return MSM_BOOT_UART_DM_E_SUCCESS; } @@ -238,40 +238,40 @@ static unsigned int msm_boot_uart_dm_init(void *uart_dm_base) { /* Configure UART mode registers MR1 and MR2 */ /* Hardware flow control isn't supported */ - writel(0x0, MSM_BOOT_UART_DM_MR1(uart_dm_base)); + write32(MSM_BOOT_UART_DM_MR1(uart_dm_base), 0x0); /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */ - writel(MSM_BOOT_UART_DM_8_N_1_MODE, - MSM_BOOT_UART_DM_MR2(uart_dm_base)); + write32(MSM_BOOT_UART_DM_MR2(uart_dm_base), + MSM_BOOT_UART_DM_8_N_1_MODE); /* Configure Interrupt Mask register IMR */ - writel(MSM_BOOT_UART_DM_IMR_ENABLED, - MSM_BOOT_UART_DM_IMR(uart_dm_base)); + write32(MSM_BOOT_UART_DM_IMR(uart_dm_base), + MSM_BOOT_UART_DM_IMR_ENABLED); /* * Configure Tx and Rx watermarks configuration registers * TX watermark value is set to 0 - interrupt is generated when * FIFO level is less than or equal to 0 */ - writel(MSM_BOOT_UART_DM_TFW_VALUE, - MSM_BOOT_UART_DM_TFWR(uart_dm_base)); + write32(MSM_BOOT_UART_DM_TFWR(uart_dm_base), + MSM_BOOT_UART_DM_TFW_VALUE); /* RX watermark value */ - writel(MSM_BOOT_UART_DM_RFW_VALUE, - MSM_BOOT_UART_DM_RFWR(uart_dm_base)); + write32(MSM_BOOT_UART_DM_RFWR(uart_dm_base), + MSM_BOOT_UART_DM_RFW_VALUE); /* Configure Interrupt Programming Register */ /* Set initial Stale timeout value */ - writel(MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB, - MSM_BOOT_UART_DM_IPR(uart_dm_base)); + write32(MSM_BOOT_UART_DM_IPR(uart_dm_base), + MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB); /* Configure IRDA if required */ /* Disabling IRDA mode */ - writel(0x0, MSM_BOOT_UART_DM_IRDA(uart_dm_base)); + write32(MSM_BOOT_UART_DM_IRDA(uart_dm_base), 0x0); /* Configure hunt character value in HCR register */ /* Keep it in reset state */ - writel(0x0, MSM_BOOT_UART_DM_HCR(uart_dm_base)); + write32(MSM_BOOT_UART_DM_HCR(uart_dm_base), 0x0); /* * Configure Rx FIFO base address @@ -286,11 +286,11 @@ static unsigned int msm_boot_uart_dm_init(void *uart_dm_base) /* Enable/Disable Rx/Tx DM interfaces */ /* Data Mover not currently utilized. */ - writel(0x0, MSM_BOOT_UART_DM_DMEN(uart_dm_base)); + write32(MSM_BOOT_UART_DM_DMEN(uart_dm_base), 0x0); /* Enable transmitter */ - writel(MSM_BOOT_UART_DM_CR_TX_ENABLE, - MSM_BOOT_UART_DM_CR(uart_dm_base)); + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CR_TX_ENABLE); /* Initialize Receive Path */ msm_boot_uart_dm_init_rx_transfer(uart_dm_base); @@ -311,7 +311,7 @@ void uart_init(int idx) dm_base = uart_board_param.uart_dm_base; - if (readl(MSM_BOOT_UART_DM_CSR(dm_base)) == UART_DM_CLK_RX_TX_BIT_RATE) + if (read32(MSM_BOOT_UART_DM_CSR(dm_base)) == UART_DM_CLK_RX_TX_BIT_RATE) return; /* UART must have been already initialized. */ gsbi_base = uart_board_param.uart_gsbi_base; @@ -325,10 +325,9 @@ void uart_init(int idx) uart_board_param.mnd_value.d_value, 0); - writel(GSBI_PROTOCOL_CODE_I2C_UART << - GSBI_CTRL_REG_PROTOCOL_CODE_S, - GSBI_CTRL_REG(gsbi_base)); - writel(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(dm_base)); + write32(GSBI_CTRL_REG(gsbi_base), + GSBI_PROTOCOL_CODE_I2C_UART << GSBI_CTRL_REG_PROTOCOL_CODE_S); + write32(MSM_BOOT_UART_DM_CSR(dm_base), UART_DM_CLK_RX_TX_BIT_RATE); /* Intialize UART_DM */ msm_boot_uart_dm_init(dm_base); @@ -355,7 +354,7 @@ void uart_tx_flush(int idx) { void *base = uart_board_param.uart_dm_base; - while (!(readl(MSM_BOOT_UART_DM_SR(base)) & + while (!(read32(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_TXEMT)) ; } diff --git a/src/soc/qualcomm/ipq806x/usb.c b/src/soc/qualcomm/ipq806x/usb.c index 69b3998624..d7dac7243c 100644 --- a/src/soc/qualcomm/ipq806x/usb.c +++ b/src/soc/qualcomm/ipq806x/usb.c @@ -101,16 +101,16 @@ static struct usb_dwc3 * const usb_host2_dwc3 = (void *)USB_HOST2_DWC3_BASE; static void setup_dwc3(struct usb_dwc3 *dwc3) { - writel(0x1 << 31 | 0x1 << 25 | 0x1 << 24 | 0x1 << 19 | 0x1 << 18 | 0x1 << 1 | 0x1 << 0 | 0, - &dwc3->usb3pipectl); + write32(&dwc3->usb3pipectl, + 0x1 << 31 | 0x1 << 25 | 0x1 << 24 | 0x1 << 19 | 0x1 << 18 | 0x1 << 1 | 0x1 << 0 | 0); - writel(0x1 << 31 | 0x9 << 10 | 0x1 << 8 | 0x1 << 6 | 0, - &dwc3->usb2phycfg); + write32(&dwc3->usb2phycfg, + 0x1 << 31 | 0x9 << 10 | 0x1 << 8 | 0x1 << 6 | 0); - writel(0x2 << 19 | 0x1 << 16 | 0x1 << 12 | 0x1 << 11 | 0x1 << 10 | 0x1 << 2 | 0, - &dwc3->ctl); + write32(&dwc3->ctl, + 0x2 << 19 | 0x1 << 16 | 0x1 << 12 | 0x1 << 11 | 0x1 << 10 | 0x1 << 2 | 0); - writel(0x32 << 22 | 0x1 << 15 | 0x10 << 0 | 0, &dwc3->uctl); + write32(&dwc3->uctl, 0x32 << 22 | 0x1 << 15 | 0x10 << 0 | 0); udelay(5); @@ -121,16 +121,16 @@ static void setup_dwc3(struct usb_dwc3 *dwc3) static void setup_phy(struct usb_qc_phy *phy) { - writel(0x1 << 24 | 0x1 << 8 | 0x1 << 7 | 0x19 << 0 | 0, - &phy->ss_phy_ctrl); + write32(&phy->ss_phy_ctrl, + 0x1 << 24 | 0x1 << 8 | 0x1 << 7 | 0x19 << 0 | 0); - writel(0x1 << 26 | 0x1 << 25 | 0x1 << 24 | 0x1 << 21 | 0x1 << 20 | 0x1 << 18 | 0x1 << 17 | 0x1 << 11 | 0x1 << 9 | 0x1 << 8 | 0x1 << 7 | 0x7 << 4 | 0x1 << 1 | 0, - &phy->hs_phy_ctrl); + write32(&phy->hs_phy_ctrl, + 0x1 << 26 | 0x1 << 25 | 0x1 << 24 | 0x1 << 21 | 0x1 << 20 | 0x1 << 18 | 0x1 << 17 | 0x1 << 11 | 0x1 << 9 | 0x1 << 8 | 0x1 << 7 | 0x7 << 4 | 0x1 << 1 | 0); - writel(0x6e << 20 | 0x20 << 14 | 0x17 << 8 | 0x9 << 3 | 0, - &phy->ss_phy_param1); + write32(&phy->ss_phy_param1, + 0x6e << 20 | 0x20 << 14 | 0x17 << 8 | 0x9 << 3 | 0); - writel(0x1 << 2, &phy->general_cfg); /* set XHCI 1.00 compliance */ + write32(&phy->general_cfg, 0x1 << 2); /* set XHCI 1.00 compliance */ udelay(5); clrbits_le32(&phy->ss_phy_ctrl, 0x1 << 7); /* deassert SS PHY reset */ @@ -141,9 +141,9 @@ static void crport_handshake(void *capture_reg, void *acknowledge_bit, u32 data) int usec = 100; if (capture_reg) - writel(data, capture_reg); + write32(capture_reg, data); - writel(0x1 << 0, acknowledge_bit); + write32(acknowledge_bit, 0x1 << 0); while (read32(acknowledge_bit) && --usec) udelay(1); diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index d7420ea8d6..a9c888d631 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -217,19 +217,20 @@ static int rkclk_set_pll(u32 *pll_con, const struct pll_div *div) (div->no == 1 || !(div->no % 2))); /* enter rest */ - writel(RK_SETBITS(PLL_RESET_MSK), &pll_con[3]); + write32(&pll_con[3], RK_SETBITS(PLL_RESET_MSK)); - writel(RK_CLRSETBITS(PLL_NR_MSK, (div->nr - 1) << PLL_NR_SHIFT) - | RK_CLRSETBITS(PLL_OD_MSK, (div->no - 1)), &pll_con[0]); + write32(&pll_con[0], + RK_CLRSETBITS(PLL_NR_MSK, (div->nr - 1) << PLL_NR_SHIFT) | RK_CLRSETBITS(PLL_OD_MSK, (div->no - 1))); - writel(RK_CLRSETBITS(PLL_NF_MSK, (div->nf - 1)), &pll_con[1]); + write32(&pll_con[1], RK_CLRSETBITS(PLL_NF_MSK, (div->nf - 1))); - writel(RK_CLRSETBITS(PLL_BWADJ_MSK, ((div->nf >> 1) - 1)), &pll_con[2]); + write32(&pll_con[2], + RK_CLRSETBITS(PLL_BWADJ_MSK, ((div->nf >> 1) - 1))); udelay(10); /* return form rest */ - writel(RK_CLRBITS(PLL_RESET_MSK), &pll_con[3]); + write32(&pll_con[3], RK_CLRBITS(PLL_RESET_MSK)); return 0; } @@ -257,9 +258,8 @@ void rkclk_init(void) u32 pclk_div; /* pll enter slow-mode */ - writel(RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_SLOW) - | RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_SLOW), - &cru_ptr->cru_mode_con); + write32(&cru_ptr->cru_mode_con, + RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_SLOW) | RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_SLOW)); /* init pll */ rkclk_set_pll(&cru_ptr->cru_gpll_con[0], &gpll_init_cfg); @@ -267,7 +267,7 @@ void rkclk_init(void) /* waiting for pll lock */ while (1) { - if ((readl(&rk3288_grf->soc_status[1]) + if ((read32(&rk3288_grf->soc_status[1]) & (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) == (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) break; @@ -288,15 +288,8 @@ void rkclk_init(void) assert((pclk_div + 1) * PD_BUS_PCLK_HZ == PD_BUS_ACLK_HZ && pclk_div < 0x7); - writel(RK_SETBITS(PD_BUS_SEL_GPLL) - | RK_CLRSETBITS(PD_BUS_PCLK_DIV_MSK, - pclk_div << PD_BUS_PCLK_DIV_SHIFT) - | RK_CLRSETBITS(PD_BUS_HCLK_DIV_MSK, - hclk_div << PD_BUS_HCLK_DIV_SHIFT) - | RK_CLRSETBITS(PD_BUS_ACLK_DIV0_MASK, - aclk_div << PD_BUS_ACLK_DIV0_SHIFT) - | RK_CLRSETBITS(PD_BUS_ACLK_DIV1_MASK, 0 << 0), - &cru_ptr->cru_clksel_con[1]); + write32(&cru_ptr->cru_clksel_con[1], + RK_SETBITS(PD_BUS_SEL_GPLL) | RK_CLRSETBITS(PD_BUS_PCLK_DIV_MSK, pclk_div << PD_BUS_PCLK_DIV_SHIFT) | RK_CLRSETBITS(PD_BUS_HCLK_DIV_MSK, hclk_div << PD_BUS_HCLK_DIV_SHIFT) | RK_CLRSETBITS(PD_BUS_ACLK_DIV0_MASK, aclk_div << PD_BUS_ACLK_DIV0_SHIFT) | RK_CLRSETBITS(PD_BUS_ACLK_DIV1_MASK, 0 << 0)); /* * peri clock pll source selection and @@ -313,33 +306,26 @@ void rkclk_init(void) assert((1 << pclk_div) * PERI_PCLK_HZ == PERI_ACLK_HZ && (pclk_div < 0x4)); - writel(RK_SETBITS(PERI_SEL_GPLL) - | RK_CLRSETBITS(PERI_PCLK_DIV_MSK, - pclk_div << PERI_PCLK_DIV_SHIFT) - | RK_CLRSETBITS(PERI_HCLK_DIV_MSK, - hclk_div << PERI_HCLK_DIV_SHIFT) - | RK_CLRSETBITS(PERI_ACLK_DIV_MSK, - aclk_div << PERI_ACLK_DIV_SHIFT), - &cru_ptr->cru_clksel_con[10]); + write32(&cru_ptr->cru_clksel_con[10], + RK_SETBITS(PERI_SEL_GPLL) | RK_CLRSETBITS(PERI_PCLK_DIV_MSK, pclk_div << PERI_PCLK_DIV_SHIFT) | RK_CLRSETBITS(PERI_HCLK_DIV_MSK, hclk_div << PERI_HCLK_DIV_SHIFT) | RK_CLRSETBITS(PERI_ACLK_DIV_MSK, aclk_div << PERI_ACLK_DIV_SHIFT)); /* PLL enter normal-mode */ - writel(RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_NORM) - | RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_NORM), - &cru_ptr->cru_mode_con); + write32(&cru_ptr->cru_mode_con, + RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_NORM) | RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_NORM)); } void rkclk_configure_cpu(void) { /* pll enter slow-mode */ - writel(RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_SLOW), - &cru_ptr->cru_mode_con); + write32(&cru_ptr->cru_mode_con, + RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_SLOW)); rkclk_set_pll(&cru_ptr->cru_apll_con[0], &apll_init_cfg); /* waiting for pll lock */ while (1) { - if (readl(&rk3288_grf->soc_status[1]) & SOCSTS_APLL_LOCK) + if (read32(&rk3288_grf->soc_status[1]) & SOCSTS_APLL_LOCK) break; udelay(1); } @@ -350,24 +336,19 @@ void rkclk_configure_cpu(void) * core clock select apll, apll clk = 1800MHz * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz */ - writel(RK_CLRBITS(CORE_SEL_PLL_MSK) - | RK_CLRSETBITS(A12_DIV_MSK, 0 << A12_DIV_SHIFT) - | RK_CLRSETBITS(MP_DIV_MSK, 3 << MP_DIV_SHIFT) - | RK_CLRSETBITS(M0_DIV_MSK, 1 << 0), - &cru_ptr->cru_clksel_con[0]); + write32(&cru_ptr->cru_clksel_con[0], + RK_CLRBITS(CORE_SEL_PLL_MSK) | RK_CLRSETBITS(A12_DIV_MSK, 0 << A12_DIV_SHIFT) | RK_CLRSETBITS(MP_DIV_MSK, 3 << MP_DIV_SHIFT) | RK_CLRSETBITS(M0_DIV_MSK, 1 << 0)); /* * set up dependent divisors for L2RAM/ATCLK and PCLK clocks. * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz */ - writel(RK_CLRSETBITS(L2_DIV_MSK, 1 << 0) - | RK_CLRSETBITS(ATCLK_DIV_MSK, (3 << ATCLK_DIV_SHIFT)) - | RK_CLRSETBITS(PCLK_DBG_DIV_MSK, (3 << PCLK_DBG_DIV_SHIFT)), - &cru_ptr->cru_clksel_con[37]); + write32(&cru_ptr->cru_clksel_con[37], + RK_CLRSETBITS(L2_DIV_MSK, 1 << 0) | RK_CLRSETBITS(ATCLK_DIV_MSK, (3 << ATCLK_DIV_SHIFT)) | RK_CLRSETBITS(PCLK_DBG_DIV_MSK, (3 << PCLK_DBG_DIV_SHIFT))); /* PLL enter normal-mode */ - writel(RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_NORM), - &cru_ptr->cru_mode_con); + write32(&cru_ptr->cru_mode_con, + RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_NORM)); } void rkclk_configure_ddr(unsigned int hz) @@ -392,21 +373,21 @@ void rkclk_configure_ddr(unsigned int hz) } /* pll enter slow-mode */ - writel(RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_SLOW), - &cru_ptr->cru_mode_con); + write32(&cru_ptr->cru_mode_con, + RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_SLOW)); rkclk_set_pll(&cru_ptr->cru_dpll_con[0], &dpll_cfg); /* waiting for pll lock */ while (1) { - if (readl(&rk3288_grf->soc_status[1]) & SOCSTS_DPLL_LOCK) + if (read32(&rk3288_grf->soc_status[1]) & SOCSTS_DPLL_LOCK) break; udelay(1); } /* PLL enter normal-mode */ - writel(RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_NORM), - &cru_ptr->cru_mode_con); + write32(&cru_ptr->cru_mode_con, + RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_NORM)); } void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy) @@ -417,22 +398,16 @@ void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy) u32 phy_psrstn_shift = 1 + 5 * ch; u32 phy_srstn_shift = 5 * ch; - writel(RK_CLRSETBITS(1 << phy_ctl_srstn_shift, - phy << phy_ctl_srstn_shift) - | RK_CLRSETBITS(1 << ctl_psrstn_shift, ctl << ctl_psrstn_shift) - | RK_CLRSETBITS(1 << ctl_srstn_shift, ctl << ctl_srstn_shift) - | RK_CLRSETBITS(1 << phy_psrstn_shift, phy << phy_psrstn_shift) - | RK_CLRSETBITS(1 << phy_srstn_shift, phy << phy_srstn_shift), - &cru_ptr->cru_softrst_con[10]); + write32(&cru_ptr->cru_softrst_con[10], + RK_CLRSETBITS(1 << phy_ctl_srstn_shift, phy << phy_ctl_srstn_shift) | RK_CLRSETBITS(1 << ctl_psrstn_shift, ctl << ctl_psrstn_shift) | RK_CLRSETBITS(1 << ctl_srstn_shift, ctl << ctl_srstn_shift) | RK_CLRSETBITS(1 << phy_psrstn_shift, phy << phy_psrstn_shift) | RK_CLRSETBITS(1 << phy_srstn_shift, phy << phy_srstn_shift)); } void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n) { u32 phy_ctl_srstn_shift = 4 + 5 * ch; - writel(RK_CLRSETBITS(1 << phy_ctl_srstn_shift, - n << phy_ctl_srstn_shift), - &cru_ptr->cru_softrst_con[10]); + write32(&cru_ptr->cru_softrst_con[10], + RK_CLRSETBITS(1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift)); } void rkclk_configure_spi(unsigned int bus, unsigned int hz) @@ -443,19 +418,16 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz) switch (bus) { /*select gpll as spi src clk, and set div*/ case 0: - writel(RK_CLRSETBITS(1 << 7 | 0x1f << 0, 1 << 7 - | (src_clk_div - 1) << 0), - &cru_ptr->cru_clksel_con[25]); + write32(&cru_ptr->cru_clksel_con[25], + RK_CLRSETBITS(1 << 7 | 0x1f << 0, 1 << 7 | (src_clk_div - 1) << 0)); break; case 1: - writel(RK_CLRSETBITS(1 << 15 | 0x1f << 8, 1 << 15 - | (src_clk_div - 1) << 8), - &cru_ptr->cru_clksel_con[25]); + write32(&cru_ptr->cru_clksel_con[25], + RK_CLRSETBITS(1 << 15 | 0x1f << 8, 1 << 15 | (src_clk_div - 1) << 8)); break; case 2: - writel(RK_CLRSETBITS(1 << 7 | 0x1f << 0, 1 << 7 - | (src_clk_div - 1) << 0), - &cru_ptr->cru_clksel_con[39]); + write32(&cru_ptr->cru_clksel_con[39], + RK_CLRSETBITS(1 << 7 | 0x1f << 0, 1 << 7 | (src_clk_div - 1) << 0)); break; default: printk(BIOS_ERR, "do not support this spi bus\n"); @@ -481,16 +453,15 @@ void rkclk_configure_i2s(unsigned int hz) i2s0_outclk_sel: clk_i2s i2s0_clk_sel: divider ouput from fraction i2s0_pll_div_con: 0*/ - writel(RK_CLRSETBITS(1 << 15 | 1 << 12 | 3 << 8 | 0x7f << 0 , - 1 << 15 | 0 << 12 | 1 << 8 | 0 << 0), - &cru_ptr->cru_clksel_con[4]); + write32(&cru_ptr->cru_clksel_con[4], + RK_CLRSETBITS(1 << 15 | 1 << 12 | 3 << 8 | 0x7f << 0, 1 << 15 | 0 << 12 | 1 << 8 | 0 << 0)); /* set frac divider */ v = clk_gcd(GPLL_HZ, hz); n = (GPLL_HZ / v) & (0xffff); d = (hz / v) & (0xffff); assert(hz == GPLL_HZ / n * d); - writel(d << 16 | n, &cru_ptr->cru_clksel_con[8]); + write32(&cru_ptr->cru_clksel_con[8], d << 16 | n); } void rkclk_configure_crypto(unsigned int hz) @@ -499,8 +470,8 @@ void rkclk_configure_crypto(unsigned int hz) assert((div - 1 < 4) && (div * hz == PD_BUS_ACLK_HZ)); assert(hz <= 150*MHz); /* Suggested max in TRM. */ - writel(RK_CLRSETBITS(0x3 << 6, (div - 1) << 6), - &cru_ptr->cru_clksel_con[26]); + write32(&cru_ptr->cru_clksel_con[26], + RK_CLRSETBITS(0x3 << 6, (div - 1) << 6)); } void rkclk_configure_tsadc(unsigned int hz) @@ -510,8 +481,8 @@ void rkclk_configure_tsadc(unsigned int hz) div = src_clk / hz; assert((div - 1 < 64) && (div * hz == 32 * KHz)); - writel(RK_CLRSETBITS(0x3f << 0, (div - 1) << 0), - &cru_ptr->cru_clksel_con[2]); + write32(&cru_ptr->cru_clksel_con[2], + RK_CLRSETBITS(0x3f << 0, (div - 1) << 0)); } static int pll_para_config(u32 freq_hz, struct pll_div *div) @@ -579,12 +550,12 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div) void rkclk_configure_edp(void) { /* clk_edp_24M source: 24M */ - writel(RK_SETBITS(1 << 15), &cru_ptr->cru_clksel_con[28]); + write32(&cru_ptr->cru_clksel_con[28], RK_SETBITS(1 << 15)); /* rst edp */ - writel(RK_SETBITS(1 << 15), &cru_ptr->cru_softrst_con[6]); + write32(&cru_ptr->cru_softrst_con[6], RK_SETBITS(1 << 15)); udelay(1); - writel(RK_CLRBITS(1 << 15), &cru_ptr->cru_softrst_con[6]); + write32(&cru_ptr->cru_softrst_con[6], RK_CLRBITS(1 << 15)); } void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz) @@ -597,15 +568,13 @@ void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz) switch (vop_id) { case 0: - writel(RK_CLRSETBITS(3 << 6 | 0x1f << 0, - 0 << 6 | (div - 1) << 0), - &cru_ptr->cru_clksel_con[31]); + write32(&cru_ptr->cru_clksel_con[31], + RK_CLRSETBITS(3 << 6 | 0x1f << 0, 0 << 6 | (div - 1) << 0)); break; case 1: - writel(RK_CLRSETBITS(3 << 14 | 0x1f << 8, - 0 << 14 | (div - 1) << 8), - &cru_ptr->cru_clksel_con[31]); + write32(&cru_ptr->cru_clksel_con[31], + RK_CLRSETBITS(3 << 14 | 0x1f << 8, 0 << 14 | (div - 1) << 8)); break; } } @@ -618,34 +587,32 @@ int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz) return -1; /* npll enter slow-mode */ - writel(RK_CLRSETBITS(NPLL_MODE_MSK, NPLL_MODE_SLOW), - &cru_ptr->cru_mode_con); + write32(&cru_ptr->cru_mode_con, + RK_CLRSETBITS(NPLL_MODE_MSK, NPLL_MODE_SLOW)); rkclk_set_pll(&cru_ptr->cru_npll_con[0], &npll_config); /* waiting for pll lock */ while (1) { - if (readl(&rk3288_grf->soc_status[1]) & SOCSTS_NPLL_LOCK) + if (read32(&rk3288_grf->soc_status[1]) & SOCSTS_NPLL_LOCK) break; udelay(1); } /* npll enter normal-mode */ - writel(RK_CLRSETBITS(NPLL_MODE_MSK, NPLL_MODE_NORM), - &cru_ptr->cru_mode_con); + write32(&cru_ptr->cru_mode_con, + RK_CLRSETBITS(NPLL_MODE_MSK, NPLL_MODE_NORM)); /* vop dclk source clk: npll,dclk_div: 1 */ switch (vop_id) { case 0: - writel(RK_CLRSETBITS(0xff << 8 | 3 << 0, - 0 << 8 | 2 << 0), - &cru_ptr->cru_clksel_con[27]); + write32(&cru_ptr->cru_clksel_con[27], + RK_CLRSETBITS(0xff << 8 | 3 << 0, 0 << 8 | 2 << 0)); break; case 1: - writel(RK_CLRSETBITS(0xff << 8 | 3 << 6, - 0 << 8 | 2 << 6), - &cru_ptr->cru_clksel_con[29]); + write32(&cru_ptr->cru_clksel_con[29], + RK_CLRSETBITS(0xff << 8 | 3 << 6, 0 << 8 | 2 << 6)); break; } return 0; @@ -654,5 +621,5 @@ int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz) int rkclk_was_watchdog_reset(void) { /* Bits 5 and 4 are "second" and "first" global watchdog reset. */ - return readl(&cru_ptr->cru_glb_rst_st) & 0x30; + return read32(&cru_ptr->cru_glb_rst_st) & 0x30; } diff --git a/src/soc/rockchip/rk3288/crypto.c b/src/soc/rockchip/rk3288/crypto.c index 20fd60a474..e57d1560e7 100644 --- a/src/soc/rockchip/rk3288/crypto.c +++ b/src/soc/rockchip/rk3288/crypto.c @@ -80,17 +80,17 @@ int vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg, return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED; } - writel(RK_SETBITS(1 << 6), &crypto->ctrl); /* Assert HASH_FLUSH */ + write32(&crypto->ctrl, RK_SETBITS(1 << 6)); /* Assert HASH_FLUSH */ udelay(1); /* for 10+ cycles to */ - writel(RK_CLRBITS(1 << 6), &crypto->ctrl); /* clear out old hash */ + write32(&crypto->ctrl, RK_CLRBITS(1 << 6)); /* clear out old hash */ /* Enable DMA byte swapping for little-endian bus (Byteswap_??FIFO) */ - writel(1 << 5 | 1 << 4 | 1 << 3, &crypto->conf); + write32(&crypto->conf, 1 << 5 | 1 << 4 | 1 << 3); - writel(HRDMA_ERR | HRDMA_DONE, &crypto->intena); /* enable interrupt */ + write32(&crypto->intena, HRDMA_ERR | HRDMA_DONE); /* enable interrupt */ - writel(data_size, &crypto->hash_msg_len); /* program total size */ - writel(1 << 3 | 0x2, &crypto->hash_ctrl); /* swap DOUT, SHA256 */ + write32(&crypto->hash_msg_len, data_size); /* program total size */ + write32(&crypto->hash_ctrl, 1 << 3 | 0x2); /* swap DOUT, SHA256 */ printk(BIOS_DEBUG, "Initialized RK3288 HW crypto for %u byte SHA256\n", data_size); @@ -101,12 +101,12 @@ int vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size) { uint32_t intsts; - writel(HRDMA_ERR | HRDMA_DONE, &crypto->intsts); /* clear interrupts */ + write32(&crypto->intsts, HRDMA_ERR | HRDMA_DONE); /* clear interrupts */ /* NOTE: This assumes that the DMA is reading from uncached SRAM. */ - writel((uint32_t)buf, &crypto->hrdmas); - writel(size / sizeof(uint32_t), &crypto->hrdmal); - writel(RK_SETBITS(1 << 3), &crypto->ctrl); /* Set HASH_START */ + write32(&crypto->hrdmas, (uint32_t)buf); + write32(&crypto->hrdmal, size / sizeof(uint32_t)); + write32(&crypto->ctrl, RK_SETBITS(1 << 3)); /* Set HASH_START */ do { intsts = read32(&crypto->intsts); if (intsts & HRDMA_ERR) { diff --git a/src/soc/rockchip/rk3288/edp.c b/src/soc/rockchip/rk3288/edp.c index 3f27195199..38e972d7cd 100644 --- a/src/soc/rockchip/rk3288/edp.c +++ b/src/soc/rockchip/rk3288/edp.c @@ -53,66 +53,52 @@ static const char *pre_emph_names[] = { static void rk_edp_init_refclk(struct rk_edp *edp) { - writel(SEL_24M, &edp->regs->analog_ctl_2); - writel(REF_CLK_24M, &edp->regs->pll_reg_1); + write32(&edp->regs->analog_ctl_2, SEL_24M); + write32(&edp->regs->pll_reg_1, REF_CLK_24M); /*initial value*/ - writel(LDO_OUTPUT_V_SEL_145 | - KVCO_DEFALUT | - CHG_PUMP_CUR_SEL_5US | - V2L_CUR_SEL_1MA, &edp->regs->pll_reg_2); - - writel(LOCK_DET_CNT_SEL_256 | - LOOP_FILTER_RESET | - PALL_SSC_RESET | - LOCK_DET_BYPASS | - PLL_LOCK_DET_MODE | - PLL_LOCK_DET_FORCE, &edp->regs->pll_reg_3); - - writel(REGULATOR_V_SEL_950MV | - STANDBY_CUR_SEL | - CHG_PUMP_INOUT_CTRL_1200MV | - CHG_PUMP_INPUT_CTRL_OP, &edp->regs->pll_reg_5); - - writel(SSC_OFFSET | SSC_MODE | SSC_DEPTH, &edp->regs->ssc_reg); - - writel(TX_SWING_PRE_EMP_MODE | - PRE_DRIVER_PW_CTRL1 | - LP_MODE_CLK_REGULATOR | - RESISTOR_MSB_CTRL | - RESISTOR_CTRL, &edp->regs->tx_common); - - writel(DP_AUX_COMMON_MODE | - DP_AUX_EN | - AUX_TERM_50OHM, &edp->regs->dp_aux); - - writel(DP_BG_OUT_SEL | - DP_DB_CUR_CTRL | - DP_BG_SEL | - DP_RESISTOR_TUNE_BG, &edp->regs->dp_bias); - - writel(CH1_CH3_SWING_EMP_CTRL | - CH0_CH2_SWING_EMP_CTRL, &edp->regs->dp_reserv2); + write32(&edp->regs->pll_reg_2, + LDO_OUTPUT_V_SEL_145 | KVCO_DEFALUT | CHG_PUMP_CUR_SEL_5US | V2L_CUR_SEL_1MA); + + write32(&edp->regs->pll_reg_3, + LOCK_DET_CNT_SEL_256 | LOOP_FILTER_RESET | PALL_SSC_RESET | LOCK_DET_BYPASS | PLL_LOCK_DET_MODE | PLL_LOCK_DET_FORCE); + + write32(&edp->regs->pll_reg_5, + REGULATOR_V_SEL_950MV | STANDBY_CUR_SEL | CHG_PUMP_INOUT_CTRL_1200MV | CHG_PUMP_INPUT_CTRL_OP); + + write32(&edp->regs->ssc_reg, SSC_OFFSET | SSC_MODE | SSC_DEPTH); + + write32(&edp->regs->tx_common, + TX_SWING_PRE_EMP_MODE | PRE_DRIVER_PW_CTRL1 | LP_MODE_CLK_REGULATOR | RESISTOR_MSB_CTRL | RESISTOR_CTRL); + + write32(&edp->regs->dp_aux, + DP_AUX_COMMON_MODE | DP_AUX_EN | AUX_TERM_50OHM); + + write32(&edp->regs->dp_bias, + DP_BG_OUT_SEL | DP_DB_CUR_CTRL | DP_BG_SEL | DP_RESISTOR_TUNE_BG); + + write32(&edp->regs->dp_reserv2, + CH1_CH3_SWING_EMP_CTRL | CH0_CH2_SWING_EMP_CTRL); } static void rk_edp_init_interrupt(struct rk_edp *edp) { /* Set interrupt pin assertion polarity as high */ - writel(INT_POL, &edp->regs->int_ctl); + write32(&edp->regs->int_ctl, INT_POL); /* Clear pending registers */ - writel(0xff, &edp->regs->common_int_sta_1); - writel(0x4f, &edp->regs->common_int_sta_2); - writel(0xff, &edp->regs->common_int_sta_3); - writel(0x27, &edp->regs->common_int_sta_4); - writel(0x7f, &edp->regs->dp_int_sta); + write32(&edp->regs->common_int_sta_1, 0xff); + write32(&edp->regs->common_int_sta_2, 0x4f); + write32(&edp->regs->common_int_sta_3, 0xff); + write32(&edp->regs->common_int_sta_4, 0x27); + write32(&edp->regs->dp_int_sta, 0x7f); /* 0:mask,1: unmask */ - writel(0x00, &edp->regs->common_int_mask_1); - writel(0x00, &edp->regs->common_int_mask_2); - writel(0x00, &edp->regs->common_int_mask_3); - writel(0x00, &edp->regs->common_int_mask_4); - writel(0x00, &edp->regs->int_sta_mask); + write32(&edp->regs->common_int_mask_1, 0x00); + write32(&edp->regs->common_int_mask_2, 0x00); + write32(&edp->regs->common_int_mask_3, 0x00); + write32(&edp->regs->common_int_mask_4, 0x00); + write32(&edp->regs->int_sta_mask, 0x00); } static void rk_edp_enable_sw_function(struct rk_edp *edp) @@ -124,7 +110,7 @@ static int rk_edp_get_pll_lock_status(struct rk_edp *edp) { u32 val; - val = readl(&edp->regs->dp_debug_ctl); + val = read32(&edp->regs->dp_debug_ctl); return (val & PLL_LOCK) ? DP_PLL_LOCKED : DP_PLL_UNLOCKED; } @@ -132,9 +118,9 @@ static void rk_edp_init_analog_func(struct rk_edp *edp) { struct stopwatch sw; - writel(0x00, &edp->regs->dp_pd); + write32(&edp->regs->dp_pd, 0x00); - writel(PLL_LOCK_CHG, &edp->regs->common_int_sta_1); + write32(&edp->regs->common_int_sta_1, PLL_LOCK_CHG); clrbits_le32(&edp->regs->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL); @@ -156,13 +142,13 @@ static void rk_edp_init_analog_func(struct rk_edp *edp) static void rk_edp_init_aux(struct rk_edp *edp) { /* Clear inerrupts related to AUX channel */ - writel(AUX_FUNC_EN_N, &edp->regs->dp_int_sta); + write32(&edp->regs->dp_int_sta, AUX_FUNC_EN_N); /* Disable AUX channel module */ setbits_le32(&edp->regs->func_en_2, AUX_FUNC_EN_N); /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ - writel(DEFER_CTRL_EN | DEFER_COUNT(1), &edp->regs->aux_ch_defer_dtl); + write32(&edp->regs->aux_ch_defer_dtl, DEFER_CTRL_EN | DEFER_COUNT(1)); /* Enable AUX channel module */ clrbits_le32(&edp->regs->func_en_2, AUX_FUNC_EN_N); @@ -175,7 +161,7 @@ static int rk_edp_aux_enable(struct rk_edp *edp) setbits_le32(&edp->regs->aux_ch_ctl_2, AUX_EN); stopwatch_init_msecs_expire(&sw, 20); do { - if (!(readl(&edp->regs->aux_ch_ctl_2) & AUX_EN)) + if (!(read32(&edp->regs->aux_ch_ctl_2) & AUX_EN)) return 0; } while (!stopwatch_expired(&sw)); @@ -189,12 +175,12 @@ static int rk_edp_is_aux_reply(struct rk_edp *edp) stopwatch_init_msecs_expire(&sw, 10); - while (!(readl(&edp->regs->dp_int_sta) & RPLY_RECEIV)) { + while (!(read32(&edp->regs->dp_int_sta) & RPLY_RECEIV)) { if (stopwatch_expired(&sw)) return -1; } - writel(RPLY_RECEIV, &edp->regs->dp_int_sta); + write32(&edp->regs->dp_int_sta, RPLY_RECEIV); return 0; } @@ -216,14 +202,14 @@ static int rk_edp_start_aux_transaction(struct rk_edp *edp) } /* Clear interrupt source for AUX CH access error */ - val = readl(&edp->regs->dp_int_sta); + val = read32(&edp->regs->dp_int_sta); if (val & AUX_ERR) { - writel(AUX_ERR, &edp->regs->dp_int_sta); + write32(&edp->regs->dp_int_sta, AUX_ERR); return -1; } /* Check AUX CH error access status */ - val = readl(&edp->regs->dp_int_sta); + val = read32(&edp->regs->dp_int_sta); if ((val & AUX_STATUS_MASK) != 0) { edp_debug("AUX CH error happens: %d\n\n", val & AUX_STATUS_MASK); @@ -249,15 +235,15 @@ static int rk_edp_dpcd_transfer(struct rk_edp *edp, /* Clear AUX CH data buffer */ val = BUF_CLR; - writel(val, &edp->regs->buf_data_ctl); + write32(&edp->regs->buf_data_ctl, val); /* Select DPCD device address */ val = AUX_ADDR_7_0(val_addr); - writel(val, &edp->regs->aux_addr_7_0); + write32(&edp->regs->aux_addr_7_0, val); val = AUX_ADDR_15_8(val_addr); - writel(val, &edp->regs->aux_addr_15_8); + write32(&edp->regs->aux_addr_15_8, val); val = AUX_ADDR_19_16(val_addr); - writel(val, &edp->regs->aux_addr_19_16); + write32(&edp->regs->aux_addr_19_16, val); /* * Set DisplayPort transaction and read 1 byte @@ -269,13 +255,14 @@ static int rk_edp_dpcd_transfer(struct rk_edp *edp, AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; for (i = 0; i < len; i++) - writel(*data++, &edp->regs->buf_data[i]); + write32(&edp->regs->buf_data[i], + *data++); } else val = AUX_LENGTH(len) | AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; - writel(val, &edp->regs->aux_ch_ctl_1); + write32(&edp->regs->aux_ch_ctl_1, val); /* Start AUX transaction */ retval = rk_edp_start_aux_transaction(edp); @@ -291,7 +278,7 @@ static int rk_edp_dpcd_transfer(struct rk_edp *edp, if (request == DPCD_READ) { for (i = 0; i < len; i++) - *data++ = (u8)readl(&edp->regs->buf_data[i]); + *data++ = (u8)read32(&edp->regs->buf_data[i]); } length -= len; @@ -357,7 +344,7 @@ static void rk_edp_set_link_training(struct rk_edp *edp, int i; for (i = 0; i < edp->link_train.lane_count; i++) - writel(training_values[i], &edp->regs->ln_link_trn_ctl[i]); + write32(&edp->regs->ln_link_trn_ctl[i], training_values[i]); } static u8 edp_link_status(const u8 *link_status, int r) @@ -484,7 +471,7 @@ static int rk_edp_link_train_cr(struct rk_edp *edp) u8 value; value = DP_TRAINING_PATTERN_1; - writel(value, &edp->regs->dp_training_ptn_set); + write32(&edp->regs->dp_training_ptn_set, value); rk_edp_dpcd_write(edp, DPCD_TRAINING_PATTERN_SET, &value, 1); memset(edp->train_set, 0, 4); @@ -557,7 +544,7 @@ static int rk_edp_link_train_ce(struct rk_edp *edp) u8 status[DP_LINK_STATUS_SIZE]; value = DP_TRAINING_PATTERN_2; - writel(value, &edp->regs->dp_training_ptn_set); + write32(&edp->regs->dp_training_ptn_set, value); rk_edp_dpcd_write(edp, DPCD_TRAINING_PATTERN_SET, &value, 1); /* channel equalization loop */ @@ -635,18 +622,18 @@ static int rk_edp_hw_link_training(struct rk_edp *edp) struct stopwatch sw; /* Set link rate and count as you want to establish*/ - writel(edp->link_train.link_rate, &edp->regs->link_bw_set); - writel(edp->link_train.lane_count, &edp->regs->lane_count_set); + write32(&edp->regs->link_bw_set, edp->link_train.link_rate); + write32(&edp->regs->lane_count_set, edp->link_train.lane_count); if (rk_edp_link_train_cr(edp)) return -1; if (rk_edp_link_train_ce(edp)) return -1; - writel(HW_LT_EN, &edp->regs->dp_hw_link_training); + write32(&edp->regs->dp_hw_link_training, HW_LT_EN); stopwatch_init_msecs_expire(&sw, 10); do { - val = readl(&edp->regs->dp_hw_link_training); + val = read32(&edp->regs->dp_hw_link_training); if (!(val & HW_LT_EN)) break; } while (!stopwatch_expired(&sw)); @@ -668,12 +655,12 @@ static int rk_edp_select_i2c_device(struct rk_edp *edp, /* Set EDID device address */ val = device_addr; - writel(val, &edp->regs->aux_addr_7_0); - writel(0x0, &edp->regs->aux_addr_15_8); - writel(0x0, &edp->regs->aux_addr_19_16); + write32(&edp->regs->aux_addr_7_0, val); + write32(&edp->regs->aux_addr_15_8, 0x0); + write32(&edp->regs->aux_addr_19_16, 0x0); /* Set offset from base address of EDID device */ - writel(val_addr, &edp->regs->buf_data[0]); + write32(&edp->regs->buf_data[0], val_addr); /* * Set I2C transaction and write address @@ -682,7 +669,7 @@ static int rk_edp_select_i2c_device(struct rk_edp *edp, */ val = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT | AUX_TX_COMM_WRITE; - writel(val, &edp->regs->aux_ch_ctl_1); + write32(&edp->regs->aux_ch_ctl_1, val); /* Start AUX transaction */ retval = rk_edp_start_aux_transaction(edp); @@ -708,7 +695,7 @@ static int rk_edp_read_bytes_from_i2c(struct rk_edp *edp, for (j = 0; j < 10; j++) { /* try 10 times */ /* Clear AUX CH data buffer */ val = BUF_CLR; - writel(val, &edp->regs->buf_data_ctl); + write32(&edp->regs->buf_data_ctl, val); /* Set normal AUX CH command */ clrbits_le32(&edp->regs->aux_ch_ctl_2, ADDR_ONLY); @@ -730,7 +717,7 @@ static int rk_edp_read_bytes_from_i2c(struct rk_edp *edp, */ val = AUX_LENGTH(16) | AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_READ; - writel(val, &edp->regs->aux_ch_ctl_1); + write32(&edp->regs->aux_ch_ctl_1, val); /* Start AUX transaction */ retval = rk_edp_start_aux_transaction(edp); @@ -742,7 +729,7 @@ static int rk_edp_read_bytes_from_i2c(struct rk_edp *edp, } /* Check if Rx sends defer */ - val = readl(&edp->regs->aux_rx_comm); + val = read32(&edp->regs->aux_rx_comm); if (val == AUX_RX_COMM_AUX_DEFER || val == AUX_RX_COMM_I2C_DEFER) { edp_debug("Defer: %d\n\n", val); @@ -754,7 +741,7 @@ static int rk_edp_read_bytes_from_i2c(struct rk_edp *edp, return -1; for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) { - val = readl(&edp->regs->buf_data[cur_data_idx]); + val = read32(&edp->regs->buf_data[cur_data_idx]); edid[i + cur_data_idx] = (u8)val; } } @@ -818,13 +805,13 @@ static void rk_edp_init_video(struct rk_edp *edp) u32 val; val = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; - writel(val, &edp->regs->common_int_sta_1); + write32(&edp->regs->common_int_sta_1, val); val = CHA_CRI(4) | CHA_CTRL; - writel(val, &edp->regs->sys_ctl_2); + write32(&edp->regs->sys_ctl_2, val); val = VID_HRES_TH(2) | VID_VRES_TH(0); - writel(val, &edp->regs->video_ctl_8); + write32(&edp->regs->video_ctl_8, val); } static void rk_edp_config_video_slave_mode(struct rk_edp *edp) @@ -843,24 +830,24 @@ static void rk_edp_set_video_cr_mn(struct rk_edp *edp, if (type == REGISTER_M) { setbits_le32(&edp->regs->sys_ctl_4, FIX_M_VID); val = m_value & 0xff; - writel(val, &edp->regs->m_vid_0); + write32(&edp->regs->m_vid_0, val); val = (m_value >> 8) & 0xff; - writel(val, &edp->regs->m_vid_1); + write32(&edp->regs->m_vid_1, val); val = (m_value >> 16) & 0xff; - writel(val, &edp->regs->m_vid_2); + write32(&edp->regs->m_vid_2, val); val = n_value & 0xff; - writel(val, &edp->regs->n_vid_0); + write32(&edp->regs->n_vid_0, val); val = (n_value >> 8) & 0xff; - writel(val, &edp->regs->n_vid_1); + write32(&edp->regs->n_vid_1, val); val = (n_value >> 16) & 0xff; - writel(val, &edp->regs->n_vid_2); + write32(&edp->regs->n_vid_2, val); } else { clrbits_le32(&edp->regs->sys_ctl_4, FIX_M_VID); - writel(0x00, &edp->regs->n_vid_0); - writel(0x80, &edp->regs->n_vid_1); - writel(0x00, &edp->regs->n_vid_2); + write32(&edp->regs->n_vid_0, 0x00); + write32(&edp->regs->n_vid_1, 0x80); + write32(&edp->regs->n_vid_2, 0x00); } } @@ -871,19 +858,19 @@ static int rk_edp_is_video_stream_clock_on(struct rk_edp *edp) stopwatch_init_msecs_expire(&sw, 100); do { - val = readl(&edp->regs->sys_ctl_1); + val = read32(&edp->regs->sys_ctl_1); /*must write value to update DET_STA bit status*/ - writel(val, &edp->regs->sys_ctl_1); - val = readl(&edp->regs->sys_ctl_1); + write32(&edp->regs->sys_ctl_1, val); + val = read32(&edp->regs->sys_ctl_1); if (!(val & DET_STA)) continue; - val = readl(&edp->regs->sys_ctl_2); + val = read32(&edp->regs->sys_ctl_2); /*must write value to update CHA_STA bit status*/ - writel(val, &edp->regs->sys_ctl_2); - val = readl(&edp->regs->sys_ctl_2); + write32(&edp->regs->sys_ctl_2, val); + val = read32(&edp->regs->sys_ctl_2); if (!(val & CHA_STA)) return 0; } while (!stopwatch_expired(&sw)); @@ -898,12 +885,12 @@ static int rk_edp_is_video_stream_on(struct rk_edp *edp) stopwatch_init_msecs_expire(&sw, 100); do { - val = readl(&edp->regs->sys_ctl_3); + val = read32(&edp->regs->sys_ctl_3); /*must write value to update STRM_VALID bit status*/ - writel(val, &edp->regs->sys_ctl_3); + write32(&edp->regs->sys_ctl_3, val); - val = readl(&edp->regs->sys_ctl_3); + val = read32(&edp->regs->sys_ctl_3); if (!(val & STRM_VALID)) return 0; } while (!stopwatch_expired(&sw)); @@ -942,16 +929,16 @@ static void rockchip_edp_force_hpd(struct rk_edp *edp) { u32 val; - val = readl(&edp->regs->sys_ctl_3); + val = read32(&edp->regs->sys_ctl_3); val |= (F_HPD | HPD_CTRL); - writel(val, &edp->regs->sys_ctl_3); + write32(&edp->regs->sys_ctl_3, val); } static int rockchip_edp_get_plug_in_status(struct rk_edp *edp) { u32 val; - val = readl(&edp->regs->sys_ctl_3); + val = read32(&edp->regs->sys_ctl_3); if (val & HPD_STATUS) return 1; @@ -1020,11 +1007,11 @@ void rk_edp_init(u32 vop_id) rk_edp.regs = (struct rk3288_edp_regs *)EDP_BASE; /* grf_edp_ref_clk_sel: from internal 24MHz or 27MHz clock */ - writel(RK_SETBITS(1 << 4), &rk3288_grf->soc_con12); + write32(&rk3288_grf->soc_con12, RK_SETBITS(1 << 4)); /* select epd signal from vop0 or vop1 */ val = (vop_id == 1) ? RK_SETBITS(1 << 5) : RK_CLRBITS(1 << 5); - writel(val, &rk3288_grf->soc_con6); + write32(&rk3288_grf->soc_con6, val); rockchip_edp_wait_hpd(&rk_edp); diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c index b84d6a0821..5fc9c7b185 100644 --- a/src/soc/rockchip/rk3288/gpio.c +++ b/src/soc/rockchip/rk3288/gpio.c @@ -52,9 +52,8 @@ static void __gpio_input(gpio_t gpio, u32 pull) clrsetbits_le32(&rk3288_pmu->gpio0pull[gpio.bank], 3 << (gpio.idx * 2), pull << (gpio.idx * 2)); else - writel(RK_CLRSETBITS(3 << (gpio.idx * 2), - pull << (gpio.idx * 2)), - &rk3288_grf->gpio1_p[(gpio.port - 1)][gpio.bank]); + write32(&rk3288_grf->gpio1_p[(gpio.port - 1)][gpio.bank], + RK_CLRSETBITS(3 << (gpio.idx * 2), pull << (gpio.idx * 2))); } void gpio_input(gpio_t gpio) @@ -74,7 +73,7 @@ void gpio_input_pullup(gpio_t gpio) int gpio_get(gpio_t gpio) { - return (readl(&gpio_port[gpio.port]->ext_porta) >> gpio.num) & 0x1; + return (read32(&gpio_port[gpio.port]->ext_porta) >> gpio.num) & 0x1; } void gpio_output(gpio_t gpio, int value) diff --git a/src/soc/rockchip/rk3288/i2c.c b/src/soc/rockchip/rk3288/i2c.c index d69bb7cb78..6174aafd3c 100644 --- a/src/soc/rockchip/rk3288/i2c.c +++ b/src/soc/rockchip/rk3288/i2c.c @@ -97,10 +97,10 @@ static int i2c_send_start(struct rk3288_i2c_regs *reg_addr) int timeout = I2C_TIMEOUT_US; i2c_info("I2c Start::Send Start bit\n"); - writel(I2C_CLEANI, ®_addr->i2c_ipd); - writel(I2C_EN | I2C_START, ®_addr->i2c_con); + write32(®_addr->i2c_ipd, I2C_CLEANI); + write32(®_addr->i2c_con, I2C_EN | I2C_START); while (timeout--) { - if (readl(®_addr->i2c_ipd) & I2C_STARTI) + if (read32(®_addr->i2c_ipd) & I2C_STARTI) break; udelay(1); } @@ -119,14 +119,14 @@ static int i2c_send_stop(struct rk3288_i2c_regs *reg_addr) int timeout = I2C_TIMEOUT_US; i2c_info("I2c Stop::Send Stop bit\n"); - writel(I2C_CLEANI, ®_addr->i2c_ipd); - writel(I2C_EN | I2C_STOP, ®_addr->i2c_con); + write32(®_addr->i2c_ipd, I2C_CLEANI); + write32(®_addr->i2c_con, I2C_EN | I2C_STOP); while (timeout--) { - if (readl(®_addr->i2c_ipd) & I2C_STOPI) + if (read32(®_addr->i2c_ipd) & I2C_STOPI) break; udelay(1); } - writel(0, ®_addr->i2c_con); + write32(®_addr->i2c_con, 0); if (timeout <= 0) { printk(BIOS_ERR, "I2C Stop::Send Stop Bit Timeout\n"); res = I2C_TIMEOUT; @@ -147,8 +147,8 @@ static int i2c_read(struct rk3288_i2c_regs *reg_addr, struct i2c_seg segment) unsigned int con = 0; unsigned int i, j; - writel(I2C_8BIT | segment.chip << 1 | 1, ®_addr->i2c_mrxaddr); - writel(0, ®_addr->i2c_mrxraddr); + write32(®_addr->i2c_mrxaddr, I2C_8BIT | segment.chip << 1 | 1); + write32(®_addr->i2c_mrxraddr, 0); con = I2C_MODE_TRX | I2C_EN | I2C_ACT2NAK; while (bytes_remaining) { bytes_transfered = MIN(bytes_remaining, 32); @@ -157,30 +157,30 @@ static int i2c_read(struct rk3288_i2c_regs *reg_addr, struct i2c_seg segment) con |= I2C_EN | I2C_NAK; words_transfered = ALIGN_UP(bytes_transfered, 4) / 4; - writel(I2C_CLEANI, ®_addr->i2c_ipd); - writel(con, ®_addr->i2c_con); - writel(bytes_transfered, ®_addr->i2c_mrxcnt); + write32(®_addr->i2c_ipd, I2C_CLEANI); + write32(®_addr->i2c_con, con); + write32(®_addr->i2c_mrxcnt, bytes_transfered); timeout = I2C_TIMEOUT_US; while (timeout--) { - if (readl(®_addr->i2c_ipd) & I2C_NAKRCVI) { - writel(0, ®_addr->i2c_mrxcnt); - writel(0, ®_addr->i2c_con); + if (read32(®_addr->i2c_ipd) & I2C_NAKRCVI) { + write32(®_addr->i2c_mrxcnt, 0); + write32(®_addr->i2c_con, 0); return I2C_NOACK; } - if (readl(®_addr->i2c_ipd) & I2C_MBRFI) + if (read32(®_addr->i2c_ipd) & I2C_MBRFI) break; udelay(1); } if (timeout <= 0) { printk(BIOS_ERR, "I2C Read::Recv Data Timeout\n"); - writel(0, ®_addr->i2c_mrxcnt); - writel(0, ®_addr->i2c_con); + write32(®_addr->i2c_mrxcnt, 0); + write32(®_addr->i2c_con, 0); return I2C_TIMEOUT; } for (i = 0; i < words_transfered; i++) { - rxdata = readl(®_addr->rxdata[i]); + rxdata = read32(®_addr->rxdata[i]); i2c_info("I2c Read::RXDATA[%d] = 0x%x\n", i, rxdata); for (j = 0; j < 4; j++) { if ((i * 4 + j) == bytes_transfered) @@ -215,32 +215,33 @@ static int i2c_write(struct rk3288_i2c_regs *reg_addr, struct i2c_seg segment) break; txdata |= (*data++) << (j * 8); } while (++j < 4); - writel(txdata, ®_addr->txdata[i]); + write32(®_addr->txdata[i], txdata); j = 0; i2c_info("I2c Write::TXDATA[%d] = 0x%x\n", i, txdata); txdata = 0; } - writel(I2C_CLEANI, ®_addr->i2c_ipd); - writel(I2C_EN | I2C_MODE_TX | I2C_ACT2NAK, ®_addr->i2c_con); - writel(bytes_transfered, ®_addr->i2c_mtxcnt); + write32(®_addr->i2c_ipd, I2C_CLEANI); + write32(®_addr->i2c_con, + I2C_EN | I2C_MODE_TX | I2C_ACT2NAK); + write32(®_addr->i2c_mtxcnt, bytes_transfered); timeout = I2C_TIMEOUT_US; while (timeout--) { - if (readl(®_addr->i2c_ipd) & I2C_NAKRCVI) { - writel(0, ®_addr->i2c_mtxcnt); - writel(0, ®_addr->i2c_con); + if (read32(®_addr->i2c_ipd) & I2C_NAKRCVI) { + write32(®_addr->i2c_mtxcnt, 0); + write32(®_addr->i2c_con, 0); return I2C_NOACK; } - if (readl(®_addr->i2c_ipd) & I2C_MBTFI) + if (read32(®_addr->i2c_ipd) & I2C_MBTFI) break; udelay(1); } if (timeout <= 0) { printk(BIOS_ERR, "I2C Write::Send Data Timeout\n"); - writel(0, ®_addr->i2c_mtxcnt); - writel(0, ®_addr->i2c_con); + write32(®_addr->i2c_mtxcnt, 0); + write32(®_addr->i2c_con, 0); return I2C_TIMEOUT; } @@ -310,5 +311,5 @@ void i2c_init(unsigned int bus, unsigned int hz) divh = clk_div * 3 / 7 - 1; divl = clk_div - divh - 2; assert((divh < 65536) && (divl < 65536)); - writel((divh << 16) | (divl << 0), ®s->i2c_clkdiv); + write32(®s->i2c_clkdiv, (divh << 16) | (divl << 0)); } diff --git a/src/soc/rockchip/rk3288/pwm.c b/src/soc/rockchip/rk3288/pwm.c index a44724959e..fb47dc8312 100644 --- a/src/soc/rockchip/rk3288/pwm.c +++ b/src/soc/rockchip/rk3288/pwm.c @@ -73,17 +73,15 @@ void pwm_init(u32 id, u32 period_ns, u32 duty_ns) unsigned long period, duty; /*use rk pwm*/ - writel(RK_SETBITS(1 << 0), &rk3288_grf->soc_con2); + write32(&rk3288_grf->soc_con2, RK_SETBITS(1 << 0)); - writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE | - PWM_CONTINUOUS | PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE | - RK_PWM_DISABLE, - &rk3288_pwm->pwm[id].pwm_ctrl); + write32(&rk3288_pwm->pwm[id].pwm_ctrl, + PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_CONTINUOUS | PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE | RK_PWM_DISABLE); period = (PD_BUS_PCLK_HZ / 1000) * period_ns / USECS_PER_SEC; duty = (PD_BUS_PCLK_HZ / 1000) * duty_ns / USECS_PER_SEC; - writel(period, &rk3288_pwm->pwm[id].pwm_period_hpr); - writel(duty, &rk3288_pwm->pwm[id].pwm_duty_lpr); + write32(&rk3288_pwm->pwm[id].pwm_period_hpr, period); + write32(&rk3288_pwm->pwm[id].pwm_duty_lpr, duty); setbits_le32(&rk3288_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE); } diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index 44f9172bee..86acf6dc3f 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -515,7 +515,7 @@ static void copy_to_reg(u32 *dest, const u32 *src, u32 n) { int i; for (i = 0; i < n / sizeof(u32); i++) { - writel(*src, dest); + write32(dest, *src); src++; dest++; } @@ -571,27 +571,27 @@ static void phy_dll_bypass_set(struct rk3288_ddr_publ_regs *ddr_publ_regs, static void dfi_cfg(struct rk3288_ddr_pctl_regs *ddr_pctl_regs, u32 dramtype) { - writel(DFI_INIT_START, &ddr_pctl_regs->dfistcfg0); - writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, - &ddr_pctl_regs->dfistcfg1); - writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &ddr_pctl_regs->dfistcfg2); - writel(TLP_RESP_TIME(7) | LP_SR_EN | LP_PD_EN, - &ddr_pctl_regs->dfilpcfg0); - - writel(TCTRL_DELAY_TIME(2), &ddr_pctl_regs->dfitctrldelay); - writel(TPHY_WRDATA_TIME(1), &ddr_pctl_regs->dfitphywrdata); - writel(TPHY_RDLAT_TIME(0xf), &ddr_pctl_regs->dfitphyrdlat); - writel(TDRAM_CLK_DIS_TIME(2), &ddr_pctl_regs->dfitdramclkdis); - writel(TDRAM_CLK_EN_TIME(2), &ddr_pctl_regs->dfitdramclken); - writel(0x1, &ddr_pctl_regs->dfitphyupdtype0); + write32(&ddr_pctl_regs->dfistcfg0, DFI_INIT_START); + write32(&ddr_pctl_regs->dfistcfg1, + DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN); + write32(&ddr_pctl_regs->dfistcfg2, DFI_PARITY_INTR_EN | DFI_PARITY_EN); + write32(&ddr_pctl_regs->dfilpcfg0, + TLP_RESP_TIME(7) | LP_SR_EN | LP_PD_EN); + + write32(&ddr_pctl_regs->dfitctrldelay, TCTRL_DELAY_TIME(2)); + write32(&ddr_pctl_regs->dfitphywrdata, TPHY_WRDATA_TIME(1)); + write32(&ddr_pctl_regs->dfitphyrdlat, TPHY_RDLAT_TIME(0xf)); + write32(&ddr_pctl_regs->dfitdramclkdis, TDRAM_CLK_DIS_TIME(2)); + write32(&ddr_pctl_regs->dfitdramclken, TDRAM_CLK_EN_TIME(2)); + write32(&ddr_pctl_regs->dfitphyupdtype0, 0x1); /* cs0 and cs1 write odt enable */ - writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), - &ddr_pctl_regs->dfiodtcfg); + write32(&ddr_pctl_regs->dfiodtcfg, + (RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL)); /* odt write length */ - writel(ODT_LEN_BL8_W(7), &ddr_pctl_regs->dfiodtcfg1); + write32(&ddr_pctl_regs->dfiodtcfg1, ODT_LEN_BL8_W(7)); /* phyupd and ctrlupd disabled */ - writel(0, &ddr_pctl_regs->dfiupdcfg); + write32(&ddr_pctl_regs->dfiupdcfg, 0); } static void pctl_cfg(u32 channel, @@ -605,39 +605,33 @@ static void pctl_cfg(u32 channel, sizeof(sdram_params->pctl_timing)); switch (sdram_params->dramtype) { case LPDDR3: - writel(sdram_params->pctl_timing.tcl - 1, - &ddr_pctl_regs->dfitrddataen); - writel(sdram_params->pctl_timing.tcwl, - &ddr_pctl_regs->dfitphywrlat); - writel(LPDDR2_S4 | MDDR_LPDDR2_CLK_STOP_IDLE(0) | LPDDR2_EN - | BURSTLENGTH_CFG(burstlen) | TFAW_CFG(6) | PD_EXIT_FAST - | PD_TYPE(1) | PD_IDLE(0), &ddr_pctl_regs->mcfg); - writel(MSCH_MAINDDR3(channel, 0), &rk3288_grf->soc_con0); - - writel(PUBL_LPDDR3_EN(channel, 1) - | PCTL_BST_DISABLE(channel, 1) - | PCTL_LPDDR3_ODT_EN(channel, sdram_params->odt), - &rk3288_grf->soc_con2); + write32(&ddr_pctl_regs->dfitrddataen, + sdram_params->pctl_timing.tcl - 1); + write32(&ddr_pctl_regs->dfitphywrlat, + sdram_params->pctl_timing.tcwl); + write32(&ddr_pctl_regs->mcfg, + LPDDR2_S4 | MDDR_LPDDR2_CLK_STOP_IDLE(0) | LPDDR2_EN | BURSTLENGTH_CFG(burstlen) | TFAW_CFG(6) | PD_EXIT_FAST | PD_TYPE(1) | PD_IDLE(0)); + write32(&rk3288_grf->soc_con0, MSCH_MAINDDR3(channel, 0)); + + write32(&rk3288_grf->soc_con2, + PUBL_LPDDR3_EN(channel, 1) | PCTL_BST_DISABLE(channel, 1) | PCTL_LPDDR3_ODT_EN(channel, sdram_params->odt)); break; case DDR3: if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) - writel(sdram_params->pctl_timing.tcl - 3, - &ddr_pctl_regs->dfitrddataen); + write32(&ddr_pctl_regs->dfitrddataen, + sdram_params->pctl_timing.tcl - 3); else - writel(sdram_params->pctl_timing.tcl - 2, - &ddr_pctl_regs->dfitrddataen); - writel(sdram_params->pctl_timing.tcwl - 1, - &ddr_pctl_regs->dfitphywrlat); - writel(MDDR_LPDDR2_CLK_STOP_IDLE(0) | DDR3_EN - | DDR2_DDR3_BL_8 | TFAW_CFG(6) | PD_EXIT_SLOW - | PD_TYPE(1) | PD_IDLE(0), &ddr_pctl_regs->mcfg); - writel(MSCH_MAINDDR3(channel, 1), &rk3288_grf->soc_con0); - - writel(PUBL_LPDDR3_EN(channel, 0) - | PCTL_BST_DISABLE(channel, 0) - | PCTL_LPDDR3_ODT_EN(channel, 0), - &rk3288_grf->soc_con2); + write32(&ddr_pctl_regs->dfitrddataen, + sdram_params->pctl_timing.tcl - 2); + write32(&ddr_pctl_regs->dfitphywrlat, + sdram_params->pctl_timing.tcwl - 1); + write32(&ddr_pctl_regs->mcfg, + MDDR_LPDDR2_CLK_STOP_IDLE(0) | DDR3_EN | DDR2_DDR3_BL_8 | TFAW_CFG(6) | PD_EXIT_SLOW | PD_TYPE(1) | PD_IDLE(0)); + write32(&rk3288_grf->soc_con0, MSCH_MAINDDR3(channel, 1)); + + write32(&rk3288_grf->soc_con2, + PUBL_LPDDR3_EN(channel, 0) | PCTL_BST_DISABLE(channel, 0) | PCTL_LPDDR3_ODT_EN(channel, 0)); break; } @@ -656,23 +650,17 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) copy_to_reg(&ddr_publ_regs->dtpr[0], &(sdram_params->phy_timing.dtpr0), sizeof(sdram_params->phy_timing)); - writel(sdram_params->noc_timing, &msch_regs->ddrtiming); - writel(0x3f, &msch_regs->readlatency); - writel(sdram_params->noc_activate, &msch_regs->activate); - writel(BUSWRTORD(2) | BUSRDTOWR(2) | BUSRDTORD(1), - &msch_regs->devtodev); - writel(PRT_DLLLOCK(div_round_up(sdram_params->ddr_freq/MHz - * 5120, 1000)) - | PRT_DLLSRST(div_round_up(sdram_params->ddr_freq/MHz - * 50, 1000)) - | PRT_ITMSRST(8), &ddr_publ_regs->ptr[0]); - writel(PRT_DINIT0(div_round_up(sdram_params->ddr_freq/MHz - * 500000, 1000)) - | PRT_DINIT1(div_round_up(sdram_params->ddr_freq/MHz - * 400, 1000)), &ddr_publ_regs->ptr[1]); - writel(PRT_DINIT2(MIN(dinit2, 0x1ffff)) - | PRT_DINIT3(div_round_up(sdram_params->ddr_freq/MHz - * 1000, 1000)), &ddr_publ_regs->ptr[2]); + write32(&msch_regs->ddrtiming, sdram_params->noc_timing); + write32(&msch_regs->readlatency, 0x3f); + write32(&msch_regs->activate, sdram_params->noc_activate); + write32(&msch_regs->devtodev, + BUSWRTORD(2) | BUSRDTOWR(2) | BUSRDTORD(1)); + write32(&ddr_publ_regs->ptr[0], + PRT_DLLLOCK(div_round_up(sdram_params->ddr_freq / MHz * 5120, 1000)) | PRT_DLLSRST(div_round_up(sdram_params->ddr_freq / MHz * 50, 1000)) | PRT_ITMSRST(8)); + write32(&ddr_publ_regs->ptr[1], + PRT_DINIT0(div_round_up(sdram_params->ddr_freq / MHz * 500000, 1000)) | PRT_DINIT1(div_round_up(sdram_params->ddr_freq / MHz * 400, 1000))); + write32(&ddr_publ_regs->ptr[2], + PRT_DINIT2(MIN(dinit2, 0x1ffff)) | PRT_DINIT3(div_round_up(sdram_params->ddr_freq / MHz * 1000, 1000))); switch (sdram_params->dramtype) { case LPDDR3: @@ -683,8 +671,8 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) DDRMD_CFG(DDRMD_LPDDR2_LPDDR3)); clrsetbits_le32(&ddr_publ_regs->dxccr, DQSNRES_MSK | DQSRES_MSK, DQSRES_CFG(4) | DQSNRES_CFG(0xc)); - i = TDQSCKMAX_VAL(readl(&ddr_publ_regs->dtpr[1])) - - TDQSCK_VAL(readl(&ddr_publ_regs->dtpr[1])); + i = TDQSCKMAX_VAL(read32(&ddr_publ_regs->dtpr[1])) + - TDQSCK_VAL(read32(&ddr_publ_regs->dtpr[1])); clrsetbits_le32(&ddr_publ_regs->dsgcr, DQSGE_MSK | DQSGX_MSK, DQSGE_CFG(i) | DQSGX_CFG(i)); break; @@ -713,7 +701,7 @@ static void phy_init(struct rk3288_ddr_publ_regs *ddr_publ_regs) setbits_le32(&ddr_publ_regs->pir, PIR_INIT | PIR_DLLSRST | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR); udelay(1); - while ((readl(&ddr_publ_regs->pgsr) & + while ((read32(&ddr_publ_regs->pgsr) & (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) != (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) ; @@ -722,9 +710,9 @@ static void phy_init(struct rk3288_ddr_publ_regs *ddr_publ_regs) static void send_command(struct rk3288_ddr_pctl_regs *ddr_pctl_regs, u32 rank, u32 cmd, u32 arg) { - writel((START_CMD | (rank << 20) | arg | cmd), &ddr_pctl_regs->mcmd); + write32(&ddr_pctl_regs->mcmd, (START_CMD | (rank << 20) | arg | cmd)); udelay(1); - while (readl(&ddr_pctl_regs->mcmd) & START_CMD) + while (read32(&ddr_pctl_regs->mcmd) & START_CMD) ; } @@ -736,7 +724,7 @@ static void memory_init(struct rk3288_ddr_publ_regs *ddr_publ_regs, | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC | (dramtype == DDR3 ? PIR_DRAMRST : 0))); udelay(1); - while ((readl(&ddr_publ_regs->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) + while ((read32(&ddr_publ_regs->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) != (PGSR_IDONE | PGSR_DLDONE)) ; } @@ -747,16 +735,16 @@ static void move_to_config_state(struct rk3288_ddr_publ_regs *ddr_publ_regs, unsigned int state; while (1) { - state = readl(&ddr_pctl_regs->stat) & PCTL_STAT_MSK; + state = read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK; switch (state) { case LOW_POWER: - writel(WAKEUP_STATE, &ddr_pctl_regs->sctl); - while ((readl(&ddr_pctl_regs->stat) & PCTL_STAT_MSK) + write32(&ddr_pctl_regs->sctl, WAKEUP_STATE); + while ((read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK) != ACCESS) ; /* wait DLL lock */ - while ((readl(&ddr_publ_regs->pgsr) & PGSR_DLDONE) + while ((read32(&ddr_publ_regs->pgsr) & PGSR_DLDONE) != PGSR_DLDONE) ; /* if at low power state,need wakeup first, @@ -765,8 +753,8 @@ static void move_to_config_state(struct rk3288_ddr_publ_regs *ddr_publ_regs, */ case ACCESS: case INIT_MEM: - writel(CFG_STATE, &ddr_pctl_regs->sctl); - while ((readl(&ddr_pctl_regs->stat) & PCTL_STAT_MSK) + write32(&ddr_pctl_regs->sctl, CFG_STATE); + while ((read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK) != CONFIG) ; break; @@ -786,8 +774,7 @@ static void set_bandwidth_ratio(u32 channel, u32 n) if (n == 1) { setbits_le32(&ddr_pctl_regs->ppcfg, 1); - writel(RK_SETBITS(1 << (8 + channel)), - &rk3288_grf->soc_con0); + write32(&rk3288_grf->soc_con0, RK_SETBITS(1 << (8 + channel))); setbits_le32(&msch_regs->ddrtiming, 1 << 31); /* Data Byte disable*/ clrbits_le32(&ddr_publ_regs->datx8[2].dxgcr, 1); @@ -799,8 +786,7 @@ static void set_bandwidth_ratio(u32 channel, u32 n) DXDLLCR_DLLDIS); } else { clrbits_le32(&ddr_pctl_regs->ppcfg, 1); - writel(RK_CLRBITS(1 << (8 + channel)), - &rk3288_grf->soc_con0); + write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << (8 + channel))); clrbits_le32(&msch_regs->ddrtiming, 1 << 31); /* Data Byte enable*/ setbits_le32(&ddr_publ_regs->datx8[2].dxgcr, 1); @@ -838,7 +824,7 @@ static int data_training(u32 channel, struct rk3288_ddr_pctl_regs *ddr_pctl_regs = rk3288_ddr_pctl[channel]; /* disable auto refresh */ - writel(0, &ddr_pctl_regs->trefi); + write32(&ddr_pctl_regs->trefi, 0); if (sdram_params->dramtype != LPDDR3) setbits_le32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1)); @@ -856,21 +842,21 @@ static int data_training(u32 channel, PIR_CLRSR); udelay(1); /* wait echo byte DTDONE */ - while ((readl(&ddr_publ_regs->datx8[0].dxgsr[0]) & rank) + while ((read32(&ddr_publ_regs->datx8[0].dxgsr[0]) & rank) != rank) ; - while ((readl(&ddr_publ_regs->datx8[1].dxgsr[0]) & rank) + while ((read32(&ddr_publ_regs->datx8[1].dxgsr[0]) & rank) != rank) ; - if (!(readl(&ddr_pctl_regs->ppcfg) & 1)) { - while ((readl(&ddr_publ_regs->datx8[2].dxgsr[0]) + if (!(read32(&ddr_pctl_regs->ppcfg) & 1)) { + while ((read32(&ddr_publ_regs->datx8[2].dxgsr[0]) & rank) != rank) ; - while ((readl(&ddr_publ_regs->datx8[3].dxgsr[0]) + while ((read32(&ddr_publ_regs->datx8[3].dxgsr[0]) & rank) != rank) ; } - if (readl(&ddr_publ_regs->pgsr) & + if (read32(&ddr_publ_regs->pgsr) & (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) { ret = -1; break; @@ -884,7 +870,7 @@ static int data_training(u32 channel, clrbits_le32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1)); /* resume auto refresh */ - writel(sdram_params->pctl_timing.trefi, &ddr_pctl_regs->trefi); + write32(&ddr_pctl_regs->trefi, sdram_params->pctl_timing.trefi); return ret; } @@ -897,30 +883,30 @@ static void move_to_access_state(u32 chnum) unsigned int state; while (1) { - state = readl(&ddr_pctl_regs->stat) & PCTL_STAT_MSK; + state = read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK; switch (state) { case LOW_POWER: - if (LP_TRIG_VAL(readl(&ddr_pctl_regs->stat)) == 1) + if (LP_TRIG_VAL(read32(&ddr_pctl_regs->stat)) == 1) return; - writel(WAKEUP_STATE, &ddr_pctl_regs->sctl); - while ((readl(&ddr_pctl_regs->stat) & PCTL_STAT_MSK) + write32(&ddr_pctl_regs->sctl, WAKEUP_STATE); + while ((read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK) != ACCESS) ; /* wait DLL lock */ - while ((readl(&ddr_publ_regs->pgsr) & PGSR_DLDONE) + while ((read32(&ddr_publ_regs->pgsr) & PGSR_DLDONE) != PGSR_DLDONE) ; break; case INIT_MEM: - writel(CFG_STATE, &ddr_pctl_regs->sctl); - while ((readl(&ddr_pctl_regs->stat) & PCTL_STAT_MSK) + write32(&ddr_pctl_regs->sctl, CFG_STATE); + while ((read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK) != CONFIG) ; case CONFIG: - writel(GO_STATE, &ddr_pctl_regs->sctl); - while ((readl(&ddr_pctl_regs->stat) & PCTL_STAT_MSK) + write32(&ddr_pctl_regs->sctl, GO_STATE); + while ((read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK) == CONFIG) ; break; @@ -943,7 +929,7 @@ static void dram_cfg_rbc(u32 chnum, else clrbits_le32(&ddr_publ_regs->dcr, PDQ_MSK); - writel(sdram_params->ddrconfig, &msch_regs->ddrconf); + write32(&msch_regs->ddrconf, sdram_params->ddrconfig); } static void dram_all_config(const struct rk3288_sdram_params *sdram_params) @@ -968,9 +954,9 @@ static void dram_all_config(const struct rk3288_sdram_params *sdram_params) dram_cfg_rbc(channel, sdram_params); } - writel(sys_reg, &rk3288_pmu->sys_reg[2]); - writel(RK_CLRSETBITS(0x1F, sdram_params->stride), - &rk3288_sgrf->soc_con2); + write32(&rk3288_pmu->sys_reg[2], sys_reg); + write32(&rk3288_sgrf->soc_con2, + RK_CLRSETBITS(0x1F, sdram_params->stride)); } void sdram_init(const struct rk3288_sdram_params *sdram_params) @@ -1007,8 +993,8 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params) phy_init(ddr_publ_regs); - writel(POWER_UP_START, &ddr_pctl_regs->powctl); - while (!(readl(&ddr_pctl_regs->powstat) & POWER_UP_DONE)) + write32(&ddr_pctl_regs->powctl, POWER_UP_START); + while (!(read32(&ddr_pctl_regs->powstat) & POWER_UP_DONE)) ; memory_init(ddr_publ_regs, sdram_params->dramtype); @@ -1045,8 +1031,8 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params) /* DS=40ohm,ODT=155ohm */ zqcr = ZDEN(1) | PU_ONDIE(0x2) | PD_ONDIE(0x2) | PU_OUTPUT(0x19) | PD_OUTPUT(0x19); - writel(zqcr, &ddr_publ_regs->zq1cr[0]); - writel(zqcr, &ddr_publ_regs->zq0cr[0]); + write32(&ddr_publ_regs->zq1cr[0], zqcr); + write32(&ddr_publ_regs->zq0cr[0], zqcr); if (sdram_params->dramtype == LPDDR3) { /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ @@ -1056,11 +1042,11 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params) MRS_CMD, LPDDR2_MA(11) | sdram_params->odt ? LPDDR2_OP(3) : 0); if (channel == 0) { - writel(0, &ddr_pctl_regs->mrrcfg0); + write32(&ddr_pctl_regs->mrrcfg0, 0); send_command(ddr_pctl_regs, 1, MRR_CMD, LPDDR2_MA(0x8)); /* S8 */ - if ((readl(&ddr_pctl_regs->mrrstat0) & 0x3) + if ((read32(&ddr_pctl_regs->mrrstat0) & 0x3) != 3) die("SDRAM initialization failed!"); } @@ -1078,7 +1064,7 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params) if (sdram_params->dramtype == LPDDR3) { u32 i; - writel(0, &ddr_pctl_regs->mrrcfg0); + write32(&ddr_pctl_regs->mrrcfg0, 0); for (i = 0; i < 17; i++) send_command(ddr_pctl_regs, 1, MRR_CMD, LPDDR2_MA(i)); @@ -1098,7 +1084,7 @@ size_t sdram_size_mb(void) if (!size_mb) { - u32 sys_reg = readl(&rk3288_pmu->sys_reg[2]); + u32 sys_reg = read32(&rk3288_pmu->sys_reg[2]); u32 ch_num = SYS_REG_DEC_NUM_CH(sys_reg); for (ch = 0; ch < ch_num; ch++) { diff --git a/src/soc/rockchip/rk3288/software_i2c.c b/src/soc/rockchip/rk3288/software_i2c.c index a71fcd16bf..2df0a2857a 100644 --- a/src/soc/rockchip/rk3288/software_i2c.c +++ b/src/soc/rockchip/rk3288/software_i2c.c @@ -81,20 +81,20 @@ void software_i2c_attach(unsigned bus) clrbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); break; case 1: - writel(IOMUX_GPIO(IOMUX_I2C1), &rk3288_grf->iomux_i2c1); + write32(&rk3288_grf->iomux_i2c1, IOMUX_GPIO(IOMUX_I2C1)); break; case 2: - writel(IOMUX_GPIO(IOMUX_I2C2), &rk3288_grf->iomux_i2c2); + write32(&rk3288_grf->iomux_i2c2, IOMUX_GPIO(IOMUX_I2C2)); break; case 3: - writel(IOMUX_GPIO(IOMUX_I2C3), &rk3288_grf->iomux_i2c3); + write32(&rk3288_grf->iomux_i2c3, IOMUX_GPIO(IOMUX_I2C3)); break; case 4: - writel(IOMUX_GPIO(IOMUX_I2C4), &rk3288_grf->iomux_i2c4); + write32(&rk3288_grf->iomux_i2c4, IOMUX_GPIO(IOMUX_I2C4)); break; case 5: - writel(IOMUX_GPIO(IOMUX_I2C5SCL), &rk3288_grf->iomux_i2c5scl); - writel(IOMUX_GPIO(IOMUX_I2C5SDA), &rk3288_grf->iomux_i2c5sda); + write32(&rk3288_grf->iomux_i2c5scl, IOMUX_GPIO(IOMUX_I2C5SCL)); + write32(&rk3288_grf->iomux_i2c5sda, IOMUX_GPIO(IOMUX_I2C5SDA)); break; default: die("Unknown I2C bus number!"); @@ -116,20 +116,20 @@ void software_i2c_detach(unsigned bus) setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); break; case 1: - writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); + write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1); break; case 2: - writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2); + write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); break; case 3: - writel(IOMUX_I2C3, &rk3288_grf->iomux_i2c3); + write32(&rk3288_grf->iomux_i2c3, IOMUX_I2C3); break; case 4: - writel(IOMUX_I2C4, &rk3288_grf->iomux_i2c4); + write32(&rk3288_grf->iomux_i2c4, IOMUX_I2C4); break; case 5: - writel(IOMUX_I2C5SCL, &rk3288_grf->iomux_i2c5scl); - writel(IOMUX_I2C5SDA, &rk3288_grf->iomux_i2c5sda); + write32(&rk3288_grf->iomux_i2c5scl, IOMUX_I2C5SCL); + write32(&rk3288_grf->iomux_i2c5sda, IOMUX_I2C5SDA); break; default: die("Unknown I2C bus number!"); diff --git a/src/soc/rockchip/rk3288/spi.c b/src/soc/rockchip/rk3288/spi.c index fe4e377a08..aa70f3e0e5 100644 --- a/src/soc/rockchip/rk3288/spi.c +++ b/src/soc/rockchip/rk3288/spi.c @@ -87,9 +87,9 @@ static void spi_cs_deactivate(struct spi_slave *slave) static void rockchip_spi_enable_chip(struct rockchip_spi *regs, int enable) { if (enable == 1) - writel(1, ®s->spienr); + write32(®s->spienr, 1); else - writel(0, ®s->spienr); + write32(®s->spienr, 0); } static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz) @@ -100,7 +100,7 @@ static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz) clk_div = SPI_SRCCLK_HZ / hz; clk_div = (clk_div + 1) & 0xfffe; assert((clk_div - 1) * hz == SPI_SRCCLK_HZ); - writel(clk_div, ®s->baudr); + write32(®s->baudr, clk_div); } void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) @@ -139,11 +139,11 @@ void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) /* Frame Format */ ctrlr0 |= (SPI_FRF_SPI << SPI_FRF_OFFSET); - writel(ctrlr0, ®s->ctrlr0); + write32(®s->ctrlr0, ctrlr0); /* fifo depth */ - writel(SPI_FIFO_DEPTH / 2 - 1, ®s->txftlr); - writel(SPI_FIFO_DEPTH / 2 - 1, ®s->rxftlr); + write32(®s->txftlr, SPI_FIFO_DEPTH / 2 - 1); + write32(®s->rxftlr, SPI_FIFO_DEPTH / 2 - 1); } int spi_claim_bus(struct spi_slave *slave) @@ -163,7 +163,7 @@ static int rockchip_spi_wait_till_not_busy(struct rockchip_spi *regs) stopwatch_init_usecs_expire(&sw, SPI_TIMEOUT_US); do { - if (!(readl(®s->sr) & SR_BUSY)) + if (!(read32(®s->sr) & SR_BUSY)) return 0; } while (!stopwatch_expired(&sw)); printk(BIOS_DEBUG, @@ -207,18 +207,18 @@ static int do_xfer(struct spi_slave *slave, const void *dout, min_xfer = MIN(*bytes_in, *bytes_out); while (min_xfer) { - uint32_t sr = readl(®s->sr); + uint32_t sr = read32(®s->sr); int xferred = 0; /* in either (or both) directions */ if (*bytes_out && !(sr & SR_TF_FULL)) { - writel(*out_buf, ®s->txdr); + write32(®s->txdr, *out_buf); out_buf++; *bytes_out -= 1; xferred = 1; } if (*bytes_in && !(sr & SR_RF_EMPT)) { - *in_buf = readl(®s->rxdr) & 0xff; + *in_buf = read32(®s->rxdr) & 0xff; in_buf++; *bytes_in -= 1; xferred = 1; @@ -266,7 +266,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, set_transfer_mode(regs, bytes_out, bytes_in); /* MAX() in case either counter is 0 */ - writel(MAX(in_now, out_now) - 1, ®s->ctrlr1); + write32(®s->ctrlr1, MAX(in_now, out_now) - 1); rockchip_spi_enable_chip(regs, 1); diff --git a/src/soc/rockchip/rk3288/timer.c b/src/soc/rockchip/rk3288/timer.c index d373f7a39c..07be49bfe9 100644 --- a/src/soc/rockchip/rk3288/timer.c +++ b/src/soc/rockchip/rk3288/timer.c @@ -41,7 +41,7 @@ void timer_monotonic_get(struct mono_time *mt) void init_timer(void) { - writel(TIMER_LOAD_VAL, &timer7_ptr->timer_load_count0); - writel(TIMER_LOAD_VAL, &timer7_ptr->timer_load_count1); - writel(1, &timer7_ptr->timer_ctrl_reg); + write32(&timer7_ptr->timer_load_count0, TIMER_LOAD_VAL); + write32(&timer7_ptr->timer_load_count1, TIMER_LOAD_VAL); + write32(&timer7_ptr->timer_ctrl_reg, 1); } diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c index a2d6ec499a..cada767889 100644 --- a/src/soc/rockchip/rk3288/tsadc.c +++ b/src/soc/rockchip/rk3288/tsadc.c @@ -94,13 +94,13 @@ void tsadc_init(void) TSHUT_CRU_EN_SRC2 | TSHUT_CRU_EN_SRC1 | TSHUT_GPIO_EN_SRC2 | TSHUT_GPIO_EN_SRC1); - writel(AUTO_PERIOD, &rk3288_tsadc->auto_period); - writel(AUTO_DEBOUNCE, &rk3288_tsadc->hight_int_debounce); - writel(AUTO_PERIOD_HT, &rk3288_tsadc->auto_period_ht); - writel(AUTO_DEBOUNCE_HT, &rk3288_tsadc->hight_tshut_debounce); + write32(&rk3288_tsadc->auto_period, AUTO_PERIOD); + write32(&rk3288_tsadc->hight_int_debounce, AUTO_DEBOUNCE); + write32(&rk3288_tsadc->auto_period_ht, AUTO_PERIOD_HT); + write32(&rk3288_tsadc->hight_tshut_debounce, AUTO_DEBOUNCE_HT); - writel(TSADC_SHUT_VALUE, &rk3288_tsadc->comp1_shut); - writel(TSADC_SHUT_VALUE, &rk3288_tsadc->comp2_shut); + write32(&rk3288_tsadc->comp1_shut, TSADC_SHUT_VALUE); + write32(&rk3288_tsadc->comp2_shut, TSADC_SHUT_VALUE); /* polarity set to high,channel1 for cpu,channel2 for gpu */ setbits_le32(&rk3288_tsadc->auto_con, TSHUT_POL_HIGH | SRC2_EN | diff --git a/src/soc/rockchip/rk3288/uart.c b/src/soc/rockchip/rk3288/uart.c index 7685ff9a41..8ba1fdee73 100644 --- a/src/soc/rockchip/rk3288/uart.c +++ b/src/soc/rockchip/rk3288/uart.c @@ -92,43 +92,42 @@ static void rk3288_uart_init(void) rk3288_uart_tx_flush(); // Disable interrupts. - writel(0, &uart_ptr->ier); + write32(&uart_ptr->ier, 0); // Force DTR and RTS to high. - writel(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr); + write32(&uart_ptr->mcr, UART8250_MCR_DTR | UART8250_MCR_RTS); // Set line configuration, access divisor latches. - writel(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr); + write32(&uart_ptr->lcr, UART8250_LCR_DLAB | line_config); // Set the divisor. - writel(divisor & 0xff, &uart_ptr->dll); - writel((divisor >> 8) & 0xff, &uart_ptr->dlm); + write32(&uart_ptr->dll, divisor & 0xff); + write32(&uart_ptr->dlm, (divisor >> 8) & 0xff); // Hide the divisor latches. - writel(line_config, &uart_ptr->lcr); + write32(&uart_ptr->lcr, line_config); // Enable FIFOs, and clear receive and transmit. - writel(UART8250_FCR_FIFO_EN | - UART8250_FCR_CLEAR_RCVR | - UART8250_FCR_CLEAR_XMIT, &uart_ptr->fcr); + write32(&uart_ptr->fcr, + UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT); } static void rk3288_uart_tx_byte(unsigned char data) { - while (!(readl(&uart_ptr->lsr) & UART8250_LSR_THRE)); - writel(data, &uart_ptr->thr); + while (!(read32(&uart_ptr->lsr) & UART8250_LSR_THRE)); + write32(&uart_ptr->thr, data); } static void rk3288_uart_tx_flush(void) { - while (!(readl(&uart_ptr->lsr) & UART8250_LSR_TEMT)); + while (!(read32(&uart_ptr->lsr) & UART8250_LSR_TEMT)); } static unsigned char rk3288_uart_rx_byte(void) { if (!rk3288_uart_tst_byte()) return 0; - return readl(&uart_ptr->rbr); + return read32(&uart_ptr->rbr); } static int rk3288_uart_tst_byte(void) { - return (readl(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR; + return (read32(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR; } diff --git a/src/soc/rockchip/rk3288/vop.c b/src/soc/rockchip/rk3288/vop.c index 378e6b8e90..915d452d4b 100644 --- a/src/soc/rockchip/rk3288/vop.c +++ b/src/soc/rockchip/rk3288/vop.c @@ -48,16 +48,14 @@ void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid) u32 xpos = 0, ypos = 0; struct rk3288_vop_regs *preg = vop_regs[vop_id]; - writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1), - &preg->win0_act_info); + write32(&preg->win0_act_info, + V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1)); - writel(V_DSP_XST(xpos + hsync_len + hback_porch) | - V_DSP_YST(ypos + vsync_len + vback_porch), - &preg->win0_dsp_st); + write32(&preg->win0_dsp_st, + V_DSP_XST(xpos + hsync_len + hback_porch) | V_DSP_YST(ypos + vsync_len + vback_porch)); - writel(V_DSP_WIDTH(hactive - 1) | - V_DSP_HEIGHT(vactive - 1), - &preg->win0_dsp_info); + write32(&preg->win0_dsp_info, + V_DSP_WIDTH(hactive - 1) | V_DSP_HEIGHT(vactive - 1)); clrsetbits_le32(&preg->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR, V_WIN0_KEY_EN(0) | @@ -66,19 +64,16 @@ void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid) switch (edid->framebuffer_bits_per_pixel) { case 16: rgb_mode = RGB565; - writel(V_RGB565_VIRWIDTH(hactive), - &preg->win0_vir); + write32(&preg->win0_vir, V_RGB565_VIRWIDTH(hactive)); break; case 24: rgb_mode = RGB888; - writel(V_RGB888_VIRWIDTH(hactive), - &preg->win0_vir); + write32(&preg->win0_vir, V_RGB888_VIRWIDTH(hactive)); break; case 32: default: rgb_mode = ARGB8888; - writel(V_ARGB888_VIRWIDTH(hactive), - &preg->win0_vir); + write32(&preg->win0_vir, V_ARGB888_VIRWIDTH(hactive)); break; } @@ -96,9 +91,9 @@ void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid) V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) | V_WIN0_EN(1)); - writel(fbbase, &preg->win0_yrgb_mst); + write32(&preg->win0_yrgb_mst, fbbase); - writel(0x01, &preg->reg_cfg_done); /* enable reg config */ + write32(&preg->reg_cfg_done, 0x01); /* enable reg config */ } void rkvop_mode_set(u32 vop_id, const struct edid *edid) @@ -116,29 +111,23 @@ void rkvop_mode_set(u32 vop_id, const struct edid *edid) clrsetbits_le32(&preg->sys_ctrl, M_ALL_OUT_EN, V_EDP_OUT_EN(1)); clrsetbits_le32(&preg->dsp_ctrl0, M_DSP_OUT_MODE, V_DSP_OUT_MODE(15)); - writel(V_HSYNC(hsync_len) | - V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch), - &preg->dsp_htotal_hs_end); + write32(&preg->dsp_htotal_hs_end, + V_HSYNC(hsync_len) | V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch)); - writel(V_HEAP(hsync_len + hback_porch + hactive) | - V_HASP(hsync_len + hback_porch), - &preg->dsp_hact_st_end); + write32(&preg->dsp_hact_st_end, + V_HEAP(hsync_len + hback_porch + hactive) | V_HASP(hsync_len + hback_porch)); - writel(V_VSYNC(vsync_len) | - V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch), - &preg->dsp_vtotal_vs_end); + write32(&preg->dsp_vtotal_vs_end, + V_VSYNC(vsync_len) | V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch)); - writel(V_VAEP(vsync_len + vback_porch + vactive)| - V_VASP(vsync_len + vback_porch), - &preg->dsp_vact_st_end); + write32(&preg->dsp_vact_st_end, + V_VAEP(vsync_len + vback_porch + vactive) | V_VASP(vsync_len + vback_porch)); - writel(V_HEAP(hsync_len + hback_porch + hactive) | - V_HASP(hsync_len + hback_porch), - &preg->post_dsp_hact_info); + write32(&preg->post_dsp_hact_info, + V_HEAP(hsync_len + hback_porch + hactive) | V_HASP(hsync_len + hback_porch)); - writel(V_VAEP(vsync_len + vback_porch + vactive)| - V_VASP(vsync_len + vback_porch), - &preg->post_dsp_vact_info); + write32(&preg->post_dsp_vact_info, + V_VAEP(vsync_len + vback_porch + vactive) | V_VASP(vsync_len + vback_porch)); - writel(0x01, &preg->reg_cfg_done); /* enable reg config */ + write32(&preg->reg_cfg_done, 0x01); /* enable reg config */ } diff --git a/src/soc/samsung/exynos5250/clock.c b/src/soc/samsung/exynos5250/clock.c index 0986f8b9bd..89001ecf14 100644 --- a/src/soc/samsung/exynos5250/clock.c +++ b/src/soc/samsung/exynos5250/clock.c @@ -178,21 +178,21 @@ unsigned long get_pll_clk(int pllreg) switch (pllreg) { case APLL: - r = readl(&exynos_clock->apll_con0); + r = read32(&exynos_clock->apll_con0); break; case BPLL: - r = readl(&exynos_clock->bpll_con0); + r = read32(&exynos_clock->bpll_con0); break; case MPLL: - r = readl(&exynos_clock->mpll_con0); + r = read32(&exynos_clock->mpll_con0); break; case EPLL: - r = readl(&exynos_clock->epll_con0); - k = readl(&exynos_clock->epll_con1); + r = read32(&exynos_clock->epll_con0); + k = read32(&exynos_clock->epll_con1); break; case VPLL: - r = readl(&exynos_clock->vpll_con0); - k = readl(&exynos_clock->vpll_con1); + r = read32(&exynos_clock->vpll_con0); + k = read32(&exynos_clock->vpll_con1); break; default: printk(BIOS_DEBUG, "Unsupported PLL (%d)\n", pllreg); @@ -246,41 +246,41 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) case PERIPH_ID_UART1: case PERIPH_ID_UART2: case PERIPH_ID_UART3: - src = readl(&exynos_clock->src_peric0); - div = readl(&exynos_clock->div_peric0); + src = read32(&exynos_clock->src_peric0); + div = read32(&exynos_clock->div_peric0); break; case PERIPH_ID_PWM0: case PERIPH_ID_PWM1: case PERIPH_ID_PWM2: case PERIPH_ID_PWM3: case PERIPH_ID_PWM4: - src = readl(&exynos_clock->src_peric0); - div = readl(&exynos_clock->div_peric3); + src = read32(&exynos_clock->src_peric0); + div = read32(&exynos_clock->div_peric3); break; case PERIPH_ID_SPI0: case PERIPH_ID_SPI1: - src = readl(&exynos_clock->src_peric1); - div = readl(&exynos_clock->div_peric1); + src = read32(&exynos_clock->src_peric1); + div = read32(&exynos_clock->div_peric1); break; case PERIPH_ID_SPI2: - src = readl(&exynos_clock->src_peric1); - div = readl(&exynos_clock->div_peric2); + src = read32(&exynos_clock->src_peric1); + div = read32(&exynos_clock->div_peric2); break; case PERIPH_ID_SPI3: case PERIPH_ID_SPI4: - src = readl(&exynos_clock->sclk_src_isp); - div = readl(&exynos_clock->sclk_div_isp); + src = read32(&exynos_clock->sclk_src_isp); + div = read32(&exynos_clock->sclk_div_isp); break; case PERIPH_ID_SATA: - src = readl(&exynos_clock->src_fsys); - div = readl(&exynos_clock->div_fsys0); + src = read32(&exynos_clock->src_fsys); + div = read32(&exynos_clock->div_fsys0); break; case PERIPH_ID_SDMMC0: case PERIPH_ID_SDMMC1: case PERIPH_ID_SDMMC2: case PERIPH_ID_SDMMC3: - src = readl(&exynos_clock->src_fsys); - div = readl(&exynos_clock->div_fsys1); + src = read32(&exynos_clock->src_fsys); + div = read32(&exynos_clock->div_fsys1); break; case PERIPH_ID_I2C0: case PERIPH_ID_I2C1: @@ -291,9 +291,9 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) case PERIPH_ID_I2C6: case PERIPH_ID_I2C7: sclk = get_pll_clk(MPLL); - sub_div = ((readl(&exynos_clock->div_top1) + sub_div = ((read32(&exynos_clock->div_top1) >> bit_info->div_bit) & 0x7) + 1; - div = ((readl(&exynos_clock->div_top0) + div = ((read32(&exynos_clock->div_top0) >> bit_info->prediv_bit) & 0x7) + 1; return (sclk / sub_div) / div; default: @@ -337,7 +337,7 @@ unsigned long get_arm_clk(void) unsigned int arm_ratio; unsigned int arm2_ratio; - div = readl(&exynos_clock->div_cpu0); + div = read32(&exynos_clock->div_cpu0); /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */ arm_ratio = (div >> 0) & 0x7; @@ -383,10 +383,10 @@ void set_mmc_clk(int dev_index, unsigned int div) dev_index -= 2; } - val = readl(addr); + val = read32(addr); val &= ~(0xff << ((dev_index << 4) + 8)); val |= (div & 0xff) << ((dev_index << 4) + 8); - writel(val, addr); + write32(addr, val); } void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) @@ -582,10 +582,10 @@ int clock_set_mshci(enum periph_id peripheral) printk(BIOS_DEBUG, "invalid peripheral\n"); return -1; } - tmp = readl(addr) & ~0xff0f; + tmp = read32(addr) & ~0xff0f; for (i = 0; i <= 0xf; i++) { if ((clock / (i + 1)) <= 400) { - writel(tmp | i << 0, addr); + write32(addr, tmp | i << 0); break; } } @@ -599,7 +599,7 @@ int clock_epll_set_rate(unsigned long rate) unsigned int lockcnt; struct stopwatch sw; - epll_con = readl(&exynos_clock->epll_con0); + epll_con = read32(&exynos_clock->epll_con0); epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK << EPLL_CON0_LOCK_DET_EN_SHIFT) | EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT | @@ -627,13 +627,13 @@ int clock_epll_set_rate(unsigned long rate) */ lockcnt = 3000 * epll_div[i].p_div; - writel(lockcnt, &exynos_clock->epll_lock); - writel(epll_con, &exynos_clock->epll_con0); - writel(epll_con_k, &exynos_clock->epll_con1); + write32(&exynos_clock->epll_lock, lockcnt); + write32(&exynos_clock->epll_con0, epll_con); + write32(&exynos_clock->epll_con1, epll_con_k); stopwatch_init_msecs_expire(&sw, TIMEOUT_EPLL_LOCK); - while (!(readl(&exynos_clock->epll_con0) & + while (!(read32(&exynos_clock->epll_con0) & (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) { if (stopwatch_expired(&sw)) { printk(BIOS_DEBUG, diff --git a/src/soc/samsung/exynos5250/clock_init.c b/src/soc/samsung/exynos5250/clock_init.c index 409230180b..9cdd729f57 100644 --- a/src/soc/samsung/exynos5250/clock_init.c +++ b/src/soc/samsung/exynos5250/clock_init.c @@ -35,12 +35,12 @@ void system_clock_init(struct mem_timings *mem, clrbits_le32(&exynos_clock->src_cpu, MUX_APLL_SEL_MASK); do { - val = readl(&exynos_clock->mux_stat_cpu); + val = read32(&exynos_clock->mux_stat_cpu); } while ((val | MUX_APLL_SEL_MASK) != val); clrbits_le32(&exynos_clock->src_core1, MUX_MPLL_SEL_MASK); do { - val = readl(&exynos_clock->mux_stat_core1); + val = read32(&exynos_clock->mux_stat_core1); } while ((val | MUX_MPLL_SEL_MASK) != val); clrbits_le32(&exynos_clock->src_top2, MUX_CPLL_SEL_MASK); @@ -50,34 +50,34 @@ void system_clock_init(struct mem_timings *mem, tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK | MUX_GPLL_SEL_MASK; do { - val = readl(&exynos_clock->mux_stat_top2); + val = read32(&exynos_clock->mux_stat_top2); } while ((val | tmp) != val); clrbits_le32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK); do { - val = readl(&exynos_clock->mux_stat_cdrex); + val = read32(&exynos_clock->mux_stat_cdrex); } while ((val | MUX_BPLL_SEL_MASK) != val); /* PLL locktime */ - writel(APLL_LOCK_VAL, &exynos_clock->apll_lock); + write32(&exynos_clock->apll_lock, APLL_LOCK_VAL); - writel(MPLL_LOCK_VAL, &exynos_clock->mpll_lock); + write32(&exynos_clock->mpll_lock, MPLL_LOCK_VAL); - writel(BPLL_LOCK_VAL, &exynos_clock->bpll_lock); + write32(&exynos_clock->bpll_lock, BPLL_LOCK_VAL); - writel(CPLL_LOCK_VAL, &exynos_clock->cpll_lock); + write32(&exynos_clock->cpll_lock, CPLL_LOCK_VAL); - writel(GPLL_LOCK_VAL, &exynos_clock->gpll_lock); + write32(&exynos_clock->gpll_lock, GPLL_LOCK_VAL); - writel(EPLL_LOCK_VAL, &exynos_clock->epll_lock); + write32(&exynos_clock->epll_lock, EPLL_LOCK_VAL); - writel(VPLL_LOCK_VAL, &exynos_clock->vpll_lock); + write32(&exynos_clock->vpll_lock, VPLL_LOCK_VAL); - writel(CLK_REG_DISABLE, &exynos_clock->pll_div2_sel); + write32(&exynos_clock->pll_div2_sel, CLK_REG_DISABLE); - writel(MUX_HPM_SEL_MASK, &exynos_clock->src_cpu); + write32(&exynos_clock->src_cpu, MUX_HPM_SEL_MASK); do { - val = readl(&exynos_clock->mux_stat_cpu); + val = read32(&exynos_clock->mux_stat_cpu); } while ((val | HPM_SEL_SCLK_MPLL) != val); val = arm_clk_ratio->arm2_ratio << 28 @@ -88,35 +88,35 @@ void system_clock_init(struct mem_timings *mem, | arm_clk_ratio->acp_ratio << 8 | arm_clk_ratio->cpud_ratio << 4 | arm_clk_ratio->arm_ratio; - writel(val, &exynos_clock->div_cpu0); + write32(&exynos_clock->div_cpu0, val); do { - val = readl(&exynos_clock->div_stat_cpu0); + val = read32(&exynos_clock->div_stat_cpu0); } while (0 != val); - writel(CLK_DIV_CPU1_VAL, &exynos_clock->div_cpu1); + write32(&exynos_clock->div_cpu1, CLK_DIV_CPU1_VAL); do { - val = readl(&exynos_clock->div_stat_cpu1); + val = read32(&exynos_clock->div_stat_cpu1); } while (0 != val); /* switch A15 clock source to OSC clock before changing APLL */ clrbits_le32(&exynos_clock->src_cpu, APLL_FOUT); /* Set APLL */ - writel(APLL_CON1_VAL, &exynos_clock->apll_con1); + write32(&exynos_clock->apll_con1, APLL_CON1_VAL); val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv, arm_clk_ratio->apll_sdiv); - writel(val, &exynos_clock->apll_con0); - while ((readl(&exynos_clock->apll_con0) & APLL_CON0_LOCKED) == 0) + write32(&exynos_clock->apll_con0, val); + while ((read32(&exynos_clock->apll_con0) & APLL_CON0_LOCKED) == 0) ; /* now it is safe to switch to APLL */ setbits_le32(&exynos_clock->src_cpu, APLL_FOUT); /* Set MPLL */ - writel(MPLL_CON1_VAL, &exynos_clock->mpll_con1); + write32(&exynos_clock->mpll_con1, MPLL_CON1_VAL); val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); - writel(val, &exynos_clock->mpll_con0); - while ((readl(&exynos_clock->mpll_con0) & MPLL_CON0_LOCKED) == 0) + write32(&exynos_clock->mpll_con0, val); + while ((read32(&exynos_clock->mpll_con0) & MPLL_CON0_LOCKED) == 0) ; /* @@ -127,159 +127,159 @@ void system_clock_init(struct mem_timings *mem, /* Set BPLL */ if (mem->use_bpll) { - writel(BPLL_CON1_VAL, &exynos_clock->bpll_con1); + write32(&exynos_clock->bpll_con1, BPLL_CON1_VAL); val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv); - writel(val, &exynos_clock->bpll_con0); - while ((readl(&exynos_clock->bpll_con0) & BPLL_CON0_LOCKED) == 0) + write32(&exynos_clock->bpll_con0, val); + while ((read32(&exynos_clock->bpll_con0) & BPLL_CON0_LOCKED) == 0) ; setbits_le32(&exynos_clock->pll_div2_sel, MUX_BPLL_FOUT_SEL); } /* Set CPLL */ - writel(CPLL_CON1_VAL, &exynos_clock->cpll_con1); + write32(&exynos_clock->cpll_con1, CPLL_CON1_VAL); val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); - writel(val, &exynos_clock->cpll_con0); - while ((readl(&exynos_clock->cpll_con0) & CPLL_CON0_LOCKED) == 0) + write32(&exynos_clock->cpll_con0, val); + while ((read32(&exynos_clock->cpll_con0) & CPLL_CON0_LOCKED) == 0) ; /* Set GPLL */ - writel(GPLL_CON1_VAL, &exynos_clock->gpll_con1); + write32(&exynos_clock->gpll_con1, GPLL_CON1_VAL); val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv); - writel(val, &exynos_clock->gpll_con0); - while ((readl(&exynos_clock->gpll_con0) & GPLL_CON0_LOCKED) == 0) + write32(&exynos_clock->gpll_con0, val); + while ((read32(&exynos_clock->gpll_con0) & GPLL_CON0_LOCKED) == 0) ; /* Set EPLL */ - writel(EPLL_CON2_VAL, &exynos_clock->epll_con2); - writel(EPLL_CON1_VAL, &exynos_clock->epll_con1); + write32(&exynos_clock->epll_con2, EPLL_CON2_VAL); + write32(&exynos_clock->epll_con1, EPLL_CON1_VAL); val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); - writel(val, &exynos_clock->epll_con0); - while ((readl(&exynos_clock->epll_con0) & EPLL_CON0_LOCKED) == 0) + write32(&exynos_clock->epll_con0, val); + while ((read32(&exynos_clock->epll_con0) & EPLL_CON0_LOCKED) == 0) ; /* Set VPLL */ - writel(VPLL_CON2_VAL, &exynos_clock->vpll_con2); - writel(VPLL_CON1_VAL, &exynos_clock->vpll_con1); + write32(&exynos_clock->vpll_con2, VPLL_CON2_VAL); + write32(&exynos_clock->vpll_con1, VPLL_CON1_VAL); val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); - writel(val, &exynos_clock->vpll_con0); - while ((readl(&exynos_clock->vpll_con0) & VPLL_CON0_LOCKED) == 0) + write32(&exynos_clock->vpll_con0, val); + while ((read32(&exynos_clock->vpll_con0) & VPLL_CON0_LOCKED) == 0) ; - writel(CLK_SRC_CORE0_VAL, &exynos_clock->src_core0); - writel(CLK_DIV_CORE0_VAL, &exynos_clock->div_core0); - while (readl(&exynos_clock->div_stat_core0) != 0) + write32(&exynos_clock->src_core0, CLK_SRC_CORE0_VAL); + write32(&exynos_clock->div_core0, CLK_DIV_CORE0_VAL); + while (read32(&exynos_clock->div_stat_core0) != 0) ; - writel(CLK_DIV_CORE1_VAL, &exynos_clock->div_core1); - while (readl(&exynos_clock->div_stat_core1) != 0) + write32(&exynos_clock->div_core1, CLK_DIV_CORE1_VAL); + while (read32(&exynos_clock->div_stat_core1) != 0) ; - writel(CLK_DIV_SYSRGT_VAL, &exynos_clock->div_sysrgt); - while (readl(&exynos_clock->div_stat_sysrgt) != 0) + write32(&exynos_clock->div_sysrgt, CLK_DIV_SYSRGT_VAL); + while (read32(&exynos_clock->div_stat_sysrgt) != 0) ; - writel(CLK_DIV_ACP_VAL, &exynos_clock->div_acp); - while (readl(&exynos_clock->div_stat_acp) != 0) + write32(&exynos_clock->div_acp, CLK_DIV_ACP_VAL); + while (read32(&exynos_clock->div_stat_acp) != 0) ; - writel(CLK_DIV_SYSLFT_VAL, &exynos_clock->div_syslft); - while (readl(&exynos_clock->div_stat_syslft) != 0) + write32(&exynos_clock->div_syslft, CLK_DIV_SYSLFT_VAL); + while (read32(&exynos_clock->div_stat_syslft) != 0) ; - writel(CLK_SRC_TOP0_VAL, &exynos_clock->src_top0); - writel(CLK_SRC_TOP1_VAL, &exynos_clock->src_top1); - writel(TOP2_VAL, &exynos_clock->src_top2); - writel(CLK_SRC_TOP3_VAL, &exynos_clock->src_top3); + write32(&exynos_clock->src_top0, CLK_SRC_TOP0_VAL); + write32(&exynos_clock->src_top1, CLK_SRC_TOP1_VAL); + write32(&exynos_clock->src_top2, TOP2_VAL); + write32(&exynos_clock->src_top3, CLK_SRC_TOP3_VAL); - writel(CLK_DIV_TOP0_VAL, &exynos_clock->div_top0); - while (readl(&exynos_clock->div_stat_top0)) + write32(&exynos_clock->div_top0, CLK_DIV_TOP0_VAL); + while (read32(&exynos_clock->div_stat_top0)) ; - writel(CLK_DIV_TOP1_VAL, &exynos_clock->div_top1); - while (readl(&exynos_clock->div_stat_top1)) + write32(&exynos_clock->div_top1, CLK_DIV_TOP1_VAL); + while (read32(&exynos_clock->div_stat_top1)) ; - writel(CLK_SRC_LEX_VAL, &exynos_clock->src_lex); + write32(&exynos_clock->src_lex, CLK_SRC_LEX_VAL); while (1) { - val = readl(&exynos_clock->mux_stat_lex); + val = read32(&exynos_clock->mux_stat_lex); if (val == (val | 1)) break; } - writel(CLK_DIV_LEX_VAL, &exynos_clock->div_lex); - while (readl(&exynos_clock->div_stat_lex)) + write32(&exynos_clock->div_lex, CLK_DIV_LEX_VAL); + while (read32(&exynos_clock->div_stat_lex)) ; - writel(CLK_DIV_R0X_VAL, &exynos_clock->div_r0x); - while (readl(&exynos_clock->div_stat_r0x)) + write32(&exynos_clock->div_r0x, CLK_DIV_R0X_VAL); + while (read32(&exynos_clock->div_stat_r0x)) ; - writel(CLK_DIV_R0X_VAL, &exynos_clock->div_r0x); - while (readl(&exynos_clock->div_stat_r0x)) + write32(&exynos_clock->div_r0x, CLK_DIV_R0X_VAL); + while (read32(&exynos_clock->div_stat_r0x)) ; - writel(CLK_DIV_R1X_VAL, &exynos_clock->div_r1x); - while (readl(&exynos_clock->div_stat_r1x)) + write32(&exynos_clock->div_r1x, CLK_DIV_R1X_VAL); + while (read32(&exynos_clock->div_stat_r1x)) ; if (mem->use_bpll) { - writel(MUX_BPLL_SEL_MASK | MUX_MCLK_CDREX_SEL | - MUX_MCLK_DPHY_SEL, &exynos_clock->src_cdrex); + write32(&exynos_clock->src_cdrex, + MUX_BPLL_SEL_MASK | MUX_MCLK_CDREX_SEL | MUX_MCLK_DPHY_SEL); } else { - writel(CLK_REG_DISABLE, &exynos_clock->src_cdrex); + write32(&exynos_clock->src_cdrex, CLK_REG_DISABLE); } - writel(CLK_DIV_CDREX_VAL, &exynos_clock->div_cdrex); - while (readl(&exynos_clock->div_stat_cdrex)) + write32(&exynos_clock->div_cdrex, CLK_DIV_CDREX_VAL); + while (read32(&exynos_clock->div_stat_cdrex)) ; - val = readl(&exynos_clock->src_cpu); + val = read32(&exynos_clock->src_cpu); val |= CLK_SRC_CPU_VAL; - writel(val, &exynos_clock->src_cpu); + write32(&exynos_clock->src_cpu, val); - val = readl(&exynos_clock->src_top2); + val = read32(&exynos_clock->src_top2); val |= CLK_SRC_TOP2_VAL; - writel(val, &exynos_clock->src_top2); + write32(&exynos_clock->src_top2, val); - val = readl(&exynos_clock->src_core1); + val = read32(&exynos_clock->src_core1); val |= CLK_SRC_CORE1_VAL; - writel(val, &exynos_clock->src_core1); + write32(&exynos_clock->src_core1, val); - writel(CLK_SRC_FSYS0_VAL, &exynos_clock->src_fsys); - writel(CLK_DIV_FSYS0_VAL, &exynos_clock->div_fsys0); - while (readl(&exynos_clock->div_stat_fsys0)) + write32(&exynos_clock->src_fsys, CLK_SRC_FSYS0_VAL); + write32(&exynos_clock->div_fsys0, CLK_DIV_FSYS0_VAL); + while (read32(&exynos_clock->div_stat_fsys0)) ; - writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_cpu); - writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_core); - writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_acp); - writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_top); - writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_lex); - writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_r0x); - writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_r1x); - writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_cdrex); - - writel(CLK_SRC_PERIC0_VAL, &exynos_clock->src_peric0); - writel(CLK_DIV_PERIC0_VAL, &exynos_clock->div_peric0); - - writel(CLK_SRC_PERIC1_VAL, &exynos_clock->src_peric1); - writel(CLK_DIV_PERIC1_VAL, &exynos_clock->div_peric1); - writel(CLK_DIV_PERIC2_VAL, &exynos_clock->div_peric2); - writel(SCLK_SRC_ISP_VAL, &exynos_clock->sclk_src_isp); - writel(SCLK_DIV_ISP_VAL, &exynos_clock->sclk_div_isp); - writel(CLK_DIV_ISP0_VAL, &exynos_clock->div_isp0); - writel(CLK_DIV_ISP1_VAL, &exynos_clock->div_isp1); - writel(CLK_DIV_ISP2_VAL, &exynos_clock->div_isp2); + write32(&exynos_clock->clkout_cmu_cpu, CLK_REG_DISABLE); + write32(&exynos_clock->clkout_cmu_core, CLK_REG_DISABLE); + write32(&exynos_clock->clkout_cmu_acp, CLK_REG_DISABLE); + write32(&exynos_clock->clkout_cmu_top, CLK_REG_DISABLE); + write32(&exynos_clock->clkout_cmu_lex, CLK_REG_DISABLE); + write32(&exynos_clock->clkout_cmu_r0x, CLK_REG_DISABLE); + write32(&exynos_clock->clkout_cmu_r1x, CLK_REG_DISABLE); + write32(&exynos_clock->clkout_cmu_cdrex, CLK_REG_DISABLE); + + write32(&exynos_clock->src_peric0, CLK_SRC_PERIC0_VAL); + write32(&exynos_clock->div_peric0, CLK_DIV_PERIC0_VAL); + + write32(&exynos_clock->src_peric1, CLK_SRC_PERIC1_VAL); + write32(&exynos_clock->div_peric1, CLK_DIV_PERIC1_VAL); + write32(&exynos_clock->div_peric2, CLK_DIV_PERIC2_VAL); + write32(&exynos_clock->sclk_src_isp, SCLK_SRC_ISP_VAL); + write32(&exynos_clock->sclk_div_isp, SCLK_DIV_ISP_VAL); + write32(&exynos_clock->div_isp0, CLK_DIV_ISP0_VAL); + write32(&exynos_clock->div_isp1, CLK_DIV_ISP1_VAL); + write32(&exynos_clock->div_isp2, CLK_DIV_ISP2_VAL); /* FIMD1 SRC CLK SELECTION */ - writel(CLK_SRC_DISP1_0_VAL, &exynos_clock->src_disp1_0); + write32(&exynos_clock->src_disp1_0, CLK_SRC_DISP1_0_VAL); val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET; - writel(val, &exynos_clock->div_fsys2); + write32(&exynos_clock->div_fsys2, val); } void clock_gate(void) diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index cff1466a64..d9f001a57f 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -38,7 +38,7 @@ static unsigned int cpu_rev; static void set_cpu_id(void) { - cpu_id = readl((void *)EXYNOS5_PRO_ID); + cpu_id = read32((void *)EXYNOS5_PRO_ID); cpu_id = (0xC000 | ((cpu_id & 0x00FFF000) >> 12)); /* diff --git a/src/soc/samsung/exynos5250/dmc_common.c b/src/soc/samsung/exynos5250/dmc_common.c index 17dff1ec92..2e64905d9d 100644 --- a/src/soc/samsung/exynos5250/dmc_common.c +++ b/src/soc/samsung/exynos5250/dmc_common.c @@ -45,19 +45,19 @@ int dmc_config_zq(struct mem_timings *mem, val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT; val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT; val |= ZQ_CLK_DIV_EN; - writel(val, &phy0_ctrl->phy_con16); - writel(val, &phy1_ctrl->phy_con16); + write32(&phy0_ctrl->phy_con16, val); + write32(&phy1_ctrl->phy_con16, val); /* Disable termination */ if (mem->zq_mode_noterm) val |= PHY_CON16_ZQ_MODE_NOTERM_MASK; - writel(val, &phy0_ctrl->phy_con16); - writel(val, &phy1_ctrl->phy_con16); + write32(&phy0_ctrl->phy_con16, val); + write32(&phy1_ctrl->phy_con16, val); /* ZQ_MANUAL_START: Enable */ val |= ZQ_MANUAL_STR; - writel(val, &phy0_ctrl->phy_con16); - writel(val, &phy1_ctrl->phy_con16); + write32(&phy0_ctrl->phy_con16, val); + write32(&phy1_ctrl->phy_con16, val); /* ZQ_MANUAL_START: Disable */ val &= ~ZQ_MANUAL_STR; @@ -67,22 +67,22 @@ int dmc_config_zq(struct mem_timings *mem, * we are looping for the ZQ_init to complete. */ i = ZQ_INIT_TIMEOUT; - while ((readl(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { + while ((read32(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { udelay(1); i--; } if (!i) return -1; - writel(val, &phy0_ctrl->phy_con16); + write32(&phy0_ctrl->phy_con16, val); i = ZQ_INIT_TIMEOUT; - while ((readl(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { + while ((read32(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { udelay(1); i--; } if (!i) return -1; - writel(val, &phy1_ctrl->phy_con16); + write32(&phy1_ctrl->phy_con16, val); return 0; } @@ -93,18 +93,18 @@ void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode) if (mode == DDR_MODE_DDR3) { val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE; - writel(val, &dmc->phycontrol0); + write32(&dmc->phycontrol0, val); } /* Update DLL Information: Force DLL Resynchronization */ - val = readl(&dmc->phycontrol0); + val = read32(&dmc->phycontrol0); val |= FP_RSYNC; - writel(val, &dmc->phycontrol0); + write32(&dmc->phycontrol0, val); /* Reset Force DLL Resynchronization */ - val = readl(&dmc->phycontrol0); + val = read32(&dmc->phycontrol0); val &= ~FP_RSYNC; - writel(val, &dmc->phycontrol0); + write32(&dmc->phycontrol0, val); } void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) @@ -121,7 +121,7 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) mask |= chip << DIRECT_CMD_CHIP_SHIFT; /* Sending NOP command */ - writel(DIRECT_CMD_NOP | mask, &dmc->directcmd); + write32(&dmc->directcmd, DIRECT_CMD_NOP | mask); /* * TODO(alim.akhtar@samsung.com): Do we need these @@ -132,15 +132,15 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) /* Sending EMRS/MRS commands */ for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) { - writel(mem->direct_cmd_msr[i] | mask, - &dmc->directcmd); + write32(&dmc->directcmd, + mem->direct_cmd_msr[i] | mask); udelay(100); } if (mem->send_zq_init) { /* Sending ZQINIT command */ - writel(DIRECT_CMD_ZQINIT | mask, - &dmc->directcmd); + write32(&dmc->directcmd, + DIRECT_CMD_ZQINIT | mask); /* * FIXME: This was originally sdelay(10000) * in the imported u-boot code. That may have @@ -166,7 +166,7 @@ void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc) mask |= chip << DIRECT_CMD_CHIP_SHIFT; /* PALL (all banks precharge) CMD */ - writel(DIRECT_CMD_PALL | mask, &dmc->directcmd); + write32(&dmc->directcmd, DIRECT_CMD_PALL | mask); udelay(100); } } @@ -174,8 +174,8 @@ void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc) void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc) { - writel(mem->memconfig, &dmc->memconfig0); - writel(mem->memconfig, &dmc->memconfig1); - writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0); - writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1); + write32(&dmc->memconfig0, mem->memconfig); + write32(&dmc->memconfig1, mem->memconfig); + write32(&dmc->membaseconfig0, DMC_MEMBASECONFIG0_VAL); + write32(&dmc->membaseconfig1, DMC_MEMBASECONFIG1_VAL); } diff --git a/src/soc/samsung/exynos5250/dmc_init_ddr3.c b/src/soc/samsung/exynos5250/dmc_init_ddr3.c index 3b26c206c1..5a3cf3ef06 100644 --- a/src/soc/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5250/dmc_init_ddr3.c @@ -31,8 +31,10 @@ static void reset_phy_ctrl(void) { - writel(LPDDR3PHY_CTRL_PHY_RESET_ENABLE, &exynos_clock->lpddr3phy_ctrl); - writel(LPDDR3PHY_CTRL_PHY_RESET_DISABLE, &exynos_clock->lpddr3phy_ctrl); + write32(&exynos_clock->lpddr3phy_ctrl, + LPDDR3PHY_CTRL_PHY_RESET_ENABLE); + write32(&exynos_clock->lpddr3phy_ctrl, + LPDDR3PHY_CTRL_PHY_RESET_DISABLE); #if 0 /* @@ -65,14 +67,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, (mem->impedance << CA_CKE_DRVR_DS_OFFSET) | (mem->impedance << CA_CS_DRVR_DS_OFFSET) | (mem->impedance << CA_ADR_DRVR_DS_OFFSET); - writel(val, &exynos_phy0_control->phy_con39); - writel(val, &exynos_phy1_control->phy_con39); + write32(&exynos_phy0_control->phy_con39, val); + write32(&exynos_phy1_control->phy_con39, val); /* Set Read Latency and Burst Length for PHY0 and PHY1 */ val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT); - writel(val, &exynos_phy0_control->phy_con42); - writel(val, &exynos_phy1_control->phy_con42); + write32(&exynos_phy0_control->phy_con42, val); + write32(&exynos_phy1_control->phy_con42, val); /* ZQ Calibration */ if (dmc_config_zq(mem, exynos_phy0_control, exynos_phy1_control)){ @@ -81,71 +83,69 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, } /* DQ Signal */ - writel(mem->phy0_pulld_dqs, &exynos_phy0_control->phy_con14); - writel(mem->phy1_pulld_dqs, &exynos_phy1_control->phy_con14); + write32(&exynos_phy0_control->phy_con14, mem->phy0_pulld_dqs); + write32(&exynos_phy1_control->phy_con14, mem->phy1_pulld_dqs); - writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) - | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT), - &exynos_dmc->concontrol); + write32(&exynos_dmc->concontrol, + mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT)); update_reset_dll(exynos_dmc, DDR_MODE_DDR3); /* DQS Signal */ - writel(mem->phy0_dqs, &exynos_phy0_control->phy_con4); - writel(mem->phy1_dqs, &exynos_phy1_control->phy_con4); + write32(&exynos_phy0_control->phy_con4, mem->phy0_dqs); + write32(&exynos_phy1_control->phy_con4, mem->phy1_dqs); - writel(mem->phy0_dq, &exynos_phy0_control->phy_con6); - writel(mem->phy1_dq, &exynos_phy1_control->phy_con6); + write32(&exynos_phy0_control->phy_con6, mem->phy0_dq); + write32(&exynos_phy1_control->phy_con6, mem->phy1_dq); - writel(mem->phy0_tFS, &exynos_phy0_control->phy_con10); - writel(mem->phy1_tFS, &exynos_phy1_control->phy_con10); + write32(&exynos_phy0_control->phy_con10, mem->phy0_tFS); + write32(&exynos_phy1_control->phy_con10, mem->phy1_tFS); val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) | (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) | (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) | (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); - writel(val, &exynos_phy0_control->phy_con12); - writel(val, &exynos_phy1_control->phy_con12); + write32(&exynos_phy0_control->phy_con12, val); + write32(&exynos_phy1_control->phy_con12, val); /* Start DLL locking */ - writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT), - &exynos_phy0_control->phy_con12); - writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT), - &exynos_phy1_control->phy_con12); + write32(&exynos_phy0_control->phy_con12, + val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT)); + write32(&exynos_phy1_control->phy_con12, + val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT)); update_reset_dll(exynos_dmc, DDR_MODE_DDR3); - writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), - &exynos_dmc->concontrol); + write32(&exynos_dmc->concontrol, + mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)); /* Memory Channel Inteleaving Size */ - writel(mem->iv_size, &exynos_dmc->ivcontrol); + write32(&exynos_dmc->ivcontrol, mem->iv_size); /* Set DMC MEMCONTROL register */ val = mem->memcontrol & ~DMC_MEMCONTROL_DSREF_ENABLE; - writel(val, &exynos_dmc->memcontrol); + write32(&exynos_dmc->memcontrol, val); - writel(mem->memconfig, &exynos_dmc->memconfig0); - writel(mem->memconfig, &exynos_dmc->memconfig1); - writel(mem->membaseconfig0, &exynos_dmc->membaseconfig0); - writel(mem->membaseconfig1, &exynos_dmc->membaseconfig1); + write32(&exynos_dmc->memconfig0, mem->memconfig); + write32(&exynos_dmc->memconfig1, mem->memconfig); + write32(&exynos_dmc->membaseconfig0, mem->membaseconfig0); + write32(&exynos_dmc->membaseconfig1, mem->membaseconfig1); /* Precharge Configuration */ - writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, - &exynos_dmc->prechconfig); + write32(&exynos_dmc->prechconfig, + mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT); /* Power Down mode Configuration */ - writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT | - mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT, - &exynos_dmc->pwrdnconfig); + write32(&exynos_dmc->pwrdnconfig, + mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT | mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT); /* TimingRow, TimingData, TimingPower and Timingaref * values as per Memory AC parameters */ - writel(mem->timing_ref, &exynos_dmc->timingref); - writel(mem->timing_row, &exynos_dmc->timingrow); - writel(mem->timing_data, &exynos_dmc->timingdata); - writel(mem->timing_power, &exynos_dmc->timingpower); + write32(&exynos_dmc->timingref, mem->timing_ref); + write32(&exynos_dmc->timingrow, mem->timing_row); + write32(&exynos_dmc->timingdata, mem->timing_data); + write32(&exynos_dmc->timingpower, mem->timing_power); /* Send PALL command */ dmc_config_prech(mem, exynos_dmc); @@ -162,19 +162,19 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, if (mem->gate_leveling_enable) { val = PHY_CON0_RESET_VAL; val |= P0_CMD_EN; - writel(val, &exynos_phy0_control->phy_con0); - writel(val, &exynos_phy1_control->phy_con0); + write32(&exynos_phy0_control->phy_con0, val); + write32(&exynos_phy1_control->phy_con0, val); val = PHY_CON2_RESET_VAL; val |= INIT_DESKEW_EN; - writel(val, &exynos_phy0_control->phy_con2); - writel(val, &exynos_phy1_control->phy_con2); + write32(&exynos_phy0_control->phy_con2, val); + write32(&exynos_phy1_control->phy_con2, val); val = PHY_CON0_RESET_VAL; val |= P0_CMD_EN; val |= BYTE_RDLVL_EN; - writel(val, &exynos_phy0_control->phy_con0); - writel(val, &exynos_phy1_control->phy_con0); + write32(&exynos_phy0_control->phy_con0, val); + write32(&exynos_phy1_control->phy_con0, val); val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) | @@ -182,30 +182,30 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) | (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); - writel(val, &exynos_phy0_control->phy_con12); - writel(val, &exynos_phy1_control->phy_con12); + write32(&exynos_phy0_control->phy_con12, val); + write32(&exynos_phy1_control->phy_con12, val); val = PHY_CON2_RESET_VAL; val |= INIT_DESKEW_EN; val |= RDLVL_GATE_EN; - writel(val, &exynos_phy0_control->phy_con2); - writel(val, &exynos_phy1_control->phy_con2); + write32(&exynos_phy0_control->phy_con2, val); + write32(&exynos_phy1_control->phy_con2, val); val = PHY_CON0_RESET_VAL; val |= P0_CMD_EN; val |= BYTE_RDLVL_EN; val |= CTRL_SHGATE; - writel(val, &exynos_phy0_control->phy_con0); - writel(val, &exynos_phy1_control->phy_con0); + write32(&exynos_phy0_control->phy_con0, val); + write32(&exynos_phy1_control->phy_con0, val); val = PHY_CON1_RESET_VAL; val &= ~(CTRL_GATEDURADJ_MASK); - writel(val, &exynos_phy0_control->phy_con1); - writel(val, &exynos_phy1_control->phy_con1); + write32(&exynos_phy0_control->phy_con1, val); + write32(&exynos_phy1_control->phy_con1, val); - writel(CTRL_RDLVL_GATE_ENABLE, &exynos_dmc->rdlvl_config); + write32(&exynos_dmc->rdlvl_config, CTRL_RDLVL_GATE_ENABLE); i = RDLVL_COMPLETE_TIMEOUT; - while ((readl(&exynos_dmc->phystatus) & + while ((read32(&exynos_dmc->phystatus) & (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) != (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) { /* @@ -219,10 +219,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, printk(BIOS_EMERG, "Timeout on RDLVL. No DRAM.\n"); return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; } - writel(CTRL_RDLVL_GATE_DISABLE, &exynos_dmc->rdlvl_config); + write32(&exynos_dmc->rdlvl_config, CTRL_RDLVL_GATE_DISABLE); - writel(0, &exynos_phy0_control->phy_con14); - writel(0, &exynos_phy1_control->phy_con14); + write32(&exynos_phy0_control->phy_con14, 0); + write32(&exynos_phy1_control->phy_con14, 0); val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) | @@ -231,8 +231,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) | (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) | (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); - writel(val, &exynos_phy0_control->phy_con12); - writel(val, &exynos_phy1_control->phy_con12); + write32(&exynos_phy0_control->phy_con12, val); + write32(&exynos_phy1_control->phy_con12, val); update_reset_dll(exynos_dmc, DDR_MODE_DDR3); } @@ -240,11 +240,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, /* Send PALL command */ dmc_config_prech(mem, exynos_dmc); - writel(mem->memcontrol, &exynos_dmc->memcontrol); + write32(&exynos_dmc->memcontrol, mem->memcontrol); /* Set DMC Concontrol and enable auto-refresh counter */ - writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) - | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), - &exynos_dmc->concontrol); + write32(&exynos_dmc->concontrol, + mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT)); return 0; } diff --git a/src/soc/samsung/exynos5250/dp-reg.c b/src/soc/samsung/exynos5250/dp-reg.c index a2c0aa482d..75dadba022 100644 --- a/src/soc/samsung/exynos5250/dp-reg.c +++ b/src/soc/samsung/exynos5250/dp-reg.c @@ -35,7 +35,7 @@ void s5p_dp_reset(struct s5p_dp_device *dp) u32 reg; struct exynos5_dp *base = dp->base; - writel(RESET_DP_TX, &base->dp_tx_sw_reset); + write32(&base->dp_tx_sw_reset, RESET_DP_TX); /* Stop Video */ clrbits_le32(&base->video_ctl_1, VIDEO_EN); @@ -44,73 +44,73 @@ void s5p_dp_reset(struct s5p_dp_device *dp) reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | HDCP_FUNC_EN_N | SW_FUNC_EN_N; - writel(reg, &base->func_en_1); + write32(&base->func_en_1, reg); reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N; - writel(reg, &base->func_en_2); + write32(&base->func_en_2, reg); udelay(20); reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0; - writel(reg, &base->lane_map); + write32(&base->lane_map, reg); - writel(0x0, &base->sys_ctl_1); - writel(0x40, &base->sys_ctl_2); - writel(0x0, &base->sys_ctl_3); - writel(0x0, &base->sys_ctl_4); + write32(&base->sys_ctl_1, 0x0); + write32(&base->sys_ctl_2, 0x40); + write32(&base->sys_ctl_3, 0x0); + write32(&base->sys_ctl_4, 0x0); - writel(0x0, &base->pkt_send_ctl); - writel(0x0, &base->dp_hdcp_ctl); + write32(&base->pkt_send_ctl, 0x0); + write32(&base->dp_hdcp_ctl, 0x0); - writel(0x5e, &base->dp_hpd_deglitch_l); - writel(0x1a, &base->dp_hpd_deglitch_h); + write32(&base->dp_hpd_deglitch_l, 0x5e); + write32(&base->dp_hpd_deglitch_h, 0x1a); - writel(0x10, &base->dp_debug_ctl); + write32(&base->dp_debug_ctl, 0x10); - writel(0x0, &base->dp_phy_test); + write32(&base->dp_phy_test, 0x0); - writel(0x0, &base->dp_video_fifo_thrd); - writel(0x20, &base->dp_audio_margin); + write32(&base->dp_video_fifo_thrd, 0x0); + write32(&base->dp_audio_margin, 0x20); - writel(0x4, &base->m_vid_gen_filter_th); - writel(0x2, &base->m_aud_gen_filter_th); + write32(&base->m_vid_gen_filter_th, 0x4); + write32(&base->m_aud_gen_filter_th, 0x2); - writel(0x00000101, &base->soc_general_ctl); + write32(&base->soc_general_ctl, 0x00000101); /* Set Analog Parameters */ - writel(0x10, &base->analog_ctl_1); - writel(0x0C, &base->analog_ctl_2); - writel(0x85, &base->analog_ctl_3); - writel(0x66, &base->pll_filter_ctl_1); - writel(0x0, &base->tx_amp_tuning_ctl); + write32(&base->analog_ctl_1, 0x10); + write32(&base->analog_ctl_2, 0x0C); + write32(&base->analog_ctl_3, 0x85); + write32(&base->pll_filter_ctl_1, 0x66); + write32(&base->tx_amp_tuning_ctl, 0x0); /* Set interrupt pin assertion polarity as high */ - writel(INT_POL0 | INT_POL1, &base->int_ctl); + write32(&base->int_ctl, INT_POL0 | INT_POL1); /* Clear pending registers */ - writel(0xff, &base->common_int_sta_1); - writel(0x4f, &base->common_int_sta_2); - writel(0xe0, &base->common_int_sta_3); - writel(0xe7, &base->common_int_sta_4); - writel(0x63, &base->dp_int_sta); + write32(&base->common_int_sta_1, 0xff); + write32(&base->common_int_sta_2, 0x4f); + write32(&base->common_int_sta_3, 0xe0); + write32(&base->common_int_sta_4, 0xe7); + write32(&base->dp_int_sta, 0x63); /* 0:mask,1: unmask */ - writel(0x00, &base->common_int_mask_1); - writel(0x00, &base->common_int_mask_2); - writel(0x00, &base->common_int_mask_3); - writel(0x00, &base->common_int_mask_4); - writel(0x00, &base->int_sta_mask); + write32(&base->common_int_mask_1, 0x00); + write32(&base->common_int_mask_2, 0x00); + write32(&base->common_int_mask_3, 0x00); + write32(&base->common_int_mask_4, 0x00); + write32(&base->int_sta_mask, 0x00); } unsigned int s5p_dp_get_pll_lock_status(struct s5p_dp_device *dp) { u32 reg; - reg = readl(&dp->base->dp_debug_ctl); + reg = read32(&dp->base->dp_debug_ctl); if (reg & PLL_LOCK) return PLL_LOCKED; else @@ -123,10 +123,10 @@ int s5p_dp_init_analog_func(struct s5p_dp_device *dp) struct stopwatch sw; struct exynos5_dp *base = dp->base; - writel(0x00, &base->dp_phy_pd); + write32(&base->dp_phy_pd, 0x00); reg = PLL_LOCK_CHG; - writel(reg, &base->common_int_sta_1); + write32(&base->common_int_sta_1, reg); clrbits_le32(&base->dp_debug_ctl, (F_PLL_LOCK | PLL_LOCK_CTRL)); @@ -159,7 +159,7 @@ void s5p_dp_init_aux(struct s5p_dp_device *dp) /* Clear interrupts related to AUX channel */ reg = RPLY_RECEIV | AUX_ERR; - writel(reg, &base->dp_int_sta); + write32(&base->dp_int_sta, reg); /* Disable AUX channel module */ setbits_le32(&base->func_en_2, AUX_FUNC_EN_N); @@ -168,12 +168,12 @@ void s5p_dp_init_aux(struct s5p_dp_device *dp) reg = (3 & AUX_BIT_PERIOD_MASK) << AUX_BIT_PERIOD_SHIFT; reg |= (0 & AUX_HW_RETRY_COUNT_MASK) << AUX_HW_RETRY_COUNT_SHIFT; reg |= (AUX_HW_RETRY_INTERVAL_600_US << AUX_HW_RETRY_INTERVAL_SHIFT); - writel(reg, &base->aux_hw_retry_ctl) ; + write32(&base->aux_hw_retry_ctl, reg); /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ reg = DEFER_CTRL_EN; reg |= (1 & DEFER_COUNT_MASK) << DEFER_COUNT_SHIFT; - writel(reg, &base->aux_ch_defer_dtl); + write32(&base->aux_ch_defer_dtl, reg); /* Enable AUX channel module */ clrbits_le32(&base->func_en_2, AUX_FUNC_EN_N); @@ -188,24 +188,24 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp) setbits_le32(&base->aux_ch_ctl_2, AUX_EN); /* Is AUX CH command reply received? */ - reg = readl(&base->dp_int_sta); + reg = read32(&base->dp_int_sta); while (!(reg & RPLY_RECEIV)) - reg = readl(&base->dp_int_sta); + reg = read32(&base->dp_int_sta); /* Clear interrupt source for AUX CH command reply */ - writel(RPLY_RECEIV, &base->dp_int_sta); + write32(&base->dp_int_sta, RPLY_RECEIV); /* Clear interrupt source for AUX CH access error */ - reg = readl(&base->dp_int_sta); + reg = read32(&base->dp_int_sta); if (reg & AUX_ERR) { printk(BIOS_ERR, "%s: AUX_ERR encountered, dp_int_sta: " "0x%02x\n", __func__, reg); - writel(AUX_ERR, &base->dp_int_sta); + write32(&base->dp_int_sta, AUX_ERR); return -1; } /* Check AUX CH error access status */ - reg = readl(&base->dp_int_sta); + reg = read32(&base->dp_int_sta); if ((reg & AUX_STATUS_MASK) != 0) { printk(BIOS_ERR, "AUX CH error happens: %d\n\n", reg & AUX_STATUS_MASK); @@ -226,22 +226,22 @@ int s5p_dp_write_byte_to_dpcd(struct s5p_dp_device *dp, for (i = 0; i < MAX_AUX_RETRY_COUNT; i++) { /* Clear AUX CH data buffer */ - writel(BUF_CLR, &base->buf_data_ctl); + write32(&base->buf_data_ctl, BUF_CLR); /* Select DPCD device address */ reg = reg_addr >> AUX_ADDR_7_0_SHIFT; reg &= AUX_ADDR_7_0_MASK; - writel(reg, &base->aux_addr_7_0); + write32(&base->aux_addr_7_0, reg); reg = reg_addr >> AUX_ADDR_15_8_SHIFT; reg &= AUX_ADDR_15_8_MASK; - writel(reg, &base->aux_addr_15_8); + write32(&base->aux_addr_15_8, reg); reg = reg_addr >> AUX_ADDR_19_16_SHIFT; reg &= AUX_ADDR_19_16_MASK; - writel(reg, &base->aux_addr_19_16); + write32(&base->aux_addr_19_16, reg); /* Write data buffer */ reg = (unsigned int)data; - writel(reg, &base->buf_data_0); + write32(&base->buf_data_0, reg); /* * Set DisplayPort transaction and write 1 byte @@ -249,7 +249,7 @@ int s5p_dp_write_byte_to_dpcd(struct s5p_dp_device *dp, * If Bit 3 is 0, I2C transaction. */ reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; - writel(reg, &base->aux_ch_ctl_1); + write32(&base->aux_ch_ctl_1, reg); /* Start AUX transaction */ retval = s5p_dp_start_aux_transaction(dp); @@ -273,18 +273,18 @@ int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp, for (i = 0; i < MAX_AUX_RETRY_COUNT; i++) { /* Clear AUX CH data buffer */ - writel(BUF_CLR, &base->buf_data_ctl); + write32(&base->buf_data_ctl, BUF_CLR); /* Select DPCD device address */ reg = reg_addr >> AUX_ADDR_7_0_SHIFT; reg &= AUX_ADDR_7_0_MASK; - writel(reg, &base->aux_addr_7_0); + write32(&base->aux_addr_7_0, reg); reg = reg_addr >> AUX_ADDR_15_8_SHIFT; reg &= AUX_ADDR_15_8_MASK; - writel(reg, &base->aux_addr_15_8); + write32(&base->aux_addr_15_8, reg); reg = reg_addr >> AUX_ADDR_19_16_SHIFT; reg &= AUX_ADDR_19_16_MASK; - writel(reg, &base->aux_addr_19_16); + write32(&base->aux_addr_19_16, reg); /* * Set DisplayPort transaction and read 1 byte @@ -292,7 +292,7 @@ int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp, * If Bit 3 is 0, I2C transaction. */ reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; - writel(reg, &base->aux_ch_ctl_1); + write32(&base->aux_ch_ctl_1, reg); /* Start AUX transaction */ retval = s5p_dp_start_aux_transaction(dp); @@ -304,7 +304,7 @@ int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp, /* Read data buffer */ if (!retval) { - reg = readl(&base->buf_data_0); + reg = read32(&base->buf_data_0); *data = (unsigned char)(reg & 0xff); } @@ -317,17 +317,17 @@ void s5p_dp_init_video(struct s5p_dp_device *dp) struct exynos5_dp *base = dp->base; reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; - writel(reg, &base->common_int_sta_1); + write32(&base->common_int_sta_1, reg); reg = 0x0; - writel(reg, &base->sys_ctl_1); + write32(&base->sys_ctl_1, reg); reg = (4 & CHA_CRI_MASK) << CHA_CRI_SHIFT; reg |= CHA_CTRL; - writel(reg, &base->sys_ctl_2); + write32(&base->sys_ctl_2, reg); reg = 0x0; - writel(reg, &base->sys_ctl_3); + write32(&base->sys_ctl_3, reg); } void s5p_dp_set_video_color_format(struct s5p_dp_device *dp, @@ -343,16 +343,16 @@ void s5p_dp_set_video_color_format(struct s5p_dp_device *dp, reg = (dynamic_range << IN_D_RANGE_SHIFT) | (color_depth << IN_BPC_SHIFT) | (color_space << IN_COLOR_F_SHIFT); - writel(reg, &base->video_ctl_2); + write32(&base->video_ctl_2, reg); /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */ - reg = readl(&base->video_ctl_3); + reg = read32(&base->video_ctl_3); reg &= ~IN_YC_COEFFI_MASK; if (coeff) reg |= IN_YC_COEFFI_ITU709; else reg |= IN_YC_COEFFI_ITU601; - writel(reg, &base->video_ctl_3); + write32(&base->video_ctl_3, reg); } int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp) @@ -360,18 +360,18 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp) u32 reg; struct exynos5_dp *base = dp->base; - reg = readl(&base->sys_ctl_1); - writel(reg, &base->sys_ctl_1); + reg = read32(&base->sys_ctl_1); + write32(&base->sys_ctl_1, reg); - reg = readl(&base->sys_ctl_1); + reg = read32(&base->sys_ctl_1); if (!(reg & DET_STA)) return -1; - reg = readl(&base->sys_ctl_2); - writel(reg, &base->sys_ctl_2); + reg = read32(&base->sys_ctl_2); + write32(&base->sys_ctl_2, reg); - reg = readl(&base->sys_ctl_2); + reg = read32(&base->sys_ctl_2); if (reg & CHA_STA) { printk(BIOS_DEBUG, "Input stream clk is changing\n"); @@ -393,28 +393,28 @@ void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp, setbits_le32(&base->sys_ctl_4, FIX_M_VID); reg = m_value >> M_VID_0_VALUE_SHIFT; - writel(reg, &base->m_vid_0); + write32(&base->m_vid_0, reg); reg = (m_value >> M_VID_1_VALUE_SHIFT); - writel(reg, &base->m_vid_1); + write32(&base->m_vid_1, reg); reg = (m_value >> M_VID_2_VALUE_SHIFT); - writel(reg, &base->m_vid_2); + write32(&base->m_vid_2, reg); reg = n_value >> N_VID_0_VALUE_SHIFT; - writel(reg, &base->n_vid_0); + write32(&base->n_vid_0, reg); reg = (n_value >> N_VID_1_VALUE_SHIFT); - writel(reg, &base->n_vid_1); + write32(&base->n_vid_1, reg); reg = (n_value >> N_VID_2_VALUE_SHIFT); - writel(reg, &base->n_vid_2); + write32(&base->n_vid_2, reg); } else { clrbits_le32(&base->sys_ctl_4, FIX_M_VID); - writel(0x00, &base->n_vid_0); - writel(0x80, &base->n_vid_1); - writel(0x00, &base->n_vid_2); + write32(&base->n_vid_0, 0x00); + write32(&base->n_vid_1, 0x80); + write32(&base->n_vid_2, 0x00); } } @@ -423,10 +423,10 @@ void s5p_dp_enable_video_master(struct s5p_dp_device *dp) u32 reg; struct exynos5_dp *base = dp->base; - reg = readl(&base->soc_general_ctl); + reg = read32(&base->soc_general_ctl); reg &= ~VIDEO_MODE_MASK; reg |= VIDEO_MODE_SLAVE_MODE; - writel(reg, &base->soc_general_ctl); + write32(&base->soc_general_ctl, reg); } int s5p_dp_is_video_stream_on(struct s5p_dp_device *dp) @@ -439,10 +439,10 @@ int s5p_dp_is_video_stream_on(struct s5p_dp_device *dp) stopwatch_init_msecs_expire(&sw, STREAM_ON_TIMEOUT); do { - reg = readl(&base->common_int_sta_1); + reg = read32(&base->common_int_sta_1); if (reg & VSYNC_DET) { i++; - writel(reg | VSYNC_DET, &base->common_int_sta_1); + write32(&base->common_int_sta_1, reg | VSYNC_DET); } if (i == 4) break; @@ -462,28 +462,28 @@ void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp, u32 reg; struct exynos5_dp *base = dp->base; - reg = readl(&base->func_en_1); + reg = read32(&base->func_en_1); reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N); reg |= MASTER_VID_FUNC_EN_N; - writel(reg, &base->func_en_1); + write32(&base->func_en_1, reg); - reg = readl(&base->video_ctl_10); + reg = read32(&base->video_ctl_10); reg &= ~INTERACE_SCAN_CFG; reg |= (video_info->interlaced << 2); - writel(reg, &base->video_ctl_10); + write32(&base->video_ctl_10, reg); - reg = readl(&base->video_ctl_10); + reg = read32(&base->video_ctl_10); reg &= ~VSYNC_POLARITY_CFG; reg |= (video_info->v_sync_polarity << 1); - writel(reg, &base->video_ctl_10); + write32(&base->video_ctl_10, reg); - reg = readl(&base->video_ctl_10); + reg = read32(&base->video_ctl_10); reg &= ~HSYNC_POLARITY_CFG; reg |= (video_info->h_sync_polarity << 0); - writel(reg, &base->video_ctl_10); + write32(&base->video_ctl_10, reg); reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; - writel(reg, &base->soc_general_ctl); + write32(&base->soc_general_ctl, reg); } void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp) @@ -491,7 +491,7 @@ void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp) u32 reg; struct exynos5_dp *base = dp->base; - reg = readl(&base->dp_hw_link_training); + reg = read32(&base->dp_hw_link_training); while (reg & HW_TRAINING_EN) - reg = readl(&base->dp_hw_link_training); + reg = read32(&base->dp_hw_link_training); } diff --git a/src/soc/samsung/exynos5250/fb.c b/src/soc/samsung/exynos5250/fb.c index 3c7c5ef27b..befb0debf0 100644 --- a/src/soc/samsung/exynos5250/fb.c +++ b/src/soc/samsung/exynos5250/fb.c @@ -122,48 +122,48 @@ void fb_init(unsigned long int fb_size, void *lcdbase, fb_size = ALIGN(fb_size, 4096); - writel(pd->ivclk | pd->fixvclk, &exynos_disp_ctrl->vidcon1); + write32(&exynos_disp_ctrl->vidcon1, pd->ivclk | pd->fixvclk); val = ENVID_ON | ENVID_F_ON | (pd->clkval_f << CLKVAL_F_OFFSET); - writel(val, &exynos_fimd->vidcon0); + write32(&exynos_fimd->vidcon0, val); val = (pd->vsync << VSYNC_PULSE_WIDTH_OFFSET) | (pd->lower_margin << V_FRONT_PORCH_OFFSET) | (pd->upper_margin << V_BACK_PORCH_OFFSET); - writel(val, &exynos_disp_ctrl->vidtcon0); + write32(&exynos_disp_ctrl->vidtcon0, val); val = (pd->hsync << HSYNC_PULSE_WIDTH_OFFSET) | (pd->right_margin << H_FRONT_PORCH_OFFSET) | (pd->left_margin << H_BACK_PORCH_OFFSET); - writel(val, &exynos_disp_ctrl->vidtcon1); + write32(&exynos_disp_ctrl->vidtcon1, val); val = ((pd->xres - 1) << HOZVAL_OFFSET) | ((pd->yres - 1) << LINEVAL_OFFSET); - writel(val, &exynos_disp_ctrl->vidtcon2); + write32(&exynos_disp_ctrl->vidtcon2, val); - writel((unsigned int)lcdbase, &exynos_fimd->vidw00add0b0); - writel((unsigned int)lcdbase + fb_size, &exynos_fimd->vidw00add1b0); + write32(&exynos_fimd->vidw00add0b0, (unsigned int)lcdbase); + write32(&exynos_fimd->vidw00add1b0, (unsigned int)lcdbase + fb_size); - writel(pd->xres * 2, &exynos_fimd->vidw00add2); + write32(&exynos_fimd->vidw00add2, pd->xres * 2); val = ((pd->xres - 1) << OSD_RIGHTBOTX_F_OFFSET); val |= ((pd->yres - 1) << OSD_RIGHTBOTY_F_OFFSET); - writel(val, &exynos_fimd->vidosd0b); - writel(pd->xres * pd->yres, &exynos_fimd->vidosd0c); + write32(&exynos_fimd->vidosd0b, val); + write32(&exynos_fimd->vidosd0c, pd->xres * pd->yres); setbits_le32(&exynos_fimd->shadowcon, CHANNEL0_EN); val = BPPMODE_F_RGB_16BIT_565 << BPPMODE_F_OFFSET; val |= ENWIN_F_ENABLE | HALF_WORD_SWAP_EN; - writel(val, &exynos_fimd->wincon0); + write32(&exynos_fimd->wincon0, val); /* DPCLKCON_ENABLE */ - writel(1 << 1, &exynos_fimd->dpclkcon); + write32(&exynos_fimd->dpclkcon, 1 << 1); } #ifdef UNUSED_CODE void exynos_fimd_disable(void) { - writel(0, &exynos_fimd->wincon0); + write32(&exynos_fimd->wincon0, 0); clrbits_le32(&exynos_fimd->shadowcon, CHANNEL0_EN); } #endif @@ -328,18 +328,18 @@ static int s5p_dp_set_lane_lane_pre_emphasis(struct s5p_dp_device *dp, reg = pre_emphasis << PRE_EMPHASIS_SET_SHIFT; switch (lane) { case 0: - writel(reg, &base->ln0_link_trn_ctl); + write32(&base->ln0_link_trn_ctl, reg); break; case 1: - writel(reg, &base->ln1_link_trn_ctl); + write32(&base->ln1_link_trn_ctl, reg); break; case 2: - writel(reg, &base->ln2_link_trn_ctl); + write32(&base->ln2_link_trn_ctl, reg); break; case 3: - writel(reg, &base->ln3_link_trn_ctl); + write32(&base->ln3_link_trn_ctl, reg); break; default: printk(BIOS_DEBUG, "%s: Invalid lane %d\n", __func__, lane); @@ -432,7 +432,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, } /* All DP analog module power up */ - writel(0x00, &base->dp_phy_pd); + write32(&base->dp_phy_pd, 0x00); /* Initialize by reading RX's DPCD */ s5p_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); @@ -463,21 +463,21 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, dp->link_train.link_rate = max_rate; /* Set link rate and count as you want to establish*/ - writel(dp->link_train.lane_count, &base->lane_count_set); - writel(dp->link_train.link_rate, &base->link_bw_set); + write32(&base->lane_count_set, dp->link_train.lane_count); + write32(&base->link_bw_set, dp->link_train.link_rate); /* Set sink to D0 (Sink Not Ready) mode. */ s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE, DPCD_SET_POWER_STATE_D0); /* Start HW link training */ - writel(HW_TRAINING_EN, &base->dp_hw_link_training); + write32(&base->dp_hw_link_training, HW_TRAINING_EN); /* Wait until HW link training done */ s5p_dp_wait_hw_link_training_done(dp); /* Get hardware link training status */ - data = readl(&base->dp_hw_link_training); + data = read32(&base->dp_hw_link_training); printk(BIOS_SPEW, "hardware link training status: 0x%08x\n", data); if (data != 0) { printk(BIOS_ERR, " H/W link training failure: 0x%x\n", data); @@ -485,11 +485,11 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, } /* Get Link Bandwidth */ - data = readl(&base->link_bw_set); + data = read32(&base->link_bw_set); dp->link_train.link_rate = data; - data = readl(&base->lane_count_set); + data = read32(&base->lane_count_set); dp->link_train.lane_count = data; printk(BIOS_SPEW, "Done training: Link bandwidth: 0x%x, lane_count: %d\n", dp->link_train.link_rate, data); @@ -541,8 +541,8 @@ int dp_controller_init(struct s5p_dp_device *dp_device) /* Enable enhanced mode */ setbits_le32(&base->sys_ctl_4, ENHANCED); - writel(dp->link_train.lane_count, &base->lane_count_set); - writel(dp->link_train.link_rate, &base->link_bw_set); + write32(&base->lane_count_set, dp->link_train.lane_count); + write32(&base->link_bw_set, dp->link_train.link_rate); s5p_dp_init_video(dp); ret = s5p_dp_config_video(dp, dp->video_info); diff --git a/src/soc/samsung/exynos5250/gpio.c b/src/soc/samsung/exynos5250/gpio.c index 203aa03a42..c7a84197d0 100644 --- a/src/soc/samsung/exynos5250/gpio.c +++ b/src/soc/samsung/exynos5250/gpio.c @@ -82,10 +82,10 @@ void gpio_cfg_pin(int gpio, int cfg) unsigned int value; struct gpio_bank *bank = gpio_get_bank(gpio); - value = readl(&bank->con); + value = read32(&bank->con); value &= ~CON_MASK(GPIO_BIT(gpio)); value |= CON_SFR(GPIO_BIT(gpio), cfg); - writel(value, &bank->con); + write32(&bank->con, value); } static int gpio_get_cfg(int gpio) @@ -93,7 +93,7 @@ static int gpio_get_cfg(int gpio) struct gpio_bank *bank = gpio_get_bank(gpio); int shift = GPIO_BIT(gpio) << 2; - return (readl(&bank->con) & CON_MASK(GPIO_BIT(gpio))) >> shift; + return (read32(&bank->con) & CON_MASK(GPIO_BIT(gpio))) >> shift; } void gpio_set_pull(int gpio, int mode) @@ -101,7 +101,7 @@ void gpio_set_pull(int gpio, int mode) unsigned int value; struct gpio_bank *bank = gpio_get_bank(gpio); - value = readl(&bank->pull); + value = read32(&bank->pull); value &= ~PULL_MASK(GPIO_BIT(gpio)); switch (mode) { @@ -113,7 +113,7 @@ void gpio_set_pull(int gpio, int mode) break; } - writel(value, &bank->pull); + write32(&bank->pull, value); } void gpio_set_drv(int gpio, int mode) @@ -121,7 +121,7 @@ void gpio_set_drv(int gpio, int mode) unsigned int value; struct gpio_bank *bank = gpio_get_bank(gpio); - value = readl(&bank->drv); + value = read32(&bank->drv); value &= ~DRV_MASK(GPIO_BIT(gpio)); switch (mode) { @@ -135,7 +135,7 @@ void gpio_set_drv(int gpio, int mode) return; } - writel(value, &bank->drv); + write32(&bank->drv, value); } void gpio_set_rate(int gpio, int mode) @@ -143,7 +143,7 @@ void gpio_set_rate(int gpio, int mode) unsigned int value; struct gpio_bank *bank = gpio_get_bank(gpio); - value = readl(&bank->drv); + value = read32(&bank->drv); value &= ~RATE_MASK(GPIO_BIT(gpio)); switch (mode) { @@ -155,7 +155,7 @@ void gpio_set_rate(int gpio, int mode) return; } - writel(value, &bank->drv); + write32(&bank->drv, value); } int gpio_direction_input(unsigned gpio) @@ -170,11 +170,11 @@ int gpio_direction_output(unsigned gpio, int value) unsigned int val; struct gpio_bank *bank = gpio_get_bank(gpio); - val = readl(&bank->dat); + val = read32(&bank->dat); val &= ~DAT_MASK(GPIO_BIT(gpio)); if (value) val |= DAT_SET(GPIO_BIT(gpio)); - writel(val, &bank->dat); + write32(&bank->dat, val); gpio_cfg_pin(gpio, GPIO_OUTPUT); @@ -186,7 +186,7 @@ int gpio_get_value(unsigned gpio) unsigned int value; struct gpio_bank *bank = gpio_get_bank(gpio); - value = readl(&bank->dat); + value = read32(&bank->dat); return !!(value & DAT_MASK(GPIO_BIT(gpio))); } @@ -195,11 +195,11 @@ int gpio_set_value(unsigned gpio, int value) unsigned int val; struct gpio_bank *bank = gpio_get_bank(gpio); - val = readl(&bank->dat); + val = read32(&bank->dat); val &= ~DAT_MASK(GPIO_BIT(gpio)); if (value) val |= DAT_SET(GPIO_BIT(gpio)); - writel(val, &bank->dat); + write32(&bank->dat, val); return 0; } diff --git a/src/soc/samsung/exynos5250/i2c.c b/src/soc/samsung/exynos5250/i2c.c index f92182a77a..e9eed406e5 100644 --- a/src/soc/samsung/exynos5250/i2c.c +++ b/src/soc/samsung/exynos5250/i2c.c @@ -117,34 +117,34 @@ static struct s3c24x0_i2c_bus i2c_busses[] = { static int i2c_int_pending(struct i2c_regs *regs) { - return readb(®s->con) & I2cConIntPending; + return read8(®s->con) & I2cConIntPending; } static void i2c_clear_int(struct i2c_regs *regs) { - writeb(readb(®s->con) & ~I2cConIntPending, ®s->con); + write8(®s->con, read8(®s->con) & ~I2cConIntPending); } static void i2c_ack_enable(struct i2c_regs *regs) { - writeb(readb(®s->con) | I2cConAckGen, ®s->con); + write8(®s->con, read8(®s->con) | I2cConAckGen); } static void i2c_ack_disable(struct i2c_regs *regs) { - writeb(readb(®s->con) & ~I2cConAckGen, ®s->con); + write8(®s->con, read8(®s->con) & ~I2cConAckGen); } static int i2c_got_ack(struct i2c_regs *regs) { - return !(readb(®s->stat) & I2cStatAck); + return !(read8(®s->stat) & I2cStatAck); } static int i2c_wait_for_idle(struct i2c_regs *regs) { int timeout = 1000 * 100; // 1s. while (timeout--) { - if (!(readb(®s->stat) & I2cStatBusy)) + if (!(read8(®s->stat) & I2cStatBusy)) return 0; udelay(10); } @@ -169,17 +169,17 @@ static int i2c_wait_for_int(struct i2c_regs *regs) static int i2c_send_stop(struct i2c_regs *regs) { - uint8_t mode = readb(®s->stat) & (I2cStatModeMask); - writeb(mode | I2cStatEnable, ®s->stat); + uint8_t mode = read8(®s->stat) & (I2cStatModeMask); + write8(®s->stat, mode | I2cStatEnable); i2c_clear_int(regs); return i2c_wait_for_idle(regs); } static int i2c_send_start(struct i2c_regs *regs, int read, int chip) { - writeb(chip << 1, ®s->ds); + write8(®s->ds, chip << 1); uint8_t mode = read ? I2cStatMasterRecv : I2cStatMasterXmit; - writeb(mode | I2cStatStartStop | I2cStatEnable, ®s->stat); + write8(®s->stat, mode | I2cStatStartStop | I2cStatEnable); i2c_clear_int(regs); if (i2c_wait_for_int(regs)) @@ -201,7 +201,7 @@ static int i2c_xmit_buf(struct i2c_regs *regs, uint8_t *data, int len) int i; for (i = 0; i < len; i++) { - writeb(data[i], ®s->ds); + write8(®s->ds, data[i]); i2c_clear_int(regs); if (i2c_wait_for_int(regs)) @@ -231,7 +231,7 @@ static int i2c_recv_buf(struct i2c_regs *regs, uint8_t *data, int len) if (i2c_wait_for_int(regs)) return 1; - data[i] = readb(®s->ds); + data[i] = read8(®s->ds); } return 0; @@ -246,7 +246,7 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int seg_count) if (!regs || i2c_wait_for_idle(regs)) return 1; - writeb(I2cStatMasterXmit | I2cStatEnable, ®s->stat); + write8(®s->stat, I2cStatMasterXmit | I2cStatEnable); int i; for (i = 0; i < seg_count; i++) { @@ -286,11 +286,11 @@ void i2c_init(unsigned bus, int speed, int slaveadd) // Set prescaler, divisor according to freq, also set ACKGEN, IRQ. val = (div & 0x0f) | 0xa0 | ((pres == 512) ? 0x40 : 0); - writel(val, &i2c->regs->con); + write32(&i2c->regs->con, val); // Init to SLAVE RECEIVE mode and clear I2CADDn. - writel(0, &i2c->regs->stat); - writel(slaveadd, &i2c->regs->add); + write32(&i2c->regs->stat, 0); + write32(&i2c->regs->add, slaveadd); // program Master Transmit (and implicit STOP). - writel(I2cStatMasterXmit | I2cStatEnable, &i2c->regs->stat); + write32(&i2c->regs->stat, I2cStatMasterXmit | I2cStatEnable); } diff --git a/src/soc/samsung/exynos5250/power.c b/src/soc/samsung/exynos5250/power.c index c7d491dd23..1b8aaa67d1 100644 --- a/src/soc/samsung/exynos5250/power.c +++ b/src/soc/samsung/exynos5250/power.c @@ -89,5 +89,5 @@ void power_enable_xclkout(void) void power_release_uart_retention(void) { - writel(1 << 28, &exynos_power->padret_uart_opt); + write32(&exynos_power->padret_uart_opt, 1 << 28); } diff --git a/src/soc/samsung/exynos5250/spi.c b/src/soc/samsung/exynos5250/spi.c index 33a8c740f7..fed3aa7518 100644 --- a/src/soc/samsung/exynos5250/spi.c +++ b/src/soc/samsung/exynos5250/spi.c @@ -46,25 +46,25 @@ static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, out_bytes = in_bytes = todo; setbits_le32(®s->ch_cfg, SPI_CH_RST); clrbits_le32(®s->ch_cfg, SPI_CH_RST); - writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, ®s->pkt_cnt); + write32(®s->pkt_cnt, ((todo * 8) / 32) | SPI_PACKET_CNT_EN); while (in_bytes) { uint32_t spi_sts; int temp; - spi_sts = readl(®s->spi_sts); + spi_sts = read32(®s->spi_sts); rx_lvl = ((spi_sts >> 15) & 0x7f); tx_lvl = ((spi_sts >> 6) & 0x7f); while (tx_lvl < 32 && out_bytes) { // TODO The "writing" (tx) is not supported now; that's // why we write garbage to keep driving FIFO clock. temp = 0xffffffff; - writel(temp, ®s->tx_data); + write32(®s->tx_data, temp); out_bytes -= 4; tx_lvl += 4; } while (rx_lvl >= 4 && in_bytes) { - temp = readl(®s->rx_data); + temp = read32(®s->rx_data); if (rxp) *rxp++ = temp; in_bytes -= 4; @@ -79,9 +79,9 @@ int exynos_spi_open(struct exynos_spi *regs) /* set the spi1 GPIO */ /* set pktcnt and enable it */ - writel(4 | SPI_PACKET_CNT_EN, ®s->pkt_cnt); + write32(®s->pkt_cnt, 4 | SPI_PACKET_CNT_EN); /* set FB_CLK_SEL */ - writel(SPI_FB_DELAY_180, ®s->fb_clk); + write32(®s->fb_clk, SPI_FB_DELAY_180); /* set CH_WIDTH and BUS_WIDTH as word */ setbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); @@ -109,10 +109,10 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) clrbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ /* Send read instruction (0x3h) followed by a 24 bit addr */ - writel((SF_READ_DATA_CMD << 24) | off, ®s->tx_data); + write32(®s->tx_data, (SF_READ_DATA_CMD << 24) | off); /* waiting for TX done */ - while (!(readl(®s->spi_sts) & SPI_ST_TX_DONE)); + while (!(read32(®s->spi_sts) & SPI_ST_TX_DONE)); for (upto = 0, i = 0; upto < len; upto += todo, i++) { todo = MIN(len - upto, (1 << 15)); @@ -132,7 +132,7 @@ int exynos_spi_close(struct exynos_spi *regs) */ clrbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); - writel(0, ®s->swap_cfg); + write32(®s->swap_cfg, 0); /* * Flush spi tx, rx fifos and reset the SPI controller diff --git a/src/soc/samsung/exynos5250/timer.c b/src/soc/samsung/exynos5250/timer.c index 1e25771dbd..2abaf3bc5d 100644 --- a/src/soc/samsung/exynos5250/timer.c +++ b/src/soc/samsung/exynos5250/timer.c @@ -27,16 +27,15 @@ static const uint32_t clocks_per_usec = MCT_HZ/1000000; static uint64_t mct_raw_value(void) { - uint64_t upper = readl(&exynos_mct->g_cnt_u); - uint64_t lower = readl(&exynos_mct->g_cnt_l); + uint64_t upper = read32(&exynos_mct->g_cnt_u); + uint64_t lower = read32(&exynos_mct->g_cnt_l); return (upper << 32) | lower; } void init_timer(void) { - writel(readl(&exynos_mct->g_tcon) | (0x1 << 8), - &exynos_mct->g_tcon); + write32(&exynos_mct->g_tcon, read32(&exynos_mct->g_tcon) | (0x1 << 8)); } void timer_monotonic_get(struct mono_time *mt) diff --git a/src/soc/samsung/exynos5250/tmu.c b/src/soc/samsung/exynos5250/tmu.c index bde11a2550..51e7ad8894 100644 --- a/src/soc/samsung/exynos5250/tmu.c +++ b/src/soc/samsung/exynos5250/tmu.c @@ -80,7 +80,7 @@ static int get_cur_temp(struct tmu_info *info) struct tmu_reg *reg = (struct tmu_reg *)info->tmu_base; /* Temperature code range between min 25 and max 125 */ - cur_temp = readl(®->current_temp) & 0xff; + cur_temp = read32(®->current_temp) & 0xff; /* Calibrate current temperature */ if (cur_temp) @@ -142,10 +142,10 @@ static void tmu_setup_parameters(struct tmu_info *info) struct tmu_reg *reg = (struct tmu_reg *)info->tmu_base; /* Must reload for using efuse value at EXYNOS */ - writel(TRIMINFO_RELOAD, ®->triminfo_control); + write32(®->triminfo_control, TRIMINFO_RELOAD); /* Get the compensation parameter */ - te_temp = readl(®->triminfo); + te_temp = read32(®->triminfo); info->te1 = te_temp & TRIM_INFO_MASK; info->te2 = ((te_temp >> 8) & TRIM_INFO_MASK); @@ -169,8 +169,8 @@ static void tmu_setup_parameters(struct tmu_info *info) (hwtrip_code << 24)); /* Set interrupt level */ - writel(rising_value, ®->threshold_temp_rise); - writel(cooling_temp, ®->threshold_temp_fall); + write32(®->threshold_temp_rise, rising_value); + write32(®->threshold_temp_fall, cooling_temp); /* * Need to init all register settings after getting parameter info @@ -183,20 +183,20 @@ static void tmu_setup_parameters(struct tmu_info *info) * TODO(bhthompson): rewrite this code such that we are not performing * a hard wipe of tmu_control and re verify functionality. */ - writel(data->slope, ®->tmu_control); + write32(®->tmu_control, data->slope); - writel(INTCLEARALL, ®->intclear); + write32(®->intclear, INTCLEARALL); /* TMU core enable */ - con = readl(®->tmu_control); + con = read32(®->tmu_control); con |= (info->tmu_mux << 20) | THERM_TRIP_EN | CORE_EN; - writel(con, ®->tmu_control); + write32(®->tmu_control, con); /* Enable HW thermal trip */ power_enable_hw_thermal_trip(); /* LEV1 LEV2 interrupt enable */ - writel(INTEN_RISE1 | INTEN_RISE2, ®->inten); + write32(®->inten, INTEN_RISE1 | INTEN_RISE2); } /* diff --git a/src/soc/samsung/exynos5250/trustzone.c b/src/soc/samsung/exynos5250/trustzone.c index c4d3bc64b6..4a8141eeaf 100644 --- a/src/soc/samsung/exynos5250/trustzone.c +++ b/src/soc/samsung/exynos5250/trustzone.c @@ -31,14 +31,14 @@ void trustzone_init(void) tzpc = (struct exynos_tzpc *)addr; if (addr == TZPC0_BASE) - writel(R0SIZE, &tzpc->r0size); + write32(&tzpc->r0size, R0SIZE); - writel(DECPROTXSET, &tzpc->decprot0set); - writel(DECPROTXSET, &tzpc->decprot1set); + write32(&tzpc->decprot0set, DECPROTXSET); + write32(&tzpc->decprot1set, DECPROTXSET); if (addr != TZPC9_BASE) { - writel(DECPROTXSET, &tzpc->decprot2set); - writel(DECPROTXSET, &tzpc->decprot3set); + write32(&tzpc->decprot2set, DECPROTXSET); + write32(&tzpc->decprot3set, DECPROTXSET); } } } diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c index c23cfed347..81386b7ec4 100644 --- a/src/soc/samsung/exynos5250/uart.c +++ b/src/soc/samsung/exynos5250/uart.c @@ -66,7 +66,7 @@ static void serial_setbrg_dev(struct s5p_uart *uart) uclk = clock_get_periph_rate(PERIPH_ID_UART3); val = uclk / default_baudrate(); - writel(val / 16 - 1, &uart->ubrdiv); + write32(&uart->ubrdiv, val / 16 - 1); /* * FIXME(dhendrix): the original uart.h had a "br_rest" value which @@ -91,12 +91,12 @@ static void exynos5_init_dev(struct s5p_uart *uart) exynos_pinmux_uart3(); /* enable FIFOs */ - writel(0x1, &uart->ufcon); - writel(0, &uart->umcon); + write32(&uart->ufcon, 0x1); + write32(&uart->umcon, 0); /* 8N1 */ - writel(0x3, &uart->ulcon); + write32(&uart->ulcon, 0x3); /* No interrupts, no DMA, pure polling */ - writel(0x245, &uart->ucon); + write32(&uart->ucon, 0x245); serial_setbrg_dev(uart); } @@ -117,7 +117,7 @@ static int exynos5_uart_err_check(struct s5p_uart *uart, int op) else mask = 0xf; - return readl(&uart->uerstat) & mask; + return read32(&uart->uerstat) & mask; } /* @@ -128,13 +128,13 @@ static int exynos5_uart_err_check(struct s5p_uart *uart, int op) static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart) { /* wait for character to arrive */ - while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | + while (!(read32(&uart->ufstat) & (RX_FIFO_COUNT_MASK | RX_FIFO_FULL_MASK))) { if (exynos5_uart_err_check(uart, 0)) return 0; } - return readb(&uart->urxh) & 0xff; + return read8(&uart->urxh) & 0xff; } /* @@ -143,17 +143,17 @@ static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart) static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data) { /* wait for room in the tx FIFO */ - while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { + while ((read32(&uart->ufstat) & TX_FIFO_FULL_MASK)) { if (exynos5_uart_err_check(uart, 1)) return; } - writeb(data, &uart->utxh); + write8(&uart->utxh, data); } static void exynos5_uart_tx_flush(struct s5p_uart *uart) { - while (readl(&uart->ufstat) & 0x1ff0000); + while (read32(&uart->ufstat) & 0x1ff0000); } uintptr_t uart_platform_base(int idx) diff --git a/src/soc/samsung/exynos5250/usb.c b/src/soc/samsung/exynos5250/usb.c index 8a91497e1f..3f6833657b 100644 --- a/src/soc/samsung/exynos5250/usb.c +++ b/src/soc/samsung/exynos5250/usb.c @@ -51,23 +51,13 @@ static void setup_dwc3(struct exynos5_usb_drd_dwc3 *dwc3) /* Set relevant registers to default values (clearing all reset bits) */ - writel(0x1 << 24 | /* activate PHY low power states */ - 0x4 << 19 | /* low power delay value */ - 0x1 << 18 | /* activate PHY low power delay */ - 0x1 << 17 | /* enable SuperSpeed PHY suspend */ - 0x1 << 1 | /* default Tx deemphasis value */ - 0, &dwc3->usb3pipectl); + write32(&dwc3->usb3pipectl, + 0x1 << 24 | 0x4 << 19 | 0x1 << 18 | 0x1 << 17 | 0x1 << 1 | 0); /* Configure PHY clock turnaround for 8-bit UTMI+, disable suspend */ - writel(0x9 << 10 | /* PHY clock turnaround for 8-bit UTMI+ */ - 0x1 << 8 | /* enable PHY sleep in L1 */ - 0x1 << 6 | /* enable PHY suspend */ - 0, &dwc3->usb2phycfg); - - writel(0x5dc << 19 | /* suspend clock scale for 24MHz */ - 0x1 << 16 | /* retry SS three times (bugfix from U-Boot) */ - 0x1 << 12 | /* port capability HOST */ - 0, &dwc3->ctl); + write32(&dwc3->usb2phycfg, 0x9 << 10 | 0x1 << 8 | 0x1 << 6 | 0); + + write32(&dwc3->ctl, 0x5dc << 19 | 0x1 << 16 | 0x1 << 12 | 0); } void setup_usb_drd_dwc3() @@ -84,44 +74,25 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy) setbits_le32(&phy->linksystem, 0x1 << 27 | 0x20 << 1); /* Disable OTG, ID0 and DRVVBUS, do not force sleep/suspend */ - writel(1 << 6, &phy->utmi); - - writel(0x88 << 23 | /* spread spectrum refclk selector */ - 0x1 << 20 | /* enable spread spectrum */ - 0x1 << 19 | /* enable prescaler refclk */ - 0x68 << 11 | /* multiplier for 24MHz refclk */ - 0x5 << 5 | /* select 24MHz refclk (weird, from U-Boot) */ - 0x1 << 4 | /* power supply in normal operating mode */ - 0x3 << 2 | /* use external refclk (undocumented on 5420?)*/ - 0x1 << 1 | /* force port reset */ - 0x1 << 0 | /* normal operating mode */ - 0, &phy->clkrst); - - writel(0x9 << 26 | /* LOS level */ - 0x3 << 22 | /* TX VREF tune */ - 0x1 << 20 | /* TX rise tune */ - 0x1 << 18 | /* TX res tune */ - 0x3 << 13 | /* TX HS X Vtune */ - 0x3 << 9 | /* TX FS/LS tune */ - 0x3 << 6 | /* SQRX tune */ - 0x4 << 3 | /* OTG tune */ - 0x4 << 0 | /* comp disc tune */ - 0, &phy->param0); - - writel(0x7f << 19 | /* reserved */ - 0x7f << 12 | /* Tx launch amplitude */ - 0x20 << 6 | /* Tx deemphasis 6dB */ - 0x1c << 0 | /* Tx deemphasis 3.5dB (value from U-Boot) */ - 0, &phy->param1); + write32(&phy->utmi, 1 << 6); + + write32(&phy->clkrst, + 0x88 << 23 | 0x1 << 20 | 0x1 << 19 | 0x68 << 11 | 0x5 << 5 | 0x1 << 4 | 0x3 << 2 | 0x1 << 1 | 0x1 << 0 | 0); + + write32(&phy->param0, + 0x9 << 26 | 0x3 << 22 | 0x1 << 20 | 0x1 << 18 | 0x3 << 13 | 0x3 << 9 | 0x3 << 6 | 0x4 << 3 | 0x4 << 0 | 0); + + write32(&phy->param1, + 0x7f << 19 | 0x7f << 12 | 0x20 << 6 | 0x1c << 0 | 0); /* disable all test features */ - writel(0, &phy->test); + write32(&phy->test, 0); /* UTMI clock select? ("must be 0x1") */ - writel(0x1 << 2, &phy->utmiclksel); + write32(&phy->utmiclksel, 0x1 << 2); /* Samsung magic, undocumented (from U-Boot) */ - writel(0x0, &phy->resume); + write32(&phy->resume, 0x0); udelay(10); clrbits_le32(&phy->clkrst, 0x1 << 1); /* deassert port reset */ @@ -144,7 +115,7 @@ void setup_usb_host_phy(int hsic_gpio) printk(BIOS_DEBUG, "Powering up USB HOST PHY (%s HSIC)\n", hsic_gpio ? "with" : "without"); - hostphy_ctrl0 = readl(&exynos_usb_host_phy->usbphyctrl0); + hostphy_ctrl0 = read32(&exynos_usb_host_phy->usbphyctrl0); hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK | HOST_CTRL0_COMMONON_N | /* HOST Phy setting */ @@ -158,7 +129,7 @@ void setup_usb_host_phy(int hsic_gpio) /* HOST Phy setting */ HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST); - writel(hostphy_ctrl0, &exynos_usb_host_phy->usbphyctrl0); + write32(&exynos_usb_host_phy->usbphyctrl0, hostphy_ctrl0); udelay(10); clrbits_le32(&exynos_usb_host_phy->usbphyctrl0, HOST_CTRL0_LINKSWRST | diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c index f6c7845c54..971364ddfe 100644 --- a/src/soc/samsung/exynos5420/clock.c +++ b/src/soc/samsung/exynos5420/clock.c @@ -47,34 +47,34 @@ unsigned long get_pll_clk(int pllreg) switch (pllreg) { case APLL: - r = readl(&exynos_clock->apll_con0); + r = read32(&exynos_clock->apll_con0); break; case MPLL: - r = readl(&exynos_clock->mpll_con0); + r = read32(&exynos_clock->mpll_con0); break; case EPLL: - r = readl(&exynos_clock->epll_con0); - k = readl(&exynos_clock->epll_con1); + r = read32(&exynos_clock->epll_con0); + k = read32(&exynos_clock->epll_con1); break; case VPLL: - r = readl(&exynos_clock->vpll_con0); - k = readl(&exynos_clock->vpll_con1); + r = read32(&exynos_clock->vpll_con0); + k = read32(&exynos_clock->vpll_con1); break; case BPLL: - r = readl(&exynos_clock->bpll_con0); + r = read32(&exynos_clock->bpll_con0); break; case RPLL: - r = readl(&exynos_clock->rpll_con0); - k = readl(&exynos_clock->rpll_con1); + r = read32(&exynos_clock->rpll_con0); + k = read32(&exynos_clock->rpll_con1); break; case SPLL: - r = readl(&exynos_clock->spll_con0); + r = read32(&exynos_clock->spll_con0); break; case CPLL: - r = readl(&exynos_clock->cpll_con0); + r = read32(&exynos_clock->cpll_con0); break; case DPLL: - r = readl(&exynos_clock->dpll_con0); + r = read32(&exynos_clock->dpll_con0); break; default: printk(BIOS_DEBUG, "Unsupported PLL (%d)\n", pllreg); @@ -169,48 +169,48 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) switch (peripheral) { case PERIPH_ID_UART0: - src = (readl(&exynos_clock->clk_src_peric0) >> 4) & 0x7; - div = (readl(&exynos_clock->clk_div_peric0) >> 8) & 0xf; + src = (read32(&exynos_clock->clk_src_peric0) >> 4) & 0x7; + div = (read32(&exynos_clock->clk_div_peric0) >> 8) & 0xf; break; case PERIPH_ID_UART1: - src = (readl(&exynos_clock->clk_src_peric0) >> 8) & 0x7; - div = (readl(&exynos_clock->clk_div_peric0) >> 12) & 0xf; + src = (read32(&exynos_clock->clk_src_peric0) >> 8) & 0x7; + div = (read32(&exynos_clock->clk_div_peric0) >> 12) & 0xf; break; case PERIPH_ID_UART2: - src = (readl(&exynos_clock->clk_src_peric0) >> 12) & 0x7; - div = (readl(&exynos_clock->clk_div_peric0) >> 16) & 0xf; + src = (read32(&exynos_clock->clk_src_peric0) >> 12) & 0x7; + div = (read32(&exynos_clock->clk_div_peric0) >> 16) & 0xf; break; case PERIPH_ID_UART3: - src = (readl(&exynos_clock->clk_src_peric0) >> 16) & 0x7; - div = (readl(&exynos_clock->clk_div_peric0) >> 20) & 0xf; + src = (read32(&exynos_clock->clk_src_peric0) >> 16) & 0x7; + div = (read32(&exynos_clock->clk_div_peric0) >> 20) & 0xf; break; case PERIPH_ID_PWM0: case PERIPH_ID_PWM1: case PERIPH_ID_PWM2: case PERIPH_ID_PWM3: case PERIPH_ID_PWM4: - src = (readl(&exynos_clock->clk_src_peric0) >> 24) & 0x7; - div = (readl(&exynos_clock->clk_div_peric0) >> 28) & 0x7; + src = (read32(&exynos_clock->clk_src_peric0) >> 24) & 0x7; + div = (read32(&exynos_clock->clk_div_peric0) >> 28) & 0x7; break; case PERIPH_ID_SPI0: - src = (readl(&exynos_clock->clk_src_peric1) >> 20) & 0x7; - div = (readl(&exynos_clock->clk_div_peric1) >> 20) & 0xf; + src = (read32(&exynos_clock->clk_src_peric1) >> 20) & 0x7; + div = (read32(&exynos_clock->clk_div_peric1) >> 20) & 0xf; break; case PERIPH_ID_SPI1: - src = (readl(&exynos_clock->clk_src_peric1) >> 24) & 0x7; - div = (readl(&exynos_clock->clk_div_peric1) >> 24) & 0xf; + src = (read32(&exynos_clock->clk_src_peric1) >> 24) & 0x7; + div = (read32(&exynos_clock->clk_div_peric1) >> 24) & 0xf; break; case PERIPH_ID_SPI2: - src = (readl(&exynos_clock->clk_src_peric1) >> 28) & 0x7; - div = (readl(&exynos_clock->clk_div_peric1) >> 28) & 0xf; + src = (read32(&exynos_clock->clk_src_peric1) >> 28) & 0x7; + div = (read32(&exynos_clock->clk_div_peric1) >> 28) & 0xf; break; case PERIPH_ID_SPI3: /* aka SPI0_ISP */ - src = (readl(&exynos_clock->clk_src_isp) >> 16) & 0x7; - div = (readl(&exynos_clock->clk_div_isp0) >> 0) & 0x7; + src = (read32(&exynos_clock->clk_src_isp) >> 16) & 0x7; + div = (read32(&exynos_clock->clk_div_isp0) >> 0) & 0x7; break; case PERIPH_ID_SPI4: /* aka SPI1_ISP */ - src = (readl(&exynos_clock->clk_src_isp) >> 12) & 0x7; - div = (readl(&exynos_clock->clk_div_isp1) >> 4) & 0x7; + src = (read32(&exynos_clock->clk_src_isp) >> 12) & 0x7; + div = (read32(&exynos_clock->clk_div_isp1) >> 4) & 0x7; break; case PERIPH_ID_I2C0: case PERIPH_ID_I2C1: @@ -229,7 +229,7 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) * TODO: Add a helper function like with the peripheral clock * select fields? */ - src = (readl(&exynos_clock->clk_src_top1) >> 8) & 0x3; + src = (read32(&exynos_clock->clk_src_top1) >> 8) & 0x3; if (src == 0x0) src = CPLL; else if (src == 0x1) @@ -240,7 +240,7 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) return -1; sclk = get_pll_clk(src); - div = ((readl(&exynos_clock->clk_div_top1) >> 8) & 0x3f) + 1; + div = ((read32(&exynos_clock->clk_div_top1) >> 8) & 0x3f) + 1; return sclk / div; default: printk(BIOS_DEBUG, "%s: invalid peripheral %d", @@ -267,7 +267,7 @@ unsigned long get_arm_clk(void) unsigned int arm_ratio; unsigned int arm2_ratio; - div = readl(&exynos_clock->clk_div_cpu0); + div = read32(&exynos_clock->clk_div_cpu0); /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */ arm_ratio = (div >> 0) & 0x7; @@ -286,7 +286,7 @@ static unsigned long get_mmc_clk(int dev_index) unsigned int sel, ratio; int shift = 0; - sel = readl(&exynos_clock->clk_src_fsys); + sel = read32(&exynos_clock->clk_src_fsys); sel = (sel >> ((dev_index * 4) + 8)) & 0x7; if (sel == 0x3) @@ -296,7 +296,7 @@ static unsigned long get_mmc_clk(int dev_index) else return 0; - ratio = readl(&exynos_clock->clk_div_fsys1); + ratio = read32(&exynos_clock->clk_div_fsys1); shift = dev_index * 10; @@ -316,10 +316,10 @@ void set_mmc_clk(int dev_index, unsigned int div) addr = &exynos_clock->clk_div_fsys1; shift = dev_index * 10; - val = readl(addr); + val = read32(addr); val &= ~(0x3ff << shift); val |= (div & 0x3ff) << shift; - writel(val, addr); + write32(addr, val); } /* Set DW MMC Controller clock */ @@ -546,10 +546,10 @@ int clock_set_mshci(enum periph_id peripheral) printk(BIOS_DEBUG, "invalid peripheral\n"); return -1; } - tmp = readl(addr) & ~0xff0f; + tmp = read32(addr) & ~0xff0f; for (i = 0; i <= 0xf; i++) { if ((clock / (i + 1)) <= 400) { - writel(tmp | i << 0, addr); + write32(addr, tmp | i << 0); break; } } @@ -563,7 +563,7 @@ int clock_epll_set_rate(unsigned long rate) unsigned int lockcnt; struct stopwatch sw; - epll_con = readl(&exynos_clock->epll_con0); + epll_con = read32(&exynos_clock->epll_con0); epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK << EPLL_CON0_LOCK_DET_EN_SHIFT) | EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT | @@ -591,13 +591,13 @@ int clock_epll_set_rate(unsigned long rate) */ lockcnt = 3000 * epll_div[i].p_div; - writel(lockcnt, &exynos_clock->epll_lock); - writel(epll_con, &exynos_clock->epll_con0); - writel(epll_con_k, &exynos_clock->epll_con1); + write32(&exynos_clock->epll_lock, lockcnt); + write32(&exynos_clock->epll_con0, epll_con); + write32(&exynos_clock->epll_con1, epll_con_k); stopwatch_init_msecs_expire(&sw, TIMEOUT_EPLL_LOCK); - while (!(readl(&exynos_clock->epll_con0) & + while (!(read32(&exynos_clock->epll_con0) & (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) { if (stopwatch_expired(&sw)) { printk(BIOS_DEBUG, "%s: Timeout waiting for EPLL lock\n", __func__); diff --git a/src/soc/samsung/exynos5420/clock_init.c b/src/soc/samsung/exynos5420/clock_init.c index 25b8beecd1..c5b4aaaa3f 100644 --- a/src/soc/samsung/exynos5420/clock_init.c +++ b/src/soc/samsung/exynos5420/clock_init.c @@ -35,186 +35,186 @@ void system_clock_init(void) exynos_mct->g_tcon |= (1 << 8); /* PLL locktime */ - writel(APLL_LOCK_VAL, &exynos_clock->apll_lock); - writel(MPLL_LOCK_VAL, &exynos_clock->mpll_lock); - writel(BPLL_LOCK_VAL, &exynos_clock->bpll_lock); - writel(CPLL_LOCK_VAL, &exynos_clock->cpll_lock); - writel(DPLL_LOCK_VAL, &exynos_clock->dpll_lock); - writel(EPLL_LOCK_VAL, &exynos_clock->epll_lock); - writel(VPLL_LOCK_VAL, &exynos_clock->vpll_lock); - writel(IPLL_LOCK_VAL, &exynos_clock->ipll_lock); - writel(SPLL_LOCK_VAL, &exynos_clock->spll_lock); - writel(KPLL_LOCK_VAL, &exynos_clock->kpll_lock); - writel(RPLL_LOCK_VAL, &exynos_clock->rpll_lock); + write32(&exynos_clock->apll_lock, APLL_LOCK_VAL); + write32(&exynos_clock->mpll_lock, MPLL_LOCK_VAL); + write32(&exynos_clock->bpll_lock, BPLL_LOCK_VAL); + write32(&exynos_clock->cpll_lock, CPLL_LOCK_VAL); + write32(&exynos_clock->dpll_lock, DPLL_LOCK_VAL); + write32(&exynos_clock->epll_lock, EPLL_LOCK_VAL); + write32(&exynos_clock->vpll_lock, VPLL_LOCK_VAL); + write32(&exynos_clock->ipll_lock, IPLL_LOCK_VAL); + write32(&exynos_clock->spll_lock, SPLL_LOCK_VAL); + write32(&exynos_clock->kpll_lock, KPLL_LOCK_VAL); + write32(&exynos_clock->rpll_lock, RPLL_LOCK_VAL); setbits_le32(&exynos_clock->clk_src_cpu, MUX_HPM_SEL_MASK); - writel(0, &exynos_clock->clk_src_top6); + write32(&exynos_clock->clk_src_top6, 0); - writel(0, &exynos_clock->clk_src_cdrex); - writel(SRC_KFC_HPM_SEL, &exynos_clock->clk_src_kfc); - writel(HPM_RATIO, &exynos_clock->clk_div_cpu1); - writel(CLK_DIV_CPU0_VAL, &exynos_clock->clk_div_cpu0); + write32(&exynos_clock->clk_src_cdrex, 0); + write32(&exynos_clock->clk_src_kfc, SRC_KFC_HPM_SEL); + write32(&exynos_clock->clk_div_cpu1, HPM_RATIO); + write32(&exynos_clock->clk_div_cpu0, CLK_DIV_CPU0_VAL); /* switch A15 clock source to OSC clock before changing APLL */ clrbits_le32(&exynos_clock->clk_src_cpu, APLL_FOUT); /* Set APLL */ - writel(APLL_CON1_VAL, &exynos_clock->apll_con1); + write32(&exynos_clock->apll_con1, APLL_CON1_VAL); val = set_pll(225, 3, 0); /* FOUT=1800MHz */ - writel(val, &exynos_clock->apll_con0); - while ((readl(&exynos_clock->apll_con0) & PLL_LOCKED) == 0) + write32(&exynos_clock->apll_con0, val); + while ((read32(&exynos_clock->apll_con0) & PLL_LOCKED) == 0) ; /* now it is safe to switch to APLL */ setbits_le32(&exynos_clock->clk_src_cpu, APLL_FOUT); - writel(SRC_KFC_HPM_SEL, &exynos_clock->clk_src_kfc); - writel(CLK_DIV_KFC_VAL, &exynos_clock->clk_div_kfc0); + write32(&exynos_clock->clk_src_kfc, SRC_KFC_HPM_SEL); + write32(&exynos_clock->clk_div_kfc0, CLK_DIV_KFC_VAL); /* switch A7 clock source to OSC clock before changing KPLL */ clrbits_le32(&exynos_clock->clk_src_kfc, KPLL_FOUT); /* Set KPLL*/ - writel(KPLL_CON1_VAL, &exynos_clock->kpll_con1); + write32(&exynos_clock->kpll_con1, KPLL_CON1_VAL); val = set_pll(0x190, 0x4, 0x2); - writel(val, &exynos_clock->kpll_con0); - while ((readl(&exynos_clock->kpll_con0) & PLL_LOCKED) == 0) + write32(&exynos_clock->kpll_con0, val); + while ((read32(&exynos_clock->kpll_con0) & PLL_LOCKED) == 0) ; /* now it is safe to switch to KPLL */ setbits_le32(&exynos_clock->clk_src_kfc, KPLL_FOUT); /* Set MPLL */ - writel(MPLL_CON1_VAL, &exynos_clock->mpll_con1); + write32(&exynos_clock->mpll_con1, MPLL_CON1_VAL); val = set_pll(0xc8, 0x3, 0x1); - writel(val, &exynos_clock->mpll_con0); - while ((readl(&exynos_clock->mpll_con0) & PLL_LOCKED) == 0) + write32(&exynos_clock->mpll_con0, val); + while ((read32(&exynos_clock->mpll_con0) & PLL_LOCKED) == 0) ; /* Set DPLL */ - writel(DPLL_CON1_VAL, &exynos_clock->dpll_con1); + write32(&exynos_clock->dpll_con1, DPLL_CON1_VAL); val = set_pll(0x190, 0x4, 0x2); - writel(val, &exynos_clock->dpll_con0); - while ((readl(&exynos_clock->dpll_con0) & PLL_LOCKED) == 0) + write32(&exynos_clock->dpll_con0, val); + while ((read32(&exynos_clock->dpll_con0) & PLL_LOCKED) == 0) ; /* Set EPLL */ - writel(EPLL_CON2_VAL, &exynos_clock->epll_con2); - writel(EPLL_CON1_VAL, &exynos_clock->epll_con1); + write32(&exynos_clock->epll_con2, EPLL_CON2_VAL); + write32(&exynos_clock->epll_con1, EPLL_CON1_VAL); val = set_pll(0x64, 0x2, 0x1); - writel(val, &exynos_clock->epll_con0); - while ((readl(&exynos_clock->epll_con0) & PLL_LOCKED) == 0) + write32(&exynos_clock->epll_con0, val); + while ((read32(&exynos_clock->epll_con0) & PLL_LOCKED) == 0) ; /* Set CPLL */ - writel(CPLL_CON1_VAL, &exynos_clock->cpll_con1); + write32(&exynos_clock->cpll_con1, CPLL_CON1_VAL); val = set_pll(0xde, 0x4, 0x1); - writel(val, &exynos_clock->cpll_con0); - while ((readl(&exynos_clock->cpll_con0) & PLL_LOCKED) == 0) + write32(&exynos_clock->cpll_con0, val); + while ((read32(&exynos_clock->cpll_con0) & PLL_LOCKED) == 0) ; /* Set IPLL */ - writel(IPLL_CON1_VAL, &exynos_clock->ipll_con1); + write32(&exynos_clock->ipll_con1, IPLL_CON1_VAL); val = set_pll(0xB9, 0x3, 0x2); - writel(val, &exynos_clock->ipll_con0); - while ((readl(&exynos_clock->ipll_con0) & PLL_LOCKED) == 0) + write32(&exynos_clock->ipll_con0, val); + while ((read32(&exynos_clock->ipll_con0) & PLL_LOCKED) == 0) ; /* Set VPLL */ - writel(VPLL_CON1_VAL, &exynos_clock->vpll_con1); + write32(&exynos_clock->vpll_con1, VPLL_CON1_VAL); val = set_pll(0xd7, 0x3, 0x2); - writel(val, &exynos_clock->vpll_con0); - while ((readl(&exynos_clock->vpll_con0) & PLL_LOCKED) == 0) + write32(&exynos_clock->vpll_con0, val); + while ((read32(&exynos_clock->vpll_con0) & PLL_LOCKED) == 0) ; /* Set BPLL */ - writel(BPLL_CON1_VAL, &exynos_clock->bpll_con1); + write32(&exynos_clock->bpll_con1, BPLL_CON1_VAL); val = set_pll(0xc8, 0x3, 0x1); - writel(val, &exynos_clock->bpll_con0); - while ((readl(&exynos_clock->bpll_con0) & PLL_LOCKED) == 0) + write32(&exynos_clock->bpll_con0, val); + while ((read32(&exynos_clock->bpll_con0) & PLL_LOCKED) == 0) ; /* Set SPLL */ - writel(SPLL_CON1_VAL, &exynos_clock->spll_con1); + write32(&exynos_clock->spll_con1, SPLL_CON1_VAL); val = set_pll(200, 0x3, 0x2); /* 400MHz */ - writel(val, &exynos_clock->spll_con0); - while ((readl(&exynos_clock->spll_con0) & PLL_LOCKED) == 0) + write32(&exynos_clock->spll_con0, val); + while ((read32(&exynos_clock->spll_con0) & PLL_LOCKED) == 0) ; /* We use RPLL as the source for FIMD video stream clock */ - writel(RPLL_CON1_VAL, &exynos_clock->rpll_con1); - writel(RPLL_CON2_VAL, &exynos_clock->rpll_con2); + write32(&exynos_clock->rpll_con1, RPLL_CON1_VAL); + write32(&exynos_clock->rpll_con2, RPLL_CON2_VAL); /* computed by gabe from first principles; u-boot is probably * wrong again */ val = set_pll(0xa0, 0x3, 0x2); - writel(val, &exynos_clock->rpll_con0); + write32(&exynos_clock->rpll_con0, val); /* note: this is a meaningless exercise. The hardware lock * detection does not work. So this just spins for some * time and is done. NO indication of success should attach * to this or any other spin on a con0 value. */ - while ((readl(&exynos_clock->rpll_con0) & PLL_LOCKED) == 0) + while ((read32(&exynos_clock->rpll_con0) & PLL_LOCKED) == 0) ; - writel(CLK_DIV_CDREX0_VAL, &exynos_clock->clk_div_cdrex0); - writel(CLK_DIV_CDREX1_VAL, &exynos_clock->clk_div_cdrex1); + write32(&exynos_clock->clk_div_cdrex0, CLK_DIV_CDREX0_VAL); + write32(&exynos_clock->clk_div_cdrex1, CLK_DIV_CDREX1_VAL); - writel(CLK_SRC_TOP0_VAL, &exynos_clock->clk_src_top0); - writel(CLK_SRC_TOP1_VAL, &exynos_clock->clk_src_top1); - writel(CLK_SRC_TOP2_VAL, &exynos_clock->clk_src_top2); - writel(CLK_SRC_TOP7_VAL, &exynos_clock->clk_src_top7); + write32(&exynos_clock->clk_src_top0, CLK_SRC_TOP0_VAL); + write32(&exynos_clock->clk_src_top1, CLK_SRC_TOP1_VAL); + write32(&exynos_clock->clk_src_top2, CLK_SRC_TOP2_VAL); + write32(&exynos_clock->clk_src_top7, CLK_SRC_TOP7_VAL); - writel(CLK_DIV_TOP0_VAL, &exynos_clock->clk_div_top0); - writel(CLK_DIV_TOP1_VAL, &exynos_clock->clk_div_top1); - writel(CLK_DIV_TOP2_VAL, &exynos_clock->clk_div_top2); + write32(&exynos_clock->clk_div_top0, CLK_DIV_TOP0_VAL); + write32(&exynos_clock->clk_div_top1, CLK_DIV_TOP1_VAL); + write32(&exynos_clock->clk_div_top2, CLK_DIV_TOP2_VAL); - writel(0, &exynos_clock->clk_src_top10); - writel(0, &exynos_clock->clk_src_top11); - writel(0, &exynos_clock->clk_src_top12); + write32(&exynos_clock->clk_src_top10, 0); + write32(&exynos_clock->clk_src_top11, 0); + write32(&exynos_clock->clk_src_top12, 0); - writel(CLK_SRC_TOP3_VAL, &exynos_clock->clk_src_top3); - writel(CLK_SRC_TOP4_VAL, &exynos_clock->clk_src_top4); - writel(CLK_SRC_TOP5_VAL, &exynos_clock->clk_src_top5); + write32(&exynos_clock->clk_src_top3, CLK_SRC_TOP3_VAL); + write32(&exynos_clock->clk_src_top4, CLK_SRC_TOP4_VAL); + write32(&exynos_clock->clk_src_top5, CLK_SRC_TOP5_VAL); /* DISP1 BLK CLK SELECTION */ - writel(CLK_SRC_DISP1_0_VAL, &exynos_clock->clk_src_disp10); - writel(CLK_DIV_DISP1_0_VAL, &exynos_clock->clk_div_disp10); + write32(&exynos_clock->clk_src_disp10, CLK_SRC_DISP1_0_VAL); + write32(&exynos_clock->clk_div_disp10, CLK_DIV_DISP1_0_VAL); /* AUDIO BLK */ - writel(AUDIO0_SEL_EPLL, &exynos_clock->clk_src_mau); - writel(DIV_MAU_VAL, &exynos_clock->clk_div_mau); + write32(&exynos_clock->clk_src_mau, AUDIO0_SEL_EPLL); + write32(&exynos_clock->clk_div_mau, DIV_MAU_VAL); /* FSYS */ - writel(CLK_SRC_FSYS0_VAL, &exynos_clock->clk_src_fsys); - writel(CLK_DIV_FSYS0_VAL, &exynos_clock->clk_div_fsys0); - writel(CLK_DIV_FSYS1_VAL, &exynos_clock->clk_div_fsys1); - writel(CLK_DIV_FSYS2_VAL, &exynos_clock->clk_div_fsys2); - - writel(CLK_SRC_ISP_VAL, &exynos_clock->clk_src_isp); - writel(CLK_DIV_ISP0_VAL, &exynos_clock->clk_div_isp0); - writel(CLK_DIV_ISP1_VAL, &exynos_clock->clk_div_isp1); - - writel(CLK_SRC_PERIC0_VAL, &exynos_clock->clk_src_peric0); - writel(CLK_SRC_PERIC1_VAL, &exynos_clock->clk_src_peric1); - - writel(CLK_DIV_PERIC0_VAL, &exynos_clock->clk_div_peric0); - writel(CLK_DIV_PERIC1_VAL, &exynos_clock->clk_div_peric1); - writel(CLK_DIV_PERIC2_VAL, &exynos_clock->clk_div_peric2); - writel(CLK_DIV_PERIC3_VAL, &exynos_clock->clk_div_peric3); - writel(CLK_DIV_PERIC4_VAL, &exynos_clock->clk_div_peric4); - - writel(CLK_DIV_CPERI1_VAL, &exynos_clock->clk_div_cperi1); - - writel(CLK_DIV2_RATIO, &exynos_clock->clkdiv2_ratio); - writel(CLK_DIV4_RATIO, &exynos_clock->clkdiv4_ratio); - writel(CLK_DIV_G2D, &exynos_clock->clk_div_g2d); - - writel(CLK_SRC_CPU_VAL, &exynos_clock->clk_src_cpu); - writel(CLK_SRC_TOP6_VAL, &exynos_clock->clk_src_top6); - writel(CLK_SRC_CDREX_VAL, &exynos_clock->clk_src_cdrex); - writel(CLK_SRC_KFC_VAL, &exynos_clock->clk_src_kfc); + write32(&exynos_clock->clk_src_fsys, CLK_SRC_FSYS0_VAL); + write32(&exynos_clock->clk_div_fsys0, CLK_DIV_FSYS0_VAL); + write32(&exynos_clock->clk_div_fsys1, CLK_DIV_FSYS1_VAL); + write32(&exynos_clock->clk_div_fsys2, CLK_DIV_FSYS2_VAL); + + write32(&exynos_clock->clk_src_isp, CLK_SRC_ISP_VAL); + write32(&exynos_clock->clk_div_isp0, CLK_DIV_ISP0_VAL); + write32(&exynos_clock->clk_div_isp1, CLK_DIV_ISP1_VAL); + + write32(&exynos_clock->clk_src_peric0, CLK_SRC_PERIC0_VAL); + write32(&exynos_clock->clk_src_peric1, CLK_SRC_PERIC1_VAL); + + write32(&exynos_clock->clk_div_peric0, CLK_DIV_PERIC0_VAL); + write32(&exynos_clock->clk_div_peric1, CLK_DIV_PERIC1_VAL); + write32(&exynos_clock->clk_div_peric2, CLK_DIV_PERIC2_VAL); + write32(&exynos_clock->clk_div_peric3, CLK_DIV_PERIC3_VAL); + write32(&exynos_clock->clk_div_peric4, CLK_DIV_PERIC4_VAL); + + write32(&exynos_clock->clk_div_cperi1, CLK_DIV_CPERI1_VAL); + + write32(&exynos_clock->clkdiv2_ratio, CLK_DIV2_RATIO); + write32(&exynos_clock->clkdiv4_ratio, CLK_DIV4_RATIO); + write32(&exynos_clock->clk_div_g2d, CLK_DIV_G2D); + + write32(&exynos_clock->clk_src_cpu, CLK_SRC_CPU_VAL); + write32(&exynos_clock->clk_src_top6, CLK_SRC_TOP6_VAL); + write32(&exynos_clock->clk_src_cdrex, CLK_SRC_CDREX_VAL); + write32(&exynos_clock->clk_src_kfc, CLK_SRC_KFC_VAL); } void clock_gate(void) diff --git a/src/soc/samsung/exynos5420/dmc_common.c b/src/soc/samsung/exynos5420/dmc_common.c index cb1546e61a..c6fe09d705 100644 --- a/src/soc/samsung/exynos5420/dmc_common.c +++ b/src/soc/samsung/exynos5420/dmc_common.c @@ -45,19 +45,19 @@ int dmc_config_zq(struct mem_timings *mem, val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT; val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT; val |= ZQ_CLK_DIV_EN; - writel(val, &phy0_ctrl->phy_con16); - writel(val, &phy1_ctrl->phy_con16); + write32(&phy0_ctrl->phy_con16, val); + write32(&phy1_ctrl->phy_con16, val); /* Disable termination */ if (mem->zq_mode_noterm) val |= PHY_CON16_ZQ_MODE_NOTERM_MASK; - writel(val, &phy0_ctrl->phy_con16); - writel(val, &phy1_ctrl->phy_con16); + write32(&phy0_ctrl->phy_con16, val); + write32(&phy1_ctrl->phy_con16, val); /* ZQ_MANUAL_START: Enable */ val |= ZQ_MANUAL_STR; - writel(val, &phy0_ctrl->phy_con16); - writel(val, &phy1_ctrl->phy_con16); + write32(&phy0_ctrl->phy_con16, val); + write32(&phy1_ctrl->phy_con16, val); /* ZQ_MANUAL_START: Disable */ val &= ~ZQ_MANUAL_STR; @@ -67,22 +67,22 @@ int dmc_config_zq(struct mem_timings *mem, * we are looping for the ZQ_init to complete. */ i = ZQ_INIT_TIMEOUT; - while ((readl(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { + while ((read32(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { udelay(1); i--; } if (!i) return -1; - writel(val, &phy0_ctrl->phy_con16); + write32(&phy0_ctrl->phy_con16, val); i = ZQ_INIT_TIMEOUT; - while ((readl(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { + while ((read32(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { udelay(1); i--; } if (!i) return -1; - writel(val, &phy1_ctrl->phy_con16); + write32(&phy1_ctrl->phy_con16, val); return 0; } @@ -93,18 +93,18 @@ void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode) if (mode == DDR_MODE_DDR3) { val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE; - writel(val, &dmc->phycontrol0); + write32(&dmc->phycontrol0, val); } /* Update DLL Information: Force DLL Resynchronization */ - val = readl(&dmc->phycontrol0); + val = read32(&dmc->phycontrol0); val |= FP_RSYNC; - writel(val, &dmc->phycontrol0); + write32(&dmc->phycontrol0, val); /* Reset Force DLL Resynchronization */ - val = readl(&dmc->phycontrol0); + val = read32(&dmc->phycontrol0); val &= ~FP_RSYNC; - writel(val, &dmc->phycontrol0); + write32(&dmc->phycontrol0, val); } void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) @@ -121,7 +121,7 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) mask |= chip << DIRECT_CMD_CHIP_SHIFT; /* Sending NOP command */ - writel(DIRECT_CMD_NOP | mask, &dmc->directcmd); + write32(&dmc->directcmd, DIRECT_CMD_NOP | mask); /* * TODO(alim.akhtar@samsung.com): Do we need these @@ -132,15 +132,15 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) /* Sending EMRS/MRS commands */ for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) { - writel(mem->direct_cmd_msr[i] | mask, - &dmc->directcmd); + write32(&dmc->directcmd, + mem->direct_cmd_msr[i] | mask); udelay(100); } if (mem->send_zq_init) { /* Sending ZQINIT command */ - writel(DIRECT_CMD_ZQINIT | mask, - &dmc->directcmd); + write32(&dmc->directcmd, + DIRECT_CMD_ZQINIT | mask); /* * FIXME: This was originally sdelay(10000) * in the imported u-boot code. That may have @@ -166,7 +166,7 @@ void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc) mask |= chip << DIRECT_CMD_CHIP_SHIFT; /* PALL (all banks precharge) CMD */ - writel(DIRECT_CMD_PALL | mask, &dmc->directcmd); + write32(&dmc->directcmd, DIRECT_CMD_PALL | mask); udelay(100); } } diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c index 8186b6dbdf..6972618ac3 100644 --- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c @@ -47,40 +47,40 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) /* Enable BYPASS mode */ setbits_le32(&exynos_clock->bpll_con1, BYPASS_EN); - writel(MUX_BPLL_SEL_FOUTBPLL, &exynos_clock->clk_src_cdrex); + write32(&exynos_clock->clk_src_cdrex, MUX_BPLL_SEL_FOUTBPLL); do { - val = readl(&exynos_clock->clk_mux_stat_cdrex); + val = read32(&exynos_clock->clk_mux_stat_cdrex); val &= BPLL_SEL_MASK; } while (val != FOUTBPLL); clrbits_le32(&exynos_clock->bpll_con1, BYPASS_EN); /* Specify the DDR memory type as DDR3 */ - val = readl(&exynos_phy0_control->phy_con0); + val = read32(&exynos_phy0_control->phy_con0); val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); val |= (mem->mem_type << PHY_CON0_CTRL_DDR_MODE_SHIFT); - writel(val, &exynos_phy0_control->phy_con0); + write32(&exynos_phy0_control->phy_con0, val); - val = readl(&exynos_phy1_control->phy_con0); + val = read32(&exynos_phy1_control->phy_con0); val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); val |= (mem->mem_type << PHY_CON0_CTRL_DDR_MODE_SHIFT); - writel(val, &exynos_phy1_control->phy_con0); + write32(&exynos_phy1_control->phy_con0, val); /* Set Read Latency and Burst Length for PHY0 and PHY1 */ val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT); - writel(val, &exynos_phy0_control->phy_con42); - writel(val, &exynos_phy1_control->phy_con42); + write32(&exynos_phy0_control->phy_con42, val); + write32(&exynos_phy1_control->phy_con42, val); - val = readl(&exynos_phy0_control->phy_con26); + val = read32(&exynos_phy0_control->phy_con26); val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET); val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET); - writel(val, &exynos_phy0_control->phy_con26); + write32(&exynos_phy0_control->phy_con26, val); - val = readl(&exynos_phy1_control->phy_con26); + val = read32(&exynos_phy1_control->phy_con26); val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET); val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET); - writel(val, &exynos_phy1_control->phy_con26); + write32(&exynos_phy1_control->phy_con26, val); /* Set Driver strength for CK, CKE, CS & CA to 0x7 * Set Driver strength for Data Slice 0~3 to 0x6 @@ -89,8 +89,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) (0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET); val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) | (0x7 << DA_1_DS_OFFSET) | (0x7 << DA_0_DS_OFFSET); - writel(val, &exynos_phy0_control->phy_con39); - writel(val, &exynos_phy1_control->phy_con39); + write32(&exynos_phy0_control->phy_con39, val); + write32(&exynos_phy1_control->phy_con39, val); /* ZQ Calibration */ if (dmc_config_zq(mem, exynos_phy0_control, exynos_phy1_control)) @@ -100,31 +100,27 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) clrbits_le32(&exynos_phy1_control->phy_con16, ZQ_CLK_DIV_EN); /* DQ Signal */ - val = readl(&exynos_phy0_control->phy_con14); + val = read32(&exynos_phy0_control->phy_con14); val |= mem->phy0_pulld_dqs; - writel(val, &exynos_phy0_control->phy_con14); - val = readl(&exynos_phy1_control->phy_con14); + write32(&exynos_phy0_control->phy_con14, val); + val = read32(&exynos_phy1_control->phy_con14); val |= mem->phy1_pulld_dqs; - writel(val, &exynos_phy1_control->phy_con14); + write32(&exynos_phy1_control->phy_con14, val); val = MEM_TERM_EN | PHY_TERM_EN; - writel(val, &exynos_drex0->phycontrol0); - writel(val, &exynos_drex1->phycontrol0); - - writel(mem->concontrol | - (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | - (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), - &exynos_drex0->concontrol); - writel(mem->concontrol | - (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | - (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), - &exynos_drex1->concontrol); + write32(&exynos_drex0->phycontrol0, val); + write32(&exynos_drex1->phycontrol0, val); + + write32(&exynos_drex0->concontrol, + mem->concontrol | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)); + write32(&exynos_drex1->concontrol, + mem->concontrol | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)); do { - val = readl(&exynos_drex0->phystatus); + val = read32(&exynos_drex0->phystatus); } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE); do { - val = readl(&exynos_drex1->phystatus); + val = read32(&exynos_drex1->phystatus); } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE); clrbits_le32(&exynos_drex0->concontrol, DFI_INIT_START); @@ -134,41 +130,41 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) update_reset_dll(exynos_drex1, mem->mem_type); /* MEMBASECONFIG0 (CS0) */ - writel(mem->membaseconfig0, &exynos_tzasc0->membaseconfig0); - writel(mem->membaseconfig0, &exynos_tzasc1->membaseconfig0); + write32(&exynos_tzasc0->membaseconfig0, mem->membaseconfig0); + write32(&exynos_tzasc1->membaseconfig0, mem->membaseconfig0); /* MEMBASECONFIG1 (CS1) */ if (mem->chips_per_channel == 2) { - writel(mem->membaseconfig1, &exynos_tzasc0->membaseconfig1); - writel(mem->membaseconfig1, &exynos_tzasc1->membaseconfig1); + write32(&exynos_tzasc0->membaseconfig1, mem->membaseconfig1); + write32(&exynos_tzasc1->membaseconfig1, mem->membaseconfig1); } /* Memory Channel Interleaving Size * Exynos5420 Channel interleaving = 128 bytes */ /* MEMCONFIG0/1 */ - writel(mem->memconfig, &exynos_tzasc0->memconfig0); - writel(mem->memconfig, &exynos_tzasc1->memconfig0); - writel(mem->memconfig, &exynos_tzasc0->memconfig1); - writel(mem->memconfig, &exynos_tzasc1->memconfig1); + write32(&exynos_tzasc0->memconfig0, mem->memconfig); + write32(&exynos_tzasc1->memconfig0, mem->memconfig); + write32(&exynos_tzasc0->memconfig1, mem->memconfig); + write32(&exynos_tzasc1->memconfig1, mem->memconfig); /* Precharge Configuration */ - writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, - &exynos_drex0->prechconfig0); - writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, - &exynos_drex1->prechconfig0); + write32(&exynos_drex0->prechconfig0, + mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT); + write32(&exynos_drex1->prechconfig0, + mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT); /* TimingRow, TimingData, TimingPower and Timingref * values as per Memory AC parameters */ - writel(mem->timing_ref, &exynos_drex0->timingref); - writel(mem->timing_ref, &exynos_drex1->timingref); - writel(mem->timing_row, &exynos_drex0->timingrow); - writel(mem->timing_row, &exynos_drex1->timingrow); - writel(mem->timing_data, &exynos_drex0->timingdata); - writel(mem->timing_data, &exynos_drex1->timingdata); - writel(mem->timing_power, &exynos_drex0->timingpower); - writel(mem->timing_power, &exynos_drex1->timingpower); + write32(&exynos_drex0->timingref, mem->timing_ref); + write32(&exynos_drex1->timingref, mem->timing_ref); + write32(&exynos_drex0->timingrow, mem->timing_row); + write32(&exynos_drex1->timingrow, mem->timing_row); + write32(&exynos_drex0->timingdata, mem->timing_data); + write32(&exynos_drex1->timingdata, mem->timing_data); + write32(&exynos_drex0->timingpower, mem->timing_power); + write32(&exynos_drex1->timingpower, mem->timing_power); if (reset) { /* Send NOP, MRS and ZQINIT commands. @@ -189,8 +185,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) * release pad retention and retain the memory content until the * initialization is complete. */ - writel(PAD_RETENTION_DRAM_COREBLK_VAL, - &exynos_power->padret_dram_cblk_opt); + write32(&exynos_power->padret_dram_cblk_opt, + PAD_RETENTION_DRAM_COREBLK_VAL); do { ret = read32(&exynos_power->padret_dram_status); } while (ret != 0x1); @@ -201,57 +197,55 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) */ for (i = 0; i < 128; i++) { for (chip = 0; chip < mem->chips_to_configure; chip++) { - writel(DIRECT_CMD_REFA | - (chip << DIRECT_CMD_CHIP_SHIFT), - &exynos_drex0->directcmd); - writel(DIRECT_CMD_REFA | - (chip << DIRECT_CMD_CHIP_SHIFT), - &exynos_drex1->directcmd); + write32(&exynos_drex0->directcmd, + DIRECT_CMD_REFA | (chip << DIRECT_CMD_CHIP_SHIFT)); + write32(&exynos_drex1->directcmd, + DIRECT_CMD_REFA | (chip << DIRECT_CMD_CHIP_SHIFT)); } } } if (mem->gate_leveling_enable) { - writel(PHY_CON0_RESET_VAL, &exynos_phy0_control->phy_con0); - writel(PHY_CON0_RESET_VAL, &exynos_phy1_control->phy_con0); + write32(&exynos_phy0_control->phy_con0, PHY_CON0_RESET_VAL); + write32(&exynos_phy1_control->phy_con0, PHY_CON0_RESET_VAL); setbits_le32(&exynos_phy0_control->phy_con0, P0_CMD_EN); setbits_le32(&exynos_phy1_control->phy_con0, P0_CMD_EN); val = PHY_CON2_RESET_VAL; val |= INIT_DESKEW_EN; - writel(val, &exynos_phy0_control->phy_con2); - writel(val, &exynos_phy1_control->phy_con2); + write32(&exynos_phy0_control->phy_con2, val); + write32(&exynos_phy1_control->phy_con2, val); - val = readl(&exynos_phy0_control->phy_con1); + val = read32(&exynos_phy0_control->phy_con1); val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); - writel(val, &exynos_phy0_control->phy_con1); + write32(&exynos_phy0_control->phy_con1, val); - val = readl(&exynos_phy1_control->phy_con1); + val = read32(&exynos_phy1_control->phy_con1); val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); - writel(val, &exynos_phy1_control->phy_con1); + write32(&exynos_phy1_control->phy_con1, val); - nLockR = readl(&exynos_phy0_control->phy_con13); + nLockR = read32(&exynos_phy0_control->phy_con13); nLockW_phy0 = (nLockR & CTRL_LOCK_COARSE_MASK) >> 2; - nLockR = readl(&exynos_phy0_control->phy_con12); + nLockR = read32(&exynos_phy0_control->phy_con12); nLockR &= ~CTRL_DLL_ON; nLockR |= nLockW_phy0; - writel(nLockR, &exynos_phy0_control->phy_con12); + write32(&exynos_phy0_control->phy_con12, nLockR); - nLockR = readl(&exynos_phy1_control->phy_con13); + nLockR = read32(&exynos_phy1_control->phy_con13); nLockW_phy1 = (nLockR & CTRL_LOCK_COARSE_MASK) >> 2; - nLockR = readl(&exynos_phy1_control->phy_con12); + nLockR = read32(&exynos_phy1_control->phy_con12); nLockR &= ~CTRL_DLL_ON; nLockR |= nLockW_phy1; - writel(nLockR, &exynos_phy1_control->phy_con12); + write32(&exynos_phy1_control->phy_con12, nLockR); val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4; for (chip = 0; chip < mem->chips_to_configure; chip++) { - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &exynos_drex0->directcmd); - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &exynos_drex1->directcmd); + write32(&exynos_drex0->directcmd, + val | (chip << DIRECT_CMD_CHIP_SHIFT)); + write32(&exynos_drex1->directcmd, + val | (chip << DIRECT_CMD_CHIP_SHIFT)); } setbits_le32(&exynos_phy0_control->phy_con2, RDLVL_GATE_EN); @@ -260,17 +254,17 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) setbits_le32(&exynos_phy0_control->phy_con0, CTRL_SHGATE); setbits_le32(&exynos_phy1_control->phy_con0, CTRL_SHGATE); - val = readl(&exynos_phy0_control->phy_con1); + val = read32(&exynos_phy0_control->phy_con1); val &= ~(CTRL_GATEDURADJ_MASK); - writel(val, &exynos_phy0_control->phy_con1); + write32(&exynos_phy0_control->phy_con1, val); - val = readl(&exynos_phy1_control->phy_con1); + val = read32(&exynos_phy1_control->phy_con1); val &= ~(CTRL_GATEDURADJ_MASK); - writel(val, &exynos_phy1_control->phy_con1); + write32(&exynos_phy1_control->phy_con1, val); - writel(CTRL_RDLVL_GATE_ENABLE, &exynos_drex0->rdlvl_config); + write32(&exynos_drex0->rdlvl_config, CTRL_RDLVL_GATE_ENABLE); i = TIMEOUT; - while (((readl(&exynos_drex0->phystatus) & RDLVL_COMPLETE_CHO) + while (((read32(&exynos_drex0->phystatus) & RDLVL_COMPLETE_CHO) != RDLVL_COMPLETE_CHO) && (i > 0)) { /* * TODO(waihong): Comment on how long this take to @@ -281,11 +275,11 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) } if (!i) return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; - writel(CTRL_RDLVL_GATE_DISABLE, &exynos_drex0->rdlvl_config); + write32(&exynos_drex0->rdlvl_config, CTRL_RDLVL_GATE_DISABLE); - writel(CTRL_RDLVL_GATE_ENABLE, &exynos_drex1->rdlvl_config); + write32(&exynos_drex1->rdlvl_config, CTRL_RDLVL_GATE_ENABLE); i = TIMEOUT; - while (((readl(&exynos_drex1->phystatus) & RDLVL_COMPLETE_CHO) + while (((read32(&exynos_drex1->phystatus) & RDLVL_COMPLETE_CHO) != RDLVL_COMPLETE_CHO) && (i > 0)) { /* * TODO(waihong): Comment on how long this take to @@ -296,23 +290,23 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) } if (!i) return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; - writel(CTRL_RDLVL_GATE_DISABLE, &exynos_drex1->rdlvl_config); + write32(&exynos_drex1->rdlvl_config, CTRL_RDLVL_GATE_DISABLE); - writel(0, &exynos_phy0_control->phy_con14); - writel(0, &exynos_phy1_control->phy_con14); + write32(&exynos_phy0_control->phy_con14, 0); + write32(&exynos_phy1_control->phy_con14, 0); val = (0x3 << DIRECT_CMD_BANK_SHIFT); for (chip = 0; chip < mem->chips_to_configure; chip++) { - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &exynos_drex0->directcmd); - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &exynos_drex1->directcmd); + write32(&exynos_drex0->directcmd, + val | (chip << DIRECT_CMD_CHIP_SHIFT)); + write32(&exynos_drex1->directcmd, + val | (chip << DIRECT_CMD_CHIP_SHIFT)); } /* Common Settings for Leveling */ val = PHY_CON12_RESET_VAL; - writel((val + nLockW_phy0), &exynos_phy0_control->phy_con12); - writel((val + nLockW_phy1), &exynos_phy1_control->phy_con12); + write32(&exynos_phy0_control->phy_con12, (val + nLockW_phy0)); + write32(&exynos_phy1_control->phy_con12, (val + nLockW_phy1)); setbits_le32(&exynos_phy0_control->phy_con2, DLL_DESKEW_EN); setbits_le32(&exynos_phy1_control->phy_con2, DLL_DESKEW_EN); @@ -322,22 +316,18 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) dmc_config_prech(mem, exynos_drex0); dmc_config_prech(mem, exynos_drex1); - writel(mem->memcontrol, &exynos_drex0->memcontrol); - writel(mem->memcontrol, &exynos_drex1->memcontrol); + write32(&exynos_drex0->memcontrol, mem->memcontrol); + write32(&exynos_drex1->memcontrol, mem->memcontrol); /* * Set DMC Concontrol: Enable auto-refresh counter, provide * read data fetch cycles and enable DREX auto set powerdown * for input buffer of I/O in none read memory state. */ - writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | - (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)| - DMC_CONCONTROL_IO_PD_CON(0x2), - &exynos_drex0->concontrol); - writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | - (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)| - DMC_CONCONTROL_IO_PD_CON(0x2), - &exynos_drex1->concontrol); + write32(&exynos_drex0->concontrol, + mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | DMC_CONCONTROL_IO_PD_CON(0x2)); + write32(&exynos_drex1->concontrol, + mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | DMC_CONCONTROL_IO_PD_CON(0x2)); /* Enable Clock Gating Control for DMC * this saves around 25 mw dmc power as compared to the power diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c index 5a3adf907e..f56148fec3 100644 --- a/src/soc/samsung/exynos5420/dp_lowlevel.c +++ b/src/soc/samsung/exynos5420/dp_lowlevel.c @@ -55,7 +55,7 @@ static inline unsigned long fradl(void *v) { #define lread32(a) fradl((void *)(a)) #else -#define lwrite32(a,b) writel((unsigned long)(a), (void *)(b)) +#define lwrite32(a,b) write32((void *)(b), (unsigned long)(a)) #define lread32(a) read32((void *)(a)) #endif diff --git a/src/soc/samsung/exynos5420/fimd.c b/src/soc/samsung/exynos5420/fimd.c index dfd123254c..8059f49f1a 100644 --- a/src/soc/samsung/exynos5420/fimd.c +++ b/src/soc/samsung/exynos5420/fimd.c @@ -47,8 +47,8 @@ static inline unsigned long fradl(void *v) { #define lreadl(a) fradl((void *)(a)) #else -#define lwritel(a,b) writel((unsigned long)(a), (void *)(b)) -#define lreadl(a) readl((void *)(a)) +#define lwritel(a,b) write32((void *)(b), (unsigned long)(a)) +#define lreadl(a) read32((void *)(a)) #endif /* not sure where we want this so ... */ diff --git a/src/soc/samsung/exynos5420/gpio.c b/src/soc/samsung/exynos5420/gpio.c index 92cdc28fc0..0a53018b3f 100644 --- a/src/soc/samsung/exynos5420/gpio.c +++ b/src/soc/samsung/exynos5420/gpio.c @@ -82,10 +82,10 @@ void gpio_cfg_pin(int gpio, int cfg) unsigned int value; struct gpio_bank *bank = gpio_get_bank(gpio); - value = readl(&bank->con); + value = read32(&bank->con); value &= ~CON_MASK(GPIO_BIT(gpio)); value |= CON_SFR(GPIO_BIT(gpio), cfg); - writel(value, &bank->con); + write32(&bank->con, value); } static int gpio_get_cfg(int gpio) @@ -93,7 +93,7 @@ static int gpio_get_cfg(int gpio) struct gpio_bank *bank = gpio_get_bank(gpio); int shift = GPIO_BIT(gpio) << 2; - return (readl(&bank->con) & CON_MASK(GPIO_BIT(gpio))) >> shift; + return (read32(&bank->con) & CON_MASK(GPIO_BIT(gpio))) >> shift; } void gpio_set_pull(int gpio, int mode) @@ -101,7 +101,7 @@ void gpio_set_pull(int gpio, int mode) unsigned int value; struct gpio_bank *bank = gpio_get_bank(gpio); - value = readl(&bank->pull); + value = read32(&bank->pull); value &= ~PULL_MASK(GPIO_BIT(gpio)); switch (mode) { @@ -113,7 +113,7 @@ void gpio_set_pull(int gpio, int mode) break; } - writel(value, &bank->pull); + write32(&bank->pull, value); } void gpio_set_drv(int gpio, int mode) @@ -121,7 +121,7 @@ void gpio_set_drv(int gpio, int mode) unsigned int value; struct gpio_bank *bank = gpio_get_bank(gpio); - value = readl(&bank->drv); + value = read32(&bank->drv); value &= ~DRV_MASK(GPIO_BIT(gpio)); switch (mode) { @@ -135,7 +135,7 @@ void gpio_set_drv(int gpio, int mode) return; } - writel(value, &bank->drv); + write32(&bank->drv, value); } void gpio_set_rate(int gpio, int mode) @@ -143,7 +143,7 @@ void gpio_set_rate(int gpio, int mode) unsigned int value; struct gpio_bank *bank = gpio_get_bank(gpio); - value = readl(&bank->drv); + value = read32(&bank->drv); value &= ~RATE_MASK(GPIO_BIT(gpio)); switch (mode) { @@ -155,7 +155,7 @@ void gpio_set_rate(int gpio, int mode) return; } - writel(value, &bank->drv); + write32(&bank->drv, value); } int gpio_direction_input(unsigned gpio) @@ -170,11 +170,11 @@ int gpio_direction_output(unsigned gpio, int value) unsigned int val; struct gpio_bank *bank = gpio_get_bank(gpio); - val = readl(&bank->dat); + val = read32(&bank->dat); val &= ~DAT_MASK(GPIO_BIT(gpio)); if (value) val |= DAT_SET(GPIO_BIT(gpio)); - writel(val, &bank->dat); + write32(&bank->dat, val); gpio_cfg_pin(gpio, GPIO_OUTPUT); @@ -186,7 +186,7 @@ int gpio_get_value(unsigned gpio) unsigned int value; struct gpio_bank *bank = gpio_get_bank(gpio); - value = readl(&bank->dat); + value = read32(&bank->dat); return !!(value & DAT_MASK(GPIO_BIT(gpio))); } @@ -195,11 +195,11 @@ int gpio_set_value(unsigned gpio, int value) unsigned int val; struct gpio_bank *bank = gpio_get_bank(gpio); - val = readl(&bank->dat); + val = read32(&bank->dat); val &= ~DAT_MASK(GPIO_BIT(gpio)); if (value) val |= DAT_SET(GPIO_BIT(gpio)); - writel(val, &bank->dat); + write32(&bank->dat, val); return 0; } diff --git a/src/soc/samsung/exynos5420/i2c.c b/src/soc/samsung/exynos5420/i2c.c index 28e3f0c331..1b541b7326 100644 --- a/src/soc/samsung/exynos5420/i2c.c +++ b/src/soc/samsung/exynos5420/i2c.c @@ -270,7 +270,7 @@ static int hsi2c_get_clk_details(struct i2c_bus *i2c, int *div, int *cycle, * temp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) * temp1 = (TSCLK_L + TSCLK_H + 2) */ - uint32_t flt_cycle = (readl(®s->i2c_conf) >> 16) & 0x7; + uint32_t flt_cycle = (read32(®s->i2c_conf) >> 16) & 0x7; int temp = (clkin / op_clk) - 8 - 2 * flt_cycle; // CLK_DIV max is 256. @@ -310,18 +310,18 @@ static void hsi2c_ch_init(struct i2c_bus *i2c, unsigned int frequency) uint32_t timing_sla = data_hd << 0; // Currently operating in fast speed mode. - writel(timing_fs1, ®s->i2c_timing_fs1); - writel(timing_fs2, ®s->i2c_timing_fs2); - writel(timing_fs3, ®s->i2c_timing_fs3); - writel(timing_sla, ®s->i2c_timing_sla); + write32(®s->i2c_timing_fs1, timing_fs1); + write32(®s->i2c_timing_fs2, timing_fs2); + write32(®s->i2c_timing_fs3, timing_fs3); + write32(®s->i2c_timing_sla, timing_sla); // Clear to enable timeout. - writel(readl(®s->i2c_timeout) & ~Hsi2cTimeoutEn, - ®s->i2c_timeout); + write32(®s->i2c_timeout, + read32(®s->i2c_timeout) & ~Hsi2cTimeoutEn); - writel(Hsi2cTrailingCount, ®s->usi_trailing_ctl); - writel(Hsi2cRxfifoEn | Hsi2cTxfifoEn, ®s->usi_fifo_ctl); - writel(readl(®s->i2c_conf) | Hsi2cAutoMode, ®s->i2c_conf); + write32(®s->usi_trailing_ctl, Hsi2cTrailingCount); + write32(®s->usi_fifo_ctl, Hsi2cRxfifoEn | Hsi2cTxfifoEn); + write32(®s->i2c_conf, read32(®s->i2c_conf) | Hsi2cAutoMode); } static void hsi2c_reset(struct i2c_bus *i2c) @@ -329,8 +329,8 @@ static void hsi2c_reset(struct i2c_bus *i2c) struct hsi2c_regs *regs = i2c->hsregs; // Set and clear the bit for reset. - writel(readl(®s->usi_ctl) | Hsi2cSwRst, ®s->usi_ctl); - writel(readl(®s->usi_ctl) & ~Hsi2cSwRst, ®s->usi_ctl); + write32(®s->usi_ctl, read32(®s->usi_ctl) | Hsi2cSwRst); + write32(®s->usi_ctl, read32(®s->usi_ctl) & ~Hsi2cSwRst); /* FIXME: This just assumes 100KHz as a default bus freq */ hsi2c_ch_init(i2c, 100000); @@ -356,13 +356,13 @@ static void i2c_ch_init(struct i2c_bus *i2c, int speed) // Set prescaler, divisor according to freq, also set ACKGEN, IRQ. val = (div & 0x0f) | 0xa0 | ((pres == 512) ? 0x40 : 0); - writel(val, ®s->con); + write32(®s->con, val); // Init to SLAVE RECEIVE mode and clear I2CADDn. - writel(0, ®s->stat); - writel(0, ®s->add); + write32(®s->stat, 0); + write32(®s->add, 0); // program Master Transmit (and implicit STOP). - writel(I2cStatMasterXmit | I2cStatEnable, ®s->stat); + write32(®s->stat, I2cStatMasterXmit | I2cStatEnable); } void i2c_init(unsigned bus, int speed, int slaveadd) @@ -430,7 +430,7 @@ static int hsi2c_senddata(struct hsi2c_regs *regs, const uint8_t *data, int len) { while (!hsi2c_check_transfer(regs) && len) { if (!(read32(®s->usi_fifo_stat) & Hsi2cTxFifoFull)) { - writel(*data++, ®s->usi_txdata); + write32(®s->usi_txdata, *data++); len--; } } @@ -452,7 +452,7 @@ static int hsi2c_segment(struct i2c_seg *seg, struct hsi2c_regs *regs, int stop) { const uint32_t usi_ctl = Hsi2cFuncModeI2c | Hsi2cMaster; - writel(HSI2C_SLV_ADDR_MAS(seg->chip), ®s->i2c_addr); + write32(®s->i2c_addr, HSI2C_SLV_ADDR_MAS(seg->chip)); /* * We really only want to stop after this transaction (I think) if the @@ -465,14 +465,14 @@ static int hsi2c_segment(struct i2c_seg *seg, struct hsi2c_regs *regs, int stop) seg->len | Hsi2cMasterRun | Hsi2cStopAfterTrans; if (seg->read) { - writel(usi_ctl | Hsi2cRxchon, ®s->usi_ctl); - writel(autoconf | Hsi2cReadWrite, ®s->i2c_auto_conf); + write32(®s->usi_ctl, usi_ctl | Hsi2cRxchon); + write32(®s->i2c_auto_conf, autoconf | Hsi2cReadWrite); if (hsi2c_recvdata(regs, seg->buf, seg->len)) return -1; } else { - writel(usi_ctl | Hsi2cTxchon, ®s->usi_ctl); - writel(autoconf, ®s->i2c_auto_conf); + write32(®s->usi_ctl, usi_ctl | Hsi2cTxchon); + write32(®s->i2c_auto_conf, autoconf); if (hsi2c_senddata(regs, seg->buf, seg->len)) return -1; @@ -481,7 +481,7 @@ static int hsi2c_segment(struct i2c_seg *seg, struct hsi2c_regs *regs, int stop) if (hsi2c_wait_for_transfer(regs) != 1) return -1; - writel(Hsi2cFuncModeI2c, ®s->usi_ctl); + write32(®s->usi_ctl, Hsi2cFuncModeI2c); return 0; } @@ -510,34 +510,34 @@ static int hsi2c_transfer(struct i2c_bus *i2c, struct i2c_seg *segments, static int i2c_int_pending(struct i2c_regs *regs) { - return readb(®s->con) & I2cConIntPending; + return read8(®s->con) & I2cConIntPending; } static void i2c_clear_int(struct i2c_regs *regs) { - writeb(readb(®s->con) & ~I2cConIntPending, ®s->con); + write8(®s->con, read8(®s->con) & ~I2cConIntPending); } static void i2c_ack_enable(struct i2c_regs *regs) { - writeb(readb(®s->con) | I2cConAckGen, ®s->con); + write8(®s->con, read8(®s->con) | I2cConAckGen); } static void i2c_ack_disable(struct i2c_regs *regs) { - writeb(readb(®s->con) & ~I2cConAckGen, ®s->con); + write8(®s->con, read8(®s->con) & ~I2cConAckGen); } static int i2c_got_ack(struct i2c_regs *regs) { - return !(readb(®s->stat) & I2cStatAck); + return !(read8(®s->stat) & I2cStatAck); } static int i2c_wait_for_idle(struct i2c_regs *regs) { int timeout = 1000 * 100; // 1s. while (timeout--) { - if (!(readb(®s->stat) & I2cStatBusy)) + if (!(read8(®s->stat) & I2cStatBusy)) return 0; udelay(10); } @@ -562,17 +562,17 @@ static int i2c_wait_for_int(struct i2c_regs *regs) static int i2c_send_stop(struct i2c_regs *regs) { - uint8_t mode = readb(®s->stat) & (I2cStatModeMask); - writeb(mode | I2cStatEnable, ®s->stat); + uint8_t mode = read8(®s->stat) & (I2cStatModeMask); + write8(®s->stat, mode | I2cStatEnable); i2c_clear_int(regs); return i2c_wait_for_idle(regs); } static int i2c_send_start(struct i2c_regs *regs, int read, int chip) { - writeb(chip << 1, ®s->ds); + write8(®s->ds, chip << 1); uint8_t mode = read ? I2cStatMasterRecv : I2cStatMasterXmit; - writeb(mode | I2cStatStartStop | I2cStatEnable, ®s->stat); + write8(®s->stat, mode | I2cStatStartStop | I2cStatEnable); i2c_clear_int(regs); if (i2c_wait_for_int(regs)) @@ -594,7 +594,7 @@ static int i2c_xmit_buf(struct i2c_regs *regs, uint8_t *data, int len) int i; for (i = 0; i < len; i++) { - writeb(data[i], ®s->ds); + write8(®s->ds, data[i]); i2c_clear_int(regs); if (i2c_wait_for_int(regs)) @@ -624,7 +624,7 @@ static int i2c_recv_buf(struct i2c_regs *regs, uint8_t *data, int len) if (i2c_wait_for_int(regs)) return 1; - data[i] = readb(®s->ds); + data[i] = read8(®s->ds); } return 0; @@ -642,7 +642,7 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) if (!regs || i2c_wait_for_idle(regs)) return 1; - writeb(I2cStatMasterXmit | I2cStatEnable, ®s->stat); + write8(®s->stat, I2cStatMasterXmit | I2cStatEnable); int i; for (i = 0; i < count; i++) { diff --git a/src/soc/samsung/exynos5420/power.c b/src/soc/samsung/exynos5420/power.c index c7d491dd23..1b8aaa67d1 100644 --- a/src/soc/samsung/exynos5420/power.c +++ b/src/soc/samsung/exynos5420/power.c @@ -89,5 +89,5 @@ void power_enable_xclkout(void) void power_release_uart_retention(void) { - writel(1 << 28, &exynos_power->padret_uart_opt); + write32(&exynos_power->padret_uart_opt, 1 << 28); } diff --git a/src/soc/samsung/exynos5420/smp.c b/src/soc/samsung/exynos5420/smp.c index 8775bc9baf..6c8fd06f20 100644 --- a/src/soc/samsung/exynos5420/smp.c +++ b/src/soc/samsung/exynos5420/smp.c @@ -152,7 +152,7 @@ static void enable_smp(void) actlr |= ACTLR_SMP; /* Dummy read to assure L2 access */ - val = readl(&exynos_power->inform0); + val = read32(&exynos_power->inform0); val &= 0; actlr |= val; @@ -200,9 +200,9 @@ static void low_power_start(void) /* On warm reset, because iRAM is not cleared, all cores will enter * low_power_start, not the initial address. So we need to check reset * status again, and jump to 0x0 in that case. */ - reg_val = readl(&exynos_power->spare0); + reg_val = read32(&exynos_power->spare0); if (reg_val != RST_FLAG_VAL) { - writel(0x0, VECTOR_LOW_POWER_FLAG); + write32(VECTOR_LOW_POWER_FLAG, 0x0); jump_bx(CORE_RESET_INIT_ADDRESS); /* restart cpu execution and never returns. */ } @@ -211,9 +211,9 @@ static void low_power_start(void) * path, bypassing first jump address and makes final jump address 0x0, * so we try to make any core set again low_power_start address, if that * becomes zero. */ - reg_val = readl(VECTOR_CORE_SEV_HANDLER); + reg_val = read32(VECTOR_CORE_SEV_HANDLER); if (reg_val != (intptr_t)low_power_start) { - writel((intptr_t)low_power_start, VECTOR_CORE_SEV_HANDLER); + write32(VECTOR_CORE_SEV_HANDLER, (intptr_t)low_power_start); dsb(); /* ask all cores to power on again. */ sev(); @@ -258,7 +258,7 @@ static void power_down_core(void) * S5E5420A User Manual, 8.8.1.202, ARM_CORE0_CONFIGURATION, two bits to * control power state in each power down level. */ - writel(0x0, &exynos_power->arm_core[core_id].config); + write32(&exynos_power->arm_core[core_id].config, 0x0); /* S5E5420A User Manual, 8.4.2.5, after ARM_CORE*_CONFIGURATION has been * set to zero, PMU will detect and wait for WFI then run power-down @@ -281,15 +281,15 @@ static void configure_secondary_cores(void) * when we want to use SMP inside firmware. */ /* Clear boot reg (hotplug address) in cpu states */ - writel(0, (void*)&exynos_cpu_states->hotplug_address); + write32((void *)&exynos_cpu_states->hotplug_address, 0); /* set low_power flag and address */ - writel((intptr_t)low_power_start, VECTOR_LOW_POWER_ADDRESS); - writel(RST_FLAG_VAL, VECTOR_LOW_POWER_FLAG); - writel(RST_FLAG_VAL, &exynos_power->spare0); + write32(VECTOR_LOW_POWER_ADDRESS, (intptr_t)low_power_start); + write32(VECTOR_LOW_POWER_FLAG, RST_FLAG_VAL); + write32(&exynos_power->spare0, RST_FLAG_VAL); /* On next SEV, shutdown all cores. */ - writel((intptr_t)power_down_core, VECTOR_CORE_SEV_HANDLER); + write32(VECTOR_CORE_SEV_HANDLER, (intptr_t)power_down_core); /* Ask all cores in WFE mode to shutdown. */ dsb(); diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index 6ceb92edd2..3d71f79529 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -69,9 +69,9 @@ static inline struct exynos_spi_slave *to_exynos_spi(struct spi_slave *slave) static void spi_sw_reset(struct exynos_spi *regs, int word) { - const uint32_t orig_mode_cfg = readl(®s->mode_cfg); + const uint32_t orig_mode_cfg = read32(®s->mode_cfg); uint32_t mode_cfg = orig_mode_cfg; - const uint32_t orig_swap_cfg = readl(®s->swap_cfg); + const uint32_t orig_swap_cfg = read32(®s->swap_cfg); uint32_t swap_cfg = orig_swap_cfg; mode_cfg &= ~(SPI_MODE_CH_WIDTH_MASK | SPI_MODE_BUS_WIDTH_MASK); @@ -89,9 +89,9 @@ static void spi_sw_reset(struct exynos_spi *regs, int word) } if (mode_cfg != orig_mode_cfg) - writel(mode_cfg, ®s->mode_cfg); + write32(®s->mode_cfg, mode_cfg); if (swap_cfg != orig_swap_cfg) - writel(swap_cfg, ®s->swap_cfg); + write32(®s->swap_cfg, swap_cfg); clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); setbits_le32(®s->ch_cfg, SPI_CH_RST); @@ -106,7 +106,7 @@ void spi_init(void) static void exynos_spi_init(struct exynos_spi *regs) { // Set FB_CLK_SEL. - writel(SPI_FB_DELAY_180, ®s->fb_clk); + write32(®s->fb_clk, SPI_FB_DELAY_180); // CPOL: Active high. clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L); @@ -157,10 +157,10 @@ static void spi_transfer(struct exynos_spi *regs, void *in, const void *out, out_bytes = in_bytes = packets * width; spi_sw_reset(regs, width == 4); - writel(packets | SPI_PACKET_CNT_EN, ®s->pkt_cnt); + write32(®s->pkt_cnt, packets | SPI_PACKET_CNT_EN); while (out_bytes || in_bytes) { - uint32_t spi_sts = readl(®s->spi_sts); + uint32_t spi_sts = read32(®s->spi_sts); int rx_lvl = ((spi_sts >> 15) & 0x1ff); int tx_lvl = ((spi_sts >> 6) & 0x1ff); @@ -171,13 +171,13 @@ static void spi_transfer(struct exynos_spi *regs, void *in, const void *out, memcpy(&data, outb, width); outb += width; } - writel(data, ®s->tx_data); + write32(®s->tx_data, data); out_bytes -= width; } if (rx_lvl >= width) { - uint32_t data = readl(®s->rx_data); + uint32_t data = read32(®s->rx_data); if (inb) { memcpy(inb, &data, width); diff --git a/src/soc/samsung/exynos5420/timer.c b/src/soc/samsung/exynos5420/timer.c index 1e25771dbd..2abaf3bc5d 100644 --- a/src/soc/samsung/exynos5420/timer.c +++ b/src/soc/samsung/exynos5420/timer.c @@ -27,16 +27,15 @@ static const uint32_t clocks_per_usec = MCT_HZ/1000000; static uint64_t mct_raw_value(void) { - uint64_t upper = readl(&exynos_mct->g_cnt_u); - uint64_t lower = readl(&exynos_mct->g_cnt_l); + uint64_t upper = read32(&exynos_mct->g_cnt_u); + uint64_t lower = read32(&exynos_mct->g_cnt_l); return (upper << 32) | lower; } void init_timer(void) { - writel(readl(&exynos_mct->g_tcon) | (0x1 << 8), - &exynos_mct->g_tcon); + write32(&exynos_mct->g_tcon, read32(&exynos_mct->g_tcon) | (0x1 << 8)); } void timer_monotonic_get(struct mono_time *mt) diff --git a/src/soc/samsung/exynos5420/tmu.c b/src/soc/samsung/exynos5420/tmu.c index 8ed78bba4a..19c72fdac3 100644 --- a/src/soc/samsung/exynos5420/tmu.c +++ b/src/soc/samsung/exynos5420/tmu.c @@ -80,7 +80,7 @@ static int get_cur_temp(struct tmu_info *info) struct tmu_reg *reg = (struct tmu_reg *)info->tmu_base; /* Temperature code range between min 25 and max 125 */ - cur_temp = readl(®->current_temp) & 0xff; + cur_temp = read32(®->current_temp) & 0xff; /* Calibrate current temperature */ if (cur_temp) @@ -142,10 +142,10 @@ static void tmu_setup_parameters(struct tmu_info *info) struct tmu_reg *reg = (struct tmu_reg *)info->tmu_base; /* Must reload for using efuse value at EXYNOS */ - writel(TRIMINFO_RELOAD, ®->triminfo_control); + write32(®->triminfo_control, TRIMINFO_RELOAD); /* Get the compensation parameter */ - te_temp = readl(®->triminfo); + te_temp = read32(®->triminfo); info->te1 = te_temp & TRIM_INFO_MASK; info->te2 = ((te_temp >> 8) & TRIM_INFO_MASK); @@ -169,8 +169,8 @@ static void tmu_setup_parameters(struct tmu_info *info) (hwtrip_code << 24)); /* Set interrupt level */ - writel(rising_value, ®->threshold_temp_rise); - writel(cooling_temp, ®->threshold_temp_fall); + write32(®->threshold_temp_rise, rising_value); + write32(®->threshold_temp_fall, cooling_temp); /* * Need to init all register settings after getting parameter info @@ -183,20 +183,20 @@ static void tmu_setup_parameters(struct tmu_info *info) * TODO(bhthompson): rewrite this code such that we are not performing * a hard wipe of tmu_control and re verify functionality. */ - writel(data->slope, ®->tmu_control); + write32(®->tmu_control, data->slope); - writel(INTCLEARALL, ®->intclear); + write32(®->intclear, INTCLEARALL); /* TMU core enable */ - con = readl(®->tmu_control); + con = read32(®->tmu_control); con |= (info->tmu_mux << 20) | THERM_TRIP_EN | CORE_EN; - writel(con, ®->tmu_control); + write32(®->tmu_control, con); /* Enable HW thermal trip */ power_enable_hw_thermal_trip(); /* LEV1 LEV2 interrupt enable */ - writel(INTEN_RISE1 | INTEN_RISE2, ®->inten); + write32(®->inten, INTEN_RISE1 | INTEN_RISE2); } /* diff --git a/src/soc/samsung/exynos5420/trustzone.c b/src/soc/samsung/exynos5420/trustzone.c index 983690dbef..5712768355 100644 --- a/src/soc/samsung/exynos5420/trustzone.c +++ b/src/soc/samsung/exynos5420/trustzone.c @@ -33,10 +33,10 @@ void trustzone_init(void) for (addr = TZPC10_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) { tzpc = (struct exynos_tzpc *)addr; if (addr == TZPC0_BASE) - writel(R0SIZE, &tzpc->r0size); - writel(DECPROTXSET, &tzpc->decprot0set); - writel(DECPROTXSET, &tzpc->decprot1set); - writel(DECPROTXSET, &tzpc->decprot2set); - writel(DECPROTXSET, &tzpc->decprot3set); + write32(&tzpc->r0size, R0SIZE); + write32(&tzpc->decprot0set, DECPROTXSET); + write32(&tzpc->decprot1set, DECPROTXSET); + write32(&tzpc->decprot2set, DECPROTXSET); + write32(&tzpc->decprot3set, DECPROTXSET); } } diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c index 74e5067b0d..bfdd54a891 100644 --- a/src/soc/samsung/exynos5420/uart.c +++ b/src/soc/samsung/exynos5420/uart.c @@ -66,7 +66,7 @@ static void serial_setbrg_dev(struct s5p_uart *uart) uclk = clock_get_periph_rate(PERIPH_ID_UART3); val = uclk / default_baudrate(); - writel(val / 16 - 1, &uart->ubrdiv); + write32(&uart->ubrdiv, val / 16 - 1); /* * FIXME(dhendrix): the original uart.h had a "br_rest" value which @@ -88,12 +88,12 @@ static void serial_setbrg_dev(struct s5p_uart *uart) static void exynos5_init_dev(struct s5p_uart *uart) { /* enable FIFOs */ - writel(0x1, &uart->ufcon); - writel(0, &uart->umcon); + write32(&uart->ufcon, 0x1); + write32(&uart->umcon, 0); /* 8N1 */ - writel(0x3, &uart->ulcon); + write32(&uart->ulcon, 0x3); /* No interrupts, no DMA, pure polling */ - writel(0x245, &uart->ucon); + write32(&uart->ucon, 0x245); serial_setbrg_dev(uart); } @@ -114,7 +114,7 @@ static int exynos5_uart_err_check(struct s5p_uart *uart, int op) else mask = 0xf; - return readl(&uart->uerstat) & mask; + return read32(&uart->uerstat) & mask; } /* @@ -125,13 +125,13 @@ static int exynos5_uart_err_check(struct s5p_uart *uart, int op) static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart) { /* wait for character to arrive */ - while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | + while (!(read32(&uart->ufstat) & (RX_FIFO_COUNT_MASK | RX_FIFO_FULL_MASK))) { if (exynos5_uart_err_check(uart, 0)) return 0; } - return readb(&uart->urxh) & 0xff; + return read8(&uart->urxh) & 0xff; } /* @@ -140,12 +140,12 @@ static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart) static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data) { /* wait for room in the tx FIFO */ - while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { + while ((read32(&uart->ufstat) & TX_FIFO_FULL_MASK)) { if (exynos5_uart_err_check(uart, 1)) return; } - writeb(data, &uart->utxh); + write8(&uart->utxh, data); } uintptr_t uart_platform_base(int idx) diff --git a/src/soc/samsung/exynos5420/usb.c b/src/soc/samsung/exynos5420/usb.c index 0df63e2666..9313fea147 100644 --- a/src/soc/samsung/exynos5420/usb.c +++ b/src/soc/samsung/exynos5420/usb.c @@ -57,23 +57,13 @@ static void setup_dwc3(struct exynos5_usb_drd_dwc3 *dwc3) /* Set relevant registers to default values (clearing all reset bits) */ - writel(0x1 << 24 | /* activate PHY low power states */ - 0x4 << 19 | /* low power delay value */ - 0x1 << 18 | /* activate PHY low power delay */ - 0x1 << 17 | /* enable SuperSpeed PHY suspend */ - 0x1 << 1 | /* default Tx deemphasis value */ - 0, &dwc3->usb3pipectl); + write32(&dwc3->usb3pipectl, + 0x1 << 24 | 0x4 << 19 | 0x1 << 18 | 0x1 << 17 | 0x1 << 1 | 0); /* Configure PHY clock turnaround for 8-bit UTMI+, disable suspend */ - writel(0x9 << 10 | /* PHY clock turnaround for 8-bit UTMI+ */ - 0x1 << 8 | /* enable PHY sleep in L1 */ - 0x1 << 6 | /* enable PHY suspend */ - 0, &dwc3->usb2phycfg); - - writel(0x5dc << 19 | /* suspend clock scale for 24MHz */ - 0x1 << 16 | /* retry SS three times (bugfix from U-Boot) */ - 0x1 << 12 | /* port capability HOST */ - 0, &dwc3->ctl); + write32(&dwc3->usb2phycfg, 0x9 << 10 | 0x1 << 8 | 0x1 << 6 | 0); + + write32(&dwc3->ctl, 0x5dc << 19 | 0x1 << 16 | 0x1 << 12 | 0); } void setup_usb_drd0_dwc3() @@ -96,44 +86,25 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy) setbits_le32(&phy->linksystem, 0x1 << 27 | 0x20 << 1); /* Disable OTG, ID0 and DRVVBUS, do not force sleep/suspend */ - writel(1 << 6, &phy->utmi); - - writel(0x88 << 23 | /* spread spectrum refclk selector */ - 0x1 << 20 | /* enable spread spectrum */ - 0x1 << 19 | /* enable prescaler refclk */ - 0x68 << 11 | /* multiplier for 24MHz refclk */ - 0x5 << 5 | /* select 24MHz refclk (weird, from U-Boot) */ - 0x1 << 4 | /* power supply in normal operating mode */ - 0x3 << 2 | /* use external refclk (undocumented on 5420?)*/ - 0x1 << 1 | /* force port reset */ - 0x1 << 0 | /* normal operating mode */ - 0, &phy->clkrst); - - writel(0x9 << 26 | /* LOS level */ - 0x3 << 22 | /* TX VREF tune */ - 0x1 << 20 | /* TX rise tune */ - 0x1 << 18 | /* TX res tune */ - 0x3 << 13 | /* TX HS X Vtune */ - 0x3 << 9 | /* TX FS/LS tune */ - 0x3 << 6 | /* SQRX tune */ - 0x4 << 3 | /* OTG tune */ - 0x4 << 0 | /* comp disc tune */ - 0, &phy->param0); - - writel(0x7f << 19 | /* reserved */ - 0x7f << 12 | /* Tx launch amplitude */ - 0x20 << 6 | /* Tx deemphasis 6dB */ - 0x1c << 0 | /* Tx deemphasis 3.5dB (value from U-Boot) */ - 0, &phy->param1); + write32(&phy->utmi, 1 << 6); + + write32(&phy->clkrst, + 0x88 << 23 | 0x1 << 20 | 0x1 << 19 | 0x68 << 11 | 0x5 << 5 | 0x1 << 4 | 0x3 << 2 | 0x1 << 1 | 0x1 << 0 | 0); + + write32(&phy->param0, + 0x9 << 26 | 0x3 << 22 | 0x1 << 20 | 0x1 << 18 | 0x3 << 13 | 0x3 << 9 | 0x3 << 6 | 0x4 << 3 | 0x4 << 0 | 0); + + write32(&phy->param1, + 0x7f << 19 | 0x7f << 12 | 0x20 << 6 | 0x1c << 0 | 0); /* disable all test features */ - writel(0, &phy->test); + write32(&phy->test, 0); /* UTMI clock select? ("must be 0x1") */ - writel(0x1 << 2, &phy->utmiclksel); + write32(&phy->utmiclksel, 0x1 << 2); /* Samsung magic, undocumented (from U-Boot) */ - writel(0x0, &phy->resume); + write32(&phy->resume, 0x0); udelay(10); clrbits_le32(&phy->clkrst, 0x1 << 1); /* deassert port reset */ @@ -163,7 +134,7 @@ void setup_usb_host_phy(int hsic_gpio) printk(BIOS_DEBUG, "Powering up USB HOST PHY (%s HSIC)\n", hsic_gpio ? "with" : "without"); - hostphy_ctrl0 = readl(&exynos_usb_host_phy->usbphyctrl0); + hostphy_ctrl0 = read32(&exynos_usb_host_phy->usbphyctrl0); hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK | HOST_CTRL0_COMMONON_N | /* HOST Phy setting */ @@ -177,7 +148,7 @@ void setup_usb_host_phy(int hsic_gpio) /* HOST Phy setting */ HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST); - writel(hostphy_ctrl0, &exynos_usb_host_phy->usbphyctrl0); + write32(&exynos_usb_host_phy->usbphyctrl0, hostphy_ctrl0); udelay(10); clrbits_le32(&exynos_usb_host_phy->usbphyctrl0, HOST_CTRL0_LINKSWRST | |