diff options
| author | Bernardo Perez Priego <bernardo.perez.priego@intel.com> | 2021-06-21 10:49:47 -0700 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-25 04:10:26 +0000 |
| commit | b4a09c03f73c966d55445b6674f0d982919c719d (patch) | |
| tree | 2a243abf097e99dd670285c5086839f5c237dcfb /src/soc/intel | |
| parent | b5a8586fe4030d25f53db76dd31f17d3c250c24b (diff) | |
soc/intel/alderlake: Update s0ix cstate table
Cstate C7 is not supported in ADL, replacing this unsupported state
with C6 in the s0ix cstate table.
BUG=None
TEST=Boot device to OS.
Print supported CStates and latencies.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I471f71481d337e3fafa4acab7fe8a39677c8710c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55734
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/acpi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 23d2a262e6..1f49719979 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -107,7 +107,7 @@ static int cstate_set_non_s0ix[] = { static int cstate_set_s0ix[] = { C_STATE_C1, - C_STATE_C7S_LONG_LAT, + C_STATE_C6_LONG_LAT, C_STATE_C10 }; |