diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-02-24 00:51:11 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-25 17:44:45 +0000 |
| commit | 928a9c8f048874018ab14a0c66108c22b7b04da2 (patch) | |
| tree | 3e142c48e7d2471ce534be514e4f709628e5ec88 /src/soc/intel | |
| parent | 972d9f2cce2792b847c4c1879f5b52c19585c37c (diff) | |
cpu,mb,nb,soc: use HPET_BASE_ADDRESS instead of magic number
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I570f7de90007b67d811d158ca33e099d5cc2d5d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62308
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/xeon_sp/acpi/southcluster.asl | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/xeon_sp/acpi/southcluster.asl b/src/soc/intel/xeon_sp/acpi/southcluster.asl index d1fd98fbab..eb687784e7 100644 --- a/src/soc/intel/xeon_sp/acpi/southcluster.asl +++ b/src/soc/intel/xeon_sp/acpi/southcluster.asl @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/hpet.h> #include <soc/iomap.h> Name(_HID,EISAID("PNP0A08")) // PCIe @@ -120,7 +121,7 @@ Name (MCRS, ResourceTemplate() { DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, 0xfed00000, 0xfedfffff, 0x00000000, + 0x00000000, HPET_BASE_ADDRESS, 0xfedfffff, 0x00000000, 0x00100000,,, PCHR) QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, |