diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-02-23 16:32:20 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-25 17:44:11 +0000 |
| commit | 972d9f2cce2792b847c4c1879f5b52c19585c37c (patch) | |
| tree | 87166acd957448e6b262a331106e7a276806043c /src/soc/intel | |
| parent | 887d4ed912ef80afbf7827150f52e207edc9c033 (diff) | |
arch/x86: consolidate HPET base address definitions
Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and
the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO
region which is 0xfed00000 on all chipsets and SoCs in the coreboot
tree. Since these two different constants are used in different places
that however might end up used in the same coreboot build, drop the
Kconfig option and use the definition from arch/x86 instead. Since it's
no longer needed to check for a mismatch of those two constants, the
corresponding checks are dropped too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/baytrail/acpi/lpc.asl | 4 | ||||
| -rw-r--r-- | src/soc/intel/braswell/acpi/lpc.asl | 4 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/pch/acpi/lpc.asl | 10 |
3 files changed, 12 insertions, 6 deletions
diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl index c76cf22fb2..5933070a6b 100644 --- a/src/soc/intel/baytrail/acpi/lpc.asl +++ b/src/soc/intel/baytrail/acpi/lpc.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/hpet.h> + /* Intel LPC Bus Device - 0:1f.0 */ Device (LPCB) @@ -44,7 +46,7 @@ Device (LPCB) Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400) + Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400) }) } diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index 0a22162fc2..76af8fd20c 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/hpet.h> + /* Intel LPC Bus Device - 0:1f.0 */ Device (LPCB) @@ -55,7 +57,7 @@ Device (LPCB) Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400) + Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400) }) } #endif diff --git a/src/soc/intel/broadwell/pch/acpi/lpc.asl b/src/soc/intel/broadwell/pch/acpi/lpc.asl index e37c6d0682..b6b77c8ed2 100644 --- a/src/soc/intel/broadwell/pch/acpi/lpc.asl +++ b/src/soc/intel/broadwell/pch/acpi/lpc.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/hpet.h> + // Intel LPC Bus Device - 0:1f.0 Device (LPCB) @@ -64,7 +66,7 @@ Device (LPCB) Name (BUF0, ResourceTemplate () { - Memory32Fixed (ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) + Memory32Fixed (ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status @@ -77,15 +79,15 @@ Device (LPCB) If (HPTE) { CreateDWordField (BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (HPAS == 1) { - HPT0 = CONFIG_HPET_ADDRESS + 0x1000 + HPT0 = HPET_BASE_ADDRESS + 0x1000 } If (HPAS == 2) { - HPT0 = CONFIG_HPET_ADDRESS + 0x2000 + HPT0 = HPET_BASE_ADDRESS + 0x2000 } If (HPAS == 3) { - HPT0 = CONFIG_HPET_ADDRESS + 0x3000 + HPT0 = HPET_BASE_ADDRESS + 0x3000 } } |