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author | Nico Huber <nico.h@gmx.de> | 2018-05-27 14:32:27 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-04 08:20:35 +0000 |
commit | 36ec3e9ba1b89416d87426eabe496d67dbb2cdbf (patch) | |
tree | d0a982f07df42bb3115e46e211a847ae9a78fac0 /src/soc/intel | |
parent | b5211ef2e7da1c1b8f8bb0208e7b2f44aa859ef7 (diff) |
arch/x86: Introduce postcar_frame_add_romcache()
Provide a common implementation to add an MTRR entry for memory-
mapped boot ROMs.
Change-Id: I9fabc6b87fb36dc3d970805eb804cd950b8849d4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions