diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2023-08-21 11:12:04 +0200 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2023-08-21 21:16:53 +0000 |
| commit | 12a1fc2939879d3ba3863619d8ab2e5f152e392c (patch) | |
| tree | 09f139eef3c18ea0f2f7128f4b592e393a7f6ac7 /src/soc/intel | |
| parent | 8fc6d18fc0ae1c47718ee51c86d38193b12e6e5d (diff) | |
soc/intel/alderlake: Guard PchPcie{Clock,Power}Gating on RPL FSP
PchPcieClockGating and PchPciePowerGating UPDs are not yet available
in RPL-S IOT FSP. It also looks like those UPDs are not generally
available in all public RaptorLake FSP headers yet, so guard it
against SOC_INTEL_RAPTORLAKE to avoid build errors.
Change-Id: Iedac21bafa3428957e054fc8fefa38f9f776772d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77337
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 402af89ed8..67fb55bb7d 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -924,7 +924,7 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, } s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); -#if CONFIG(FSP_TYPE_IOT) +#if CONFIG(FSP_TYPE_IOT) && !CONFIG(SOC_INTEL_RAPTORLAKE) /* * Intel requires that all enabled PCH PCIe ports have a CLK_REQ signal connected. * The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1 |