diff options
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 402af89ed8..67fb55bb7d 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -924,7 +924,7 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, } s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); -#if CONFIG(FSP_TYPE_IOT) +#if CONFIG(FSP_TYPE_IOT) && !CONFIG(SOC_INTEL_RAPTORLAKE) /* * Intel requires that all enabled PCH PCIe ports have a CLK_REQ signal connected. * The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1 |