soc/intel/xeon_sp/spr: Add Sapphire Rapids ramstage code

It implements SPR ramstage including silicon initialization, MSR
programming, MP init and certain registers locking before booting
to payload.

Change-Id: I128fdc6e58c49fb5abf911d6ffa91e7411f6d1e2
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

1 files changed, 42 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/spr/xhci.c b/src/soc/intel/xeon_sp/spr/xhci.c
new file mode 100644
index 0000000000..544ea16ba9
--- /dev/null
+++ b/src/soc/intel/xeon_sp/spr/xhci.c
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <soc/pci_devs.h>
+#include <soc/xhci.h>
+#include <types.h>
+
+static uint8_t *get_xhci_bar(void)
+{
+	const struct resource *res;
+	res = probe_resource(PCH_DEV_XHCI, PCI_BASE_ADDRESS_0);
+	if (!res) {
+		printk(BIOS_ERR, "XHCI BAR is not found\n");
+		return NULL;
+	}
+	return (void *)(uintptr_t)res->base;
+}
+
+void write_usb_oc_mapping(const struct usb_oc_mapping *config, uint8_t pins)
+{
+	uint8_t *mbar = get_xhci_bar();
+	uint8_t i;
+
+	if (mbar == NULL) {
+		printk(BIOS_ERR, "XHCI BAR is invalid, skip USB OC mapping configuration\n");
+		return;
+	}
+	for (i = 0; i < pins; i++)
+		write32(mbar + config[i].pin, config[i].port);
+}
+
+void lock_oc_cfg(bool lock)
+{
+	uint32_t cfg = pci_read_config32(PCH_DEV_XHCI, SYS_BUS_CFG2);
+
+	if (lock)
+		cfg |= OCCFGDONE;
+	else
+		cfg &= ~(OCCFGDONE);
+	pci_write_config32(PCH_DEV_XHCI, SYS_BUS_CFG2, cfg);
+}