From 3ed903fda9cb9b7237067f301d1efdb297a05a24 Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Wed, 25 Jan 2023 11:37:27 -0800 Subject: soc/intel/xeon_sp/spr: Add Sapphire Rapids ramstage code It implements SPR ramstage including silicon initialization, MSR programming, MP init and certain registers locking before booting to payload. Change-Id: I128fdc6e58c49fb5abf911d6ffa91e7411f6d1e2 Signed-off-by: Jonathan Zhang Signed-off-by: Johnny Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/72443 Tested-by: build bot (Jenkins) Reviewed-by: Lean Sheng Tan --- src/soc/intel/xeon_sp/spr/xhci.c | 42 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 src/soc/intel/xeon_sp/spr/xhci.c (limited to 'src/soc/intel/xeon_sp/spr/xhci.c') diff --git a/src/soc/intel/xeon_sp/spr/xhci.c b/src/soc/intel/xeon_sp/spr/xhci.c new file mode 100644 index 0000000000..544ea16ba9 --- /dev/null +++ b/src/soc/intel/xeon_sp/spr/xhci.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static uint8_t *get_xhci_bar(void) +{ + const struct resource *res; + res = probe_resource(PCH_DEV_XHCI, PCI_BASE_ADDRESS_0); + if (!res) { + printk(BIOS_ERR, "XHCI BAR is not found\n"); + return NULL; + } + return (void *)(uintptr_t)res->base; +} + +void write_usb_oc_mapping(const struct usb_oc_mapping *config, uint8_t pins) +{ + uint8_t *mbar = get_xhci_bar(); + uint8_t i; + + if (mbar == NULL) { + printk(BIOS_ERR, "XHCI BAR is invalid, skip USB OC mapping configuration\n"); + return; + } + for (i = 0; i < pins; i++) + write32(mbar + config[i].pin, config[i].port); +} + +void lock_oc_cfg(bool lock) +{ + uint32_t cfg = pci_read_config32(PCH_DEV_XHCI, SYS_BUS_CFG2); + + if (lock) + cfg |= OCCFGDONE; + else + cfg &= ~(OCCFGDONE); + pci_write_config32(PCH_DEV_XHCI, SYS_BUS_CFG2, cfg); +} -- cgit v1.2.3