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authorArthur Heymans <arthur@aheymans.xyz>2022-08-24 14:44:26 +0200
committerFelix Held <felix-coreboot@felixheld.de>2024-01-15 13:30:29 +0000
commit550f55e4f63dcb6d16132d2f5596e653fe2d1579 (patch)
treeb345429ab193bf29b6e6c03ecaec10ffe0c63def /src/soc/intel/xeon_sp/spr/chip.c
parentd873d3a7ec6d39a792fc08bab4f24d7957866609 (diff)
soc/intel/xeon_sp: Redesign resource allocation
The xeon_sp code worked around the coreboot allocator rather than using it. Now the allocator is able to deal with the multiple IIOs so this is not necessary anymore. Instead do the following: - Parse the FSP HOB information about IIO into coreboot PCI domains - Use existing scan_bus and read_resource - Handle IOAT stacks with multiple domains in soc-specific code TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/spr/chip.c')
-rw-r--r--src/soc/intel/xeon_sp/spr/chip.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/xeon_sp/spr/chip.c b/src/soc/intel/xeon_sp/spr/chip.c
index f9c43dbe9a..3b3c65e4a0 100644
--- a/src/soc/intel/xeon_sp/spr/chip.c
+++ b/src/soc/intel/xeon_sp/spr/chip.c
@@ -47,9 +47,9 @@ const char *soc_acpi_name(const struct device *dev)
#endif
static struct device_operations pci_domain_ops = {
- .read_resources = &pci_domain_read_resources,
- .set_resources = &xeonsp_pci_domain_set_resources,
- .scan_bus = &xeonsp_pci_domain_scan_bus,
+ .read_resources = iio_pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .scan_bus = iio_pci_domain_scan_bus,
#if CONFIG(HAVE_ACPI_TABLES)
.write_acpi_tables = &northbridge_write_acpi_tables,
.acpi_name = soc_acpi_name