soc/intel/xeon_sp: Redesign resource allocation

The xeon_sp code worked around the coreboot allocator rather than using
it. Now the allocator is able to deal with the multiple IIOs so this is
not necessary anymore.

Instead do the following:
- Parse the FSP HOB information about IIO into coreboot PCI domains
- Use existing scan_bus and read_resource
- Handle IOAT stacks with multiple domains in soc-specific code

TEST=intel/archercity CRB

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

6 files changed, 160 insertions, 27 deletions

diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index 396072448d..5a21f47b43 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -12,6 +12,7 @@ config SOC_INTEL_SAPPHIRERAPIDS_SP
 	select PLATFORM_USES_FSP2_3
 	select SOC_INTEL_CSE_SERVER_SKU
 	select XEON_SP_COMMON_BASE
+	select HAVE_IOAT_DOMAINS
 	help
 	  Intel Sapphire Rapids-SP support
 
diff --git a/src/soc/intel/xeon_sp/spr/Makefile.inc b/src/soc/intel/xeon_sp/spr/Makefile.inc
index 3e4f9cd329..7a0d9586c5 100644
--- a/src/soc/intel/xeon_sp/spr/Makefile.inc
+++ b/src/soc/intel/xeon_sp/spr/Makefile.inc
@@ -13,7 +13,7 @@ romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
 romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
 
 ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c xhci.c numa.c reset.c
-ramstage-y += crashlog.c
+ramstage-y += crashlog.c ioat.c
 ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
 ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += soc_smihandler_util.c
diff --git a/src/soc/intel/xeon_sp/spr/chip.c b/src/soc/intel/xeon_sp/spr/chip.c
index f9c43dbe9a..3b3c65e4a0 100644
--- a/src/soc/intel/xeon_sp/spr/chip.c
+++ b/src/soc/intel/xeon_sp/spr/chip.c
@@ -47,9 +47,9 @@ const char *soc_acpi_name(const struct device *dev)
 #endif
 
 static struct device_operations pci_domain_ops = {
-	.read_resources = &pci_domain_read_resources,
-	.set_resources = &xeonsp_pci_domain_set_resources,
-	.scan_bus = &xeonsp_pci_domain_scan_bus,
+	.read_resources = iio_pci_domain_read_resources,
+	.set_resources = pci_domain_set_resources,
+	.scan_bus = iio_pci_domain_scan_bus,
 #if CONFIG(HAVE_ACPI_TABLES)
 	.write_acpi_tables = &northbridge_write_acpi_tables,
 	.acpi_name = soc_acpi_name
diff --git a/src/soc/intel/xeon_sp/spr/ioat.c b/src/soc/intel/xeon_sp/spr/ioat.c
new file mode 100644
index 0000000000..f10863a607
--- /dev/null
+++ b/src/soc/intel/xeon_sp/spr/ioat.c
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdbool.h>
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/resource.h>
+
+#include <defs_iio.h>
+#include <hob_iiouds.h>
+#include <IioPcieConfigUpd.h>
+
+#include <soc/chip_common.h>
+
+/*
+ * Used for IIO stacks for accelerators and other functionality (IOAT).
+ * Those have only integrated PCI endpoints (no bridges) behind the host bridge.
+ */
+
+static struct device_operations ioat_domain_ops = {
+	.read_resources = noop_read_resources,
+	.set_resources = pci_domain_set_resources,
+	.scan_bus = pci_host_bridge_scan_bus,
+};
+
+static void create_ioat_domain(struct bus *const upstream, const unsigned int domain_base,
+				const unsigned int bus_base, const unsigned int bus_limit,
+				const resource_t mem32_base, const resource_t mem32_limit,
+				const resource_t mem64_base, const resource_t mem64_limit)
+{
+	struct device_path path = {
+		.type = DEVICE_PATH_DOMAIN,
+		.domain = {
+			.domain = domain_base + bus_base,
+		},
+	};
+	struct device *const domain = alloc_dev(upstream, &path);
+	if (!domain)
+		die("%s: out of memory.\n", __func__);
+
+	domain->ops = &ioat_domain_ops;
+
+	domain->link_list = calloc(1, sizeof(struct bus));
+	if (!domain->link_list)
+		die("%s: out of memory.\n", __func__);
+
+	struct bus *const bus = domain->link_list;
+	bus->secondary = bus_base;
+	bus->subordinate = bus->secondary;
+	bus->max_subordinate = bus_limit;
+
+	unsigned int index = 0;
+
+	if (mem32_base <= mem32_limit) {
+		struct resource *const res = new_resource(domain, index++);
+		res->base = mem32_base;
+		res->limit = mem32_limit;
+		res->size = res->limit - res->base + 1;
+		res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
+	}
+
+	if (mem64_base <= mem64_limit) {
+		struct resource *const res = new_resource(domain, index++);
+		res->base = mem64_base;
+		res->limit = mem64_limit;
+		res->size = res->limit - res->base + 1;
+		res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
+	}
+}
+
+void soc_create_ioat_domains(struct bus *const bus, const STACK_RES *const sr)
+{
+	const unsigned int domain_base = MAX_SOCKET * MAX_LOGIC_IIO_STACK;
+
+	if (sr->BusLimit < sr->BusBase + HQM_BUS_OFFSET + HQM_RESERVED_BUS) {
+		printk(BIOS_WARNING,
+			"Ignoring IOAT domain with limited bus range.\n");
+		return;
+	}
+
+	if (sr->PciResourceMem64Limit - sr->PciResourceMem64Base + 1
+	    < 2 * CPM_MMIO_SIZE + 2 * HQM_MMIO_SIZE) {
+		printk(BIOS_WARNING,
+		       "Ignoring IOAT domain with limited 64-bit MMIO window.\n");
+		return;
+	}
+
+	/* The FSP HOB doesn't provide accurate information about the
+	   resource allocation. Hence use pre-defined offsets. Based
+	   on ACPI code in create_dsdt_dino_resource(), soc_acpi.c: */
+	resource_t mem64_base, mem64_limit, bus_base, bus_limit;
+
+	/* CPM0 */
+	mem64_base = sr->PciResourceMem64Base;
+	mem64_limit = mem64_base + CPM_MMIO_SIZE - 1;
+	bus_base = sr->BusBase + CPM_BUS_OFFSET;
+	bus_limit = bus_base + CPM_RESERVED_BUS;
+	create_ioat_domain(bus, domain_base, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit);
+
+	/* HQM0 */
+	mem64_base = mem64_limit + 1;
+	mem64_limit = mem64_base + HQM_MMIO_SIZE - 1;
+	bus_base = sr->BusBase + HQM_BUS_OFFSET;
+	bus_limit = bus_base + HQM_RESERVED_BUS;
+	create_ioat_domain(bus, domain_base, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit);
+
+	/* CPM1 (optional) */
+	mem64_base = mem64_limit + 1;
+	mem64_limit = mem64_base + CPM_MMIO_SIZE - 1;
+	bus_base = sr->BusBase + CPM1_BUS_OFFSET;
+	bus_limit = bus_base + CPM_RESERVED_BUS;
+	if (bus_limit <= sr->BusLimit)
+		create_ioat_domain(bus, domain_base, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit);
+
+	/* HQM1 (optional) */
+	mem64_base = mem64_limit + 1;
+	mem64_limit = mem64_base + HQM_MMIO_SIZE - 1;
+	bus_base = sr->BusBase + HQM1_BUS_OFFSET;
+	bus_limit = bus_base + HQM_RESERVED_BUS;
+	if (bus_limit <= sr->BusLimit)
+		create_ioat_domain(bus, domain_base, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit);
+
+	/* DINO */
+	mem64_base = mem64_limit + 1;
+	mem64_limit = sr->PciResourceMem64Limit;
+	bus_base = sr->BusBase;
+	bus_limit = bus_base;
+	create_ioat_domain(bus, domain_base, bus_base, bus_limit, sr->PciResourceMem32Base, sr->PciResourceMem32Limit,
+		mem64_base, mem64_limit);
+}
diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c
index 193b85978a..e7ce5e3773 100644
--- a/src/soc/intel/xeon_sp/spr/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c
@@ -188,6 +188,9 @@ static void create_dsdt_iou_cxl_resource(uint8_t socket, uint8_t stack, const ST
 
 static void create_dsdt_dino_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled)
 {
+	if (!stack_enabled)
+		return;
+
 	/*
 	   Stacks 8 .. B (TYPE_DINO)
 		Scope: DI<socket><stack> for DINO, ResourceTemplate: DT
@@ -247,6 +250,11 @@ static void create_dsdt_dino_resource(uint8_t socket, uint8_t stack, const STACK
 			snprintf(tres, sizeof(tres), "HU%d%X", socket, stack);
 		}
 
+		/* Note, some SKU doesn't provide CPM1 and HQM1 and owns smaller bus ranges
+		 accordingly*/
+		if (bus_limit > ri->BusLimit)
+			continue;
+
 		printk(BIOS_DEBUG,
 		       "\tCreating Dino ResourceTemplate %s for socket: %d, "
 		       "stack: %d\n bus_base:0x%x, bus_limit:0x%x\n",
@@ -255,30 +263,19 @@ static void create_dsdt_dino_resource(uint8_t socket, uint8_t stack, const STACK
 		acpigen_write_name(tres);
 		acpigen_write_resourcetemplate_header();
 
-		if (stack_enabled) {
-			acpigen_resource_word(2, 0xc, 0, 0, bus_base, bus_limit, 0x0,
-					      (bus_limit - bus_base + 1));
-
-			/* Mem32 resource */
-			if (rlist[i] == DSDT_DINO)
-				acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base,
-						       ri->PciResourceMem32Limit, 0x0,
-						       (ri->PciResourceMem32Limit
-							- ri->PciResourceMem32Base + 1));
-
-			/* Mem64 resource */
-			acpigen_resource_qword(0, 0xc, 1, 0, mem64_base, mem64_limit, 0,
-					       (mem64_limit - mem64_base + 1));
-		} else {
-			acpigen_resource_word(2, 0, 0, 0, 0, 0, 0, 0);
+		acpigen_resource_word(2, 0xc, 0, 0, bus_base, bus_limit, 0x0,
+			(bus_limit - bus_base + 1));
 
-			/* Mem32 resource */
-			if (rlist[i] == DSDT_DINO)
-				acpigen_resource_dword(0, 0, 1, 0, 0, 0, 0, 0);
+		/* Mem32 resource */
+		if (rlist[i] == DSDT_DINO)
+			acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base,
+				ri->PciResourceMem32Limit, 0x0,
+				(ri->PciResourceMem32Limit
+				- ri->PciResourceMem32Base + 1));
 
-			/* Mem64 resource */
-			acpigen_resource_qword(0, 0, 1, 0, 0, 0, 0, 0);
-		}
+		/* Mem64 resource */
+		acpigen_resource_qword(0, 0xc, 1, 0, mem64_base, mem64_limit, 0,
+			(mem64_limit - mem64_base + 1));
 
 		acpigen_write_resourcetemplate_footer();
 	}
diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c
index f352145121..86fe803e85 100644
--- a/src/soc/intel/xeon_sp/spr/soc_util.c
+++ b/src/soc/intel/xeon_sp/spr/soc_util.c
@@ -68,11 +68,16 @@ const struct SystemMemoryMapElement *get_system_memory_map_elment(uint8_t *num)
 	return hob->Element;
 }
 
-bool is_iio_stack_res(const STACK_RES *res)
+bool stack_needs_resource_alloc(const STACK_RES *res)
 {
 	return res->Personality == TYPE_UBOX_IIO || res->Personality == TYPE_DINO;
 }
 
+bool is_pcie_iio_stack_res(const STACK_RES *res)
+{
+	return res->Personality == TYPE_UBOX_IIO;
+}
+
 /*
  * Given a stack resource, figure out whether the corresponding stack has
  * CXL device.