diff options
| author | Gang Chen <gang.c.chen@intel.com> | 2024-06-18 06:39:12 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-11-14 14:29:23 +0000 |
| commit | 3d32f915a9c4d60046574690db966d1f14eebe65 (patch) | |
| tree | 79cb2533cca5fb7fa593bc77ac23b5873268eba2 /src/soc/intel/xeon_sp/gnr | |
| parent | 97412d1929e88a929f73a229e40ca85a38168d7e (diff) | |
soc/intel/xeon_sp: Reserve PRMRR
PRMRR (Protected Region Memory Range Region) are not accessible as
normal DRAM regions and needs to be explicitly reserved in memory
map.
Change-Id: I81d17b1376459510f7c0d43ba4b519b1f2bd3e1f
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/gnr')
| -rw-r--r-- | src/soc/intel/xeon_sp/gnr/soc_util.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/gnr/soc_util.c b/src/soc/intel/xeon_sp/gnr/soc_util.c index 9d8e815f8e..6912809d2d 100644 --- a/src/soc/intel/xeon_sp/gnr/soc_util.c +++ b/src/soc/intel/xeon_sp/gnr/soc_util.c @@ -134,6 +134,20 @@ uint8_t get_cxl_node_count(void) return count; } +unsigned int get_prmrr_count(void) +{ + uint32_t cpu_id = cpu_get_cpuid(); + + switch (cpu_id & CPUID_ALL_STEPPINGS_MASK) { + case CPUID_GRANITERAPIDS: + return 0x7; + case CPUID_SIERRAFOREST: + return 0x4; + default: + return 0; + } +} + bool is_memtype_reserved(uint16_t mem_type) { return false; |