From 3d32f915a9c4d60046574690db966d1f14eebe65 Mon Sep 17 00:00:00 2001
From: Gang Chen <gang.c.chen@intel.com>
Date: Tue, 18 Jun 2024 06:39:12 +0800
Subject: soc/intel/xeon_sp: Reserve PRMRR

PRMRR (Protected Region Memory Range Region) are not accessible as
normal DRAM regions and needs to be explicitly reserved in memory
map.

Change-Id: I81d17b1376459510f7c0d43ba4b519b1f2bd3e1f
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/xeon_sp/gnr/soc_util.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

(limited to 'src/soc/intel/xeon_sp/gnr')

diff --git a/src/soc/intel/xeon_sp/gnr/soc_util.c b/src/soc/intel/xeon_sp/gnr/soc_util.c
index 9d8e815f8e..6912809d2d 100644
--- a/src/soc/intel/xeon_sp/gnr/soc_util.c
+++ b/src/soc/intel/xeon_sp/gnr/soc_util.c
@@ -134,6 +134,20 @@ uint8_t get_cxl_node_count(void)
 	return count;
 }
 
+unsigned int get_prmrr_count(void)
+{
+	uint32_t cpu_id = cpu_get_cpuid();
+
+	switch (cpu_id & CPUID_ALL_STEPPINGS_MASK) {
+	case CPUID_GRANITERAPIDS:
+		return 0x7;
+	case CPUID_SIERRAFOREST:
+		return 0x4;
+	default:
+		return 0;
+	}
+}
+
 bool is_memtype_reserved(uint16_t mem_type)
 {
 	return false;
-- 
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