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authorArthur Heymans <arthur@aheymans.xyz>2022-12-02 12:42:27 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-12-06 17:06:35 +0000
commit8a3e2b836435f34a1031de190f48f02a8daf26db (patch)
tree7735f6d4ec3578b6a19a10d9c17ddaa3ebbb2114 /src/soc/intel/xeon_sp/cpx/Kconfig
parent8a979d92c98f4ec2374b6f04a795ae65b4c52c5a (diff)
soc/intel/xeon_sp: Read ioapic configuration from hardware
This is more robust than hardcoding whathever FSP has set up and is a lot less code. Change-Id: I6423ddc139d742879d791b054ea082768749c0a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70265 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx/Kconfig')
-rw-r--r--src/soc/intel/xeon_sp/cpx/Kconfig4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index 52de09ab7b..aa344ce16c 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -112,10 +112,6 @@ config XEON_SP_HAVE_IIO_IOAPIC
bool
default y
-config XEON_SP_PCH_IOAPIC_GSI_BASES
- hex
- default 0x78
-
if INTEL_TXT
config INTEL_TXT_SINIT_SIZE