From 8a3e2b836435f34a1031de190f48f02a8daf26db Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Fri, 2 Dec 2022 12:42:27 +0100
Subject: soc/intel/xeon_sp: Read ioapic configuration from hardware

This is more robust than hardcoding whathever FSP has set up and is a
lot less code.

Change-Id: I6423ddc139d742879d791b054ea082768749c0a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70265
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/xeon_sp/cpx/Kconfig | 4 ----
 1 file changed, 4 deletions(-)

(limited to 'src/soc/intel/xeon_sp/cpx/Kconfig')

diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index 52de09ab7b..aa344ce16c 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -112,10 +112,6 @@ config XEON_SP_HAVE_IIO_IOAPIC
 	bool
 	default y
 
-config XEON_SP_PCH_IOAPIC_GSI_BASES
-	hex
-	default 0x78
-
 if INTEL_TXT
 
 config INTEL_TXT_SINIT_SIZE
-- 
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