diff options
author | Shuo Liu <shuo.liu@intel.com> | 2024-04-06 05:13:27 +0800 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2024-04-09 12:33:25 +0000 |
commit | e43f387022168d8adf2bffe6901286a81517b10e (patch) | |
tree | 512cf1d59ce0fc1faf365528889f6e2b4e346e8c /src/soc/intel/xeon_sp/acpi.c | |
parent | 9d6333c839fe5a4932b3cb47d824f81295302e2c (diff) |
soc/intel/xeon_sp: Add iio_ioapic.c
Move the soc_get_ioapic_info for platforms with IIO IO-APICs to
a separate file from src/soc/intel/xeon_sp/acpi.c.
TEST=Build intel/archerticy CRB
Change-Id: I59022b7685539491604724ef3b550da1cfd53f13
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/intel/xeon_sp/acpi.c')
-rw-r--r-- | src/soc/intel/xeon_sp/acpi.c | 39 |
1 files changed, 0 insertions, 39 deletions
diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 9ee8d6a59b..0d66aec282 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -90,45 +90,6 @@ const acpi_cstate_t *soc_get_cstate_map(size_t *entries) return map; } -#if CONFIG(XEON_SP_HAVE_IIO_IOAPIC) -static uintptr_t xeonsp_ioapic_bases[CONFIG(XEON_SP_HAVE_IIO_IOAPIC) * 8 + 1]; - -size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[]) -{ - int index = 0; - const IIO_UDS *hob = get_iio_uds(); - - *ioapic_bases = xeonsp_ioapic_bases; - - for (int socket = 0; socket < CONFIG_MAX_SOCKET; socket++) { - if (!soc_cpu_is_enabled(socket)) - continue; - for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { - const STACK_RES *ri = - &hob->PlatformData.IIO_resource[socket].StackRes[stack]; - uint32_t ioapic_base = ri->IoApicBase; - if (ioapic_base == 0 || ioapic_base == 0xFFFFFFFF) - continue; - assert(index < ARRAY_SIZE(xeonsp_ioapic_bases)); - xeonsp_ioapic_bases[index++] = ioapic_base; - if (!CONFIG(XEON_SP_HAVE_IIO_IOAPIC)) - return index; - /* - * Stack 0 has non-PCH IOAPIC and PCH IOAPIC. - * The IIO IOAPIC is placed at 0x1000 from the reported base. - */ - if (socket == 0 && stack == 0) { - ioapic_base += 0x1000; - assert(index < ARRAY_SIZE(xeonsp_ioapic_bases)); - xeonsp_ioapic_bases[index++] = ioapic_base; - } - } - } - - return index; -} -#endif - void iio_domain_set_acpi_name(struct device *dev, const char *prefix) { const union xeon_domain_path dn = { |