soc/intel/tigerlake: Update C-State info

C-State latency table was exposed by both intel-idle driver and
BIOS/coreboot. And table in Kernel was used before.
After kernel patch (https://patchwork.kernel.org/patch/11290319/),
only BIOS/coreboot exposes C-State latency table through _CST.
As current C-State latency table info is not correct for Tigerlake,
update proper info according to BWG and reference code.

- Update latency: CpuPowerMgmt.h
  Use BIOS reference code as values in BWG is not up-to-dated
- Remove MSR program for latency: BWG 4.6.4.3.4

Reference:
- TGL BWG #611569 Rev 0.7.6
- https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/
ClientOneSiliconPkg/Cpu/Include/CpuPowerMgmt.h

BUG=b:155223704
BRANCH=None
TEST=Boot to OS and check C-State latency
expected result
>cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency}
POLL
C1_ACPI
C2_ACPI
C3_ACPI
0
1
253
1048

For detail, refer Bug info.

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I8bf2976ad35b4cf6f637a99c26b4f98f9f6ee563
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>

1 files changed, 7 insertions, 13 deletions

diff --git a/src/soc/intel/tigerlake/include/soc/cpu.h b/src/soc/intel/tigerlake/include/soc/cpu.h
index 0d8e17f49b..b52a0c4bfd 100644
--- a/src/soc/intel/tigerlake/include/soc/cpu.h
+++ b/src/soc/intel/tigerlake/include/soc/cpu.h
@@ -6,13 +6,13 @@
 
 #include <intelblocks/msr.h>
 
-/* Latency times in units of 32768ns */
-#define C_STATE_LATENCY_CONTROL_0_LIMIT	0x9d
-#define C_STATE_LATENCY_CONTROL_1_LIMIT	0x9d
-#define C_STATE_LATENCY_CONTROL_2_LIMIT	0x9d
-#define C_STATE_LATENCY_CONTROL_3_LIMIT	0x9d
-#define C_STATE_LATENCY_CONTROL_4_LIMIT	0x9d
-#define C_STATE_LATENCY_CONTROL_5_LIMIT	0x9d
+/* Latency times in us */
+#define C1_LATENCY	1
+#define C6_LATENCY	127
+#define C7_LATENCY	253
+#define C8_LATENCY	260
+#define C9_LATENCY	487
+#define C10_LATENCY	1048
 
 /* Power in units of mW */
 #define C1_POWER	0x3e8
@@ -25,12 +25,6 @@
 /* Common Timer Copy (CTC) frequency - 38.4MHz. */
 #define CTC_FREQ	38400000
 
-#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
-	(((1 << ((base)*5)) * (limit)) / 1000)
-#define C_STATE_LATENCY_FROM_LAT_REG(reg) \
-	C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
-				      (IRTL_1024_NS >> 10))
-
 /* Configure power limits for turbo mode */
 void set_power_limits(u8 power_limit_1_time);