diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-03-22 16:39:57 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-28 16:04:23 +0000 |
| commit | eb6ebc025ed5de4985ef756efe38917fca827981 (patch) | |
| tree | 943e7e0f75ae3446345746127a6d16cd3b438e1d /src/soc/intel/tigerlake/Kconfig | |
| parent | 6edbb18901565d60bc61fda9ac75da08cb94ff84 (diff) | |
soc/intel/tigerlake: Move TCSS code to intel/common/block
The Type-C subsystem ("TCSS") IP block is similar between TGL and
ADL. For pre-boot purposes, the limited amount of functionality required
appears to be common between the two, therefore move the functionality
to intel/common/block and rename from `early_tcss to `tcss` along the way.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1c6bb9c7098691f0c828f9d5ab4bd522515ae966
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51753
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/Kconfig')
| -rw-r--r-- | src/soc/intel/tigerlake/Kconfig | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index afebc0f3c4..d77ad52723 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -239,17 +239,6 @@ config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x2000 -config EARLY_TCSS - bool "Enable early TCSS device Init" - help - Sets up USB2/3 port mapping in TCSS MUX and sets MUX to disconnect state - -config EARLY_TCSS_DISPLAY - bool "Enable early TCSS display" if EARLY_TCSS - depends on EARLY_TCSS && RUN_FSP_GOP - help - Enable displays to be detected over Type-C ports during boot. - config DATA_BUS_WIDTH int default 128 |