FSP 1.1: Replace soc_ prefix with fsp_

Rename soc_display_upd_value to fsp_display_upd_value since the routine
was moved from src/soc/intel/common into src/drivers/intel/fsp1_1.

BRANCH=none
BUG=None
TEST=Build and run on Kunimitsu

Change-Id: Ifadf9dcdf8c81f8de961e074226c349fb9634792
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 95238782702999a178989467694ac1f15c079615
Original-Change-Id: Ibd26ea41bd5c7a54ecd3c237f7fb7bad6dbf7d8a
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/306351
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12157
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>

2 files changed, 219 insertions, 219 deletions

diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 51dcbd32c8..2613d38474 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -368,204 +368,204 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *original,
 {
 	/* Display the parameters for SiliconInit */
 	printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
-	soc_display_upd_value("LogoPtr", 4,
+	fsp_display_upd_value("LogoPtr", 4,
 			(uint32_t)original->LogoPtr,
 			(uint32_t)params->LogoPtr);
-	soc_display_upd_value("LogoSize", 4,
+	fsp_display_upd_value("LogoSize", 4,
 		(uint32_t)original->LogoSize,
 		(uint32_t)params->LogoSize);
-	soc_display_upd_value("GraphicsConfigPtr", 4,
+	fsp_display_upd_value("GraphicsConfigPtr", 4,
 		(uint32_t)original->GraphicsConfigPtr,
 		(uint32_t)params->GraphicsConfigPtr);
-	soc_display_upd_value("MicrocodeRegionBase", 4,
+	fsp_display_upd_value("MicrocodeRegionBase", 4,
 		(uint32_t)original->MicrocodeRegionBase,
 		(uint32_t)params->MicrocodeRegionBase);
-	soc_display_upd_value("MicrocodeRegionSize", 4,
+	fsp_display_upd_value("MicrocodeRegionSize", 4,
 		(uint32_t)original->MicrocodeRegionSize,
 		(uint32_t)params->MicrocodeRegionSize);
-	soc_display_upd_value("TurboMode", 1,
+	fsp_display_upd_value("TurboMode", 1,
 		(uint32_t)original->TurboMode,
 		(uint32_t)params->TurboMode);
-	soc_display_upd_value("Device4Enable", 1,
+	fsp_display_upd_value("Device4Enable", 1,
 		original->Device4Enable,
 		params->Device4Enable);
-	soc_display_upd_value("SataSalpSupport", 1, original->SataSalpSupport,
+	fsp_display_upd_value("SataSalpSupport", 1, original->SataSalpSupport,
 		params->SataSalpSupport);
-	soc_display_upd_value("SataPortsEnable[0]", 1,
+	fsp_display_upd_value("SataPortsEnable[0]", 1,
 		original->SataPortsEnable[0], params->SataPortsEnable[0]);
-	soc_display_upd_value("SataPortsEnable[1]", 1,
+	fsp_display_upd_value("SataPortsEnable[1]", 1,
 		original->SataPortsEnable[1], params->SataPortsEnable[1]);
-	soc_display_upd_value("SataPortsEnable[2]", 1,
+	fsp_display_upd_value("SataPortsEnable[2]", 1,
 		original->SataPortsEnable[2], params->SataPortsEnable[2]);
-	soc_display_upd_value("SataPortsEnable[3]", 1,
+	fsp_display_upd_value("SataPortsEnable[3]", 1,
 		original->SataPortsEnable[3], params->SataPortsEnable[3]);
-	soc_display_upd_value("SataPortsEnable[4]", 1,
+	fsp_display_upd_value("SataPortsEnable[4]", 1,
 		original->SataPortsEnable[4], params->SataPortsEnable[4]);
-	soc_display_upd_value("SataPortsEnable[5]", 1,
+	fsp_display_upd_value("SataPortsEnable[5]", 1,
 		original->SataPortsEnable[5], params->SataPortsEnable[5]);
-	soc_display_upd_value("SataPortsEnable[6]", 1,
+	fsp_display_upd_value("SataPortsEnable[6]", 1,
 		original->SataPortsEnable[6], params->SataPortsEnable[6]);
-	soc_display_upd_value("SataPortsEnable[7]", 1,
+	fsp_display_upd_value("SataPortsEnable[7]", 1,
 		original->SataPortsEnable[7], params->SataPortsEnable[7]);
-	soc_display_upd_value("SataPortsDevSlp[0]", 1,
+	fsp_display_upd_value("SataPortsDevSlp[0]", 1,
 		original->SataPortsDevSlp[0], params->SataPortsDevSlp[0]);
-	soc_display_upd_value("SataPortsDevSlp[1]", 1,
+	fsp_display_upd_value("SataPortsDevSlp[1]", 1,
 		original->SataPortsDevSlp[1], params->SataPortsDevSlp[1]);
-	soc_display_upd_value("SataPortsDevSlp[2]", 1,
+	fsp_display_upd_value("SataPortsDevSlp[2]", 1,
 		original->SataPortsDevSlp[2], params->SataPortsDevSlp[2]);
-	soc_display_upd_value("SataPortsDevSlp[3]", 1,
+	fsp_display_upd_value("SataPortsDevSlp[3]", 1,
 		original->SataPortsDevSlp[3], params->SataPortsDevSlp[3]);
-	soc_display_upd_value("SataPortsDevSlp[4]", 1,
+	fsp_display_upd_value("SataPortsDevSlp[4]", 1,
 		original->SataPortsDevSlp[4], params->SataPortsDevSlp[4]);
-	soc_display_upd_value("SataPortsDevSlp[5]", 1,
+	fsp_display_upd_value("SataPortsDevSlp[5]", 1,
 		original->SataPortsDevSlp[5], params->SataPortsDevSlp[5]);
-	soc_display_upd_value("SataPortsDevSlp[6]", 1,
+	fsp_display_upd_value("SataPortsDevSlp[6]", 1,
 		original->SataPortsDevSlp[6], params->SataPortsDevSlp[6]);
-	soc_display_upd_value("SataPortsDevSlp[7]", 1,
+	fsp_display_upd_value("SataPortsDevSlp[7]", 1,
 		original->SataPortsDevSlp[7], params->SataPortsDevSlp[7]);
-	soc_display_upd_value("EnableAzalia", 1,
+	fsp_display_upd_value("EnableAzalia", 1,
 		original->EnableAzalia,	params->EnableAzalia);
-	soc_display_upd_value("DspEnable", 1, original->DspEnable,
+	fsp_display_upd_value("DspEnable", 1, original->DspEnable,
 		params->DspEnable);
-	soc_display_upd_value("IoBufferOwnership", 1,
+	fsp_display_upd_value("IoBufferOwnership", 1,
 		original->IoBufferOwnership, params->IoBufferOwnership);
-	soc_display_upd_value("PortUsb20Enable[0]", 1,
+	fsp_display_upd_value("PortUsb20Enable[0]", 1,
 		original->PortUsb20Enable[0], params->PortUsb20Enable[0]);
-	soc_display_upd_value("PortUsb20Enable[1]", 1,
+	fsp_display_upd_value("PortUsb20Enable[1]", 1,
 		original->PortUsb20Enable[1], params->PortUsb20Enable[1]);
-	soc_display_upd_value("PortUsb20Enable[2]", 1,
+	fsp_display_upd_value("PortUsb20Enable[2]", 1,
 		original->PortUsb20Enable[2], params->PortUsb20Enable[2]);
-	soc_display_upd_value("PortUsb20Enable[3]", 1,
+	fsp_display_upd_value("PortUsb20Enable[3]", 1,
 		original->PortUsb20Enable[3], params->PortUsb20Enable[3]);
-	soc_display_upd_value("PortUsb20Enable[4]", 1,
+	fsp_display_upd_value("PortUsb20Enable[4]", 1,
 		original->PortUsb20Enable[4], params->PortUsb20Enable[4]);
-	soc_display_upd_value("PortUsb20Enable[5]", 1,
+	fsp_display_upd_value("PortUsb20Enable[5]", 1,
 		original->PortUsb20Enable[5], params->PortUsb20Enable[5]);
-	soc_display_upd_value("PortUsb20Enable[6]", 1,
+	fsp_display_upd_value("PortUsb20Enable[6]", 1,
 		original->PortUsb20Enable[6], params->PortUsb20Enable[6]);
-	soc_display_upd_value("PortUsb20Enable[7]", 1,
+	fsp_display_upd_value("PortUsb20Enable[7]", 1,
 		original->PortUsb20Enable[7], params->PortUsb20Enable[7]);
-	soc_display_upd_value("PortUsb20Enable[8]", 1,
+	fsp_display_upd_value("PortUsb20Enable[8]", 1,
 		original->PortUsb20Enable[8], params->PortUsb20Enable[8]);
-	soc_display_upd_value("PortUsb20Enable[9]", 1,
+	fsp_display_upd_value("PortUsb20Enable[9]", 1,
 		original->PortUsb20Enable[9], params->PortUsb20Enable[9]);
-	soc_display_upd_value("PortUsb20Enable[10]", 1,
+	fsp_display_upd_value("PortUsb20Enable[10]", 1,
 		original->PortUsb20Enable[10], params->PortUsb20Enable[10]);
-	soc_display_upd_value("PortUsb20Enable[11]", 1,
+	fsp_display_upd_value("PortUsb20Enable[11]", 1,
 		original->PortUsb20Enable[11], params->PortUsb20Enable[11]);
-	soc_display_upd_value("PortUsb20Enable[12]", 1,
+	fsp_display_upd_value("PortUsb20Enable[12]", 1,
 		original->PortUsb20Enable[12], params->PortUsb20Enable[12]);
-	soc_display_upd_value("PortUsb20Enable[13]", 1,
+	fsp_display_upd_value("PortUsb20Enable[13]", 1,
 		original->PortUsb20Enable[13], params->PortUsb20Enable[13]);
-	soc_display_upd_value("PortUsb20Enable[14]", 1,
+	fsp_display_upd_value("PortUsb20Enable[14]", 1,
 		original->PortUsb20Enable[14], params->PortUsb20Enable[14]);
-	soc_display_upd_value("PortUsb20Enable[15]", 1,
+	fsp_display_upd_value("PortUsb20Enable[15]", 1,
 		original->PortUsb20Enable[15], params->PortUsb20Enable[15]);
-	soc_display_upd_value("PortUsb30Enable[0]", 1,
+	fsp_display_upd_value("PortUsb30Enable[0]", 1,
 		original->PortUsb30Enable[0], params->PortUsb30Enable[0]);
-	soc_display_upd_value("PortUsb30Enable[1]", 1,
+	fsp_display_upd_value("PortUsb30Enable[1]", 1,
 		original->PortUsb30Enable[1], params->PortUsb30Enable[1]);
-	soc_display_upd_value("PortUsb30Enable[2]", 1,
+	fsp_display_upd_value("PortUsb30Enable[2]", 1,
 		original->PortUsb30Enable[2], params->PortUsb30Enable[2]);
-	soc_display_upd_value("PortUsb30Enable[3]", 1,
+	fsp_display_upd_value("PortUsb30Enable[3]", 1,
 		original->PortUsb30Enable[3], params->PortUsb30Enable[3]);
-	soc_display_upd_value("PortUsb30Enable[4]", 1,
+	fsp_display_upd_value("PortUsb30Enable[4]", 1,
 		original->PortUsb30Enable[4], params->PortUsb30Enable[4]);
-	soc_display_upd_value("PortUsb30Enable[5]", 1,
+	fsp_display_upd_value("PortUsb30Enable[5]", 1,
 		original->PortUsb30Enable[5], params->PortUsb30Enable[5]);
-	soc_display_upd_value("PortUsb30Enable[6]", 1,
+	fsp_display_upd_value("PortUsb30Enable[6]", 1,
 		original->PortUsb30Enable[6], params->PortUsb30Enable[6]);
-	soc_display_upd_value("PortUsb30Enable[7]", 1,
+	fsp_display_upd_value("PortUsb30Enable[7]", 1,
 		original->PortUsb30Enable[7], params->PortUsb30Enable[7]);
-	soc_display_upd_value("PortUsb30Enable[8]", 1,
+	fsp_display_upd_value("PortUsb30Enable[8]", 1,
 		original->PortUsb30Enable[8], params->PortUsb30Enable[8]);
-	soc_display_upd_value("PortUsb30Enable[9]", 1,
+	fsp_display_upd_value("PortUsb30Enable[9]", 1,
 		original->PortUsb30Enable[9], params->PortUsb30Enable[9]);
-	soc_display_upd_value("XdciEnable", 1, original->XdciEnable,
+	fsp_display_upd_value("XdciEnable", 1, original->XdciEnable,
 		params->XdciEnable);
-	soc_display_upd_value("SsicPortEnable", 1, original->SsicPortEnable,
+	fsp_display_upd_value("SsicPortEnable", 1, original->SsicPortEnable,
 		params->SsicPortEnable);
-	soc_display_upd_value("SmbusEnable", 1, original->SmbusEnable,
+	fsp_display_upd_value("SmbusEnable", 1, original->SmbusEnable,
 		params->SmbusEnable);
-	soc_display_upd_value("SerialIoDevMode[0]", 1,
+	fsp_display_upd_value("SerialIoDevMode[0]", 1,
 		original->SerialIoDevMode[0], params->SerialIoDevMode[0]);
-	soc_display_upd_value("SerialIoDevMode[1]", 1,
+	fsp_display_upd_value("SerialIoDevMode[1]", 1,
 		original->SerialIoDevMode[1], params->SerialIoDevMode[1]);
-	soc_display_upd_value("SerialIoDevMode[2]", 1,
+	fsp_display_upd_value("SerialIoDevMode[2]", 1,
 		original->SerialIoDevMode[2], params->SerialIoDevMode[2]);
-	soc_display_upd_value("SerialIoDevMode[3]", 1,
+	fsp_display_upd_value("SerialIoDevMode[3]", 1,
 		original->SerialIoDevMode[3], params->SerialIoDevMode[3]);
-	soc_display_upd_value("SerialIoDevMode[4]", 1,
+	fsp_display_upd_value("SerialIoDevMode[4]", 1,
 		original->SerialIoDevMode[4], params->SerialIoDevMode[4]);
-	soc_display_upd_value("SerialIoDevMode[5]", 1,
+	fsp_display_upd_value("SerialIoDevMode[5]", 1,
 		original->SerialIoDevMode[5], params->SerialIoDevMode[5]);
-	soc_display_upd_value("SerialIoDevMode[6]", 1,
+	fsp_display_upd_value("SerialIoDevMode[6]", 1,
 		original->SerialIoDevMode[6], params->SerialIoDevMode[6]);
-	soc_display_upd_value("SerialIoDevMode[7]", 1,
+	fsp_display_upd_value("SerialIoDevMode[7]", 1,
 		original->SerialIoDevMode[7], params->SerialIoDevMode[7]);
-	soc_display_upd_value("SerialIoDevMode[8]", 1,
+	fsp_display_upd_value("SerialIoDevMode[8]", 1,
 		original->SerialIoDevMode[8], params->SerialIoDevMode[8]);
-	soc_display_upd_value("SerialIoDevMode[9]", 1,
+	fsp_display_upd_value("SerialIoDevMode[9]", 1,
 		original->SerialIoDevMode[9], params->SerialIoDevMode[9]);
-	soc_display_upd_value("SerialIoDevMode[10]", 1,
+	fsp_display_upd_value("SerialIoDevMode[10]", 1,
 		original->SerialIoDevMode[10], params->SerialIoDevMode[10]);
-	soc_display_upd_value("ScsEmmcEnabled", 1, original->ScsEmmcEnabled,
+	fsp_display_upd_value("ScsEmmcEnabled", 1, original->ScsEmmcEnabled,
 		params->ScsEmmcEnabled);
-	soc_display_upd_value("ScsEmmcHs400Enabled", 1,
+	fsp_display_upd_value("ScsEmmcHs400Enabled", 1,
 		original->ScsEmmcHs400Enabled, params->ScsEmmcHs400Enabled);
-	soc_display_upd_value("ScsSdCardEnabled", 1, original->ScsSdCardEnabled,
+	fsp_display_upd_value("ScsSdCardEnabled", 1, original->ScsSdCardEnabled,
 		params->ScsSdCardEnabled);
-	soc_display_upd_value("IshEnable", 1, original->IshEnable,
+	fsp_display_upd_value("IshEnable", 1, original->IshEnable,
 		params->IshEnable);
-	soc_display_upd_value("ShowSpiController", 1,
+	fsp_display_upd_value("ShowSpiController", 1,
 		original->ShowSpiController, params->ShowSpiController);
-	soc_display_upd_value("HsioMessaging", 1, original->HsioMessaging,
+	fsp_display_upd_value("HsioMessaging", 1, original->HsioMessaging,
 		params->HsioMessaging);
-	soc_display_upd_value("Heci3Enabled", 1, original->Heci3Enabled,
+	fsp_display_upd_value("Heci3Enabled", 1, original->Heci3Enabled,
 		params->Heci3Enabled);
-	soc_display_upd_value("RtcLock", 1, original->RtcLock,
+	fsp_display_upd_value("RtcLock", 1, original->RtcLock,
 		params->RtcLock);
-	soc_display_upd_value("EnableSata", 1, original->EnableSata,
+	fsp_display_upd_value("EnableSata", 1, original->EnableSata,
 		params->EnableSata);
-	soc_display_upd_value("SataMode", 1, original->SataMode,
+	fsp_display_upd_value("SataMode", 1, original->SataMode,
 		params->SataMode);
-	soc_display_upd_value("NumOfDevIntConfig", 1,
+	fsp_display_upd_value("NumOfDevIntConfig", 1,
 		original->NumOfDevIntConfig,
 		params->NumOfDevIntConfig);
-	soc_display_upd_value("PxRcConfig[PARC]", 1,
+	fsp_display_upd_value("PxRcConfig[PARC]", 1,
 		original->PxRcConfig[PCH_PARC],
 		params->PxRcConfig[PCH_PARC]);
-	soc_display_upd_value("PxRcConfig[PBRC]", 1,
+	fsp_display_upd_value("PxRcConfig[PBRC]", 1,
 		original->PxRcConfig[PCH_PBRC],
 		params->PxRcConfig[PCH_PBRC]);
-	soc_display_upd_value("PxRcConfig[PCRC]", 1,
+	fsp_display_upd_value("PxRcConfig[PCRC]", 1,
 		original->PxRcConfig[PCH_PCRC],
 		params->PxRcConfig[PCH_PCRC]);
-	soc_display_upd_value("PxRcConfig[PDRC]", 1,
+	fsp_display_upd_value("PxRcConfig[PDRC]", 1,
 		original->PxRcConfig[PCH_PDRC],
 		params->PxRcConfig[PCH_PDRC]);
-	soc_display_upd_value("PxRcConfig[PERC]", 1,
+	fsp_display_upd_value("PxRcConfig[PERC]", 1,
 		original->PxRcConfig[PCH_PERC],
 		params->PxRcConfig[PCH_PERC]);
-	soc_display_upd_value("PxRcConfig[PFRC]", 1,
+	fsp_display_upd_value("PxRcConfig[PFRC]", 1,
 		original->PxRcConfig[PCH_PFRC],
 		params->PxRcConfig[PCH_PFRC]);
-	soc_display_upd_value("PxRcConfig[PGRC]", 1,
+	fsp_display_upd_value("PxRcConfig[PGRC]", 1,
 		original->PxRcConfig[PCH_PGRC],
 		params->PxRcConfig[PCH_PGRC]);
-	soc_display_upd_value("PxRcConfig[PHRC]", 1,
+	fsp_display_upd_value("PxRcConfig[PHRC]", 1,
 		original->PxRcConfig[PCH_PHRC],
 		params->PxRcConfig[PCH_PHRC]);
-	soc_display_upd_value("GpioIrqRoute", 1,
+	fsp_display_upd_value("GpioIrqRoute", 1,
 		original->GpioIrqRoute,
 		params->GpioIrqRoute);
-	soc_display_upd_value("SciIrqSelect", 1,
+	fsp_display_upd_value("SciIrqSelect", 1,
 		original->SciIrqSelect,
 		params->SciIrqSelect);
-	soc_display_upd_value("TcoIrqSelect", 1,
+	fsp_display_upd_value("TcoIrqSelect", 1,
 		original->TcoIrqSelect,
 		params->TcoIrqSelect);
-	soc_display_upd_value("TcoIrqEnable", 1,
+	fsp_display_upd_value("TcoIrqEnable", 1,
 		original->TcoIrqEnable,
 		params->TcoIrqEnable);
 }
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 3c60b163fa..3cf817bbde 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -113,296 +113,296 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
 	/* Display the parameters for MemoryInit */
 	printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
 
-	soc_display_upd_value("PlatformMemorySize", 8,
+	fsp_display_upd_value("PlatformMemorySize", 8,
 		old->PlatformMemorySize, new->PlatformMemorySize);
-	soc_display_upd_value("MemorySpdPtr00", 4, old->MemorySpdPtr00,
+	fsp_display_upd_value("MemorySpdPtr00", 4, old->MemorySpdPtr00,
 		new->MemorySpdPtr00);
-	soc_display_upd_value("MemorySpdPtr01", 4, old->MemorySpdPtr01,
+	fsp_display_upd_value("MemorySpdPtr01", 4, old->MemorySpdPtr01,
 		new->MemorySpdPtr01);
-	soc_display_upd_value("MemorySpdPtr10", 4, old->MemorySpdPtr10,
+	fsp_display_upd_value("MemorySpdPtr10", 4, old->MemorySpdPtr10,
 		new->MemorySpdPtr10);
-	soc_display_upd_value("MemorySpdPtr11", 4, old->MemorySpdPtr11,
+	fsp_display_upd_value("MemorySpdPtr11", 4, old->MemorySpdPtr11,
 		new->MemorySpdPtr11);
-	soc_display_upd_value("MemorySpdDataLen", 2, old->MemorySpdDataLen,
+	fsp_display_upd_value("MemorySpdDataLen", 2, old->MemorySpdDataLen,
 		new->MemorySpdDataLen);
-	soc_display_upd_value("DqByteMapCh0[0]", 1, old->DqByteMapCh0[0],
+	fsp_display_upd_value("DqByteMapCh0[0]", 1, old->DqByteMapCh0[0],
 		new->DqByteMapCh0[0]);
-	soc_display_upd_value("DqByteMapCh0[1]", 1, old->DqByteMapCh0[1],
+	fsp_display_upd_value("DqByteMapCh0[1]", 1, old->DqByteMapCh0[1],
 		new->DqByteMapCh0[1]);
-	soc_display_upd_value("DqByteMapCh0[2]", 1, old->DqByteMapCh0[2],
+	fsp_display_upd_value("DqByteMapCh0[2]", 1, old->DqByteMapCh0[2],
 		new->DqByteMapCh0[2]);
-	soc_display_upd_value("DqByteMapCh0[3]", 1, old->DqByteMapCh0[3],
+	fsp_display_upd_value("DqByteMapCh0[3]", 1, old->DqByteMapCh0[3],
 		new->DqByteMapCh0[3]);
-	soc_display_upd_value("DqByteMapCh0[4]", 1, old->DqByteMapCh0[4],
+	fsp_display_upd_value("DqByteMapCh0[4]", 1, old->DqByteMapCh0[4],
 		new->DqByteMapCh0[4]);
-	soc_display_upd_value("DqByteMapCh0[5]", 1, old->DqByteMapCh0[5],
+	fsp_display_upd_value("DqByteMapCh0[5]", 1, old->DqByteMapCh0[5],
 		new->DqByteMapCh0[5]);
-	soc_display_upd_value("DqByteMapCh0[6]", 1, old->DqByteMapCh0[6],
+	fsp_display_upd_value("DqByteMapCh0[6]", 1, old->DqByteMapCh0[6],
 		new->DqByteMapCh0[6]);
-	soc_display_upd_value("DqByteMapCh0[7]", 1, old->DqByteMapCh0[7],
+	fsp_display_upd_value("DqByteMapCh0[7]", 1, old->DqByteMapCh0[7],
 		new->DqByteMapCh0[7]);
-	soc_display_upd_value("DqByteMapCh0[8]", 1, old->DqByteMapCh0[8],
+	fsp_display_upd_value("DqByteMapCh0[8]", 1, old->DqByteMapCh0[8],
 		new->DqByteMapCh0[8]);
-	soc_display_upd_value("DqByteMapCh0[9]", 1, old->DqByteMapCh0[9],
+	fsp_display_upd_value("DqByteMapCh0[9]", 1, old->DqByteMapCh0[9],
 		new->DqByteMapCh0[9]);
-	soc_display_upd_value("DqByteMapCh0[10]", 1, old->DqByteMapCh0[10],
+	fsp_display_upd_value("DqByteMapCh0[10]", 1, old->DqByteMapCh0[10],
 		new->DqByteMapCh0[10]);
-	soc_display_upd_value("DqByteMapCh0[11]", 1, old->DqByteMapCh0[11],
+	fsp_display_upd_value("DqByteMapCh0[11]", 1, old->DqByteMapCh0[11],
 		new->DqByteMapCh0[11]);
-	soc_display_upd_value("DqByteMapCh1[0]", 1, old->DqByteMapCh1[0],
+	fsp_display_upd_value("DqByteMapCh1[0]", 1, old->DqByteMapCh1[0],
 		new->DqByteMapCh1[0]);
-	soc_display_upd_value("DqByteMapCh1[1]", 1, old->DqByteMapCh1[1],
+	fsp_display_upd_value("DqByteMapCh1[1]", 1, old->DqByteMapCh1[1],
 		new->DqByteMapCh1[1]);
-	soc_display_upd_value("DqByteMapCh1[2]", 1, old->DqByteMapCh1[2],
+	fsp_display_upd_value("DqByteMapCh1[2]", 1, old->DqByteMapCh1[2],
 		new->DqByteMapCh1[2]);
-	soc_display_upd_value("DqByteMapCh1[3]", 1, old->DqByteMapCh1[3],
+	fsp_display_upd_value("DqByteMapCh1[3]", 1, old->DqByteMapCh1[3],
 		new->DqByteMapCh1[3]);
-	soc_display_upd_value("DqByteMapCh1[4]", 1, old->DqByteMapCh1[4],
+	fsp_display_upd_value("DqByteMapCh1[4]", 1, old->DqByteMapCh1[4],
 		new->DqByteMapCh1[4]);
-	soc_display_upd_value("DqByteMapCh1[5]", 1, old->DqByteMapCh1[5],
+	fsp_display_upd_value("DqByteMapCh1[5]", 1, old->DqByteMapCh1[5],
 		new->DqByteMapCh1[5]);
-	soc_display_upd_value("DqByteMapCh1[6]", 1, old->DqByteMapCh1[6],
+	fsp_display_upd_value("DqByteMapCh1[6]", 1, old->DqByteMapCh1[6],
 		new->DqByteMapCh1[6]);
-	soc_display_upd_value("DqByteMapCh1[7]", 1, old->DqByteMapCh1[7],
+	fsp_display_upd_value("DqByteMapCh1[7]", 1, old->DqByteMapCh1[7],
 		new->DqByteMapCh1[7]);
-	soc_display_upd_value("DqByteMapCh1[8]", 1, old->DqByteMapCh1[8],
+	fsp_display_upd_value("DqByteMapCh1[8]", 1, old->DqByteMapCh1[8],
 		new->DqByteMapCh1[8]);
-	soc_display_upd_value("DqByteMapCh1[9]", 1, old->DqByteMapCh1[9],
+	fsp_display_upd_value("DqByteMapCh1[9]", 1, old->DqByteMapCh1[9],
 		new->DqByteMapCh1[9]);
-	soc_display_upd_value("DqByteMapCh1[10]", 1, old->DqByteMapCh1[10],
+	fsp_display_upd_value("DqByteMapCh1[10]", 1, old->DqByteMapCh1[10],
 		new->DqByteMapCh1[10]);
-	soc_display_upd_value("DqByteMapCh1[11]", 1, old->DqByteMapCh1[11],
+	fsp_display_upd_value("DqByteMapCh1[11]", 1, old->DqByteMapCh1[11],
 		new->DqByteMapCh1[11]);
-	soc_display_upd_value("DqsMapCpu2DramCh0[0]", 1,
+	fsp_display_upd_value("DqsMapCpu2DramCh0[0]", 1,
 		old->DqsMapCpu2DramCh0[0], new->DqsMapCpu2DramCh0[0]);
-	soc_display_upd_value("DqsMapCpu2DramCh0[1]", 1,
+	fsp_display_upd_value("DqsMapCpu2DramCh0[1]", 1,
 		old->DqsMapCpu2DramCh0[1], new->DqsMapCpu2DramCh0[1]);
-	soc_display_upd_value("DqsMapCpu2DramCh0[2]", 1,
+	fsp_display_upd_value("DqsMapCpu2DramCh0[2]", 1,
 		old->DqsMapCpu2DramCh0[2], new->DqsMapCpu2DramCh0[2]);
-	soc_display_upd_value("DqsMapCpu2DramCh0[3]", 1,
+	fsp_display_upd_value("DqsMapCpu2DramCh0[3]", 1,
 		old->DqsMapCpu2DramCh0[3], new->DqsMapCpu2DramCh0[3]);
-	soc_display_upd_value("DqsMapCpu2DramCh0[4]", 1,
+	fsp_display_upd_value("DqsMapCpu2DramCh0[4]", 1,
 		old->DqsMapCpu2DramCh0[4], new->DqsMapCpu2DramCh0[4]);
-	soc_display_upd_value("DqsMapCpu2DramCh0[5]", 1,
+	fsp_display_upd_value("DqsMapCpu2DramCh0[5]", 1,
 		old->DqsMapCpu2DramCh0[5], new->DqsMapCpu2DramCh0[5]);
-	soc_display_upd_value("DqsMapCpu2DramCh0[6]", 1,
+	fsp_display_upd_value("DqsMapCpu2DramCh0[6]", 1,
 		old->DqsMapCpu2DramCh0[6], new->DqsMapCpu2DramCh0[6]);
-	soc_display_upd_value("DqsMapCpu2DramCh0[7]", 1,
+	fsp_display_upd_value("DqsMapCpu2DramCh0[7]", 1,
 		old->DqsMapCpu2DramCh0[7], new->DqsMapCpu2DramCh0[7]);
-	soc_display_upd_value("DqsMapCpu2DramCh1[0]", 1,
+	fsp_display_upd_value("DqsMapCpu2DramCh1[0]", 1,
 		old->DqsMapCpu2DramCh1[0], new->DqsMapCpu2DramCh1[0]);
-	soc_display_upd_value("DqsMapCpu2DramCh1[1]", 1,
+	fsp_display_upd_value("DqsMapCpu2DramCh1[1]", 1,
 		old->DqsMapCpu2DramCh1[1], new->DqsMapCpu2DramCh1[1]);
-	soc_display_upd_value("DqsMapCpu2DramCh1[2]", 1,
+	fsp_display_upd_value("DqsMapCpu2DramCh1[2]", 1,
 		old->DqsMapCpu2DramCh1[2], new->DqsMapCpu2DramCh1[2]);
-	soc_display_upd_value("DqsMapCpu2DramCh1[3]", 1,
+	fsp_display_upd_value("DqsMapCpu2DramCh1[3]", 1,
 		old->DqsMapCpu2DramCh1[3], new->DqsMapCpu2DramCh1[3]);
-	soc_display_upd_value("DqsMapCpu2DramCh1[4]", 1,
+	fsp_display_upd_value("DqsMapCpu2DramCh1[4]", 1,
 		old->DqsMapCpu2DramCh1[4], new->DqsMapCpu2DramCh1[4]);
-	soc_display_upd_value("DqsMapCpu2DramCh1[5]", 1,
+	fsp_display_upd_value("DqsMapCpu2DramCh1[5]", 1,
 		old->DqsMapCpu2DramCh1[5], new->DqsMapCpu2DramCh1[5]);
-	soc_display_upd_value("DqsMapCpu2DramCh1[6]", 1,
+	fsp_display_upd_value("DqsMapCpu2DramCh1[6]", 1,
 		old->DqsMapCpu2DramCh1[6], new->DqsMapCpu2DramCh1[6]);
-	soc_display_upd_value("DqsMapCpu2DramCh1[7]", 1,
+	fsp_display_upd_value("DqsMapCpu2DramCh1[7]", 1,
 		old->DqsMapCpu2DramCh1[7], new->DqsMapCpu2DramCh1[7]);
-	soc_display_upd_value("DqPinsInterleaved", 1,
+	fsp_display_upd_value("DqPinsInterleaved", 1,
 		old->DqPinsInterleaved, new->DqPinsInterleaved);
-	soc_display_upd_value("RcompResistor[0]", 2, old->RcompResistor[0],
+	fsp_display_upd_value("RcompResistor[0]", 2, old->RcompResistor[0],
 		new->RcompResistor[0]);
-	soc_display_upd_value("RcompResistor[1]", 2, old->RcompResistor[1],
+	fsp_display_upd_value("RcompResistor[1]", 2, old->RcompResistor[1],
 		new->RcompResistor[1]);
-	soc_display_upd_value("RcompResistor[2]", 2, old->RcompResistor[2],
+	fsp_display_upd_value("RcompResistor[2]", 2, old->RcompResistor[2],
 		new->RcompResistor[2]);
-	soc_display_upd_value("RcompTarget[0]", 1, old->RcompTarget[0],
+	fsp_display_upd_value("RcompTarget[0]", 1, old->RcompTarget[0],
 		new->RcompTarget[0]);
-	soc_display_upd_value("RcompTarget[1]", 1, old->RcompTarget[1],
+	fsp_display_upd_value("RcompTarget[1]", 1, old->RcompTarget[1],
 		new->RcompTarget[1]);
-	soc_display_upd_value("RcompTarget[2]", 1, old->RcompTarget[2],
+	fsp_display_upd_value("RcompTarget[2]", 1, old->RcompTarget[2],
 		new->RcompTarget[2]);
-	soc_display_upd_value("RcompTarget[3]", 1, old->RcompTarget[3],
+	fsp_display_upd_value("RcompTarget[3]", 1, old->RcompTarget[3],
 		new->RcompTarget[3]);
-	soc_display_upd_value("RcompTarget[4]", 1, old->RcompTarget[4],
+	fsp_display_upd_value("RcompTarget[4]", 1, old->RcompTarget[4],
 		new->RcompTarget[4]);
-	soc_display_upd_value("CaVrefConfig", 1, old->CaVrefConfig,
+	fsp_display_upd_value("CaVrefConfig", 1, old->CaVrefConfig,
 		new->CaVrefConfig);
-	soc_display_upd_value("SmramMask", 1, old->SmramMask, new->SmramMask);
-	soc_display_upd_value("MrcFastBoot", 1, old->MrcFastBoot,
+	fsp_display_upd_value("SmramMask", 1, old->SmramMask, new->SmramMask);
+	fsp_display_upd_value("MrcFastBoot", 1, old->MrcFastBoot,
 		new->MrcFastBoot);
-	soc_display_upd_value("IedSize", 4, old->IedSize, new->IedSize);
-	soc_display_upd_value("TsegSize", 4, old->TsegSize, new->TsegSize);
-	soc_display_upd_value("MmioSize", 2, old->MmioSize, new->MmioSize);
-	soc_display_upd_value("EnableLan", 1, old->EnableLan, new->EnableLan);
-	soc_display_upd_value("EnableTraceHub", 1, old->EnableTraceHub,
+	fsp_display_upd_value("IedSize", 4, old->IedSize, new->IedSize);
+	fsp_display_upd_value("TsegSize", 4, old->TsegSize, new->TsegSize);
+	fsp_display_upd_value("MmioSize", 2, old->MmioSize, new->MmioSize);
+	fsp_display_upd_value("EnableLan", 1, old->EnableLan, new->EnableLan);
+	fsp_display_upd_value("EnableTraceHub", 1, old->EnableTraceHub,
 		new->EnableTraceHub);
-	soc_display_upd_value("PcieRpEnable[0]", 1, old->PcieRpEnable[0],
+	fsp_display_upd_value("PcieRpEnable[0]", 1, old->PcieRpEnable[0],
 		new->PcieRpEnable[0]);
-	soc_display_upd_value("PcieRpEnable[1]", 1, old->PcieRpEnable[1],
+	fsp_display_upd_value("PcieRpEnable[1]", 1, old->PcieRpEnable[1],
 		new->PcieRpEnable[1]);
-	soc_display_upd_value("PcieRpEnable[2]", 1, old->PcieRpEnable[2],
+	fsp_display_upd_value("PcieRpEnable[2]", 1, old->PcieRpEnable[2],
 		new->PcieRpEnable[2]);
-	soc_display_upd_value("PcieRpEnable[3]", 1, old->PcieRpEnable[3],
+	fsp_display_upd_value("PcieRpEnable[3]", 1, old->PcieRpEnable[3],
 		new->PcieRpEnable[3]);
-	soc_display_upd_value("PcieRpEnable[4]", 1, old->PcieRpEnable[4],
+	fsp_display_upd_value("PcieRpEnable[4]", 1, old->PcieRpEnable[4],
 		new->PcieRpEnable[4]);
-	soc_display_upd_value("PcieRpEnable[5]", 1, old->PcieRpEnable[5],
+	fsp_display_upd_value("PcieRpEnable[5]", 1, old->PcieRpEnable[5],
 		new->PcieRpEnable[5]);
-	soc_display_upd_value("PcieRpEnable[6]", 1, old->PcieRpEnable[6],
+	fsp_display_upd_value("PcieRpEnable[6]", 1, old->PcieRpEnable[6],
 		new->PcieRpEnable[6]);
-	soc_display_upd_value("PcieRpEnable[7]", 1, old->PcieRpEnable[7],
+	fsp_display_upd_value("PcieRpEnable[7]", 1, old->PcieRpEnable[7],
 		new->PcieRpEnable[7]);
-	soc_display_upd_value("PcieRpEnable[8]", 1, old->PcieRpEnable[8],
+	fsp_display_upd_value("PcieRpEnable[8]", 1, old->PcieRpEnable[8],
 		new->PcieRpEnable[8]);
-	soc_display_upd_value("PcieRpEnable[9]", 1, old->PcieRpEnable[9],
+	fsp_display_upd_value("PcieRpEnable[9]", 1, old->PcieRpEnable[9],
 		new->PcieRpEnable[9]);
-	soc_display_upd_value("PcieRpEnable[10]", 1, old->PcieRpEnable[10],
+	fsp_display_upd_value("PcieRpEnable[10]", 1, old->PcieRpEnable[10],
 		new->PcieRpEnable[10]);
-	soc_display_upd_value("PcieRpEnable[11]", 1, old->PcieRpEnable[11],
+	fsp_display_upd_value("PcieRpEnable[11]", 1, old->PcieRpEnable[11],
 		new->PcieRpEnable[11]);
-	soc_display_upd_value("PcieRpEnable[12]", 1, old->PcieRpEnable[12],
+	fsp_display_upd_value("PcieRpEnable[12]", 1, old->PcieRpEnable[12],
 		new->PcieRpEnable[12]);
-	soc_display_upd_value("PcieRpEnable[13]", 1, old->PcieRpEnable[13],
+	fsp_display_upd_value("PcieRpEnable[13]", 1, old->PcieRpEnable[13],
 		new->PcieRpEnable[13]);
-	soc_display_upd_value("PcieRpEnable[14]", 1, old->PcieRpEnable[14],
+	fsp_display_upd_value("PcieRpEnable[14]", 1, old->PcieRpEnable[14],
 		new->PcieRpEnable[14]);
-	soc_display_upd_value("PcieRpEnable[15]", 1, old->PcieRpEnable[15],
+	fsp_display_upd_value("PcieRpEnable[15]", 1, old->PcieRpEnable[15],
 		new->PcieRpEnable[15]);
-	soc_display_upd_value("PcieRpEnable[16]", 1, old->PcieRpEnable[16],
+	fsp_display_upd_value("PcieRpEnable[16]", 1, old->PcieRpEnable[16],
 		new->PcieRpEnable[16]);
-	soc_display_upd_value("PcieRpEnable[17]", 1, old->PcieRpEnable[17],
+	fsp_display_upd_value("PcieRpEnable[17]", 1, old->PcieRpEnable[17],
 		new->PcieRpEnable[17]);
-	soc_display_upd_value("PcieRpEnable[18]", 1, old->PcieRpEnable[18],
+	fsp_display_upd_value("PcieRpEnable[18]", 1, old->PcieRpEnable[18],
 		new->PcieRpEnable[18]);
-	soc_display_upd_value("PcieRpEnable[19]", 1, old->PcieRpEnable[19],
+	fsp_display_upd_value("PcieRpEnable[19]", 1, old->PcieRpEnable[19],
 		new->PcieRpEnable[19]);
-	soc_display_upd_value("PcieRpClkReqSupport[0]", 1,
+	fsp_display_upd_value("PcieRpClkReqSupport[0]", 1,
 		old->PcieRpClkReqSupport[0],
 		new->PcieRpClkReqSupport[0]);
-	soc_display_upd_value("PcieRpClkReqSupport[1]", 1,
+	fsp_display_upd_value("PcieRpClkReqSupport[1]", 1,
 		old->PcieRpClkReqSupport[1],
 		new->PcieRpClkReqSupport[1]);
-	soc_display_upd_value("PcieRpClkReqSupport[2]", 1,
+	fsp_display_upd_value("PcieRpClkReqSupport[2]", 1,
 		old->PcieRpClkReqSupport[2],
 		new->PcieRpClkReqSupport[2]);
-	soc_display_upd_value("PcieRpClkReqSupport[3]", 1,
+	fsp_display_upd_value("PcieRpClkReqSupport[3]", 1,
 		old->PcieRpClkReqSupport[3],
 		new->PcieRpClkReqSupport[3]);
-	soc_display_upd_value("PcieRpClkReqSupport[4]", 1,
+	fsp_display_upd_value("PcieRpClkReqSupport[4]", 1,
 		old->PcieRpClkReqSupport[4],
 		new->PcieRpClkReqSupport[4]);
-	soc_display_upd_value("PcieRpClkReqSupport[5]", 1,
+	fsp_display_upd_value("PcieRpClkReqSupport[5]", 1,
 		old->PcieRpClkReqSupport[5],
 		new->PcieRpClkReqSupport[5]);
-	soc_display_upd_value("PcieRpClkReqSupport[6]", 1,
+	fsp_display_upd_value("PcieRpClkReqSupport[6]", 1,
 		old->PcieRpClkReqSupport[6],
 		new->PcieRpClkReqSupport[6]);
-	soc_display_upd_value("PcieRpClkReqSupport[7]", 1,
+	fsp_display_upd_value("PcieRpClkReqSupport[7]", 1,
 		old->PcieRpClkReqSupport[7],
 		new->PcieRpClkReqSupport[7]);
-	soc_display_upd_value("PcieRpClkReqSupport[8]", 1,
+	fsp_display_upd_value("PcieRpClkReqSupport[8]", 1,
 		old->PcieRpClkReqSupport[8],
 		new->PcieRpClkReqSupport[8]);
-	soc_display_upd_value("PcieRpClkReqSupport[9]", 1,
+	fsp_display_upd_value("PcieRpClkReqSupport[9]", 1,
 		old->PcieRpClkReqSupport[9],
 		new->PcieRpClkReqSupport[9]);
-	soc_display_upd_value("PcieRpClkReqSupport[10]", 1,
+	fsp_display_upd_value("PcieRpClkReqSupport[10]", 1,
 		old->PcieRpClkReqSupport[10],
 		new->PcieRpClkReqSupport[10]);
-	soc_display_upd_value("PcieRpClkReqSupport[11]", 1,
+	fsp_display_upd_value("PcieRpClkReqSupport[11]", 1,
 		old->PcieRpClkReqSupport[11],
 		new->PcieRpClkReqSupport[11]);
-	soc_display_upd_value("PcieRpClkReqSupport[12]", 1,
+	fsp_display_upd_value("PcieRpClkReqSupport[12]", 1,
 		old->PcieRpClkReqSupport[12],
 		new->PcieRpClkReqSupport[12]);
-	soc_display_upd_value("PcieRpClkReqSupport[13]", 1,
+	fsp_display_upd_value("PcieRpClkReqSupport[13]", 1,
 		old->PcieRpClkReqSupport[13],
 		new->PcieRpClkReqSupport[13]);
-	soc_display_upd_value("PcieRpClkReqSupport[14]", 1,
+	fsp_display_upd_value("PcieRpClkReqSupport[14]", 1,
 		old->PcieRpClkReqSupport[14],
 		new->PcieRpClkReqSupport[14]);
-	soc_display_upd_value("PcieRpClkReqSupport[15]", 1,
+	fsp_display_upd_value("PcieRpClkReqSupport[15]", 1,
 		old->PcieRpClkReqSupport[15],
 		new->PcieRpClkReqSupport[15]);
-	soc_display_upd_value("PcieRpClkReqSupport[16]", 1,
+	fsp_display_upd_value("PcieRpClkReqSupport[16]", 1,
 		old->PcieRpClkReqSupport[16],
 		new->PcieRpClkReqSupport[16]);
-	soc_display_upd_value("PcieRpClkReqSupport[17]", 1,
+	fsp_display_upd_value("PcieRpClkReqSupport[17]", 1,
 		old->PcieRpClkReqSupport[17],
 		new->PcieRpClkReqSupport[17]);
-	soc_display_upd_value("PcieRpClkReqSupport[18]", 1,
+	fsp_display_upd_value("PcieRpClkReqSupport[18]", 1,
 		old->PcieRpClkReqSupport[18],
 		new->PcieRpClkReqSupport[18]);
-	soc_display_upd_value("PcieRpClkReqSupport[19]", 1,
+	fsp_display_upd_value("PcieRpClkReqSupport[19]", 1,
 		old->PcieRpClkReqSupport[19],
 		new->PcieRpClkReqSupport[19]);
-	soc_display_upd_value("PcieRpClkReqNumber[0]", 1,
+	fsp_display_upd_value("PcieRpClkReqNumber[0]", 1,
 		old->PcieRpClkReqNumber[0],
 		new->PcieRpClkReqNumber[0]);
-	soc_display_upd_value("PcieRpClkReqNumber[1]", 1,
+	fsp_display_upd_value("PcieRpClkReqNumber[1]", 1,
 		old->PcieRpClkReqNumber[1],
 		new->PcieRpClkReqNumber[1]);
-	soc_display_upd_value("PcieRpClkReqNumber[2]", 1,
+	fsp_display_upd_value("PcieRpClkReqNumber[2]", 1,
 		old->PcieRpClkReqNumber[2],
 		new->PcieRpClkReqNumber[2]);
-	soc_display_upd_value("PcieRpClkReqNumber[3]", 1,
+	fsp_display_upd_value("PcieRpClkReqNumber[3]", 1,
 		old->PcieRpClkReqNumber[3],
 		new->PcieRpClkReqNumber[3]);
-	soc_display_upd_value("PcieRpClkReqNumber[4]", 1,
+	fsp_display_upd_value("PcieRpClkReqNumber[4]", 1,
 		old->PcieRpClkReqNumber[4],
 		new->PcieRpClkReqNumber[4]);
-	soc_display_upd_value("PcieRpClkReqNumber[5]", 1,
+	fsp_display_upd_value("PcieRpClkReqNumber[5]", 1,
 		old->PcieRpClkReqNumber[5],
 		new->PcieRpClkReqNumber[5]);
-	soc_display_upd_value("PcieRpClkReqNumber[6]", 1,
+	fsp_display_upd_value("PcieRpClkReqNumber[6]", 1,
 		old->PcieRpClkReqNumber[6],
 		new->PcieRpClkReqNumber[6]);
-	soc_display_upd_value("PcieRpClkReqNumber[7]", 1,
+	fsp_display_upd_value("PcieRpClkReqNumber[7]", 1,
 		old->PcieRpClkReqNumber[7],
 		new->PcieRpClkReqNumber[7]);
-	soc_display_upd_value("PcieRpClkReqNumber[8]", 1,
+	fsp_display_upd_value("PcieRpClkReqNumber[8]", 1,
 		old->PcieRpClkReqNumber[8],
 		new->PcieRpClkReqNumber[8]);
-	soc_display_upd_value("PcieRpClkReqNumber[9]", 1,
+	fsp_display_upd_value("PcieRpClkReqNumber[9]", 1,
 		old->PcieRpClkReqNumber[9],
 		new->PcieRpClkReqNumber[9]);
-	soc_display_upd_value("PcieRpClkReqNumber[10]", 1,
+	fsp_display_upd_value("PcieRpClkReqNumber[10]", 1,
 		old->PcieRpClkReqNumber[10],
 		new->PcieRpClkReqNumber[10]);
-	soc_display_upd_value("PcieRpClkReqNumber[11]", 1,
+	fsp_display_upd_value("PcieRpClkReqNumber[11]", 1,
 		old->PcieRpClkReqNumber[11],
 		new->PcieRpClkReqNumber[11]);
-	soc_display_upd_value("PcieRpClkReqNumber[12]", 1,
+	fsp_display_upd_value("PcieRpClkReqNumber[12]", 1,
 		old->PcieRpClkReqNumber[12],
 		new->PcieRpClkReqNumber[12]);
-	soc_display_upd_value("PcieRpClkReqNumber[13]", 1,
+	fsp_display_upd_value("PcieRpClkReqNumber[13]", 1,
 		old->PcieRpClkReqNumber[13],
 		new->PcieRpClkReqNumber[13]);
-	soc_display_upd_value("PcieRpClkReqNumber[14]", 1,
+	fsp_display_upd_value("PcieRpClkReqNumber[14]", 1,
 		old->PcieRpClkReqNumber[14],
 		new->PcieRpClkReqNumber[14]);
-	soc_display_upd_value("PcieRpClkReqNumber[15]", 1,
+	fsp_display_upd_value("PcieRpClkReqNumber[15]", 1,
 		old->PcieRpClkReqNumber[15],
 		new->PcieRpClkReqNumber[15]);
-	soc_display_upd_value("PcieRpClkReqNumber[16]", 1,
+	fsp_display_upd_value("PcieRpClkReqNumber[16]", 1,
 		old->PcieRpClkReqNumber[16],
 		new->PcieRpClkReqNumber[16]);
-	soc_display_upd_value("PcieRpClkReqNumber[17]", 1,
+	fsp_display_upd_value("PcieRpClkReqNumber[17]", 1,
 		old->PcieRpClkReqNumber[17],
 		new->PcieRpClkReqNumber[17]);
-	soc_display_upd_value("PcieRpClkReqNumber[18]", 1,
+	fsp_display_upd_value("PcieRpClkReqNumber[18]", 1,
 		old->PcieRpClkReqNumber[18],
 		new->PcieRpClkReqNumber[18]);
-	soc_display_upd_value("PcieRpClkReqNumber[19]", 1,
+	fsp_display_upd_value("PcieRpClkReqNumber[19]", 1,
 		old->PcieRpClkReqNumber[19],
 		new->PcieRpClkReqNumber[19]);
-	soc_display_upd_value("IgdDvmt50PreAlloc", 1, old->IgdDvmt50PreAlloc,
+	fsp_display_upd_value("IgdDvmt50PreAlloc", 1, old->IgdDvmt50PreAlloc,
 		new->IgdDvmt50PreAlloc);
-	soc_display_upd_value("InternalGfx", 1, old->InternalGfx,
+	fsp_display_upd_value("InternalGfx", 1, old->InternalGfx,
 		new->InternalGfx);
-	soc_display_upd_value("ApertureSize", 1, old->ApertureSize,
+	fsp_display_upd_value("ApertureSize", 1, old->ApertureSize,
 		new->ApertureSize);
-	soc_display_upd_value("SaGv", 1, old->SaGv, new->SaGv);
-	soc_display_upd_value("RMT", 1, old->RMT, new->RMT);
-	soc_display_upd_value("Cio2Enable", 1, old->Cio2Enable, new->Cio2Enable);
+	fsp_display_upd_value("SaGv", 1, old->SaGv, new->SaGv);
+	fsp_display_upd_value("RMT", 1, old->RMT, new->RMT);
+	fsp_display_upd_value("Cio2Enable", 1, old->Cio2Enable, new->Cio2Enable);
 }
 
 /* SOC initialization after RAM is enabled. */