diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-10-15 12:07:03 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-27 15:19:03 +0100 |
| commit | 94b856ef9afaca880909d22b24d5443408c47920 (patch) | |
| tree | 14a76715a13535b5c2991103adf4820f776f1dd5 /src/soc/intel/skylake | |
| parent | 597de2849d8a0861ba0d7fca32948bdf37378eed (diff) | |
FSP 1.1: Move common FSP code
Move the FSP common code from the src/soc/intel/common directory into
the src/drivers/intel/fsp1_1 directory. Rename the Kconfig values
associated with this common code.
BRANCH=none
BUG=None
TEST=Build and run on kunimitsu
Change-Id: If1ca613b5010424c797e047c2258760ac3724a5a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e8228cb2a12df1cc06646071fafe10e50bf01440
Original-Change-Id: I4ea84ea4e3e96ae0cfdbbaeb1316caee83359293
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/306350
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12156
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/ramstage.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/romstage.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/smm.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/skylake/ramstage.c | 1 |
5 files changed, 8 insertions, 9 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 2ea20a0803..d63fa70d9a 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -19,6 +19,10 @@ config CPU_SPECIFIC_OPTIONS select COLLECT_TIMESTAMPS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_MICROCODE_IN_CBFS + select FSP_RAM_INIT + select FSP_ROMSTAGE + select FSP_STACK + select FSP_STAGE_CACHE select GENERIC_GPIO_LIB select HAS_PRECBMEM_TIMESTAMP_REGION select HAVE_HARD_RESET @@ -39,11 +43,7 @@ config CPU_SPECIFIC_OPTIONS select RELOCATABLE_RAMSTAGE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE - select SOC_INTEL_COMMON_FSP_RAM_INIT - select SOC_INTEL_COMMON_FSP_ROMSTAGE select SOC_INTEL_COMMON_RESET - select SOC_INTEL_COMMON_STACK - select SOC_INTEL_COMMON_STAGE_CACHE select SMM_MODULES select SMM_TSEG select SMP diff --git a/src/soc/intel/skylake/include/soc/ramstage.h b/src/soc/intel/skylake/include/soc/ramstage.h index fb06b3386f..5c10393b23 100644 --- a/src/soc/intel/skylake/include/soc/ramstage.h +++ b/src/soc/intel/skylake/include/soc/ramstage.h @@ -23,7 +23,7 @@ #include <chip.h> #include <device/device.h> -#include <soc/intel/common/ramstage.h> +#include <fsp/ramstage.h> void pch_enable_dev(device_t dev); void soc_init_pre_device(void *chip_info); diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h index a88de66441..1d4254873b 100644 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -21,7 +21,7 @@ #ifndef _SOC_ROMSTAGE_H_ #define _SOC_ROMSTAGE_H_ -#include <soc/intel/common/romstage.h> +#include <fsp/romstage.h> struct chipset_power_state; struct chipset_power_state *fill_power_state(void); diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 212a4448b0..5f5167d74d 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -23,8 +23,8 @@ #include <stdint.h> #include <cpu/x86/msr.h> -#include <soc/intel/common/romstage.h> -#include <soc/intel/common/memmap.h> +#include <fsp/memmap.h> +#include <fsp/romstage.h> #include <soc/gpio.h> struct ied_header { diff --git a/src/soc/intel/skylake/ramstage.c b/src/soc/intel/skylake/ramstage.c index 3646843e87..e215978597 100644 --- a/src/soc/intel/skylake/ramstage.c +++ b/src/soc/intel/skylake/ramstage.c @@ -19,7 +19,6 @@ */ #include <soc/ramstage.h> -#include <soc/intel/common/ramstage.h> void soc_init_pre_device(void *chip_info) { |