diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-03-07 14:02:23 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-03-28 16:38:42 +0200 |
| commit | 03e971cd23e96b9293fc3ecc420f56ad91326cd9 (patch) | |
| tree | 722243549211ec6204f190f1d2c1d825d41aa466 /src/soc/intel/skylake/romstage | |
| parent | 0637e567e13adab5b204a33fc57a54f437761f3f (diff) | |
soc/intel/common/block: Add cache as ram init and teardown code
Create sample model for common car init and teardown programming.
TEST=Booted Reef, KCRD/EVE, GLKRVP with CAR_CQOS, CAR_NEM_ENHANCED
and CAR_NEM configs till post code 0x2a.
Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18381
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/skylake/romstage')
| -rw-r--r-- | src/soc/intel/skylake/romstage/car_stage_fsp20.S | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/romstage/car_stage_fsp20.S b/src/soc/intel/skylake/romstage/car_stage_fsp20.S index c6401fa597..5ef8bd61bf 100644 --- a/src/soc/intel/skylake/romstage/car_stage_fsp20.S +++ b/src/soc/intel/skylake/romstage/car_stage_fsp20.S @@ -37,7 +37,8 @@ car_stage_entry: /* Switch to the stack in RAM */ movl %eax, %esp - #include <soc/car_teardown.S> + /* chipset_teardown_car() is expected to disable cache-as-ram. */ + call chipset_teardown_car /* Display the MTRRs */ call soc_display_mtrrs |